Dual multiplication region configuration for near infrared sensitivity in silicon-based CMOS single photon avalanche diodes

Abstract

A near infrared sensitivity enhanced non-isolated substrate silicon-based single photon avalanche diode is disclosed, comprising a p-well layer (101), a high voltage n-well (102), the p-well layer and the high voltage n-well layer positioned against each other and configured to form a main junction (100) defining an active region (104), the p-well layer comprising a doping according to a doping concentration profile, the p-well layer is configured to have a first double peak in a doping concentration profile of the p-well layer throughout the active region, the first double peak corresponding to a respective p-type doped region, and the high voltage n-well is configured to have a second double peak corresponding to a respective n-type doped region, the second double peak corresponding to a respective p-type doped region, and the second double peak corresponding to a respective n-type doped region. The n-doped region is configured to achieve an n-p-n-p type device junction distribution, whereby further, the p-well layer is lightly doped and configured to obtain a wide depletion region, i.e., at least 1 [mu] m wide, and the high voltage n-well layer is further configured to extend beyond the p-well layer to form a guard ring (103) around the active region.

Description

TECHNICAL FIELD

[0001] The present invention relates to a single photon avalanche diode, and more particularly, to a single photon avalanche diode that addresses low probability of photon detection at near infrared (NIR) wavelengths and high overbias requirement in a wide depletion (active) region scheme, while utilizing standard silicon-based (Si) CMOS processes. BACKGROUND

[0002] Applications such as light detection and ranging (LiDAR), optical tomography, and fiber-optic communications require high sensitivity photodetection in the near infrared (NIR) [1]-[3]. Therefore, there is a growing effort to improve the near infrared (NIR) efficiency in solid-state photodetectors. In such detectors, single-photon avalanche diodes (SPADs) exhibit photon counting capability and low jitter in a compact and often low-cost form. To enhance sensitivity in the near infrared (NIR), wider depletion regions have been investigated to enable collection of deeply absorbed near infrared (NIR) photons in silicon [4]-

[11] . There are two main challenges in the wide depletion region scheme. First, creating single photon avalanche diodes (SPADs) with wide depletion regions becomes more difficult while scaling down CMOS process nodes, as the doping concentration tends to increase in the reduced size of smaller nodes. Second, the electric field strength becomes relatively low in the wide depletion region, and it linearly decays from the avalanche multiplication region towards the edge of the depletion region. Therefore, a high overbias voltage (about 10V) is required for the wide depletion device to increase the electric field strength and the probability of avalanche triggering. However, the high overbias voltage required can complicate the pixel circuit design when the overbias becomes higher than the rail-to-rail voltage range allowed in digital circuits. SUMMARY

[0003] The present invention provides a near-infrared sensitivity enhanced non-isolated substrate silicon-based single-photon avalanche diode, comprising a p-well layer, a high-voltage n-well, the p-well layer and the high-voltage n-well layer positioned against each other and configured to form a main junction defining an active region, the p-well layer comprising a doping according to a doping concentration profile, the p-well layer configured to have a first double peak in the doping concentration profile throughout the p-well layer in the active region, the first double peak corresponding to a respective p-type doped region, and the high-voltage n-well configured to have a second double peak, the second double peak corresponding to a respective n-type doped region, the n-type doped region configured to achieve an n-p-n-p type device junction profile, whereby further, the p-well layer is lightly doped and configured to obtain a wide depletion region, i.e. at least 1 pm wide, the high-voltage n-well layer further configured to extend beyond the p-well layer to form a guard ring around the active region.

[0004] In a preferred embodiment, the n-p-n-p type device junction profile is further configured such that the wide depletion region confines two different multiplication regions, and one of the n-type doped regions is sandwiched between the p-type doped regions, and has a well-designed doping concentration and depth configured such that the electric field between the two p-n junctions never reaches zero. BRIEF DESCRIPTION OF DRAWINGS

[0005] The present invention will be better understood by a detailed description of preferred embodiments thereof, with reference to the attached drawings, in which Figure 1 A cross-section of an example embodiment of a device according to the present invention is shown; Figure 2 includes (a) an electric field profile of an example embodiment of a device according to the present invention having double multiplication regions and (b) a single-photon avalanche diode (SPAD) having a wide depletion region; (c) a plot of an electric field comparison showing the electric field intensity at the center of each device along the y-axis; (d) a schematic of a cross-section of a single-photon avalanche diode (SPAD) having a wide depletion region; wherein the white line on the electric field profile corresponds to the depletion region boundary; Figure 3 includes (a) current-voltage (I-V) measurements on a single-photon avalanche diode (SPAD) under ambient light and room temperature; and (b) light emission tests on the device under 3V and 5V overbias voltage; Figure 4 A plot including DCR characteristics of devices from five different dies according to the present invention versus overbias voltage; Figure 5 A inter-arrival avalanche time histogram including exponential fit and post-pulse probability under an overbias voltage of 5.5V; Figure 6 A plot including PDP measurements of a device according to the present invention under 1V to 5.5V overbias voltage; Figure 7A temporal jitter histogram comprising a device according to the present application, obtained at 850 nm and 5.5 V overbias voltage; Figure 8 comprises: (a) a plot showing peak PDP versus DCR per unit area; and (b) a plot showing PDP at 850 nm versus overbias voltage, compared to prior art front-side (FSI) single photon avalanche diodes (SPADs) fabricated in the same and other CMOS process nodes; Figure 9 A plot comprising the resulting doping profile (n-p-n-p) representing doping concentration in depth; Figure 10 Indicating photon absorption and avalanche multiplication process at longer wavelengths in wide depletion single photon avalanche diodes (SPADs) with (a) one multiplication region, (b) double multiplication region; and Figure 11 Showing the following electron-hole avalanche breakdown probability: (a) an example embodiment of a device according to the present application with double multiplication region approach, and (b) a reference wide depletion region single photon avalanche diode (SPAD); (c) the value of avalanche breakdown probability at the center of each device along the y-axis.

[0006] Throughout the drawings, the same reference designators will be used to refer to same or like features. DETAILED DESCRIPTION

[0007] The present invention proposes a single-photon avalanche diode (SPAD) device that solves the low near-infrared (NIR) sensitivity and high overbias requirement in the wide-depletion region approach used in the design of Si CMOS SPADs. The present invention shows that higher near-infrared (NIR) sensitivity at lower overbias voltage than prior art devices (see "BACKGROUND" section and Figure 8) can be achieved by total avalanche breakdown or avalanche trigger probability enhancement in the depletion region. In order to be able to increase the avalanche trigger probability, extensive numerical simulations of process Technology Computer Aided Design (TCAD) were performed, which made it possible to design a bimodal electric field distribution composed of two peaks in the same depletion region, where each peak corresponds to a different multiplication region, thus naming the region obtained by this method as a dual-multiplication region configuration. The dual-multiplication region comprises two different multiplication regions. Due to these two separate multiplication regions, both photo-generated electrons and holes within the depletion region can experience avalanche multiplication. Furthermore, due to the two different multiplication regions, photo-generated carriers that are generated in the neutral substrate but diffuse to the depletion region have a higher chance of triggering an avalanche. The dual-multiplication region configuration obtained is different from the prior art design of wide-depletion and near-infrared (NIR) enhanced single-photon avalanche diodes (SPADs), where the devices only have one multiplication region and the strength of the electric field remains low in the remaining depletion region. Due to this electric field engineering and design of non-isolated substrate devices, the near-infrared (NIR) PDP is increased at lower overbias voltage, while not sacrificing the sensitivity in the visible spectrum. If the pixel circuitry allows an increase in the overbias voltage, the maximum achievable near-infrared (NIR) PDP is also enhanced. The device has been fabricated in a 110 nm CIS process node and has an active region with a diameter of 10 pm.

[0008] Device design and process computer-aided design (TCAD) simulation Reference Figure 1 shows a cross-section of an example embodiment of a device according to the present invention, where the semiconductor used can be silicon. In order to create two multiplication regions confined to the same depletion region (enhanced avalanche trigger probability of carriers), a p-well layer 101 comprising a doping concentration profile (not shown in Figure 1 the first bimodal profile 900 shown in Figure 9 the first bimodal profile 900 shown in Figure 9As shown, there is a n-well high voltage second peak 901 and a p-well first peak 900, which should form two different depletion regions and multiplication regions. However, the two depletion regions are merged because the n-type doped region sandwiched between the p-type doped regions (which corresponds to the second peak in the high voltage n-well layer as shown in Figure 9 The high voltage n-well layer 102 extends to form a guard ring 103 around the main junction 100 and to prevent the device from suffering from premature edge breakdown. A high voltage is applied to the device between the P+ anode electrode 106 / high voltage p-well anode electrode 105 and the N+ cathode electrode 107.

[0009] Dual multiplication center in a wide depletion region The electric field inside a single photon avalanche diode (SPAD) is designed via the doping profile depicted in Figure 9 In this configuration, the total doping concentration varies as n-p-n-p, which should in fact form two p-n junctions and depletion regions. The first intersection between the n-layer and the p-layer should correspond to the first junction and the third intersection should yield the second intersection. However, it is expected that the electric field will decay when the n-type doping exceeds the p-type doping. If the second junction is located before the electric field reaches zero, then the two depletion regions with their respective multiplication regions should merge to form only one depletion region. This can be achieved with the n-type doping and depth in the middle being adapted so that a zero electric field is not created before the second junction. Thus, a second multiplication region in the same depletion region can be achieved via this second peak in the doping layer 101. Therefore, having a second peak in the layer 101 that exceeds the n-type doping is necessary to achieve a second multiplication region. Thus, in the electric field profile of the resulting device, a double peak is expected, with each peak substantially corresponding to a different avalanche multiplication region, which makes the name double multiplication region for this method. This is different from the design of any wide depletion region single photon avalanche diode (SPAD), which has only a single multiplication region. By inserting a second multiplication region into the same depletion region, the avalanche trigger probability, and thus the near-infrared (NIR) sensitivity, is significantly enhanced even at lower overbias voltages.

[0010] As mentioned above, the material used to manufacture the device is silicon, and the process is a 110 nm CMOS image sensor (CIS, CMOS Image Sensor). The high voltage can be, for example, about 3.3 V.

[0011] Various example size values for the device include an active junction diameter of 10 pm, and in Figure 1 Figure 1 from left P+ region 106 to right P+ region 106 is 16 pm (when reading

[0012] The width of the depletion region can be, for example, 1 pm. ​

[0013] Electric field and avalanche breakdown probability The electric field simulation from the device of Figure 1 is shown in Fig. 2. The simulation was performed on a process computer-aided design (TCAD) numerical tool. The layer's doping profile used in the cross-section of Figure 1 is imported into the simulation environment. Figure 1 The doping profile is shown in Fig. 2 (a) containing a plot of the doping concentration as a function of depth, including curves labeled "double-peak p-well" and "high-voltage n-well". Then, the electric field strength at different voltages is calculated by solving the coupled Poisson equation and electron-hole drift-diffusion equations. As shown in Fig. 2 (a), in addition to the first electric field peak indicated with a first color tone 200, a second peak appears in the field distribution of the proposed device at 1 V overbias, which is depicted with a second color tone 201. The electric field variation from 1 V to 5 V overbias voltage is also given, where the second peak becomes more pronounced with the first color tone 200 of its appearance. Furthermore, the strength of the electric field at the center of the device along the y-axis from 1 V to 5 V overbias is provided in Fig. 2 (b). This indicates that the electric field distribution indeed has double peaks 202 and 203 (see Fig. 2 (c)), which are confined to one depletion region, the boundary of which is shown by the arrow 204 in Fig. 2 (b). Each peak 202 and 203 is higher than the critical avalanche breakdown field in silicon, which is 3 x 107 V / cm, and corresponds to different multiplication regions. Thus, the second peak 203 will behave as a second multiplication center for the carriers, which is a new concept for single-photon avalanche diode (SPAD) design and can be used for any CMOS process. Therefore, the electric field simulation proves the insertion of two multiplication regions into one wide depletion region. So far, there is no second multiplication region in other designed single-photon avalanche diodes (SPADs), an example of which is simulated and its electric field distribution 205 is shown in Fig. 2 (b) and Fig. 2 (c), which shows there is only one peak corresponding to only one multiplication region in those devices. The cross-section of this exemplary single-photon avalanche diode (SPAD) is provided in Fig. 2 (d), which is modified from the literature [6] and has a similar depletion region width as the proposed device designed with the double multiplication region method. The depletion width of both devices is indicated by the arrow 204 in Fig. 2 (a) and 2 (b). Figure 9 Figure 1 5 V / cm, and corresponds to different multiplication regions. Thus, the second peak 203 will behave as a second multiplication center for the carriers, which is a new concept for single-photon avalanche diode (SPAD) design and can be used for any CMOS process. Therefore, the electric field simulation proves the insertion of two multiplication regions into one wide depletion region. So far, there is no second multiplication region in other designed single-photon avalanche diodes (SPADs), an example of which is simulated and its electric field distribution 205 is shown in Fig. 2 (b) and Fig. 2 (c), which shows there is only one peak corresponding to only one multiplication region in those devices. The cross-section of this exemplary single-photon avalanche diode (SPAD) is provided in Fig. 2 (d), which is modified from the literature [6] and has a similar depletion region width as the proposed device designed with the double multiplication region method. The depletion width of both devices is indicated by the arrow 204 in Fig. 2 (a) and 2 (b).

[0014] One advantage of this new single-photon avalanche diode (SPAD) electric field distribution with two separate multiplication regions in a wide depletion region is the increased total avalanche trigger probability of photo-generated carriers, thus enhancing the near-infrared (NIR) sensitivity of the device and reaching a high near-infrared (NIR) PDP at a relatively lower overbias voltage. This advantage is conceptualized in Figure 10 .​​Figure 10 (a) represents a wide depletion region single photon avalanche diode (SPAD) 1000 with one multiplication region 1001. As shown in this scheme, when an electron-hole pair 1002 is generated in the middle of the depletion region 1003 upon absorption of a photon 1004, only the photo-generated electron (e - ) 1002 can trigger an avalanche, while the hole (h + ) travels to the substrate. Moreover, due to one multiplication region 1001, the photo-generated electron 1005, which is generated in the neutral substrate of the depletion region 1003 and diffuses to the depletion, has only one chance to trigger an avalanche. On the other hand, Figure 10 (b) represents a device designed with the double multiplication region approach. It shows that due to the inserted second multiplication region 1007, the photo-generated hole (h + ) 1006 in the middle of the depletion region 1003 can also trigger an avalanche. Moreover, the diffusing photo-generated electron from the substrate can now also have up to two chances to trigger an avalanche. Thus, it is guaranteed that the total avalanche breakdown probability and the near-infrared (NIR) PDP of a single photon avalanche diode (SPAD) is increased with the double multiplication region approach. The drawback is that this concept is also valid for thermally generated or via tunneling generated carriers, which increases the noise of the single photon avalanche diode (SPADs).

[0015] To prove this claim of an enhanced avalanche breakdown probability with the double multiplication region approach, the breakdown probability of the proposed device with two multiplication regions and the example wide depletion region single photon avalanche diode (SPAD) with one multiplication region was simulated, as shown in Figure 11 (a) and Figure 11 (b), respectively. The total avalanche trigger probability obtained by the wide depletion region single photon avalanche diode (SPAD) is exemplified to be 33% in the middle of the device, while due to the presence of the second multiplication region, it reaches 77% in the proposed single photon avalanche diode (SPAD, as can be observed from Figure 11 (c)). Moreover, if absorption outside the depletion region is considered, which can occur at near-infrared (NIR) wavelengths, the photo-generated electron that is going to diffuse to the depletion region has a 1.2 times higher probability to trigger an avalanche, as calculated from the edge of the depletion region. Thus, operating the double multiplication region device at lower overbias voltages can achieve similar or higher near-infrared (NIR) PDPs than conventional wide depletion region single photon avalanche diodes (SPADs) with only one multiplication region.

[0016] Characterization results Current-voltage (I-V) measurement and light emission test Figure 3 (a) shows Figure 1current-voltage (I-V) characteristics of the device under ambient light and room temperature. A breakdown voltage, which appears as a sharp increase in current, occurs at 29.8 V. To verify that the device does not experience premature edge breakdown, light emission tests were performed under over-bias voltages of 3 V and 5 V. Figure 3(b) shows that there is no edge breakdown effect in the proposed device due to the guard ring structure implemented in the design. These results prove that the device is working properly in Geiger mode.

[0017] DCR measurement DCR measurements were performed with an externally connected 660 kOhm resistor to quench and recharge the single-photon avalanche diodes (SPADs). The same single-photon avalanche diodes (SPADs) were measured from different dies to collect statistical data about the noise. Figure 4 DCR measurements with respect to over-bias voltage belonging to five devices are presented. According to this plot, device 3 was chosen as a reference since it corresponds to the median in the noise measurements. The DCR of this device varies from 8 cps at 1 V to 295 cps at 5.5 V over-bias and room temperature. Therefore, the DCR per unit area becomes 3.7 cps / pm2at 5.5 V over-bias. 2 In the following, the characterization results of device 3 will be presented.

[0018] Post-pulse probability measurement The after-pulse histogram of the device was obtained with the avalanche interval time method. To measure the time interval between pulses, a high-speed digital oscilloscope (Tele-Dyne LeCroy WavePro 760ZI-A) was used. Figure 5 The after-pulse histogram obtained under dim light is shown in Figure 5. The histogram 500 corresponds to the measured pulse arrival interval time histogram, and the curve 501 is the fitted curve. Since the single-photon avalanche diodes (SPADs) are passively quenched and recharged by an external resistor, the dead time of the single-photon avalanche diodes (SPADs) is approximately 7 ps. The after-pulse probability of the device is 5.4% at 5.5 V over-bias, which is calculated as the ratio of the area between the measured curve and the fitted curve to the area under the fitted curve. Therefore, this low after-pulse probability indicates that the defect concentration in the fabricated device is also expected to be low.

[0019] Photon detection probability measurement The PDP of the device was measured by a monochromator setup, where a xenon lamp emits broadband light and a monochromator selects each wavelength by a grating. Then, an integrating sphere was used to provide spatially uniform light onto the single-photon avalanche diodes (SPADs) and a calibrated reference detector to accurately assess the impinging photon count. In this configuration, as Figure 6The measured PDP of the device is obtained from 1 V to 5.5 V overbias voltage. As more evident at 5.5 V, the peak PDP actually occurs at two different wavelengths, i.e. 450 nm and 500 nm. It is believed that this is related to the bimodal nature of the electric field profile of the device, resulting in two multiplication regions that are most favorable for detecting these wavelengths. At 4 V overbias voltage and 500 nm wavelength, the PDP of the device is 50%, while at 5.5 V overbias, the PDP at 500 nm reaches 78%. Moreover, the near-infrared (NIR) sensitivity of the device is also enhanced due to the second multiplication region inserted in the wide depletion region and keeping the substrate unisolated from the junction. At 850 nm, the single-photon avalanche diode (SPAD) has only 13% and 25.5% PDP at 4 V and 5.5 V overbias voltage, respectively.

[0020] Jitter measurement To measure the temporal jitter, the time-correlated single-photon counting (TCSPC) technique is employed. The device is illuminated with an 850 nm (A.L.S. GmbH) pulsed laser operating at 100 kHz, and the incident power is reduced to the single-photon level with an absorbing neutral density filter. To detect the time difference between the laser clock signal and the positive edge of each avalanche pulse, the same high-speed digital oscilloscope is used. Figure 7 The jitter histogram acquired at 850 nm and 5.5 V overbias is provided in FIG. 8. The jitter is calculated in full width at half maximum (FWHM) and is 240 ps at 5.5 V overbias voltage. Two peaks in the temporal jitter are observed due to many diffused carriers from the substrate reaching the depletion region because of the non-isolated substrate structure. The smaller peak is the contribution of the carriers generated in the depletion region, and the other peak represents the contribution of the diffused carriers.

[0021] Comparison with the prior art In FIG. 8, front-illuminated (FSI) CMOS single-photon avalanche diodes (SPADs) with the best performance of wide depletion and near-infrared (NIR) enhanced sensitivity are selected for comparison with the device 3 mentioned above. FIG. 8(a) indicates the peak PDP achieved with these single-photon avalanche diodes (SPADs) as a function of the normalized DCR with an active region. It can be seen that device 3 achieves the highest PDP ever reported among these front-illuminated (FSI) wide-depletion single-photon avalanche diodes (SPADs). The noise of device 3 per unit area DCR also matches most of the state-of-the-art single-photon avalanche diodes (SPADs). FIG. 8(b) shows the PDP comparison versus overbias voltage at 850 nm wavelength. This demonstrates that device 3 indeed eliminates the need for high overbias required in wide-depletion devices, as the insertion of the second multiplication region into the same wide-depletion region in this work increases the total avalanche triggering probability. FIG. 8(b) also shows that device 3 reaches one of the highest PDPs at near-infrared (NIR).

[0022] CONCLUSION A new technique named dual multiplication region is proposed to achieve high near-infrared (NIR) PDPs at a relatively lower overbias voltage in wide-depletion single-photon avalanche diodes (SPADs). Contrary to the conventional wide-depletion devices with only one multiplication region, this technique aims to insert a second multiplication region. As Figure 11 (a) Figure 11 shown in the avalanche breakdown probability simulation in process computer-aided design (TCAD) in FIG. 8(c), the second multiplication region significantly increases the triggering probability. The reason for this increase is also explained in Figure 10 (a) Figure 10 (b). To implement the second multiplication region, a dual-peak p-well is used in combination with a high-voltage n-well layer, where the two peaks result in two p-n junctions and, thus, two multiplication regions. Between the two peaks, the n-type doping exceeds the p-type doping to cause an electric field decay and separate the two different multiplication regions, as shown in Figure 9 The characterization results of this device show that high PDPs at near-infrared (NIR) can indeed be achieved at an overbias voltage of 5.5 V, reaching 25.5% at 850 nm, while keeping the noise at an acceptable level of 295 cps. Due to the non-isolated substrate and wide-depletion single-photon avalanche diode (SPAD) structure, high near-infrared (NIR) PDPs are achieved, where the breakdown probability of the carriers is higher. Due to the avalanche triggering probability enhancement at a given overbias, the need for high overbias voltage is addressed. However, the jitter of the single-photon avalanche diode (SPAD) drops to 236 ps due to the detection of diffused carriers from the substrate.

[0023] REFERENCES [1] K. Morimoto, A. Ardelean, M.-L. Wu, A. C. Ulku, I. M. Antolovic, C. Bruschini, and E. Charbon, “Megapixel time-gated spad image sensor for 2d and 3d imaging applications,” Optica, vol. 7, no. 4, pp. 346-354, 2020. [2] J. M. Pavia, M. Scandini, S. Lindner, M. Wolf, and E. Charbon, “A 1 x 400 backside-illuminated spad sensor with 49.7 ps resolution, 30 pj / sample tdc s fabricated in 3d cmos technology for near-infrared optical tomography,” IEEE Journal of Solid-State Circuits, vol. 50, no. 10, pp. 2406-2418, 2015. [3] M. T. Rakher, L. Ma, O. Slattery, X. Tang, and K. Srini-vasan, “Quantum transduction of telecommunications-band single photons from a quantum dot by frequency upconversion,” Nature Photonics, vol. 4, no. 11, pp. 786-791, 2010. [4] M. Moreno-Garc´ A. H. Xu, L. Gasparini, and M. Perenzoni, “Low-noise single photon avalanche diodes in a 110 nm cmos technology,” in 2018 48th European Solid-State Device Research Conference (ESSDERC). IEEE, 2018, pp. 94-97. [5] I. Vornicu, J. M. Lopez-Martinez, F. N. Bandi, R. C. Galan, and A. Rodriguez-Vazquez, “Design of high-efficiency spads for lidar applications in 110 nm cmos technology,” IEEE Sensors Journal, vol. 21, no. 4, pp. 4776-4785, 2020. [6] E. A. Webster, L. A. Grant, and R. K. Henderson, “A high-performance single-photon avalanche diode in 130-nm cmos imaging technology,” IEEE Electron Device Letters, vol. 33, no. 11, pp. 1589-1591, 2012. [7] M. Sanzaro, P. Gattari, F. Villa, A. Tosi, G. Croce, and F. Zappa, “Single-photon avalanche diodes in a 0.16 µm bcd technology with sharp timing response and red-enhanced sensitivity,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 24, no. 2, pp. 1-9, 2017. [8] F. Gramuglia, P. Keshavarzian, E. Kizilkan, C. Bruschini, S. S. Tan, M. Tng, E. Quek, M.-J. Lee, and E. Charbon, “Engineering breakdown probability profile for pdp and dcr optimization in a spad fabricated in a standard 55 nm bcd process,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 28, no. 2: Optical Detectors, pp. 1–10, 2021. [9] M. Ghioni, A. Gulinatti, I. Rech, F. Zappa, and S. Cova, “Progress in silicon single-photon avalanche diodes,” IEEE Journal of selected topics in quantum electronics, vol. 13, no. 4, pp. 852–862, 2007.

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Claims

1. A near-infrared sensitivity-enhanced non-isolated substrate silicon-based single-photon avalanche diode, comprising: p-well layer (101). High voltage n-well (102). The p-well layer (101) and the high-voltage n-well layer (102) are positioned against each other and configured to form a main junction (100) defining an active region (104). The p-well layer (101) includes doping according to a doping concentration distribution. The p-well layer (101) is configured to have a first double peak (900) in the doping concentration distribution of the entire p-well layer in the active region (104), the first double peak (900) corresponding to a corresponding p-type doped region, and the high-voltage n-well (102) is configured to have a second double peak (901), the second double peak (901) corresponding to a corresponding n-type doped region, the n-type doped region being configured to realize an npnp type device junction distribution. Therefore, the p-well layer is lightly doped and configured to obtain a wide depletion region, i.e., at least 1 μm wide. The high-voltage n-well layer (102) is also configured to extend beyond the p-well layer (101) to form a guard ring (103) around the active region (104).

2. The near-infrared sensitivity-enhanced non-isolated substrate silicon-based single-photon avalanche diode according to claim 1, wherein... The junction distribution of the NPNP type device is further configured such that... The wide depletion region restricts two distinct doubling regions, and One of the n-type doped regions is sandwiched between the p-type doped regions and has a well-designed doping concentration and depth configured such that the electric field between the two pn junctions never reaches zero.

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