Comparator-based voltage regulation system and method for operating voltage regulation system

Abstract

The invention relates to a voltage regulation system, comprising a semiconductor switch for regulating an output voltage on the basis of a gate voltage, a first switch and a second switch, each of which is designed to increase or decrease the gate voltage in a closed state, a clocked comparator, the comparator is configured to compare the output voltage and a reference voltage, and the control logic is configured to control the first switch and the second switch according to the comparison of the outputs of the comparator from two consecutive clock cycles, a polarity switch, and a reference switch. The polarity switch is designed to switch the input of the comparator for the output voltage and the reference voltage for each clock cycle of the comparator. The invention also relates to a method for operating a voltage regulation system.

Description

Technical Field

[0001] The present invention relates to a comparator-based voltage regulation system that operates using a comparator and a reference voltage. Background Technology

[0002] Voltage regulation systems are known from existing technologies. Low dropout (LDO) regulators are a common solution for many power management units (PMUs) because they are highly efficient and operate without switching noise. However, traditional LDOs based on analog error amplifiers have limited scalability. Furthermore, increasingly lower supply voltages significantly complicate the design of analog error amplifiers. Therefore, digital LDOs have been developed, which use comparators instead of amplifiers. Digital LDOs use transistors on the output side that operate in switching mode and not in the saturation range. However, due to these transistors, the output signal is highly unstable. Therefore, large capacitive or inductive loads are typically required to smooth the signal.

[0003] CN112947662A describes a voltage regulation system that cancels out the ripple of the output signal using two comparators. Therefore, this voltage regulation system operates using two reference voltages.

[0004] US2020 / 0127569A1 describes a voltage regulation system in which a low-pass filter is arranged on the output side to filter high-frequency components of a PWM signal. Summary of the Invention

[0005] The voltage regulation system according to the invention enables voltage regulation using only a comparator and a reference voltage. Additionally, a large load is not required on the output side to smooth the output signal.

[0006] The voltage regulation system incorporates a semiconductor switch for use based on gate voltage V. G Adjust the output voltage V out A first switch and a second switch, respectively configured to increase or decrease the gate voltage V in the closed state. G A clock-driven comparator used to compare the output voltage V. out and reference voltage V Ref Control logic for operating the first and second switches based on a comparison of the comparator's outputs over two consecutive clock cycles; and a polarity reversal switch. The polarity switching switch is configured to switch the comparator's output voltage V for each clock cycle of the comparator. out and reference voltage V RefThe input terminal. With this structure, hysteresis can be generated in a comparator-based LDO by using the comparator's bias voltage. Thus, the voltage regulator can operate with low supply voltage and low output ripple. Furthermore, large capacitor or inductive output loads are not required to reduce output ripple. Moreover, in the voltage regulator according to the invention, low-frequency noise is not transmitted to the output terminal; it only affects the voltage limit of the hysteresis.

[0007] Preferred extensions of the invention are shown below.

[0008] Preferably, the control logic has a 2-bit shift register, which is specifically formed by two D flip-flops. Due to the bistable nature of D flip-flops, the states of the D flip-flops can be stored indefinitely. Thus, past states can be considered in the current observation.

[0009] In one implementation, a 2-bit shift register is connected to an XOR gate on the input side, the XOR gate being configured to invert the comparator's output. Thus, a signal is output only when a signal is applied to one of the inputs. If signals are applied to both inputs, no signal is output to the XOR gate.

[0010] The inverting output of a D flip-flop is preferably connected to a NAND gate and a NOR gate. A NAND gate outputs a signal if only one of its inputs receives a signal. A NOR gate outputs a signal only when no signal is applied to either of its inputs.

[0011] Here, the first switch can be controlled by a NAND gate, and the second switch can be controlled by a NOR gate. Thus, these switches can be controlled differently using the same input signal.

[0012] Comparators are particularly well-designed as dynamic feedback latches. This type of comparator is easily expandable, energy-efficient, and space-saving.

[0013] In another embodiment, the control logic includes mode-switching logic, which is configured to select between two operating modes and preferably has three or more flip-flops. The mode-switching logic allows the circuit to switch from a normal mode to a precision mode and a speed mode. Therefore, the circuit can be adapted to different operating requirements.

[0014] In precision mode, the first supply current of the first switch and the second supply current of the second switch are reduced to a minimum to ensure stability. In speed mode, the first supply current of the first switch and the second supply current of the second switch are increased to their maximum values ​​to reach the desired output voltage more quickly. In speed mode, the supply current is at least twice that of the supply current in normal circuit operation. The supply current can be adjusted by a predetermined setting or by means of a voltage-controlled current source as a function of the voltage difference between the reference voltage and the output voltage. Depending on the desired function of the circuit, it is also conceivable to select the supply current values ​​of the two switches from a range between minimum and maximum values. The voltage-controlled current source as the supply current allows for faster settling times in the event of glitches or during circuit commissioning.

[0015] Advantageously, the mode switching logic is configured to short-circuit the comparator signals to the first and second switches and to short-circuit the output voltage signal and the reference voltage signal to the comparator inputs. If all bits of the shift register are identical, the short-circuiting of the comparator signals to the first and second switches occurs via a transmission gate or logic gate. This short-circuiting process reduces delays in signal transmission.

[0016] Preferably, a capacitor is arranged after the first and second switches, the capacitor maintaining the gate voltage V of the semiconductor switch. G This keeps voltage fluctuations on the semiconductor switch low. Furthermore, it enables faster voltage adaptation.

[0017] Preferably, the clock signal for the polarity switching switch used to switch the input terminals of the comparator is half the clock signal of the comparator. This prevents the polarity switching switch from switching the input terminals during an ongoing comparison. Consequently, the probability of generating an erroneous signal at the output terminal of the comparator is greatly reduced.

[0018] Furthermore, the present invention relates to a method in which a first supply current of a first switch and a second supply current of a second switch are increased to a maximum value in order to regulate the gate voltage V. G In this way, the desired output voltage can be reached more quickly. This method can be implemented using the voltage regulation system described above.

[0019] In a further step of the method, the first supply current of the first switch and the second supply current of the second switch are reduced to a minimum value to adjust the gate voltage V. G This improves the stability of the circuit. Attached Figure Description

[0020] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The drawings show...

[0021] Figure 1 A block circuit diagram of the voltage regulation system according to the present invention is shown.

[0022] Figure 2 A block diagram of a voltage regulation system with logic circuitry according to the present invention is shown.

[0023] Figure 3 A voltage graph showing the voltage regulation system according to the present invention as a function of time is shown, and

[0024] Figure 4 A block circuit diagram of the voltage regulation system according to the present invention in another operating mode is shown.

[0025] Preferably, in all the drawings, all the same components, elements and / or units are given the same reference numerals. Detailed Implementation

[0026] Figure 1 A voltage regulation system 1 is shown, which has a semiconductor switch 2 for adjusting the voltage based on the gate voltage V. G Adjust the output voltage V out and a first switch 3 and a second switch 4, the first switch and the second switch being respectively configured to increase or decrease the gate voltage V in the closed state. G . Figure 1 The voltage regulation system 1 also includes a clock-driven comparator 5, configured to compare the output voltage V. out and reference voltage V Ref The system also includes control logic 6, configured to operate the first switch 3 and the second switch 4 based on a comparison of the outputs of comparator 5 over two consecutive clock cycles. Furthermore, the voltage regulation system includes a polarity reversing switch 7 configured to switch the output voltage V of comparator 5 for each clock cycle of comparator 5. out and reference voltage V Ref The input terminal. If two consecutive clock cycles are not the same, the first switch 3 or the second switch 4 is operated. The output of comparator 5 is compared with the inverted output of comparator 5 in the next clock cycle. If V out For the minuend and V ref If the difference between the subtrahend and the subtrahend is greater than the inherent bias voltage of comparator 5, the second switch is operated to reduce the gate voltage V by discharging the second supply current 15 through capacitor 16. G And thus reduce V out If V Ref For the minuend and V outIf the difference between the subtrahend and the input is greater than the inherent bias voltage of comparator 5, the first switch is actuated to increase the gate voltage V by charging capacitor 16 with the magnitude of the first supply current 15. G And thus increase V out If V out and V Ref If the values ​​are equal or the difference between the two values ​​is lower than the inherent bias voltage of comparator 5, then the gate voltage V on capacitor 16... G The value remains the same. Capacitor 16 is preferably formed as a capacitor. Therefore, energy is only consumed when the input of comparator 5 is changed and when voltage regulation is performed. In some cases, voltage regulation can be performed solely by semiconductor switch 2, which is in particular formed as a MOSFET. For this purpose, the MOSFET operates in source follower mode. Capacitor 16 is arranged after the first switch 3 and the second switch 4, and the capacitor maintains the gate voltage V of semiconductor switch 2. G The clock signal of polarity switching switch 7 is half the speed of the clock signal of comparator 5, and is used to switch the input terminals of comparator 5.

[0027] exist Figure 2 The circuit diagram illustrates the interconnection of the logic gates for control logic 6. Control logic 6 has a 2-bit shift register 9, which, in the example shown, is formed by two D flip-flops 8. The 2-bit shift register 9 is connected to an XOR gate 10 on its input side, which is configured to invert the output of comparator 5. The inverted outputs of the D flip-flops 8 are connected to a NAND gate 11 and a NOR gate 12, respectively. A first switch 3 can be controlled by the NAND gate 11, and a second switch 4 can be controlled by the NOR gate. The second switch 4 is controlled when both D flip-flops 8 are in state "1" (i.e., logic one). The first switch 3 is controlled when both D flip-flops 8 are in state "0" (i.e., logic zero). In all other cases, no current flows through the first switch 3 and the second switch 4.

[0028] Figure 3 As shown, the clock signal of the polarity switching switch 7 used to switch the inputs of comparator 5 is half the speed of the clock signal of comparator 5. The output voltage of comparator 5 changes alternately until the output voltage V... out With reference voltage V Ref The difference is lower than a pre-defined threshold. When the threshold for V is reached... out When the desired voltage level is reached, the comparator signal remains constant.

[0029] Figure 4 This section explains the functionality of speed mode in mode switching logic 13. Mode switching logic 13... Figure 4The section is marked with a separate box because it shorts the signal of comparator 5 to the first switch 3 and the second switch 4, thus bypassing the rest of the control logic 6. However, preferably, it is configured as part of the control logic 6. Mode switching logic 13 also shorts the output voltage signal and the reference voltage signal to the input of comparator 5. This is to adjust the gate voltage V in speed mode. G The first supply current 14 of the first switch 3 and the second supply current 15 of the second switch 4 are increased to their maximum values. In a preferred embodiment, the mode switching logic 13 is configured to select between two operating modes and has more than three flip-flops. In addition to the speed mode, the operating modes include a normal mode and a precision mode. In precision mode, the first supply current 14 of the first switch 3 and the second supply current 15 of the second switch 4 are reduced to their minimum values ​​to regulate the gate voltage V. G In normal mode, the supply currents 14 and 15 are at their base values. These base values ​​are preferably located between the minimum and maximum values ​​of the supply currents 14 and 15. Therefore, switching from precision mode to speed mode and vice versa is performed through the normal mode. In another embodiment, the switching from precision mode to speed mode and vice versa is also performed directly. This allows for the adjustment of the desired voltage regulation with a relatively small delay time.

Claims

1. A voltage regulation system (1) having - a control logic (6) configured for controlling the first switch (3) and the second switch (4) depending on a comparison of the outputs of a comparator (5) in two successive clock cycles, - a semiconductor switch (2) for regulating an output voltage (V G ) on the basis of a gate voltage (V out ), - a first switch (3) and a second switch (4), configured for increasing or decreasing, respectively, the gate voltage (V G ), in the closed state - a clock-driven comparator (5) configured for comparing the output voltage (V out ) and a reference voltage (V Ref ), and - the control logic (6) having a 2-bit shift register (9), in particular formed by two D flip-flops (8). - a polarity switch (7) configured for switching the inputs of the comparator (5) for the output voltage (V out ) and the reference voltage (V Ref ) for each clock cycle of the comparator (5).

2. The voltage regulating system (1) according to claim 1, characterized in that - the 2-bit shift register (9) being connected on the input side with an XOR gate (10) configured for inverting the outputs of the comparator (5).

3. The voltage regulating system (1) according to claim 2, characterized in that - the inverted outputs of the D flip-flops (8) being connected with a NAND gate (11) and a NOR gate (12).

4. Voltage regulating system (1) according to one of claims 2 or 3, characterized in that - the first switch (3) being controllable by the NAND gate (11) and the second switch (4) being controllable by the NOR gate (12).

5. Voltage regulating system (1) according to one of claims 2 to 4, characterized in that - the comparator (5) being formed as a dynamic feedback latch (17).

6. Voltage regulating system (1) according to one of claims 1 to 5, characterized in that - the control logic (6) having a mode switching logic (13) configured for selecting between two operating modes and preferably having more than three flip-flops.

7. Voltage regulating system (1) according to one of claims 1 to 6, characterized in that - the mode switching logic (13) being configured for:

8. The voltage regulation system (1) according to claim 7, characterized in that - short-circuiting the signals of the comparator (5) to the first switch (3) and the second switch (4), and - short-circuiting an output voltage signal and a reference voltage signal to the inputs of the comparator (5). - the clock signal of a polarity switching switch (7) for exchanging the inputs of the comparator (5) being half as fast as the clock signal of the comparator (5).

9. Voltage regulating system (1) according to one of claims 1 to 8, characterized in that A capacitor (16) is arranged after the first switch (3) and the second switch (4), which capacitor maintains the gate voltage (V G ) of the semiconductor switch (2).

10. Voltage regulating system (1) according to one of claims 1 to 9, characterized in that ​ 11. Method for operating a voltage regulating system (1) according to one of claims 1 to 10, characterized in that The first supply current (14) of the first switch (3) and the second supply current (15) of the second switch (4) are boosted to a maximum value for regulating the gate voltage (V G ).

12. The method of claim 11, wherein, reducing the first supply current (14) of the first switch (3) and the second supply current (15) of the second switch (4) to a minimum value for regulating the gate voltage (V G ).

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