A low-power pulse neural network computing circuit

Abstract

This invention provides a low-power spiking neural network computing circuit, including a pulse data encoding module, an input buffer and routing module, a multiply-accumulate calculation array, an output buffer and routing module, a neuron array, a winner-take-all calculation module, and a calculation iteration control module. When the calculation type is a general calculation mode, the pulse data encoding module and the neuron array are turned off. When the calculation type is a neuron calculation mode, the pulse data encoding module and the neuron array are turned on. The winner-take-all calculation module controls the multiply-accumulate calculation array and the neuron array to operate in sparse mode based on the state of the output pulses of the neuron array, turning off some calculation units and some neurons. This invention reduces overall power consumption by optimizing the underlying circuit structure, using a simplified neuron circuit as the core of computation, resulting in low circuit overhead; and utilizes the winner-take-all rule to achieve sparse computation, resulting in low dynamic power consumption.

Description

Technical Field

[0001] This invention relates to the field of deep neural network technology, and more specifically, to a low-power spiking neural network computing circuit. Background Technology

[0002] With the widespread application of deep neural network models in various digital devices, the demand for computing power is increasing dramatically. Dedicated processors designed to meet this demand (such as GPGPUs, TPUs, and NPUs) offer powerful performance and have become the cornerstone of computing power for neural network applications. However, behind the impressive performance of these processors lies an increasingly serious power consumption problem. High power consumption not only limits the improvement of computing density, leading to the "power wall," but also brings challenges in heat dissipation and short device battery life. Therefore, it is necessary to research new processor design technologies to improve processor energy efficiency and overcome the limitations of the "power wall."

[0003] Neuromorphic computing is a novel computing paradigm inspired by the biological brain, aiming to process complex information with extremely low power consumption by simulating the brain's structure and working principles. Spiking neural networks (SNNs) are a typical model of this paradigm. Unlike traditional artificial neural networks, SNNs use discrete pulse signals for communication and computation. Their most significant characteristic is event-driven computation: neurons are only activated and produce output pulses when they receive an input pulse and the membrane potential reaches a threshold. This mechanism naturally leads to sparse and asynchronous computation—neurons remain resting most of the time, and computation occurs only between necessary moments and necessary neurons. It is precisely this highly sparse activity characteristic that fundamentally avoids the energy consumption of continuous large-scale parallel computation in traditional processors, enabling dedicated SNN processors to achieve orders-of-magnitude improvements in energy efficiency compared to traditional neural network processor architectures when processing spatiotemporal data tasks such as vision and speech.

[0004] However, existing SNN processor patents focus on the implementation of spiking neural network functions, such as implementing or accelerating complex neuron models and event-driven mechanisms in SNNs. Significant shortcomings remain regarding the crucial low-power design, especially in the design of the underlying neuron structure. No solutions similar to this application have been found that reduce power consumption by optimizing the neuron structure and designing specific learning rules.

[0005] Current spiking neural network (SNN) processor patents have the following drawbacks: First, hardware efficiency is sacrificed in pursuit of biological rationality or training convenience. Specifically, while complex neuron models (such as IZH) can accurately simulate neural dynamics, their hardware implementation requires a large number of computational and storage units, resulting in high static power consumption and resource overhead. Second, the mechanisms for handling the spatiotemporal sparsity of pulse sequences are inefficient; a large number of invalid pulses and synapses still participate in computation, failing to fully utilize sparsity to reduce energy consumption. Third, existing spiking neural network circuits often rely on peripheral devices such as FPGAs, further introducing additional power consumption. These underlying structural problems collectively limit the full potential of SNN processors' energy efficiency, especially when dealing with large-scale SNNs. Summary of the Invention

[0006] This invention addresses the technical problems existing in the prior art by providing a low-power spiking neural network computing circuit, overcoming the shortcomings of existing spiking neural network models, such as high hardware overhead and low power consumption.

[0007] This invention provides a low-power spiking neural network computing circuit, including a pulse data encoding module, an input buffer and routing module, a multiply-accumulate calculation array, an output buffer and routing module, a neuron array, a winner-take-all calculation module, and a calculation iteration control module;

[0008] The computation iteration control module receives CPU configuration information, which includes the computation type.

[0009] When the calculation type is general calculation mode, the pulse data encoding module and the neuron array are turned off; general data is read from the input buffer and routing module, input into the multiply-accumulate calculation array for calculation, and the calculation result is stored in the output buffer and routing module; the output buffer and routing module is controlled to write the calculation result back to the general data storage module.

[0010] When the computation type is neuron computation mode, the pulse data encoding module and the neuron array are activated, and the multiply-accumulate computation array is set to sparse computation mode. Neuron data is obtained from the neuron data storage module. The neuron data is encoded into pulse data by the pulse data encoding module. The pulse data is transmitted to the multiply-accumulate computation array for computation through the input buffer and routing module. The computation result is transmitted to the neuron array as the neuron input current through the output buffer and routing module for operation. The output pulse of the neuron array is transmitted to the winner-take-all computation module. The winner-take-all computation module controls the multiply-accumulate computation array and the neuron array to work in sparse mode according to the state of the output pulse of the neuron array.

[0011] This invention provides a low-power spiking neural network computing circuit, comprising a pulse data encoding module, an input buffer and routing module, a multiply-accumulate calculation array, an output buffer and routing module, a neuron array, a winner-take-all calculation module, and a calculation iteration control module. When the calculation type is a general calculation mode, the pulse data encoding module and the neuron array are turned off. When the calculation type is a neuron calculation mode, the pulse data encoding module and the neuron array are turned on. The winner-take-all calculation module controls the multiply-accumulate calculation array and the neuron array to operate in sparse mode based on the state of the output pulses of the neuron array, turning off some calculation units and some neurons. This invention reduces overall power consumption by optimizing the underlying circuit structure, using a simplified neuron circuit as the core of computation, resulting in low circuit overhead; and utilizes the winner-take-all rule to achieve sparse computation, resulting in low dynamic power consumption. Attached Figure Description

[0012] Figure 1 The diagram shows the overall structure of a low-power spiking neural network computing circuit according to an embodiment of the present invention.

[0013] Figure 2 The diagram shows the overall structure of the computing core in a low-power spiking neural network computing circuit according to an embodiment of the present invention.

[0014] Figure 3 This is a schematic diagram of the state transition of the computational iteration control module according to an embodiment of the present invention;

[0015] Figure 4(a) is a schematic diagram of the pipeline operation mode of the general computing model;

[0016] Figure 4(b) is a schematic diagram of the pipeline operation mode of the neuron computing model;

[0017] Figure 5 A diagram of the internal electrical structure of each neuron;

[0018] Figure 6 Internal circuit diagram of the winner-takes-all calculation module;

[0019] Figure 7 This is a schematic diagram of the state transitions of the WTA controller;

[0020] Figure 8 This is an overall flowchart of a low-power spiking neural network computing circuit provided in one embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0022] This invention provides a low-power spiking neural network computing circuit based on the winner-takes-all rule, which solves the problems of high hardware overhead, insufficient utilization efficiency of sparse computing and high cost of peripheral devices in existing neuron implementations, and effectively improves the energy efficiency of spiking neural network circuits.

[0023] See Figure 1 This diagram illustrates the overall structure of a spiking neural network (SNN) computing circuit according to an embodiment of the present invention. The core of the SNN computing circuit consists of a multiply-accumulate array, a neuron array, and a winner-takes-all computing module. The computing core interacts with the CPU and memory management module via an internal data bus and control bus, using Direct Data Transfer (DMA) to move data between the computing core and the CPU. Data storage is divided into two types: the first is a general-purpose data storage module, used to store the following types of data: 1. CPU runtime data; 2. Data in the SNN that is not directly related to the spiking neurons, such as feature extraction data and linear transformation data. The second type is a neuron data storage module, used to store information related to the spiking neurons, such as neuron model parameters and neuron connection matrices. In addition, the CPU is connected to an external data bus via an AXI master interface and an AXI slave interface.

[0024] The core structure diagram of the spiking neural network computing circuit designed in this invention is as follows: Figure 2 As shown,

[0025] Figure 2A low-power spiking neural network computing circuit is provided, comprising a pulse data encoding module, an input buffer and routing module, a multiply-accumulate calculation array, an output buffer and routing module, a neuron array, a winner-take-all calculation module, and a calculation iteration control module. The calculation iteration control module is connected to the CPU via a control bus and is connected to the pulse data encoding module, the input buffer and routing module, the multiply-accumulate calculation array, the output buffer and routing module, and the neuron array. The winner-take-all calculation module is connected to both the multiply-accumulate calculation array and the neuron array. The pulse data encoding module, the input buffer and routing module, and the output buffer and routing module are connected to a storage management module via an internal data bus. The storage management module is connected to both the general data storage module and the neuron data storage module. The neuron array and the winner-take-all calculation module are both connected to the internal data bus.

[0026] Its working principle is as follows: the CPU sends start and stop signals to the computation iteration control module via the control bus, while the operation control of the entire computing core is handled by the computation iteration control module. The computation iteration control module directly controls pulse data encoding, input / output buffer routing, and multiply-accumulate calculation array. The winner-takes-all computation module contains a separate control module.

[0027] The calculation iteration control module receives CPU configuration information via a control bus, and the configuration information includes the calculation type.

[0028] When the calculation type is general calculation mode, the pulse data encoding module and the neuron array are turned off; general data is read from the input buffer and routing module, input into the multiply-accumulate calculation array for calculation, and the calculation result is stored in the output buffer and routing module; the output buffer and routing module is controlled to write the calculation result back to the general data storage module.

[0029] When the computation type is neuron computation mode, the pulse data encoding module and the neuron array are activated, and the multiply-accumulate computation array is set to sparse computation mode. Neuron data is obtained from the neuron data storage module. The neuron data is encoded into pulse data by the pulse data encoding module. The pulse data is transmitted to the multiply-accumulate computation array for computation through the input buffer and routing module. The computation result is transmitted to the neuron array as the neuron input current through the output buffer and routing module for operation. The output pulse of the neuron array is transmitted to the winner-take-all computation module. The winner-take-all computation module controls the multiply-accumulate computation array and the neuron array to work in sparse mode according to the state of the output pulse of the neuron array.

[0030] like Figure 2As shown, the multiply-accumulate computation array includes multiple PE computation units. These PE computation units perform calculations on general data or neuron data. The calculation results for general data are written back to the general data storage module via an output buffer and routing module, or the calculation results for neuron data are transmitted as neuron input current to the neuron array for computation via the output buffer and routing module. Specifically, after the PE computation units in the multiply-accumulate computation array perform calculations on the neuron data, the calculation results are input to the corresponding neurons via the output buffer and routing module. In other words, there is a correspondence between the PE computation units in the multiply-accumulate computation array and the neurons in the neuron array.

[0031] in, Figure 2 The working principle is as follows: The pulse data encoding module encodes the input data into pulse signals for processing by the multiply-accumulate array. Besides processing pulse data, the multiply-accumulate array also has the capability to process non-pulse data; therefore, an input buffer and routing are designed to select between pulse and non-pulse data. The multiply-accumulate array consists of multiple PE computing units, and its output is sent to the output buffer and routing. The output routing has two directions: first, writing the data back to storage via the internal data bus (in general computing mode); second, transmitting the data as neuron input current to the neuron array (in neuron computing mode). The neuron array consists of neurons neuron0 to neuronN, and the output pulses of the neuron array are transmitted to the winner-take-all computing module. There is a feedback control path between the winner-take-all computing module, the neuron array, and the multiply-accumulate array. Both the neuron array and the winner-take-all computing module exchange data with storage via the internal data bus.

[0032] Among them, see Figure 3 This describes the state transition diagram of the computational iteration control module. The computational iteration control module comprises five states: initial state, configuration state, general computation mode, neuron computation mode, and data allocation state. The state transition process is as follows:

[0033] (1) When powered on, it is in the initial state S0. After receiving the CPU configuration data, it transitions to the configuration state S1.

[0034] (2) In configuration state S1, the CPU configuration information is parsed. The configuration information includes the calculation type, calculation event, and data address required for the calculation. The calculation iteration control will perform state transitions according to the calculation type in the configuration data.

[0035] (3) If the computation type is general computation, then jump to general computation mode S2. In general computation mode, the computation iteration control will shut down the pulse data encoding module and the neuron array, read the data from the input buffer, and after the multiply-accumulate array computation array completes the computation, control the output route to write the data back to the general data storage.

[0036] (4) If the computation type is neuron computation, then jump to neuron computation mode S3. In neuron computation mode, the computation iteration control will activate the pulse data encoding module and the neuron array, and set the multiply-accumulate computation array to sparse computation mode to match the input pulses. The data is encoded into pulses through pulse data encoding, and is transmitted to the multiply-accumulate computation array by the input route. After the computation is completed, the output route will use the output data as the neuron input current and transmit it to the neuron array.

[0037] (5) When the computation mode configuration of general computation mode S2 and neuron computation mode S3 is completed, it will enter the data allocation state S4. At this time, the computation iteration control module controls the allocation of data flow of routing and caching, and monitors the computation status. When all computations are completed, it will finally jump to the initial state S0.

[0038] Figures 4(a) and 4(b) illustrate the pipelined operation of the computing core architecture. Figure 4(a) shows the pipelined operation under the general computing model, and Figure 4(b) shows the pipelined operation under the neuronal computing model. Figure 4(a) and 4(b) As can be seen, general data and neuron data are read in batches from the general data storage module and the neuron data storage module, respectively, and then entered into the multiply-accumulate calculation array for calculation.

[0039] See Figure 5 This shows a diagram of the internal structure of a neuron array, based on... Figure 5 The neuron array includes multiple neurons, and each neuron includes a combined gating unit, a first register, a neuron computing unit, an addition circuit, and a threshold comparison and suppression circuit. The threshold comparison and suppression circuit includes a comparison unit and a suppression circuit.

[0040] The first register temporarily stores the neuron membrane voltage at time t. The clock segment of the first register is controlled by the combined gating unit, which reads the neuron membrane voltage from the first register. Send to the neuron computing unit;

[0041] The calculation result is read from the PE calculation unit in the multiply-accumulate calculation array as the neuron input current. Send to the neuron computing unit;

[0042] Neuron model parameters are read from the neuron data storage module via the internal data bus. Send to the neuron computing unit;

[0043] Based on neuronal membrane voltage Neuron input current and neuron model parameters The calculation is performed to obtain the result, and the result is then compared with the neuron membrane voltage through the addition circuit. Add them together and output the result. The addition result Input the threshold comparison and suppression circuit;

[0044] The comparison unit will compare the addition result. The result of the addition is compared with the voltage threshold Vth. If the voltage is greater than the voltage threshold Vth, then a neuron pulse is output; otherwise, no neuron pulse is output.

[0045] When the suppression circuit receives a lateral suppression signal, it suppresses the addition result. It is transferred to the first register.

[0046] See Figure 5 The combined gating unit includes an OR gate and a clock gating module. One input of the OR gate is connected to a lateral suppression signal, and the other input is connected to a resting state signal. The output of the OR gate is connected to the input of the clock gating module, and the output of the clock gating module is connected to the first register. When either the lateral suppression signal or the resting state signal is present, the OR gate outputs a suppression signal, turning off the clock, thus deactivating the neuron. The lateral suppression signal is input to the winner-takes-all calculation module, and the resting state signal is input to the calculation iteration control module.

[0047] Neuron membrane voltage at current moment The current neuron membrane voltage is temporarily stored in the first register composed of D flip-flops, and then read from the first register. The calculation result of the PE calculation unit in the multiply-accumulate calculation array is used as the input current. The parameters are input into the neuron and read from the neuron data storage module via the internal data bus. The input is then fed into the neurons.

[0048] The neuronal computational unit in a neuron calculates based on the neuronal membrane voltage at the current moment. Input current and neuron model parameters , to perform calculations.

[0049] The neuron module is based on the following neuron dynamics model:

[0050] ;

[0051] In the equation This refers to the neuron membrane voltage. For neuron model parameters, Input current to neurons, Let represent the network runtime. This equation is a continuous differential equation, and to implement it on digital circuits, it needs to be discretized. Discretization using the Euler method yields the following expression:

[0052] ;

[0053] In the formula Setting the discretized simulation time interval to 1 simplifies the expression to:

[0054] .

[0055] Among them, the neuron computational unit operation is obtained Then the calculation result and The input addition circuit performs addition to obtain the neuron's modulus voltage at time t+1. .

[0056] The neuron computational unit contains a built-in function f, which will... The function is split into n function logic segments , ,...,..., To facilitate timing optimization, the initial value of each logic segment is... initial value Correspondingly, V(t) is also registered through n D flip-flops (second registers), each initially set to 0, and the computation cycle number is T1. The output of the neuron computation unit is input to the adder circuit (computation cycle number T2), and the output of the adder circuit is... , The signal is compared with a threshold Vth. If the signal is greater than Vth, a neuron pulse (i.e., the winning neuron) is output. It is also connected to the inhibition circuit, so if the neuron is subjected to lateral inhibition, then It will not be passed to the first register; otherwise, the neuron modulus voltage in the first register will be updated to... The number of calculation cycles for this process is T3. T1+T2+T3 corresponds to dt of the model, meaning the above process is completed within one dt.

[0057] See Figure 6 The diagram shows the internal structure of the winner-take-all computation module, which mainly includes a neuron spiking management unit, a WTA control unit, a WTA buffer, and a lateral inhibition vector generation circuit.

[0058] The neuron pulse management unit receives neuron pulses output by N+1 neurons in the neuron array, and constructs an N+1-dimensional neuron pulse information vector Vs based on all neuron pulses. Each bit in the neuron pulse information vector Vs corresponds one-to-one with each neuron. A value of 1 indicates that the neuron has generated a pulse, and a value of 0 indicates that the neuron has not generated a pulse. The neuron pulse information vector Vs is input to the WTA control unit.

[0059] The WTA control unit obtains the tag ID of the winning neuron from the neuron pulse information vector Vs, and the tag ID of the winning neuron is input into the WTA buffer. The neuron with a bit of 1 in the neuron pulse information vector Vs is the winning neuron.

[0060] The WTA control unit reads the connection information of the neuron corresponding to the tag ID from the neuron connection matrix stored in the WTA buffer according to the tag ID of the winning neuron, and inputs it into the lateral inhibition vector generation circuit to generate an N+1 dimensional lateral inhibition vector VI. In the lateral inhibition vector VI, if the bit value is 1, it means that the neuron corresponding to the bit will be inhibited; otherwise, the corresponding neuron will not be inhibited.

[0061] The lateral inhibition vector VI is input to the combined gating unit of each neuron and to each PE computation unit of the multiply-accumulate computation array.

[0062] Specifically, such as Figure 6 As shown, neurons nueron0 to neuronN are connected to the neuronal impulse management unit, and all neuronal impulses constitute an N+1 dimensional neuronal impulse information vector Vs: Each bit in this vector corresponds one-to-one with a neuron. A value of 1 indicates that the neuron has generated a pulse (i.e., the winning neuron), and a value of 0 indicates that the neuron has not generated a pulse. This vector is input into the WTA Controller (Winner-Take-All Control Unit). The WTA Controller obtains the tag ID (0, 1, 2…N) of the winning neuron from the neuron pulse information vector Vs. The tag is input into the WTA Buffer (Winner-Take-All Buffer). The WTA Buffer stores the neuron connection matrix, which is a symmetric matrix. This indicates whether there is a connection between the i-th neuron (0,1,…N) and the j-th neuron (0,1,…N). It is directional, with a value of 1 (connected) or 0 (no connected). The elements on the diagonal of the matrix... (i=j) indicates whether the neuron itself has a connection pathway, with a value of 1 (connected) or 0 (unconnected). The WTA controller reads the corresponding row of the connection matrix through the label ID and inputs it into the lateral inhibition vector generation circuit. The winning neuron will inhibit the neurons it is connected to.

[0063] The lateral inhibition vector generation circuit includes an OR gate, two D flip-flops, and a clock gating unit. Since multiple neurons may win, multiple readouts are required. Each readout row is ORed with the previous result after passing through the OR gate, ultimately yielding an N+1 dimensional lateral inhibition vector VI. In the lateral inhibition vector VI, each bit value of 1 indicates that the corresponding neuron will be inhibited; otherwise, it will not be inhibited. Finally, the lateral inhibition vector is input to the neuron impulse management unit (NEM) via the WTA controller. The NEM sends the lateral inhibition vector to each neuron to shut it down. Similarly, the lateral inhibition vector is also input to the multiply-accumulate computation array, corresponding to the shutdown of the gating clock of the computation unit.

[0064] See Figure 7 This describes the state transitions of the WTA controller. The WTA controller has five states: initial state, impulse information vector resolution, connection matrix reading, suppression vector generation, and suppression vector transmission. The state transition process is as follows:

[0065] (1) When powered on, the initial state is S0. If no winning neuron is generated, the state remains in the initial state. If a winning neuron is generated, the state enters S1.

[0066] (2) In the pulse information vector parsing state S1, the pulse information vector data is converted into the number of winning neurons and the label.

[0067] (3) In the connection matrix reading state S2, the WTA controller provides the tag data to the WTA buffer, and the row corresponding to the tag will be read out and input to the lateral suppression vector generation circuit.

[0068] (4) In the lateral inhibition vector generation state S3, the WTA controller opens the lateral inhibition circuit through the clock gating unit to generate the lateral inhibition vector of a winning neuron. Then, the WTA controller re-enters state S2 and reads the connection information of the remaining winning neurons. This continues until the connection information of all winning neurons has been read.

[0069] (5) After the inhibition vector is generated, the inhibition vector is sent. The lateral inhibition vector is input into the neuron array and the multiply-accumulate calculation array through the neuron pulse management, and the gate clock of the corresponding module is turned off.

[0070] See Figure 8 To further describe the low-power spiking neural network computing circuit based on the winner-takes-all rule of the present invention, the complete operation flow of the entire computing device will be given below. This workflow mainly includes the following steps:

[0071] 801: Build and train a spiking neural network model in software, and then convert it into a data stream file that can be deployed to a spiking neural network computing circuit.

[0072] 802: Download the data stream file of the spiking neural network to the device's storage.

[0073] 803: Parse the spiking neural network data stream file to generate neuron data, including neuron model parameters and neuron connection matrix.

[0074] 804: Based on the spiking neural network data stream file, generate the instructions and configuration data required for the spiking neural network computing circuit to complete inference.

[0075] 805: Power on and start the spiking neural network computing core.

[0076] 806: Input the task data into the spiking neural network computing circuit. The task data is preprocessed image data or audio data.

[0077] 807: Read network layer data from a spiking neural network data stream file.

[0078] 808: Parse network layer data, including network layer computation type, weight parameters, and hyperparameters.

[0079] 809, 811, 813: This network layer is directly connected to the spiking neurons and completes the calculations corresponding to the neuron's computational pattern, as shown in Figure 4(a).

[0080] 810, 812, 814, 815, 816: This network layer is directly connected to the spiking neurons and completes the calculations corresponding to the neuron's computational pattern, as shown in Figure 4(b).

[0081] 817: Complete network layer data storage (general data storage or neuron storage).

[0082] 818: Determine whether the final layer output of the model has been completed. If not, continue reading the data of the next network layer, i.e., 807; otherwise, proceed to 819.

[0083] 819: Retrieve the network layer inference results from the corresponding storage location.

[0084] 820: Perform data validation and display the results on the software.

[0085] This invention provides a low-power spiking neural network computing circuit. The low-power advantages of this device are reflected in three aspects: Firstly, in terms of system architecture, it is implemented as a processor core, tightly coupled with the bus and memory, eliminating the additional overhead of peripheral devices and improving the upper limit of energy efficiency. Secondly, in terms of computing units, it adopts a simplified neuron model and circuit, resulting in a simple structure, low hardware overhead, and the ability to reduce dynamic power consumption using gated clock technology. Thirdly, in terms of the operating mechanism, the key winner-takes-all rule is hardware-based, which adaptively generates suppression signals based on the neuron spiking output, and then shuts down the large-scale multiply-accumulate array and neuron array through a feedback loop, fully utilizing the spatiotemporal sparsity of the spiking to drastically reduce dynamic power consumption.

[0086] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0087] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0088] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0089] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0090] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0091] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0092] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A low-power spiking neural network computing circuit, characterized in that, It includes a pulse data encoding module, an input buffer and routing module, a multiply-accumulate calculation array, an output buffer and routing module, a neuron array, a winner-take-all calculation module, and a calculation iteration control module; The computation iteration control module receives CPU configuration information, which includes the computation type. When the calculation type is general calculation mode, the pulse data encoding module and the neuron array are turned off; general data is read from the input buffer and routing module, input into the multiply-accumulate calculation array for calculation, and the calculation result is stored in the output buffer and routing module; the output buffer and routing module is controlled to write the calculation result back to the general data storage module. When the computation type is neuron computation mode, the pulse data encoding module and the neuron array are turned on, and the multiply-accumulate computation array is set to sparse computation mode. Neuron data is obtained from the neuron data storage module. The neuron data is encoded into pulse data by the pulse data encoding module. The pulse data is transmitted to the multiply-accumulate calculation array for calculation through the input buffer and routing module. The calculation result is transmitted to the neuron array as the neuron input current through the output buffer and routing module for operation. The output pulse of the neuron array is transmitted to the winner-take-all calculation module. The winner-take-all calculation module controls the multiply-accumulate calculation array and the neuron array to work in sparse mode according to the state of the output pulse of the neuron array.

2. The low-power spiking neural network computing circuit according to claim 1, characterized in that, The computational iteration control module is connected to the CPU via a control bus. The computational iteration control module is connected to the pulse data encoding module, the input buffer and routing module, the multiply-accumulate calculation array, the output buffer and routing module, and the neuron array, respectively. The winner-takes-all calculation module is connected to the multiply-accumulate calculation array and the neuron array, respectively. The pulse data encoding module, the input buffer and routing module, and the output buffer and routing module are connected to the storage management module via an internal data bus. The storage management module is connected to the general data storage module and the neuron data storage module, respectively. The neuron array and the winner-takes-all calculation module are both connected to the internal data bus.

3. The low-power spiking neural network computing circuit according to claim 1, characterized in that, The general data includes CPU running data and data that are not directly related to the spiking neurons in the neuron array; the neuron data includes information associated with the spiking neurons, including at least neuron model parameters and neuron connection matrices.

4. The low-power spiking neural network computing circuit according to claim 1, characterized in that, The multiply-accumulate calculation array includes multiple PE calculation units. The multiple PE calculation units perform calculations on the general data or the neuron data, and write the calculation results of the general data back to the general data storage module through the output buffer and routing module, or transmit the calculation results of the neuron data as neuron input current to the neuron array for operation through the output buffer and routing module.

5. The low-power spiking neural network computing circuit according to claim 1, characterized in that, The neuron array includes multiple neurons, and each neuron includes a combined gating unit, a first register, a neuron computing unit, an addition circuit, and a threshold comparison and suppression circuit, wherein the threshold comparison and suppression circuit includes a comparison unit and a suppression circuit. The first register temporarily stores the neuron membrane voltage at time t. The clock segment of the first register is controlled by the combined gating unit, which reads the neuron membrane voltage from the first register. Send to the neuron computing unit; The calculation result is read from the PE calculation unit in the multiply-accumulate calculation array as the neuron input current. Send to the neuron computing unit; Neuron model parameters are read from the neuron data storage module via the internal data bus. Send to the neuron computing unit; The neuron computing unit is based on the neuron membrane voltage. Neuron input current and neuron model parameters The calculation is performed to obtain the result, and the result is then compared with the neuron membrane voltage through the addition circuit. Add them together and output the result. The addition result Input the threshold comparison and suppression circuit; The comparison unit will compare the addition result. The result of the addition is compared with the voltage threshold Vth. If the voltage exceeds the threshold voltage Vth, then a neuron pulse is output. Otherwise, no neuron pulses are output; When the suppression circuit receives a lateral suppression signal, it suppresses the addition result. It is transferred to the first register.

6. The low-power spiking neural network computing circuit according to claim 5, characterized in that, The combined gating unit includes an OR gate and a clock gating module. One input of the OR gate is connected to a lateral suppression signal, and the other input is connected to a rest state signal. The output of the OR gate is connected to the input of the clock gating module, and the output of the clock gating module is connected to the first register.

7. The low-power spiking neural network computing circuit according to claim 5, characterized in that, The built-in neuron computing unit The function will... The function is split into n function logic segments , ,...,..., And n second registers, where n is a positive integer, and the initial value of each function logic segment is... initial value , It is stored in n second registers, where the initial value of each second register is 0; The f function operates on neuron data based on the following neuron dynamics model: ； in, This refers to the neuron membrane voltage. For neuron model parameters, The input current to the neuron is the calculation result of the multiply-accumulate calculation array. Network uptime; The addition circuit combines the calculation result with the neuron membrane voltage. Add them together and output the result. ,include: 。 8. The low-power spiking neural network computing circuit according to claim 5, characterized in that, The winner-take-all calculation module includes a neuron spiking management unit, a WTA control unit, a WTA buffer, and a lateral inhibition vector generation circuit; The neuron pulse management unit receives neuron pulses output by N+1 neurons in the neuron array, and constructs an N+1-dimensional neuron pulse information vector Vs based on all neuron pulses. Each bit in the neuron pulse information vector Vs corresponds one-to-one with each neuron. A value of 1 indicates that the neuron has generated a pulse, and a value of 0 indicates that the neuron has not generated a pulse. The neuron pulse information vector Vs is input to the WTA control unit. The WTA control unit obtains the tag ID of the winning neuron from the neuron pulse information vector Vs, and the tag ID of the winning neuron is input into the WTA buffer. The neuron with a bit of 1 in the neuron pulse information vector Vs is the winning neuron. The WTA control unit reads the connection information of the neuron corresponding to the tag ID from the neuron connection matrix stored in the WTA buffer according to the tag ID of the winning neuron, and inputs it into the lateral inhibition vector generation circuit to generate an N+1 dimensional lateral inhibition vector VI. In the lateral inhibition vector VI, if the bit value is 1, it means that the neuron corresponding to the bit will be inhibited; otherwise, the corresponding neuron will not be inhibited. The lateral inhibition vector VI is input to the combined gating unit of each neuron and to each PE computation unit of the multiply-accumulate computation array.

9. The low-power spiking neural network computing circuit according to claim 8, characterized in that, Elements in the neuron connection matrix The value indicates whether there is a connection between the i-th neuron and the j-th neuron. A value of 1 indicates a connection, and a value of 0 indicates no connection. The diagonal elements in the neuron connection matrix indicate whether the neuron itself has a connection path. A value of 1 indicates that the neuron itself has a connection path, and a value of 0 indicates that the neuron itself has no connection path. i, j = 0, 1, 2, ..., N.

10. The low-power spiking neural network computing circuit according to claim 9, characterized in that, The WTA control unit reads the connection information of the neuron corresponding to the label ID from the neuron connection matrix stored in the WTA buffer, based on the label ID of the winning neuron, and inputs it into the lateral inhibition vector generation circuit to generate an N+1 dimensional lateral inhibition vector VI, including: The WTA control unit reads the row corresponding to the winning neuron label ID in the neuron connection matrix each time, and performs an OR operation again on the row read each time and the result of the previous OR operation to obtain an N+1 dimensional lateral inhibition vector VI.

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