An LED chip defect detection method, device and medium based on artificial intelligence

Abstract

The application discloses an LED chip defect detection method and device based on artificial intelligence, and a medium, relates to the technical field of semiconductor manufacturing detection, and comprises the following steps: calculating the time window of a calibration wafer at each detection station according to a calibration configuration file, combining array parameters to divide a grid, generating a multimodal trigger plan and a chip identification corresponding relationship, correcting, registering, cropping and normalizing multimodal original data, and combining the multimodal original data into single-chip multimodal data according to the chip identification corresponding relationship; inputting the single-chip multimodal data into an artificial intelligence defect judgment model, generating an LED chip defect category and grading result through feature extraction and feature fusion; and realizing high-precision alignment of multimodal detection data in the physical space and time dimension by constructing a unified mapping relationship of images, electricity and space-time positions, improving the reliability of defect identification and accurately removing defective products.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing detection, and in particular to an LED chip defect detection method, device and medium based on artificial intelligence. BACKGROUND

[0002] In recent years, with the promotion of high-density integration and miniaturization trend, higher requirements are put forward for detection accuracy, efficiency and multi-dimensional information fusion capability. The traditional LED chip defect detection method mainly relies on single modal visual imaging technology, such as template matching or threshold segmentation algorithm based on bright field or dark field optical image, supplemented by simple electrical parameter sampling inspection. Image acquisition is usually completed in a fixed station. With the improvement of industrial camera resolution and optimization of image processing algorithm, some systems introduce luminescence images (such as EL or PL imaging) to assist in identifying internal crystal defects or poor contact problems.

[0003] Although some advanced devices try to integrate optical and electrical detection means, there are still significant limitations in actual application. Since the calibration wafer is in a continuous motion state in the detection pipeline, the trigger timing of each sensor (such as high-speed camera, current probe, etc.) is not accurately coupled with the position of the calibration wafer. Therefore, misalignment of multi-modal data in spatial coordinates or time stamps is easily caused, especially in high-throughput production lines. Microsecond-level time deviation can cause pixel-level spatial deviation, so that multi-modal features of the same chip cannot be effectively associated, which seriously restricts the recognition ability of artificial intelligence models for complex defects (such as micro-cracks accompanied by local leakage). SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides an LED chip defect detection method based on artificial intelligence to solve the problem of feature misalignment caused by multi-modal detection data out of synchronization in time and space, which affects the defect recognition accuracy.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In the first aspect, the present application provides an LED chip defect detection method based on artificial intelligence, which comprises:

[0008] The host computer loads the LED chip layout and array parameters, collects calibration images and electrical calibration data on the calibration wafer, and calculates camera parameters and time position parameters to generate a calibration configuration file.

[0009] Calculate the time window of the calibration wafer at each detection station according to the calibration configuration file, and divide the grid in combination with the array parameters to generate a multi-modal trigger plan and a chip identification corresponding relationship;

[0010] According to the multi-modal trigger plan, collect appearance images, light-emitting images and current-voltage data, and organize them into multi-modal raw data according to the chip identification corresponding relationship;

[0011] Correct, register, crop and normalize the multi-modal raw data, and combine them into single-chip multi-modal data according to the chip identification corresponding relationship;

[0012] Input the single-chip multi-modal data into the artificial intelligence defect judgment model, generate LED chip defect categories and grading results through feature extraction and feature fusion;

[0013] Summarize the LED chip defect categories and grading results with the time position parameters to form a grading result table, and control the sorting equipment to sort out the scrap chips and degraded chips at the corresponding positions according to the grading result table, to generate an LED chip defect detection and sorting result table.

[0014] As a preferred scheme of the LED chip defect detection method based on artificial intelligence, the specific steps of generating the calibration configuration file are as follows,

[0015] Load the LED chip layout and array parameters to set the running speed of the conveying mechanism and the position of the detection station, collect appearance calibration images, light-emitting calibration images and electrical calibration data, and record the encoder count;

[0016] According to the appearance calibration images and the light-emitting calibration images, calculate the intrinsic parameters, extrinsic parameters and geometric distortion parameters of each imaging camera, and establish the conversion relationship between the image coordinates and the physical coordinates of the calibration wafer;

[0017] According to the electrical calibration data and the encoder count, establish the corresponding relationship between the electrical test channel and the chip position, and the time and the position of the calibration wafer, output the camera parameters and the time position parameters; organize and store the camera parameters and the time position parameters, and generate the calibration configuration file.

[0018] As a preferred scheme of the LED chip defect detection method based on artificial intelligence, the specific steps of generating the multi-modal trigger plan and the chip identification corresponding relationship are as follows,

[0019] Load the calibration configuration file to read the time position parameters, and obtain the size of the calibration wafer and the position of each detection station;

[0020] According to the LED chip array parameters, calculate the center coordinates of the LED chips in the calibration wafer coordinate system, and divide the chip array grid on the calibration wafer which is consistent with the actual chip arrangement;

[0021] According to the time position parameter and the position of each detection station, the start and end time of the corresponding chip array grid entering the appearance imaging station, the light emission imaging station and the electrical test station in sequence is calculated, and the start and end time is taken as the time window of the calibration wafer in each detection station;

[0022] A unique chip identification is allocated to each chip array grid, and the chip identification is associated with the corresponding physical coordinates and the time window of each detection station, and appearance exposure parameters, light emission excitation parameters and electrical test parameters are set for each detection station position to generate a multi-modal triggering plan;

[0023] The multi-modal triggering plan and the corresponding relationship between the chip identification and the physical coordinates are sorted and stored in the upper computer to form a multi-modal triggering plan and chip identification corresponding relationship.

[0024] As a preferred scheme of the LED chip defect detection method based on artificial intelligence, the multi-modal raw data is sorted according to the chip identification corresponding relationship, and the specific steps are as follows,

[0025] The multi-modal triggering plan and the chip identification corresponding relationship are loaded, and the triggering time window related to the time position parameter is sent to the programmable logic controller;

[0026] The programmable logic controller monitors the encoder count in real time according to the time position parameter, sends the acquisition triggering signal to the appearance imaging station and the light emission imaging station, and performs current-voltage test to obtain the appearance image, the light emission image and the corresponding current-voltage data;

[0027] According to the chip identification corresponding relationship and the acquisition time, the image information of the corresponding chip array grid in the appearance image and the light emission image is associated with the current-voltage data in the corresponding time window under the corresponding chip identification corresponding relationship, and is classified and sorted to form multi-modal raw data.

[0028] As a preferred scheme of the LED chip defect detection method based on artificial intelligence, the multi-modal raw data is sorted according to the chip identification corresponding relationship, and the specific steps are as follows,

[0029] The camera parameters, the time position parameters and the chip array grid information are obtained from the calibration configuration file and the multi-modal triggering plan, the appearance image and the light emission image are corrected for distortion, and the light emission image is registered to the coordinate system of the appearance image by using the conversion relationship between the image coordinates and the physical coordinates of the calibration wafer;

[0030] According to the center coordinates of each chip in the chip array grid and the grid size, a chip appearance image and a chip light emission image are obtained in the corrected appearance image and the light emission image, and size normalization and brightness normalization processing are performed to obtain a standardized chip appearance image and a standardized chip light emission image;

[0031] The current-voltage data in the multi-modal raw data is denoised, interpolated and resampled according to the chip identification and the collection time, the current-voltage data of different lengths are converted into one-dimensional vectors, and amplitude normalization is performed, and an electrical feature vector is output;

[0032] The standardized chip appearance image, the standardized chip light emission image and the electrical feature vector are combined according to the chip identification correspondence to form single-chip multi-modal data.

[0033] As a preferred scheme of the LED chip defect detection method based on artificial intelligence, the steps of generating the LED chip defect category and the grading result are as follows,

[0034] The single-chip multi-modal data is input into an artificial intelligence defect judgment model, and appearance feature vectors, light emission feature vectors and electrical high-dimensional feature vectors are extracted through appearance feature extraction sub-networks, light emission feature extraction sub-networks and electrical feature extraction sub-networks respectively, and splicing and nonlinear transformation are performed to obtain a fusion feature representation;

[0035] According to the fusion feature representation, the probability distribution of the LED chip in the defect category is calculated through a classification sub-network, and the defect category with the maximum probability is selected as the LED chip defect category;

[0036] The grading level corresponding to the LED chip is output through a grading sub-network according to the fusion feature representation, and is arranged according to the chip identification to form a grading result.

[0037] As a preferred scheme of the LED chip defect detection method based on artificial intelligence, the steps of forming the grading result table are as follows,

[0038] The LED chip defect category and the grading result, the time position parameters and the calibration wafer size information stored in the calibration configuration file are read; the time point of the LED chip passing through the sorting position and the trajectory coordinates are calculated according to the time position parameters and the position relationship of each detection station and the sorting station in the conveying direction;

[0039] The time point and the trajectory coordinates are associated with the corresponding chip identification, the calibration wafer physical coordinates, the LED chip defect category and the grading result to generate a grading result table.

[0040] As a preferred scheme of the LED chip defect detection method based on artificial intelligence, the steps of generating the LED chip defect detection and sorting result table are as follows,

[0041] The grading result corresponding to the chip identifier in the grading result table is combined with the time position parameter in the calibration configuration file to calculate the time point at which each chip identifier passes through the sorting station and the position of the conveying path, and a sorting control instruction sequence is generated.

[0042] According to the sorting control instruction sequence, the sorting mechanism is triggered to act at the corresponding time point, and the chips marked as scrap and degraded chips are separated from the conveying path of qualified chips and introduced into the corresponding collection path. The grading result table is compared and counted with the sorting execution record to obtain the LED chip defect detection and sorting result table.

[0043] In a second aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and wherein the computer program, when executed by the processor, implements any step of the LED chip defect detection method based on artificial intelligence according to the first aspect of the present application.

[0044] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any step of the LED chip defect detection method based on artificial intelligence according to the first aspect of the present application.

[0045] The present application has the following beneficial effects: by constructing a unified mapping relationship of images, electricity and space-time positions, high-precision alignment of multi-modal detection data in physical space and time dimension is achieved, and the reliability of defect identification is improved; the artificial intelligence model can efficiently fuse appearance, light emission and electrical characteristics, and high-accuracy defect classification and grading are supported, and the sorting equipment can accurately remove defective products, achieving the comprehensive beneficial effects of high detection accuracy, low misjudgment rate, high efficiency and suitability for large-scale production. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0047] Fig. 1 The flowchart of the LED chip defect detection method based on artificial intelligence.

[0048] Fig. 2 The flowchart of the calibration configuration and single-chip multi-modal data acquisition.

[0049] Fig. 3 A structural diagram of an artificial intelligence defect judgment model.

[0050] Fig. 4 A flowchart for generating a test result. DETAILED DESCRIPTION

[0051] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0052] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without the specific details given herein, that the present application can be practiced with other than the described embodiments, and that variations from the particular embodiments described herein can be made and still be within the scope of the present application.

[0053] Secondly, the "one embodiment" or "embodiment" referred to herein means that the specific features, structures or characteristics can be included in at least one implementation of the present application. The "in one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments.

[0054] Reference Figs. 1-4 For one embodiment of the present application, the embodiment provides an LED chip defect detection method based on artificial intelligence, comprising the following steps:

[0055] S1. Load the LED chip layout and array parameters through the host computer, collect calibration images and electrical calibration data on the calibration wafer, and calculate camera parameters and time position parameters to generate a calibration configuration file.

[0056] S1.1. Set the running speed of the conveying mechanism and the detection station position by loading the LED chip layout and array parameters, collect appearance calibration images, light-emitting calibration images and electrical calibration data, and record the encoder count.

[0057] Specifically, the LED chip layout and array parameters are loaded in the host computer, the running speed of the conveying mechanism and the triggering positions of the detection stations are calculated according to the arrangement interval of the LED chip array on the calibration wafer and the positions of the appearance imaging station, the light emitting imaging station and the electrical test station in the conveying direction, so that the calibration wafer passes through the appearance imaging station, the light emitting imaging station and the electrical test station in turn at a stable speed, the appearance calibration image acquisition, the light emitting calibration image acquisition and the electrical calibration data acquisition are triggered when the calibration wafer passes through the center positions of the stations, and the current encoder count is read synchronously at each acquisition triggering time, the encoder count is stored in association with the corresponding detection station position and acquisition time, and is used to form one-to-one correspondence records of the appearance calibration image, the light emitting calibration image, the electrical calibration data and the encoder count.

[0058] S1.2. Calculate the intrinsic parameters, extrinsic parameters and geometric distortion parameters of each imaging camera according to the appearance calibration image and the light emitting calibration image, and establish the conversion relationship between the image coordinates and the physical coordinates of the calibration wafer.

[0059] Specifically, the appearance calibration image and the light emitting calibration image are loaded, the feature point pixel coordinates corresponding to the known physical coordinates on the calibration wafer are obtained by using the corner detection or feature point extraction algorithm, the feature point pixel coordinates in the appearance calibration image are paired with the physical coordinates in the calibration wafer coordinate system, the camera calibration algorithm is called to solve the focal length, principal point position, rotation amount, translation amount and geometric distortion coefficient of the appearance imaging camera, the intrinsic parameters, extrinsic parameters and geometric distortion parameters of the appearance imaging camera are obtained, and the conversion relationship from the appearance image coordinates to the physical coordinates of the calibration wafer is constructed; in the same way, the feature point pixel coordinates in the light emitting calibration image are paired with the physical coordinates of the calibration wafer, the intrinsic parameters, extrinsic parameters and geometric distortion parameters of the light emitting imaging camera are solved, and the conversion relationship from the light emitting image coordinates to the physical coordinates of the calibration wafer is established.

[0060] S1.3. Establish the corresponding relationship between the electrical test channel and the chip position and the time and the calibration wafer position according to the electrical calibration data and the encoder count, output the camera parameters and the time position parameters; the camera parameters and the time position parameters are sorted and stored in association, and a calibration configuration file is generated.

[0061] Specifically, according to the electrical calibration data and the encoder count, each current-voltage response in the electrical calibration data is associated with a corresponding chip position on the calibration wafer to establish a corresponding relationship between the electrical test channel and the chip position, with the electrical test channel number as the index; the encoder count and the time information recorded during the electrical calibration process are used to calculate the corresponding relationship between the time and the position of the calibration wafer in the calibration wafer coordinate system, combined with the movement direction of the conveying mechanism and the physical coordinates of the calibration wafer, and the time-position parameters are sorted; after the calculation of the corresponding relationship between the electrical test channel and the chip position and the calculation of the time-position parameters are completed, the time-position parameters and the camera parameters are sorted and stored in the host computer according to a unified field order, and a calibration configuration file is generated.

[0062] It should be noted that the expression describing the relationship between the time and the position of the calibration wafer in the conveying direction is:

[0063] ;

[0064] wherein, represents the time of the calibration wafer reference point in the conveying direction, represents the reference time of the corresponding physical position, represents the running speed of the conveying mechanism, represents the current acquisition or trigger judgment time, represents the reference time of the position measurement.

[0065] S2. According to the calibration configuration file, the time window of the calibration wafer in each detection station is calculated, and the grid is divided in combination with the array parameters, to generate a multi-modal trigger plan and a chip identification corresponding relationship.

[0066] S2.1. Load the calibration configuration file to read the time-position parameters, and obtain the size of the calibration wafer and the positions of each detection station.

[0067] Specifically, the calibration configuration file is loaded in the host computer, the time-position parameters, the size of the calibration wafer and the positions of each detection station are read through the calibration configuration file, and the time-position parameters, the size of the calibration wafer and the positions of each detection station are corresponded to a unified calibration wafer coordinate system; the LED chip array parameters are loaded in the host computer, the number of rows and columns of LED chips, the row spacing and the column spacing are obtained through the LED chip array parameters, and a one-to-one correspondence is established between the number of rows and columns of LED chips, the row spacing and the column spacing and the size of the calibration wafer; after the reading and the corresponding relationship establishment of the time-position parameters, the size of the calibration wafer, the positions of each detection station and the number of rows and columns of LED chips, the row spacing and the column spacing are completed, the time-position parameters, the size of the calibration wafer, the positions of each detection station and the number of rows and columns of LED chips, the row spacing and the column spacing are uniformly stored in the host computer memory.

[0068] S2.2. Calculate the LED chip center coordinates in the calibration wafer coordinate system according to the LED chip array parameters, and divide the chip array grid consistent with the actual chip arrangement on the calibration wafer.

[0069] Specifically, after loading the calibration configuration file to read the time position parameters, the calibration wafer size and the positions of each detection station, and loading the LED chip array parameters to obtain the number of rows and columns of LED chips, the row spacing and the column spacing, the reference origin of the calibration wafer is selected in the calibration wafer coordinate system, for example, the center of the calibration wafer or a fixed edge corner point of the calibration wafer as the coordinate origin, the row index and the column index are set for each row and each column according to the number of rows and columns of LED chips, the coordinates of each LED chip center are calculated by multiplying the row index and the row spacing and multiplying the column index and the column spacing and superimposing the position coordinates of the reference origin, and each LED chip center coordinates are associated with the corresponding row index and column index; after obtaining all the LED chip center coordinates, the rectangular region is constructed in the calibration wafer coordinate system according to the row spacing and the column spacing with each LED chip center coordinates as the geometric center, each rectangular region is defined as a chip array grid unit boundary, so that all chip array grid units are arranged continuously in the row direction and the column direction and cover the actual arrangement area of LED chips on the calibration wafer, forming a chip array grid consistent with the actual chip arrangement on the calibration wafer.

[0070] S2.3. Calculate the start and end time of each chip array grid entering the appearance imaging station, the light emission imaging station and the electrical test station in sequence according to the time position parameters and the positions of each detection station, and record the start and end time as the time window of the calibration wafer in each detection station.

[0071] Specifically, after obtaining the time position parameters, the positions of each detection station and the center coordinates of each chip array grid, the time required for each chip array grid center to move from the reference position to the appearance imaging station position, the light emission imaging station position and the electrical test station position is calculated using the correspondence between the encoder count in the time position parameters and the displacement of the calibration wafer in the conveying direction and the time, and the theoretical time point of the chip array grid center entering the vicinity of each detection station is obtained in combination with the positions of the appearance imaging station, the light emission imaging station and the electrical test station in the calibration wafer coordinate system; then, according to the conveying mechanism running speed and the effective action length of the appearance image acquisition, the light emission image acquisition and the current-voltage test in the conveying direction, a time allowance is set before and after each theoretical time point, the start time and the end time of each chip array grid in the appearance imaging station, the light emission imaging station and the electrical test station are calculated, and the start time and the end time are recorded as the time window of the calibration wafer in the corresponding detection station.

[0072] S2.4. Assign a unique chip identification to each chip array grid, and associate the chip identification with the corresponding physical coordinates and time window of each detection station, while setting the appearance exposure parameters, light emission excitation parameters and electrical test parameters for each detection station position, and generate a multi-modal triggering plan.

[0073] Specifically, after obtaining the center coordinates of each chip array grid and the corresponding appearance imaging station time window, light emission imaging station time window and electrical test station time window, in the host computer, a unique chip identification is generated for each chip array grid according to the row index and column index in the LED chip array parameter, and the unique chip identification is bound with the physical coordinates of the chip array grid center in the calibration wafer coordinate system and the corresponding appearance imaging station time window, light emission imaging station time window and electrical test station time window; according to the requirements of exposure and excitation conditions for appearance image acquisition, light emission image acquisition and current-voltage test, appearance exposure parameters are configured for the appearance imaging station, light emission excitation parameters are configured for the light emission imaging station, and electrical test parameters are configured for the electrical test station, and the appearance exposure parameters, light emission excitation parameters and electrical test parameters are combined with the chip identification and the corresponding time window to form a multi-modal acquisition instruction entry for a single chip identification. In the host computer, all multi-modal acquisition instruction entries are sorted according to the time position parameters and chip identification sequence to generate a multi-modal triggering plan.

[0074] S2.5. In the host computer, the multi-modal triggering plan and the corresponding relationship between the chip identification and the physical coordinates are sorted and stored to form a multi-modal triggering plan and chip identification corresponding relationship.

[0075] Specifically, in the host computer, the multi-modal acquisition instruction entries are read one by one from the multi-modal triggering plan according to the chip identification, and for each chip identification, the physical coordinates of the chip array grid center in the calibration wafer coordinate system and the appearance imaging station time window, light emission imaging station time window, electrical test station time window and the corresponding appearance exposure parameters, light emission excitation parameters, electrical test parameters are extracted, and the above information is combined into a multi-modal triggering plan record. Then, the multi-modal triggering plan records are organized into a table structure according to the chip identification sequence or the calibration wafer physical coordinates sequence, and the chip identification, physical coordinates, detection station time window and corresponding acquisition parameters are stored in the table structure, and the table structure is saved in the host computer storage medium, so that the corresponding relationship between the multi-modal triggering plan and the chip identification and the physical coordinates can be directly called by the subsequent steps, forming a multi-modal triggering plan and chip identification corresponding relationship.

[0076] S3. According to the multi-modal triggering plan, appearance images, light emission images and current-voltage data are collected, and are sorted into multi-modal raw data according to the chip identification corresponding relationship.

[0077] S3.1. Load the multi-modal trigger plan and chip identification correspondence, and issue the trigger time window related to the time position parameter to the programmable logic controller.

[0078] Specifically, the time position parameter is read from the calibration configuration file, and the multi-modal trigger plan and the chip identification correspondence list are loaded from the storage medium. The start time and end time of the appearance imaging station time window, the light emission imaging station time window, and the electrical test station time window are parsed for each record associated with the chip identification in the multi-modal trigger plan. The detection station time window is converted into a trigger time window represented by the encoder count or a unified time reference according to the correspondence between the encoder count and the time in the time position parameter. After the conversion is completed, the appearance imaging station trigger time window, the light emission imaging station trigger time window, and the electrical test station trigger time window are grouped respectively. The information including the trigger time window, the detection station type, and the associated chip identification is issued to the internal storage area of the programmable logic controller through the communication interface between the upper computer and the programmable logic controller.

[0079] S3.2. The programmable logic controller monitors the encoder count in real time according to the time position parameter, and sends the acquisition trigger signal to the appearance imaging station and the light emission imaging station, and performs current-voltage test to obtain the appearance image, the light emission image, and the corresponding current-voltage data.

[0080] Specifically, after receiving the multi-modal trigger plan and the trigger time window related to the time position parameter, the programmable logic controller continuously reads the encoder count output by the conveying mechanism, and compares the real-time encoder count with the appearance imaging station trigger time window, the light emission imaging station trigger time window, and the electrical test trigger time window one by one. When the real-time encoder count falls within the appearance imaging station trigger time window, the acquisition trigger signal is sent to the appearance imaging station to drive the appearance imaging camera to complete the exposure acquisition and generate the appearance image. When the real-time encoder count falls within the light emission imaging station trigger time window, the acquisition trigger signal is sent to the light emission imaging station, and the light emission condition is controlled to meet the light emission image acquisition requirement to generate the light emission image. When the real-time encoder count falls within the electrical test trigger time window, the electrical test process is controlled according to the preset current-voltage test parameters to apply current-voltage excitation to the corresponding LED chip and acquire the current-voltage response. The obtained current-voltage response is arranged as current-voltage data. The appearance image, the light emission image, and the current-voltage data corresponding to the chip array position are obtained synchronously during the continuous motion of the calibration wafer.

[0081] S3.3. According to the chip identification correspondence and the acquisition time, the image information of the corresponding chip array grid in the appearance image and the light emission image is associated with the current-voltage data in the corresponding time window under the corresponding chip identification correspondence, and is classified and arranged to form the multi-modal raw data.

[0082] Specifically, the chip identification corresponding relationship, the multi-modal trigger plan record, the appearance image, the light emission image, and the current-voltage data are read in the host computer, the chip array grid range covered by each frame of appearance image and each frame of light emission image is determined according to the acquisition time corresponding to each frame of appearance image and each frame of light emission image combined with the time position parameter, and the chip identification corresponding to each chip array grid is retrieved from the chip identification corresponding relationship according to the physical coordinates of the chip array grid in the calibration wafer coordinate system; the current-voltage data whose time stamp falls into the electrical test station time window is retrieved in the current-voltage data record according to the acquisition time by using the electrical test station time window recorded in the chip identification corresponding relationship, the retrieved current-voltage data is associated with the corresponding chip identification; the image region corresponding to the chip array grid in the appearance image and the image region corresponding to the chip array grid in the light emission image are indexed in the host computer, the appearance image information and the light emission image information corresponding to each chip identification are combined with the associated current-voltage data according to the chip identification, and the multi-modal original data is formed by storage.

[0083] S4. The multi-modal original data is corrected, registered, cropped, and normalized, and combined into single-chip multi-modal data according to the chip identification corresponding relationship.

[0084] S4.1. The camera parameters, the time position parameters, and the chip array grid information are obtained from the calibration configuration file and the multi-modal trigger plan, the appearance image and the light emission image are corrected for distortion, and the light emission image is registered to the coordinate system of the appearance image by using the conversion relationship between the image coordinates and the physical coordinates of the calibration wafer.

[0085] Specifically, the camera parameters and the time position parameters are read from the calibration configuration file, the chip array grid information and the shooting time and the field of view coverage related to the appearance image and the light emission image acquisition are read from the multi-modal trigger plan, the appearance image is corrected for distortion and reprojected according to the intrinsic parameters, extrinsic parameters, and geometric distortion parameters in the camera parameters, a one-to-one correspondence between each pixel position in the appearance image and the physical coordinates of the calibration wafer is established, the light emission image is corrected for distortion by using the same camera parameters, the image coordinates in the light emission image are converted into the corresponding physical coordinates of the calibration wafer, the light emission image that has been mapped to the physical coordinate system of the calibration wafer is interpolated and resampled according to the conversion relationship between the image coordinates and the physical coordinates of the calibration wafer combined with the chip array grid information, and the light emission image is re-expressed in the image coordinate system used by the appearance image.

[0086] S4.2. According to the center coordinates of each chip in the chip array grid and the grid size, a chip appearance image and a chip luminescence image are obtained in the corrected appearance image and the corrected luminescence image, and size normalization and brightness normalization processing are performed to obtain a standardized chip appearance image and a standardized chip luminescence image.

[0087] Specifically, according to the center coordinates of each chip in the chip array grid and the grid size, a chip appearance image region corresponding to the chip identification is intercepted in the corrected appearance image with the center coordinates of the chip as the cropping center and the grid size as the boundary, and a chip luminescence image region corresponding to the chip identification is intercepted in the corrected luminescence image in the same way. The chip appearance image and the chip luminescence image are uniformly scaled to a preset target resolution, so that the chip appearance image and the chip luminescence image are consistent in pixel size. Then, according to the gray scale distribution of the chip appearance image and the chip luminescence image, linear gray scale stretching or histogram equalization brightness normalization processing is performed on the chip appearance image and the chip luminescence image, respectively, to obtain the chip appearance image and the chip luminescence image corresponding to the chip identification and completing size normalization and brightness normalization.

[0088] S4.3. The current-voltage data in the multi-modal raw data is denoised, interpolated and resampled according to the chip identification and the collection time, the current-voltage data of different lengths are converted into one-dimensional vectors, and amplitude normalization is performed, and the electrical characteristic vector is output.

[0089] Specifically, according to the chip identification and the collection time, the current-voltage data sequence corresponding to each chip identification is extracted from the current-voltage data in the multi-modal raw data, and the current-voltage data sequence is arranged in the order of collection time. Each current-voltage data sequence is denoised by using a filtering algorithm, such as using a moving average method to weaken transient peak interference. Then, the current-voltage data sequence is interpolated at the voltage sampling points or the current sampling points, and the interpolated current-voltage data sequence is resampled according to a uniform sampling step. The current-voltage data sequences of different sampling points are converted into one-dimensional vectors with consistent lengths. The one-dimensional vectors are amplitude normalized based on the range of current-voltage values in each one-dimensional vector, so that the current-voltage values fall within a uniform amplitude interval. The normalized one-dimensional vector is associated with the corresponding chip identification as an electrical characteristic vector output.

[0090] S4.4. The standardized chip appearance image, the standardized chip luminescence image and the electrical characteristic vector are combined according to the correspondence relationship of the chip identification to form a single-chip multi-modal data.

[0091] Specifically, the chip appearance image, the chip light emission image, the electrical characteristic vector, and the chip identification correspondence relationship obtained after preprocessing are read, and a single-chip multi-modal data record is established in the memory with the chip identification as the key. The chip appearance image, the chip light emission image, and the electrical characteristic vector corresponding to the chip identification are written in the single-chip multi-modal data record in a fixed order. When multiple image frames or multiple groups of electrical characteristic vectors point to the same chip identification, the chip appearance image, the chip light emission image, and the electrical characteristic vector are sorted according to the chip identification correspondence relationship and the collection time, and written into the corresponding single-chip multi-modal data record, so that each chip identification corresponds to a unique set of chip appearance image, chip light emission image, and electrical characteristic vector. After the processing of all chip identifications is completed, all single-chip multi-modal data records are sorted according to the chip identification order or the calibrated wafer physical coordinate order to form a single-chip multi-modal data indexed by the chip identification.

[0092] S5. The single-chip multi-modal data is input into the artificial intelligence defect judgment model, and the LED chip defect category and grading result are generated through feature extraction and feature fusion.

[0093] S5.1. The single-chip multi-modal data is input into the artificial intelligence defect judgment model, and the appearance feature vector, the light emission feature vector, and the electrical high-dimensional feature vector are extracted through the appearance feature extraction subnetwork, the light emission feature extraction subnetwork, and the electrical feature extraction subnetwork respectively, and are spliced and nonlinearly transformed to obtain a fusion feature representation.

[0094] Specifically, the single-chip multi-modal data is read one by one according to the chip identification, and the chip appearance image corresponding to each chip identification is sent to the appearance feature extraction subnetwork in the artificial intelligence defect judgment model. Multi-layer convolution operation and nonlinear activation operation are performed on the chip appearance image to obtain an appearance feature vector representing contour topography, surface defect texture, and other information. At the same time, the chip light emission image is sent to the light emission feature extraction subnetwork in the artificial intelligence defect judgment model to extract features such as brightness distribution, light emission uniformity, and dark spots, and obtain a light emission feature vector. The electrical characteristic vector of the corresponding chip is sent to the electrical feature extraction subnetwork in the artificial intelligence defect judgment model, and a multi-layer fully connected operation is performed to obtain an electrical high-dimensional feature vector containing current-voltage response change law. After obtaining the appearance feature vector, the light emission feature vector, and the electrical high-dimensional feature vector, they are spliced in order inside the artificial intelligence defect judgment model to form a single long vector, and the single long vector is input into the nonlinear transformation layer in the artificial intelligence defect judgment model. Through a series of linear transformations and nonlinear activation operations, the multi-source information is compressed and reorganized to obtain a fusion feature representation representing the comprehensive appearance state, light emission state, and electrical state of the corresponding chip.

[0095] It should be noted that the artificial intelligence defect judgment model includes an appearance feature extraction subnetwork, a light emission feature extraction subnetwork, an electrical feature extraction subnetwork, a multi-modal feature fusion structure, a classification subnetwork, and a grading subnetwork;

[0096] The training process of the artificial intelligence defect judgment model is based on historical acquisition and has completed chip appearance images, chip light emission images, electrical feature vectors, and corresponding defect category labels and grading level labels to form a training sample set. The training sample set is divided into a training subset and a validation subset. In the training stage, the corresponding chip appearance image, chip light emission image, and electrical feature vector of each chip identifier in the training subset are input into the artificial intelligence defect judgment model. Through the appearance feature extraction subnetwork, the light emission feature extraction subnetwork, the electrical feature extraction subnetwork, and the multi-modal feature fusion structure, the fusion feature representation is obtained. Then, the classification subnetwork outputs the defect category probability distribution, and the grading subnetwork outputs the grading score or grading level. The defect category probability distribution and the defect category label are used to calculate the classification loss, and the grading output and the grading level label are used to calculate the grading loss. The total loss function of the artificial intelligence defect judgment model is formed by weighted summation. The existing back propagation algorithm and gradient descent algorithm are used to iteratively update the trainable parameters in the appearance feature extraction subnetwork, the light emission feature extraction subnetwork, the electrical feature extraction subnetwork, the multi-modal feature fusion structure, the classification subnetwork, and the grading subnetwork. After each several rounds of parameter update, the validation subset is used to evaluate the defect category prediction accuracy and the grading level prediction accuracy. When the total loss function and the validation indicators tend to be stable in multiple iterations, the artificial intelligence defect judgment model training is completed.

[0097] Further, the appearance feature extraction subnetwork is an image feature extraction structure based on a convolutional neural network. The chip appearance image is input, and the profile morphology, scratches, edge collapse, particles, and pollution points related to the appearance defects are extracted through multi-layer convolution operation, pooling operation, and nonlinear activation operation. The appearance feature vector is output.

[0098] The light emission feature extraction subnetwork is based on a convolutional neural network structure. The chip light emission image is input, and the brightness distribution, light emission uniformity, dark spots, bright spots, and light spot morphology related to the light emission defects are extracted through multi-layer convolution operation, pooling operation, and nonlinear activation operation. The light emission feature vector is output.

[0099] The electrical feature extraction subnetwork is a one-dimensional feature extraction structure based on a fully connected neural network. The electrical feature vector is input, and the current-voltage response curve shape, inflection point position, and slope change related to the electrical behavior are extracted through multi-layer fully connected operation and nonlinear activation operation. The electrical high-dimensional feature vector is output.

[0100] The classification sub-network is a defect category determination structure based on a full connection neural network, takes the fused feature representation as input, obtains an output vector with the same number of preset defect categories through several layers of full connection operation and nonlinear activation operation, and maps the output vector to a probability distribution of each defect category through probability normalization operation, and is used to determine the defect category of the LED chip.

[0101] The grading sub-network is a grading level determination structure based on a full connection neural network, takes the fused feature representation as input, and outputs a set of grading scores or directly outputs grading level labels through multi-layer full connection operation and nonlinear activation operation, and is used to determine the grading level of the LED chip.

[0102] S5.2. Calculate the probability distribution of the LED chip in the defect category according to the fused feature representation through the classification sub-network, and select the defect category with the maximum probability as the defect category of the LED chip.

[0103] Specifically, the fused feature representation is input into the classification sub-network, and the fused feature representation is mapped to an output dimension with the same number of defect categories through several full connection operations and nonlinear activation operations. The probability value corresponding to the output dimension is obtained by performing probability normalization operation on the output dimension, forming the probability distribution of the LED chip in each defect category, and selecting the defect category with the maximum probability value in the probability distribution. The defect category is taken as the defect category of the LED chip corresponding to the fused feature representation.

[0104] S5.3. Output the grading level corresponding to the LED chip according to the fused feature representation through the grading sub-network, and arrange according to the chip identification to form the grading result.

[0105] Specifically, the grading sub-network maps the fused feature representation to a grading score vector corresponding to each grading level through multi-layer full connection operation and nonlinear activation operation, and then compares the grading score vectors according to the size of the grading score to determine the grading level corresponding to each LED chip from the grading score vector. The grading level and the defect category of the LED chip are combined and stored according to the chip identification, so that each chip identification is associated with an LED chip defect category and a grading level, forming the LED chip defect category and grading result arranged according to the chip identification.

[0106] S6. The LED chip defect category and the grading result are summarized with the time position parameter to form a grading result table, and the grading result table is used to control the sorting device to sort the scrap chips and the degraded chips at the corresponding positions, and generate an LED chip defect detection and sorting result table.

[0107] S6.1. Read the LED chip defect category and grading result, and the time position parameter and calibration wafer size information stored in the calibration configuration file; calculate the time point when the LED chip passes the sorting position and the trajectory coordinate in the sorting position according to the time position parameter and the positional relationship between each detection station and sorting station in the conveying direction.

[0108] Specifically, the LED chip defect category and grading result are read from the storage medium, and the time position parameter and calibration wafer size information stored in the calibration configuration file are read synchronously. By reading the LED chip defect category and grading result, the time position parameter and the calibration wafer size information, the time reference information and the space reference information corresponding to each LED chip in the conveying direction are obtained. Then, according to the corresponding relationship between the time and the conveying position recorded in the time position parameter, combined with the installation position of each detection station in the conveying direction and the installation position of each sorting station in the conveying direction, the whole process of each LED chip from entering the detection station to reaching the sorting station is calculated in time along the conveying direction. In the time calculation process, the positional difference between each detection station and each sorting station in the conveying direction is sequentially accumulated according to the time node sequence provided by the time position parameter, so as to obtain the time point when each LED chip passes the sorting position. After obtaining the time point when each LED chip passes the sorting position, the corresponding relationship between the conveying direction and the wafer plane coordinate is established by using the time position parameter and the calibration wafer size information, and the trajectory coordinate of the LED chip in the sorting position is calculated on the conveying trajectory matching the time point.

[0109] S6.2. Associate the time point and the trajectory coordinate with the corresponding chip identification, calibration wafer physical coordinate, LED chip defect category and grading result, and generate a grading result table.

[0110] Specifically, the chip identification corresponding to the time point is extracted for the LED chip, the chip identification is paired with the time point to form a time point record indexed by the chip identification, the corresponding calibration wafer physical coordinate is found in the calibration configuration file according to the chip identification, the calibration wafer physical coordinate is combined with the chip identification, the time point and the trajectory coordinate, so that the time position relationship of each LED chip in the sorting process and the calibration wafer physical coordinate form a unique association relationship. After the association is completed, the LED chip defect category and grading result generated by the detection process are continued to be called based on the chip identification, the LED chip defect category and grading result are combined with the chip identification, the calibration wafer physical coordinate, the time point and the trajectory coordinate into the same record, and are arranged in sequence as a structured record set containing a chip identification field, a calibration wafer physical coordinate field, a time point field, a trajectory coordinate field, an LED chip defect category field and a grading result field. The structured record set is output as a grading result table in the form of rows and columns.

[0111] S6.3. Combine the grading result corresponding to the chip identification in the grading result table with the time position parameter in the calibration configuration file, calculate the time point of each chip identification corresponding LED chip passing through the sorting station and the position in the conveying path, and generate a sorting control instruction sequence.

[0112] Specifically, the grading result corresponding to each chip identification in the grading result table is read, and the time position parameter and the position of the sorting station in the conveying direction are read from the calibration configuration file. According to the motion speed relationship of the calibration wafer on the conveying mechanism recorded by the time position parameter, the physical coordinates of each chip identification in the calibration wafer coordinate system are converted into the time increment required for motion from the detection position to the position of the sorting station, and the time point of each chip identification corresponding LED chip passing through the sorting station is obtained by superimposing the detection completion time. In combination with the track number of the conveying mechanism or the conveying path distribution rule, the position of the LED chip in the conveying path when passing through the sorting station is determined. The time point, conveying path position, and sorting action type corresponding to the grading result are combined with the chip identification, and arranged in time sequence to form a sorting control instruction sequence.

[0113] S6.4. According to the sorting control instruction sequence, trigger the sorting mechanism action at the corresponding time point, separate and introduce the marked scrap chips and degraded chips from the conveying path of qualified chips into the corresponding collection path, compare and count the grading result table with the sorting execution record to obtain the LED chip defect detection and sorting result table.

[0114] Specifically, the sorting control instructions in the sorting control instruction sequence are read in time sequence, the encoder count is monitored in real time during the motion of the LED chip driven by the conveying mechanism, and when the encoder count matches the time point of the LED chip passing through the sorting station recorded in the sorting control instruction, the separation action is performed at the conveying path position given in the instruction. The LED chip with a grading result of scrap chip is separated from the qualified chip conveying path and introduced into the scrap collection path, and the LED chip with a grading result of degraded chip is separated from the qualified chip conveying path and introduced into the degraded collection path, while the LED chip with a grading result of qualified chip is output along the original conveying path. The chip identification, action time point, and sorting action type saved in the sorting execution record in the upper computer are read, the sorting execution record is compared with the grading result table by chip identification, the number of LED chips corresponding to each grading level and the distribution into different collection paths are counted, and the comparison result and the counting result are combined into the LED chip defect detection and sorting result table.

[0115] The embodiment also provides a computer device suitable for the LED chip defect detection method based on artificial intelligence, including a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute the computer executable instructions to realize the LED chip defect detection method based on artificial intelligence proposed in the above embodiment.

[0116] The computer device can be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, an operator network, NFC (Near Field Communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0117] The embodiment also provides a storage medium having a computer program stored thereon, the program being executed by a processor to realize the LED chip defect detection method based on artificial intelligence proposed in the above embodiment. The storage medium can be realized by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk or an optical disk.

[0118] It should be noted that the above examples are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application is described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or equivalently replaced, without departing from the spirit and scope of the technical solutions of the present application, which should be covered in the scope of the claims of the present application.

Claims

1. A method for detecting defects in LED chips based on artificial intelligence, characterized in that: The application relates to a LED chip defect detection and sorting method and device based on multi-modal artificial intelligence. The calibration configuration file is generated by loading LED chip layout and array parameters, collecting calibration images and electrical calibration data on a calibration wafer, calculating camera parameters and time position parameters, and generating the calibration configuration file; According to the calibration configuration file, the time window of the calibration wafer in each detection station is calculated, and a grid is divided in combination with the array parameters, a multi-modal trigger plan and a chip identification corresponding relationship are generated; According to the multi-modal trigger plan, appearance images, light emission images and current-voltage data are collected, and are arranged into multi-modal original data according to the chip identification corresponding relationship; The multi-modal original data is corrected, registered, cropped and normalized, and is combined into single-chip multi-modal data according to the chip identification corresponding relationship; The single-chip multi-modal data is input into an artificial intelligence defect judgment model, feature extraction and feature fusion are carried out, and LED chip defect categories and grading results are generated; The LED chip defect categories and grading results are summarized with the time position parameters to form a grading result table, and the grading result table is used to control a sorting device to sort out defective chips and degraded chips at corresponding positions, and a LED chip defect detection and sorting result table is generated; The multi-modal trigger plan and the chip identification corresponding relationship are generated in the following specific steps, The time position parameters are read by loading the calibration configuration file, and the size of the calibration wafer and the positions of the detection stations are obtained; According to the LED chip array parameters, the center coordinates of the LED chips in the calibration wafer coordinate system are calculated, and a chip array grid consistent with the actual chip arrangement is divided on the calibration wafer; According to the time position parameters and the positions of the detection stations, the start and end time of the corresponding chip array grid entering the appearance imaging station, the light emission imaging station and the electrical test station in sequence is calculated, and the start and end time is used as the time window of the calibration wafer in each detection station; A unique chip identification is allocated to each chip array grid, and the chip identification is associated with the corresponding physical coordinates and the time window of each detection station, meanwhile, appearance exposure parameters, light emission excitation parameters and electrical test parameters are set for the positions of each detection station, and a multi-modal trigger plan is generated; The multi-modal trigger plan, the chip identification and the corresponding relationship of the physical coordinates are arranged and stored in the host computer to form the multi-modal trigger plan and the chip identification corresponding relationship; The LED chip defect categories and grading results are generated in the following specific steps, The single-chip multi-modal data is input into an artificial intelligence defect judgment model, appearance feature vectors, light emission feature vectors and electrical high-dimensional feature vectors are extracted through an appearance feature extraction subnetwork, a light emission feature extraction subnetwork and an electrical feature extraction subnetwork respectively, and are spliced and nonlinearly transformed to obtain a fusion feature representation; According to the fusion feature representation, the probability distribution of the LED chip in the defect category is calculated through a classification subnetwork, and the defect category with the maximum probability is selected as the LED chip defect category; The grading level corresponding to the LED chip is output through a grading subnetwork according to the fusion feature representation, and is arranged according to the chip identification to form the grading result. 2.The AI-based LED chip defect detection method of claim 1, wherein: The calibration configuration file is generated in the following specific steps, The operation speed of the conveying mechanism and the position of the detection station are transmitted by loading the LED chip layout and array parameter setting, appearance calibration images, light-emitting calibration images and electrical calibration data are collected, and encoder counts are recorded; The intrinsic parameters, extrinsic parameters and geometric distortion parameters of each imaging camera are calculated according to the appearance calibration images and the light-emitting calibration images, and the conversion relationship between the image coordinates and the physical coordinates of the calibration wafer is established; The corresponding relationship between the electrical test channel and the chip position and the corresponding relationship between the time and the position of the calibration wafer are established according to the electrical calibration data and the encoder counts, and the camera parameters and the time position parameters are output; the camera parameters and the time position parameters are sorted and associatedly stored to generate a calibration configuration file. 3.The AI-based LED chip defect detection method of claim 1, wherein: The multi-modal raw data is sorted according to the chip identification corresponding relationship, and the specific steps are as follows, The time position parameter related trigger time window is issued to the programmable logic controller by loading the multi-modal trigger plan and the chip identification corresponding relationship; The programmable logic controller monitors the encoder count in real time according to the time position parameter, sends the collection trigger signal to the appearance imaging station and the light-emitting imaging station, and performs current-voltage test to obtain the appearance image, the light-emitting image and the corresponding current-voltage data; According to the chip identification corresponding relationship and the collection time, the image information of the corresponding chip array grid in the appearance image and the light-emitting image is associated with the current-voltage data in the corresponding time window to the corresponding chip identification corresponding relationship, and is classified and sorted to form multi-modal raw data. 4.The AI-based LED chip defect detection method of claim 1, wherein: The single-chip multi-modal data is combined according to the chip identification corresponding relationship, and the specific steps are as follows, The camera parameters, time position parameters and chip array grid information are obtained from the calibration configuration file and the multi-modal trigger plan, the appearance image and the light-emitting image are corrected, and the light-emitting image is registered to the coordinate system of the appearance image by using the conversion relationship between the image coordinates and the physical coordinates of the calibration wafer; According to the center coordinates of each chip in the chip array grid and the grid size, the chip appearance image and the chip light-emitting image are obtained in the corrected appearance image and the light-emitting image, and size normalization and brightness normalization processing are performed to obtain the standardized chip appearance image and the standardized chip light-emitting image; The current-voltage data in the multi-modal raw data is denoised, interpolated and resampled according to the chip identification and the collection time, the current-voltage data of different lengths are converted into one-dimensional vectors, and amplitude normalization is performed to output the electrical feature vector; The standardized chip appearance image, the standardized chip light-emitting image and the electrical feature vector are combined according to the chip identification corresponding relationship to form single-chip multi-modal data. 5.The AI-based LED chip defect detection method of claim 1, wherein: The grading result table is formed, and the specific steps are as follows, The time point and the trajectory coordinate of the LED chip passing through the sorting position are calculated according to the time position parameter and the positional relationship of each detection station and the sorting station in the conveying direction, and the LED chip defect category and the grading result and the time position parameter and the physical coordinates of the calibration wafer stored in the calibration configuration file are read; The time point and the trajectory coordinate are associated with the corresponding chip identification, the physical coordinates of the calibration wafer, the LED chip defect category and the grading result to generate a grading result table. 6.The AI-based LED chip defect detection method of claim 1, wherein: The generated LED chip defect detection and sorting result table has the following specific steps, The grading result corresponding to the chip identifier in the grading result table is combined with the time position parameter in the calibration configuration file to calculate the time point at which each chip identifier passes through the sorting station and the position of the chip identifier on the conveying path, and a sorting control instruction sequence is generated; According to the sorting control instruction sequence, the sorting mechanism is triggered to act at the corresponding time point, and the chips marked as scrap and degraded chips are separated from the conveying path of the qualified chips and introduced into the corresponding collection path. The grading result table is compared and counted with the sorting execution record to obtain the LED chip defect detection and sorting result table. 7.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is characterized in that: The processor executes the computer program to implement the steps of the LED chip defect detection method based on artificial intelligence according to any one of claims 1-6.

8. A computer readable storage medium having stored thereon a computer program, characterized in that: The computer program is executed by the processor to implement the steps of the LED chip defect detection method based on artificial intelligence according to any one of claims 1-6.

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