Switching converter operation under light load conditions

Abstract

A gate driving module of the switching converter drives a high-side switch and a low-side switch, so that in a period of a control signal: i. At a first time point, the low-side switch is turned on and the high-side switch is turned off; ii. At a second point in time immediately after the first point in time, the low-side switch is turned off and the high-side switch remains turned off; and iii, at a third time point delayed for a period of time from the second time point, the high-side switch is turned on, and the low-side switch is kept turned off. And at a third time point, the voltage on the effective stray capacitor only reaches a part of the input voltage (less than the input voltage), and then the voltage on the effective stray capacitor rises to the input voltage during the continuous conduction period of the high-side switch from the third time point.

Description

[0001] Priority Statement

[0002] This application relates to and claims priority to the following pending Indian provisional patent applications: 1) entitled "SPS (Smart Power Stage) ZVS (Zero Voltage Switching)", application number 202441087560, filed on November 13, 2024, agent number AURA-368-INPR; and 2) entitled "SPS (Smart Power Stage) ZVS (Zero Voltage Switching)", application number 202441097428, filed on December 10, 2024, agent number AURA-368-INPR2.

[0003] Secondly, this application also claims priority to a pending U.S. patent application entitled "Operation of a Switch under Light Load Conditions," application number 19 / 059,346, filed February 21, 2025. The entire contents of the aforementioned application are incorporated herein by reference only, without inconsistency with this specification. Technical Field

[0004] The embodiments of this application generally relate to switching converters, and more specifically, to the operation of switching converters under light load conditions. Background Technology

[0005] A switching converter is a component that generates a controlled direct current (DC) voltage from an input power supply voltage using one or more switches, as is well known in the relevant technical field. Switching converters can be used as stand-alone power supplies or as voltage regulation modules in various environments, such as laptops and mobile phones.

[0006] A switching converter typically includes a pair of switches connected to an inductor. Each switch is generally implemented by a transistor (e.g., a MOSFET), and the two switches are connected in series between the input supply voltage and a reference terminal (e.g., ground). The switch closer to the input voltage terminal (i.e., the source of the converter's input power) is called the "high-side switch," and the other is called the "low-side switch." These switches are driven by control circuitry that turns on the transistor at continuous, non-overlapping time intervals, allowing the currently conducting switch to operate within the inductor for the corresponding time period.

[0007] In switching converters, various known losses typically occur, such as switching losses, inductor core losses, and conduction losses, which reduce the converter's efficiency. As is well known in the relevant technical field, the efficiency of a switching converter is usually measured as the ratio of output power to input power.

[0008] Switching converters often operate under light load conditions, meaning that the load at the output is only a small fraction of the maximum rated power (e.g., less than 10%). Generally, even under light load conditions, it is desirable for switching converters to maintain high efficiency.

[0009] Various embodiments of this application relate to the operation of switching converters under light load conditions. Summary of the Invention

[0010] This invention provides a switch converter, comprising: a high-side switch and a low-side switch, the high-side switch and the low-side switch being connected in series in a switching node and operating together to provide an regulated power supply voltage to an output node based on an input voltage received at an input node, the input voltage having a first magnitude; the high-side switch and the low-side switch being connected in series between the input node and a ground terminal providing a constant reference potential; wherein an inductor is coupled between the switching node and the output node; the high-side switch and the low-side switch respectively drive the inductor based on a control signal; and a gate driving module driving the high-side switch and the low-side switch to turn on or off with a logic level based on the control signal, wherein there is a connection between the switching node and the ground terminal. In an effective parasitic capacitance, the gate drive module drives the high-side switch and the low-side switch such that, within one cycle of the control signal: at a first time point, the low-side switch is turned on when the high-side switch is off; at a second time point following the first time point, the low-side switch is off while the high-side switch remains off; and at a third time point following the second time point after a delay, the high-side switch is turned on when the low-side switch remains off, wherein by the third time point, the voltage across the effective parasitic capacitance is only a portion of the first size, and as the high-side switch remains on from the third time point, the voltage across the effective parasitic capacitance further rises to the first size, wherein the portion is less than one.

[0011] In some embodiments, the period of the control signal begins from the first time point, wherein the time length defined by the first time point and the second time point is equal to a first pre-calculated value, such that the current in the inductor reaches a predetermined magnitude at the second time point, wherein the delay time is equal to a second pre-calculated value.

[0012] In some embodiments, the gate drive module is further capable of driving the high-side switch and the low-side switch such that during the period of the control signal: at a fourth time point after the third time point, the high-side switch is turned off and the low-side switch remains off; at a fifth time point after the fourth time point, the low-side switch is turned on and the high-side switch remains off; at a sixth time point after the fifth time point, the low-side switch is turned off and the high-side switch remains off, wherein by the fifth time point, the voltage of the switching node (SW) reaches a first negative threshold voltage, and from the fifth time point onwards, the voltage of the switching node rises to zero while the low-side switch remains on, wherein by the sixth time point, the inductor current drops to zero.

[0013] In some embodiments, the effective parasitic capacitance is an equivalent capacitance consisting of a combination of a first parasitic capacitance located between the high-side switching current terminals and a second parasitic capacitance located between the low-side switching current terminals.

[0014] In some embodiments, the low-side switch includes a plurality of parallel segments, each segment including a plurality of corresponding transistors, wherein each transistor includes a first current terminal, a second current terminal, and a control terminal, and the control terminals of the plurality of transistors in the corresponding segments are interconnected, wherein each segment can be controlled by a corresponding common gate drive signal to drive the control terminals of the plurality of transistors in the corresponding segment, wherein when the common gate drive signal of a segment of the plurality of segments is driven to a first logic state, the plurality of transistors in that segment are turned on; and when the common gate drive signal of that segment of the plurality of segments is driven to a second logic state, the plurality of transistors in that segment are turned off, wherein during the time period between the first time point and the second time point, the common gate drive signal of a first subset of the plurality of segments is driven to the first logic state, while the remaining common gate drive signals are driven to the second logic state, wherein during the time period between the fifth time point and the sixth time point, the common gate drive signal of all segments of the plurality of segments is driven to the first logic state.

[0015] In some embodiments, the switch converter operates only in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), wherein the converter operates in CCM when the load current demand exceeds a threshold current; otherwise, it operates in DCM, wherein when the converter operates in DCM, the mode signal is a second logic state, wherein the first logic state is logic high and the second logic state is logic low.

[0016] In some embodiments, the switching converter further includes: a negative threshold voltage detector, which receives a control signal and a switching node voltage, and generates a negative threshold crossover signal of a first logic state when the switching node voltage exceeds a first negative threshold; and a zero current detector, which is connected to the inductor current path and generates a zero current indication signal of the first logic state when the inductor current is zero.

[0017] In some embodiments, the switching converter includes a memory for storing configuration bits, and the gate drive module includes: a first inverter coupled to receive the mode signal and generate a first inverter output; a drive control module coupled to receive the first inverter output signal and the configuration bits, and to generate a local indication signal, wherein the drive control module generates a logic high output when the first inverter output is logic high and the configuration bit is logic high; and a PWM-local generator module coupled to receive the control signal and the local indication signal, and to receive calculation inputs including the inductance value of the inductor, the size of the effective parasitic capacitance, the desired size, and the fraction, and to generate a PWM-local generator. The signal; wherein the PWM-local generator block calculates the first pre-calculated value, the first pre-set size, and the second pre-calculated value based on the calculation input when the local indicator signal is logic high, and the PWM-local generator block generates a PWM-local signal to specify the first time point, the second time point, the third time point, the fourth time point, the fifth time point, and the sixth time point; a multiplexer (MUX) coupled to receive the control signal and the PWM-local signal as input, and uses the local indicator signal as a selection signal; when the local indicator signal is logic low, the MUX forwards the control signal as the MUX output; when the local indicator signal is logic high, the MUX... The PWM-local signal is forwarded to the MUX output; a PWM-level converter module is coupled to receive the MUX output and generate a low-side drive signal (LS-drive signal), wherein the PWM-level converter generates a logic high when the MUX output is logic low, and a logic low otherwise; an SR latch is coupled to receive the negative threshold crossover signal at a set input, receive the zero current indication signal at a reset input, and generate a Q output based on the set input and the reset input; an OR gate is coupled to receive the Q output and the LS-drive signal as input, and the OR gate generates an OR output; wherein the OR output is coupled to a common gate drive signal of a first subset of the plurality of segments, and the Q output is coupled to a common gate drive signal of the remaining segments.

[0018] In some embodiments, the negative threshold voltage detector includes: a resistor; a second inverter; a first current source coupled between a second constant reference potential and a first terminal of the resistor; a first transistor, a first current terminal of the first transistor coupled to a second terminal of the resistor, a second current terminal of the first transistor coupled to the first constant reference potential, and a control terminal of the first transistor coupled to the intersection of the first current source and the first terminal of the resistor; a second transistor, a control terminal of the second transistor coupled to a second terminal of the resistor, a first current terminal of the second transistor coupled to the input of the second inverter, and a second current terminal coupled to the SW node; and a second current source coupled between the second constant reference potential and the input of the second inverter, wherein when the output of the second inverter is logic high, it indicates that the voltage of the switching node is equal to or greater than the first negative threshold voltage; and when the output of the second inverter is logic low, it indicates the opposite situation.

[0019] This application provides a voltage regulation module (VRM), comprising: a power supply stage including: a high-side switch and a low-side switch, connected in series at a switching node, and operating together to provide a required regulated supply voltage to an output node based on an input voltage received from an input node, wherein the input voltage is a first magnitude; the high-side switch and the low-side switch are connected in series between the input node and a ground terminal providing a first constant reference potential; an inductor is connected between the switching node and the output node; wherein the high-side switch and the low-side switch drive the inductor according to a control signal; a gate driving module for driving the high-side switch and the low-side switch to turn on or off according to the logic level of the control signal; wherein there is an effective parasitic capacitance between the switching node and the ground terminal; wherein the gate driving module drives the high-side switch to turn on during a first time period in each cycle of the control signal, driving the... The low-side switch is turned on during a second time period, wherein the magnitude of the first time period is sufficient to maintain the regulated supply voltage at a desired magnitude in steady state, and the gate drive module further drives the low-side switch and the high-side switch such that during the control signal cycle: at a first time point, the low-side switch is turned on and the high-side switch is turned off; at a second time point immediately following the first time point, the low-side switch is turned off and the high-side switch remains off; at a third time point immediately following a delay time of the second time point, the high-side switch is turned on and the low-side switch remains off, wherein by the third time point, the voltage on the effective parasitic capacitance has only reached a fraction of a first magnitude, which is the fraction, and from the third time point onwards, the effective parasitic capacitance voltage rises to the first magnitude during the continuous on-state of the high-side switch, wherein the fraction is less than one; and a phase controller provides the magnitude of the first duration in the control signal.

[0020] In some embodiments, the control signal period begins at the first time point, wherein the time between the first time point and the second time point is equal to a first pre-calculated value, so that the current of the inductor reaches a predetermined size at the second time point, wherein the delay time is equal to a second pre-calculated value, so that the voltage on the effective parasitic capacitance reaches the first size of the fraction at the third time point.

[0021] In some embodiments, the gate drive module further drives the high-side switch and the low-side switch such that during the control signal cycle: at a fourth time point immediately following the third time point, the high-side switch is off and the low-side switch remains off; at a fifth time point immediately following the fourth time point, the low-side switch is on and the high-side switch remains off; and at a sixth time point immediately following the fifth time point, the low-side switch is off and the high-side switch remains off, wherein by the fifth time point, the switching node (SW) voltage reaches a first negative threshold voltage, and from the fifth time point onwards, the switching node voltage rises to zero during the low-side switch on, wherein by the sixth time point, the inductor current drops to zero.

[0022] In some embodiments, the phase controller includes: a first memory storing a first configuration bit; a control module coupled to receive the regulated supply voltage and the desired reference voltage, and generating an error signal based on the difference between the reference voltage and the regulated supply voltage; a mode module coupled to receive the threshold current and current load current information, and generating a logic high mode signal when the current load current is less than the threshold current, otherwise generating a logic low signal; a PWM generator module coupled to receive the error signal, the mode signal, and the load current information, and generating an operating mode indication signal and a common control signal, wherein when the mode signal is logic high, the PWM generator generates a logic low operating mode indication signal; wherein the PWM generator module generates the common control signal based at least on information including the current load current; and a phase management module coupled to receive the operating mode indication signal. The system comprises: a common control signal and phase management information, the phase management information including the current load current, the required current, and a first current; the phase management module generating the control signal and a synchronization (SYNC) signal; and a logic module coupled to receive a mode signal and computational information, the computational information including inductance value, effective parasitic capacitance, required current, and fraction; the logic module generating a first pre-calculated value and a second pre-calculated value; wherein when the mode signal is logic high: the phase management module operates only during the power phase, wherein the phase manager module converts the common control signal into a control signal for the power phase, and the phase manager module converts the operating mode indication signal into a synchronization (SYNC) signal for the power phase; wherein when the first configuration bit is logic high: the logic module calculates the first pre-calculated value, the predetermined current size, and the second pre-calculated value based on the computational information, wherein the PWM generator module generates the common control signal based on the first pre-calculated value and the second pre-calculated value, wherein the control signal is used to specify the first time point, the second time point, the third time point, and the fourth time point.

[0023] In some embodiments, the effective parasitic capacitance is constituted by an equivalent capacitance consisting of a first parasitic capacitance located between the high-side switching current terminals and a second parasitic capacitance located between the low-side switching current terminals.

[0024] In some embodiments, the low-side switch includes multiple parallel segments, each segment including a corresponding plurality of transistors, wherein each transistor includes a first current terminal, a second current terminal, and a control terminal, and the control terminals of the plurality of transistors in the corresponding segment are interconnected, wherein each segment can be controlled by a corresponding common gate drive signal to drive the control terminals of the plurality of transistors in the corresponding segment, wherein when the common gate drive signal of a certain segment is in a first logic state, the transistor of the corresponding segment is turned on, and when the signal is in a second logic state, the transistor of the corresponding segment is turned off, wherein during the time between the first time point and the second time point, the common gate drive signal of the segments of the first subset is in the first logic state, and the signal of the remaining segments is in the second logic state, wherein during the time between the fifth time point and the sixth time point, the common gate drive signal of all segments is in the first logic state.

[0025] In some embodiments, the power supply phase further includes: a negative threshold voltage detector coupled to receive the control signal and the switching node voltage, which generates a logic high negative threshold crossover signal when the switching node voltage exceeds a first negative threshold; and a zero current detector coupled to the path through which the inductor current flows, which generates a logic high zero current inductor signal when the magnitude of the current is zero.

[0026] In some embodiments, the power supply stage includes a second memory storing a second configuration bit, and the gate drive module includes: a first inverter coupled to receive a synchronization signal and generate a first inverter output; a drive control module coupled to receive the first inverter output and the second configuration bit, generating a logic-high local indication signal when the first inverter output is logic high and the second configuration bit is logic high; a PWM-local generator module coupled to receive a control signal, a local indication signal, and an arithmetic input, the arithmetic input including inductance value, effective parasitic capacitance size, desired size, and fraction, the PWM-local generator module generating a PWM-local signal; a multiplexer (MUX) coupled to receive the control signal and the PWM-local signal as input, and using the local indication signal as a selection signal, wherein when the local indication signal is logic low, the MUX forwards the control signal as a MUX output; when the local indication signal is logic high, the MUX forwards the PWM-local signal as the MUX output; and a PWM-level conversion module coupled to receive the MUX signal. The system outputs and generates a low-side drive signal (LS-drive signal), wherein the PWM level converter generates a logic high when the MUX output is logic low, and otherwise generates a logic low; an SR-latch, coupled to receive the negative threshold crossover signal at a setting input and a zero current indication signal as a reset input, the SR-latch generates a Q output based on the setting input and the reset input; an OR gate, coupled to receive the Q output and the LS drive as input, the OR gate generates an OR output, wherein the OR output is connected to a common gate drive signal of a first subset of the plurality of segments; wherein the Q output is connected to the remaining common gate drive signals of the plurality of segments; wherein when the local indication signal is logic high: the PWM local generator module calculates a first pre-calculated value, a first predetermined amplitude, and a second pre-calculated value based on the calculation input; wherein the PWM local generator module generates a PWM local signal that satisfies a first time point, a second time point, a third time point, and a fourth time point.

[0027] In some embodiments, the negative threshold voltage detector includes: a resistor; a second inverter; a first current source coupled between a second constant reference potential and a first terminal of the resistor; a first transistor, a first current terminal of the first transistor coupled to a second terminal of the resistor; wherein a second current terminal of the first transistor is coupled to the first constant reference potential; wherein a control terminal of the first transistor is coupled to the connection point between the first current source and the first terminal of the resistor; a second transistor, a control terminal of the second transistor coupled to a second terminal of the resistor, wherein a first current terminal of the second transistor is coupled to the input of the second inverter, and a second current terminal of the second transistor is coupled to a switching node; and a second current source coupled between the second constant reference potential and the input of the second inverter, wherein when the output of the second inverter is logic high, it indicates that the voltage of the switching node is greater than or equal to the first negative threshold voltage, and when the output of the second inverter is logic low, it indicates the opposite situation. Attached Figure Description

[0028] The exemplary embodiments of this application will be described with reference to the accompanying drawings, which are briefly described below.

[0029] Figure 1 A block diagram showing an example apparatus that can implement the structure of several embodiments of this application.

[0030] Figure 2 A block diagram illustrating the details of a voltage regulator module (VRM) in one embodiment of this application.

[0031] Figure 3 This is a schematic diagram illustrating the specific implementation details of a power stage in one embodiment of this application.

[0032] Figure 4A A block diagram illustrating an example apparatus for demonstrating the operation of a switch converter under light load conditions in one embodiment of this application.

[0033] Figure 4B Another timing diagram (not drawn to scale) illustrates the operation of the switch converter under light load conditions in one embodiment of this application.

[0034] Figure 5 This is a schematic diagram illustrating the specific implementation details of the low-side switch in one embodiment of this application.

[0035] Figure 6 This is a schematic diagram illustrating the specific implementation details of a phase controller in one embodiment of this application.

[0036] Figure 7This is a schematic diagram illustrating the specific implementation details of the gate driver block in one embodiment of this application.

[0037] Figure 8 This is a schematic diagram illustrating the specific implementation details of the negative-threshold voltage detector block in one embodiment of this application.

[0038] In the accompanying drawings, the same reference numerals typically denote identical, functionally similar, and / or structurally similar components. The first appearance of a component in a drawing can be identified by the leftmost digit (or group of digits) of its reference numerals. Detailed Implementation

[0039] 1. Overview

[0040] One embodiment of this application relates to a switch converter comprising a high-side switch and a low-side switch connected in series at a switching node. These switches collectively provide a regulated output voltage at the output based on an input voltage received at the input terminal. The input voltage has a first voltage magnitude. The high-side switch and the low-side switch are connected in series between the input terminal and ground, and an inductor is coupled between the switching node and the output node, driven by the high-side switch and the low-side switch respectively according to a control signal. A gate driver block in the switch converter drives the high-side switch and the low-side switch to turn on and off according to the logic potential of the control signal. An effective parasitic capacitance exists between the switching node and ground.

[0041] According to one embodiment of this application, the gate drive module drives the high-side and low-side switches in the following manner, so that they operate in one cycle of the control signal: i. at a first time point, the low-side switch is turned on, while the high-side switch is turned off; ii. at a second time point after the first time point, the low-side switch is turned off, while the high-side switch remains off; iii. at a third time point after the second time point and after a delay period, the high-side switch is turned on, while the low-side switch remains off.

[0042] When the third time point is reached, the voltage across the effective parasitic capacitor is only a portion of the first voltage. After the third time point, with the high-side switch continuously conducting, the voltage rises to the first voltage, where this portion is less than 1 (i.e. less than the full size).

[0043] By charging the capacitor to a potential lower than the first voltage, an optimal balance can be achieved among various known losses, thereby improving the efficiency of the switching converter.

[0044] According to another embodiment of this application, the period of the control signal starts from a first time point, the time length between the first time point and the second time point is equal to a first pre-calculated value, so that the current in the inductor reaches a predetermined size at the second time point; and the delay time is equal to a second pre-calculated value.

[0045] According to another embodiment of this application, the gate drive module further drives the high-side switch and the low-side switch to operate as follows during the control signal cycle: at a fourth time point after the third time point, the high-side switch is turned off, while the low-side switch remains off; at a fifth time point after the fourth time point, the low-side switch is turned on, while the high-side switch remains off; at a sixth time point after the fifth time point, the low-side switch is turned off, while the high-side switch remains off. At the fifth time point, the voltage of the switching node (SW node) reaches the voltage of the first negative threshold, and then rises to zero voltage during the period when the low-side switch is on; while the current in the inductor drops to zero at the sixth time point.

[0046] Various embodiments of this application will be illustrated by the following examples. However, those skilled in the art will understand that this application can be implemented without certain specific details, or using other methods, components, materials, etc. In some cases, to avoid obscuring the features of this application, known structures, materials, or operations are not described in detail. Furthermore, the described features / implementations can be combined in various different implementations; for the sake of brevity, this document only lists some combinations.

[0047] 2. System Implementation

[0048] Figure 1 A block diagram illustrating an exemplary system architecture that can implement several embodiments of the present disclosure is provided. System 100 includes a power module 110, a central processing unit (CPU) 120, a storage device 130, a network interface 140, and peripheral devices 150. In one embodiment, system 100 may correspond to a computer (e.g., a desktop computer, a laptop computer, etc.); however, in other embodiments, system 100 may represent other types of systems. It is understood that system 100 may contain more or fewer... Figure 1 The shown is a block component.

[0049] CPU 120 typically represents a processor or System-on-Chip (SoC) and schematically receives supply voltages Va and Vb from power module 110 via paths 112A and 112B, respectively. For example, Va may be lower than Vb and is used to power the core parts of the CPU, such as the Arithmetic Logic Unit (ALU), microprogram sequencer, and cache; while Vb can be used to power the rest of CPU 120, such as input / output (I / O) units, I / O buffers, and on-chip peripheral circuits. CPU 120 provides various signals (collectively referred to as signals contained in path 121), including information specifying its power supply requirements to power supply module 110. Examples of such signals may include signals indicating specific operating modes (in terms of power consumption), such as PS1, PS2, and PS3, which correspond to "Power Save States for Improved Efficiency."

[0050] Storage device 130 represents a type of memory, which may include volatile and non-volatile memory. For example, in a personal computer, storage devices may include magnetic storage (hard disk) and solid-state memory (RAM, Flash, etc.). Storage device 130 receives a supply voltage via path 113 to provide power to its various internal circuits and modules.

[0051] Network interface 140 provides bidirectional communication between system 100 and a computer network (or more broadly, the Internet). Network interface 140 implements the electronic circuitry required for communication, conforming to specific physical layer and data link layer standards, such as Ethernet or Wi-Fi™. Furthermore, network interface 140 may also include a network protocol stack to enable communication with other computers on the same local area network (LAN) and to conduct large-scale network communication via routable protocols such as Internet Protocol (IP). Network interface 140 receives power via path 114 to drive its internal circuitry and modules, and transmits and receives data with external systems and CPU 120 via paths 141 and 124, respectively.

[0052] Peripheral device 150 represents one or more peripheral circuits, such as a speaker, microphone, user interface device, etc. Peripheral device 150 receives power via path 115 and communicates with external devices via path 151.

[0053] Power module 110 receives power from one or more power sources (e.g., batteries) via path 101 and operates to provide the required supply voltage on paths 112A, 112B, 113, 114, and 115. In one embodiment, power module 110 is designed to include one or more multi-phase DC-DC converters for generating the supply voltage. Power module 110 controls the multi-phase converters to adjust the output current (increase or decrease) based on signals received from CPU 120 via path 121, the adjustment depending on specific control signals (e.g., PS1, PS2, PS3, etc.).

[0054] In this embodiment, the power module 110 is a voltage regulator module (VRM), sometimes also called a processor power module (PPM), which contains one or more buck switching converters to convert high-voltage power to multiple lower supply voltages. However, in other embodiments, other types of DC-DC converters, such as boost, buck-boost, and hysteretic converters, can be used instead of buck converters. By using a VRM, multiple devices or integrated circuits (ICs) requiring different supply voltages can be installed on the same platform (e.g., a personal computer motherboard). Therefore, the following description will use... Figure 2 The process continues based on the VRM shown.

[0055] 3. Voltage Regulator Module (VRM)

[0056] Figure 2 A block diagram illustrating the details of the VRM in the embodiments of this disclosure. Figure 1 The power module 110 shown is implemented as a voltage regulation module (VRM), which is structured as a multi-phase switching converter to generate two sets of regulated output voltages Va (240) and Vb (250).

[0057] VRM 110 includes a phase controller 210, multiple Smart PowerStages (SPSs or power stages) SPSA-1 (220-1) to SPSA-6 (220-6), and SPSB-1 ​​(230-1) to SPSB-3 (230-3); it also includes inductors 225A-1 to 225A-6 and 227B-1 to 227B-3, output capacitors 226A-1 to 226A-6 and 228B-1 to 228B-3, and bootstrap capacitors 224A-1 to 224A-6 and 224B-1 to 224B-3. Each bootstrap capacitor corresponding to an SPS is connected between the switching node (SW) and the bootstrap node of that SPS. For example, bootstrap capacitor 224A-1 is connected between switching nodes SWA-1 (221-1) and BOOTA-1 (215-1). Although the figure shows the bootstrap capacitor configured externally to each SPS, in other embodiments, the bootstrap capacitor may also be integrated internally into the SPS. It should be noted that, generally speaking, the term "voltage regulator" can refer to a standalone regulator (e.g., a standalone switching converter) or a part of such a regulator (e.g., a smart power stage SPS).

[0058] Power supply Va (240) (Rail-A) is generated by a six-phase buck converter (containing six SPSs: 220-1 to 220-6), while power supply Vb (250) (Rail-B) is generated by a three-phase buck converter (containing three SPSs: 230-1 to 230-3). Nodes / paths 240 and 250 can respectively correspond to... Figure 1 The paths 112A and 112B in the text. Figure 2 The switching nodes 221-1 to 221-6 corresponding to each power stage are also shown. For simplicity, the other power supply circuits used to generate the supply voltage on paths 113, 114, and 115 are not shown. Figure 2 As shown in the document. These smart power stages may be individually or collectively referred to as reference numbers 220 / 230 (depending on the context). Similarly, inductors 225A-1 to 225A-6 and 227B-1 to 227B-3 may be individually or collectively referred to as 225 and 227 (depending on the context). The labeling of other modules / components / signals in this document also follows the same naming convention.

[0059] In one embodiment of this application, each power stage and phase controller is implemented as a separate integrated circuit (IC). However, in other embodiments, the power stages and phase controllers may be implemented using different architectures or integrated designs.

[0060] The phase controller 210 combines one or more power stages operating on the same rail to produce a regulated output voltage. Figure 2 In this example, phase controller 210 operates in conjunction with one or more power stages (i.e., SPSA-1 to SPSA-6) of track A to generate a regulated output voltage Va (240). Similarly, phase controller 210 operates in conjunction with one or more power stages (i.e., SPSB-1 ​​to SPSB-3) of track B to generate a regulated output voltage Vb (250). Therefore, Va (240) and Vb (250) are input as feedback signals to phase controller 210, enabling one or more feedback loops within it to operate to stabilize and regulate these two sets of voltages. Phase controller 210 also receives inductor current information (i.e., the current IL flowing through each inductor 225, numbered 290) from each SPS to support various functions, such as voltage regulation in current-mode control, current limiting, short-circuit protection, and current balancing control of each SPS in the same converter (or on the same track), ensuring that the current generated by each SPS is substantially equal in amplitude. Other signals flowing between phase controller 210 and each SPS will be further described in subsequent paragraphs.

[0061] A combination of phase controller 210 (and its internal circuitry), a smart power stage (SPS), and its corresponding inductors and capacitors constitutes a "phase" of the rail. For example, SPSA-1, inductor 225A-1, capacitor 226A-1, and corresponding portions of phase controller 210 together form a buck converter, which is one phase of a six-phase buck converter. It is worth noting that although the figure shows each phase having its own independent capacitor (e.g., 226A-1), in another embodiment, a single, larger capacitor with a larger capacitance can be configured only at nodes 240 (and 250). Furthermore, in other embodiments, multiple capacitors can be configured near the load (i.e., the circuitry powered by the corresponding supply voltage) to improve output stability and transient response.

[0062] Understandably, the phase controller 210, combined with a set of SPS and external components such as inductors and capacitors, can function as a switching converter to provide a regulated output voltage. Here, the term "switching converter" is defined to include: a standalone switching converter (i.e., a non-multiphase converter), a switching converter within a multiphase voltage regulator or module (which contains multiple independent switching phases), and a portion of a switching converter, such as a smart power stage (SPS).

[0063] The phase controller 210 can be designed to implement Automatic Phase Management (APM). Therefore, the number of power stages (or phases) activated by the phase controller 210 can vary depending on the magnitude of the actual load current. For example, when the load current on a track (e.g., Va 240) is small, the number of power stages activated is relatively small; conversely, when the load current is large, more power stages will be activated to meet output demands and maintain high-efficiency operation.

[0064] For example, when the load current drawn from track A (Va 240) is very low, the phase controller 210 may only activate / operate one power stage, called the "active power stage," to generate Va, while keeping the other five power stages in an "inactive state." Therefore, the phase controller 210 will only generate one set of PWM (Pulse Width Modulation) signals to control the switching of the high-side and low-side switches of this single active power stage to generate Va; while for the other five inactive power stages, the PWM signals will remain in a high-impedance state (Hi-Z). Therefore, the high-side and low-side switches of those five inactive power stages will be off (i.e., not switching).

[0065] Each SPS (or more broadly, a power stage) may include the following components: a high-side switch, a low-side switch, gate drive circuitry for driving both switches, a temperature monitoring circuit, and an inductor current sensing circuit / module for providing information to the phase controller 210 indicating the magnitude of the inductor current (290). The current output by the SPS (and therefore the magnitude of the inductor current) typically depends on the current drawn from the load. However, from an operational perspective, the high-side and low-side switches of the SPS can be considered as components that "drive" the inductor. Under steady-state conditions, the average inductor current equals the load current to maintain the output voltage stable at the desired value. Each SPS receives a power input (all SPSs can share the same power supply), which is connected to the high-side switch (whose detailed structure will be described in a later section). Figure 2 In this specification, the power source is designated as 201, and the voltage is in. In the VRM 110 embodiment of this disclosure, a typical value of Vin is approximately 12 volts (V). Furthermore, the SPS 220 also receives a voltage Vcc via power terminal 202.

[0066] Each SPSA communicates with the phase controller 210 via corresponding signals PWM, SYNC, CS, and TEMP. For example, SPSA-1 connects to the phase controller 210 via signals / paths PWMA-1 (211), SYNC-A (212), CSA-1 (213), and TEMPA (214). SPSA-6 communicates with the phase controller 210 via signals PWMA-6, SYNC-A, CSA-6, and TEMPA (214), although in Figure 2 In the diagram, the connections of PWMA-6, SYNC-A, and CSA-6 to the phase controller are not explicitly shown. Similarly, SPSB-1 ​​is connected to the phase controller 210 via signal / path PWMB-1 (216), SYNC-B (217), CSB-1 (218), and TEMPB (219); while SPSB-3 communicates via PWMB-3, SYNC-B, CSB-3, and TEMPB (219), but... Figure 2 The connection details are also omitted. The connection method between other SPSs and phase controller 210 is the same.

[0067] The TEMP signal is an output (e.g., voltage) of the SPS to the phase controller 210, providing temperature information for the SPS. The phase controller 210 can process the TEMP signal (or the information contained therein) to adjust the output current of that phase or shut down the VRM in the event of an overheating fault. The TEMP outputs of each phase of a converter are connected in parallel via wires and converge to a single input of the phase controller (e.g., TEMPA 214). The maximum value of the TEMP output signal of a phase is driven to this wired connection.

[0068] The SYNC signal is input to the SPS and is used by the phase controller 210 for various purposes, such as waking up the SPS when the power module 110 is powered on, or indicating the power mode of the multiphase converter (e.g., PS2, PS3), i.e., the output current demand state. Typically, all SPSs of the same converter share a single SYNC signal (e.g., SYNC-A 212). When the SYNC signal is set to a high-impedance state (Hi-Z), it indicates that all SPSs should be turned off (i.e., enter an inactive state), and the corresponding supply voltage is no longer generated. In one embodiment, the voltage level of the Hi-Z state is between the logic high (HIGH) and logic low (LOW) of the SYNC signal. When SYNC = Hi-Z, the state machine (not shown) inside the SPS treats it as a "chip disable" signal and accordingly shuts down all modules within the power stage. SYNC = HIGH can be used as a "chip enable" or "chip reset" signal. In the embodiments of this application, SYNC=LOW indicates the operating state of VRM 110 in DCM mode (Discontinuous Conduction Mode).

[0069] The signal CS (current sensing signal) is a signal from the SPS / phase input to the phase controller 210, containing information about the instantaneous magnitude of the current in the phase inductor. This information can be in the form of current, voltage, digital value, etc., depending on the power supply stage and the specific implementation of the phase controller 210. The CS module in the SPS is responsible for performing the current sensing operation and transmitting the signal CS to the phase controller 210.

[0070] In one embodiment of this application, the current sensing module of the power supply stage transmits the sensed inductor current information to the phase controller 210 in the form of a current. This current may be the same magnitude as the inductor current, or (more commonly) a scaled version of the inductor current. Correspondingly, in this embodiment, the phase controller 210 is designed to receive information in the form of a current, and when scaling is used, the scaling factor is known to both the phase controller 210 and the corresponding power supply stage.

[0071] The PWM signal is a signal input from the phase controller 210 to the SPS, and can be considered a "phase control signal" used to control the operation (on and off state) of the power switch in the corresponding phase of the SPS. In one embodiment of this application, the PWM signal is a pulse width modulation (PWM) signal. Therefore, in this embodiment, the PWM signal is a fixed frequency, variable duty cycle signal. The duty cycle of the PWM signal is set by the phase controller 210 to generate the required power supply voltage and / or control / change the current supplied by that phase. For example, the duty cycle of PWMA-1 (211) will be set according to the required Va (240) voltage and the current required by SPSA-1 (220-1). However, in general, the characteristics of the PWM signal may vary depending on the specific implementation details of the power supply 110.

[0072] For example, in another embodiment, the phase controller 210 may employ a constant-on-time control technique to generate Va. In this embodiment, the signal PWM will be a variable-frequency, fixed-pulse-width (fixed-on-time) signal (i.e., a pulse-frequency modulation signal, although PWM is still used herein for reference). The frequency of this signal is typically proportional to the required regulated voltage (Va) and load current. In another embodiment, the signal PWM may switch between a fixed-frequency pulse-width modulation signal and a fixed-on-time variable-frequency signal based on load current requirements, the efficiency required by power supply 110, and other considerations; this design will be understood by those skilled in the art.

[0073] PWM signals can be generated with logic high, logic low, or high impedance (Hi-Z) states. Typically, the logic high and logic low states of a PWM signal correspond to the positive and negative rail voltages of the power supply circuit generating the PWM signal (within the error / noise range), respectively, while the Hi-Z state corresponds to the middle rail voltage (or a voltage range near the middle rail voltage) of the power supply—this is known in the relevant technical field. However, other conventions can be used for the three states of a PWM signal, as those familiar with the relevant technology will understand. Generally, the PWM signal needs to be maintained within the aforementioned voltage range for a predetermined minimum duration for the power supply stage to correctly identify the Hi-Z state.

[0074] The PWM signal controls the on / off state of the high-side switch and low-side switch in the phase / power phase through logic high (HIGH) and logic low (LOW) states. In one embodiment, a logic high level of PWMA-1 turns off the high-side switch in SPSA-1 and turns on the low-side switch; a logic low level of PWMA-1 turns on the high-side switch in SPSA-1 and turns off the low-side switch. The time interval during which the high-side switch is in the on state can be considered as the "first phase" (or "high-side phase"), and the time interval during which the low-side switch is in the on state can be considered as the "second phase" (or "low-side phase"). The first phase and the second phase alternate, thus exhibiting periodicity. The high-side switch and the low-side switch can be considered as periodically "driving" the inductor in the first phase and the second phase, respectively. It should be noted that the terms "first phase" and "second phase" should not be confused with the phase of a multiphase converter (as previously stated).

[0075] The Hi-Z state of the PWM signal informs the power supply stage that it should not generate an output voltage, i.e., it is in a "non-operating state." Therefore, when the PWM is in the Hi-Z state, both the high-side and low-side switches of this stage are off, and the power supply stage can enter a low-power or shutdown mode. Generally, the phase controller 210 is designed to generate a PWM signal that indicates three states, one of which represents the corresponding power supply stage should be in a non-operating state. Those familiar with the relevant technology will understand that this three-state capability can be implemented in different ways. For example, the phase controller 210 can be designed to generate a conventional binary signal, and the power supply stage can determine that the Hi-Z state is when the PWM signal is off (i.e., no PWM signal is generated at all).

[0076] For each SPS of the same converter, the PWM signals can be staggered, meaning there is a phase delay between them, so that the high-side switches of different SPSs on the same rail will not turn on simultaneously. One reason for using this technique is, for example, to ensure that the instantaneous peak current drawn from the input voltage Vin remains low at all times.

[0077] As is known in the relevant technical field, switching converters can operate in one of two modes—Continuous Conduction Mode (CCM) or Discontinuous Conduction Mode (DCM). CCM refers to a mode in which the inductor current flows continuously throughout the entire switching cycle. In CCM, the inductor current is allowed to become negative. Switching converters typically operate at a fixed frequency with a variable duty cycle in CCM mode.

[0078] DCM refers to a mode where the inductor current drops to zero for a certain period of the switching cycle. In DCM, the inductor current is not allowed to become negative. When the inductor current drops to zero, the low-side switch turns off to prevent the inductor current from reversing (negative current), as reverse current would draw current from the load. Therefore, the inductor current will remain zero until the high-side switch turns on in the next PWM cycle. To achieve the desired load current, the switching frequency needs to be changed in DCM mode. For example, when using constant-ON-time control, the time both switches are off increases as the load current decreases, and vice versa.

[0079] Generally, the phase controller 210 operates the power supply stages in continuous conduction mode (CCM) under high load conditions and in discontinuous conduction mode (DCM) under low load conditions. "Low load" as used herein refers to a load on the output that is a small fraction of the rated maximum power (e.g., less than 10%). In DCM mode, the phase controller 210 may only maintain operation on a few power supply stages. The phase controller 210's operation of the power supply stages in DCM mode to improve efficiency is known in the art.

[0080] In one embodiment, in DCM mode, the phase controller 210 maintains only a single power stage in operation and switches it over time to achieve wear leveling. In other words, in DCM mode, when only one power stage is operating, that operating power stage changes periodically (e.g., from SPS-1 to SPS-2), and techniques such as round-robin sequences can be used to evenly distribute the load across the power stages.

[0081] It should be noted that although the following examples are primarily for multiphase switching converters with only one operating power stage in DCM mode, the related techniques disclosed herein are also applicable to stand-alone switching converters, and those skilled in the art will understand this after reading this document.

[0082] Generally, known loss components affecting the overall efficiency of switching converters include: switching loss (loss caused by the power switch being turned on / off), conduction loss (loss caused by voltage drop across the switch), and dead-time loss (loss caused by a short circuit between Vin and ground due to the simultaneous on of two switches during the power supply phase). Among these, parasitic capacitances associated with the switches significantly contribute to some of the losses, such as switching loss, which will be further explained below.

[0083] Both the high-side and low-side switches in the SPS 220 are implemented as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and have associated parasitic capacitances, as is known in the art. During each PWM cycle, in the high-side phase, the SW node voltage rises to Vin, and a charging current flows from the power supply (Vin) through the high-side switch into the corresponding parasitic capacitance. In the low-side phase, when the SW node voltage drops to zero, this parasitic capacitance discharges to ground through the low-side switch. This charging and discharging process of the parasitic capacitance through the corresponding switch results in power loss. Such power / efficiency losses are undesirable, especially when the switching converter is operating under low-load conditions.

[0084] The technology described in this application can improve the efficiency of switching converters while minimizing the resulting losses, especially when the switching converter is operating in discontinuous conduction mode (DCM) and the load current is typically low, this technology has significant advantages.

[0085] Several technical aspects of this application are described in relation to the operation of a switching converter under low-load conditions. The following description continues to illustrate an exemplary implementation of a power supply stage based on the technology disclosed herein.

[0086] 4. Smart Power Stage (SPS)

[0087] Figure 3 This is a block diagram illustrating the power supply stage in a detailed embodiment of this application. The diagram shows the detailed structure of SPSA-1 (220-1), assumed to be the power supply stage operating in DCM mode. Other SPSs can also be implemented with a similar structure to SPSA-1. SPSA-1 includes a gate driver 310, a high-side switch (HS switch) 320, a low-side switch (LS switch) 330, a negative-threshold voltage detector 340, and a zero-current detector 350. Furthermore, Figure 3It also shows inductor 225A-1, output capacitor 226A-1, and equivalent parasitic capacitance 360. When power stage 220 is implemented as an integrated circuit (IC), P51 to P55 represent the SW, SYNC, Vin, Vcc, and PWM pins, respectively. In other implementations (e.g., discrete component form), P51 to P55 represent the corresponding circuit nodes. Vcc (202) is used to power the internal blocks of power stage 220-1. The drain terminal of HS switch 320 is connected to Vin (201), while the source terminal of LS switch 330 is connected to ground. Although for simplicity, Figure 3 Not shown, but power stage 220 may contain other blocks / circuits, such as a level-converter for gate driver 310, a temperature sensor, etc.

[0088] Capacitor 360 is a concentrated representation of the drain-to-source parasitic capacitance of HS switch 320 and LS switch 330. In other words, capacitor 360 represents the equivalent parallel capacitance of the parasitic capacitance between the source and drain terminals of HS switch 320 and LS switch 330. Node 240 provides the supply voltage Va. Figure 3 Only components relevant to understanding the technology disclosed herein are depicted. It is understood that SPS 220-1 may contain more or fewer blocks than shown in Figure 3.

[0089] It should be noted here that a single gate driver block is not necessarily required. Two independent gate drivers can also be used: one to drive the gate of the high-side switch (HS switch) to turn on or off, and the other to drive the gate of the low-side switch (LS switch) to turn on or off.

[0090] The gate driver 310 generates drive signals en-HS 312 and en-LS 313-1 to 313-4 based on the signal PWMA-1 (211) from the phase controller 210. The gate driver 310 determines whether SPS-1 is in DCM mode based on the logic level of the signal SYNCA (212). In one embodiment, when a logic low is received on path 212, the gate driver 310 determines that SPS-1 will operate in DCM mode. The gate driver 310 also receives signals 363 (neg-volt) and 373 (zero-current), the details of which will be described in detail below. Although this embodiment describes the SYNC pin as being used to transmit the operating mode (DCM / CCM) from the phase controller 210 to the SPS 220, those skilled in the art will understand that the operating mode can also be conveniently transmitted through other methods or pins.

[0091] The HS switch 320 is implemented as an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The LS switch 330 is implemented as a multi-gate N-type enhancement MOSFET with four independent gate terminals; details will be provided later. Figure 5 Further explanation is provided below.

[0092] It should be noted here that other implementations of switches with similar characteristics can also benefit from the features described herein. For example, the LS switch 330 may have fewer or more separate gate terminals in other implementations, as those skilled in the art will understand from this document.

[0093] Gate driver 310 provides drive to the gate terminal of the MOSFET. When PWMA-1 is logic high, gate driver 310 generates corresponding voltages on paths 312 (en-HS) and 313-1 to 313-4 (en-LS[1]-en-LS[4]), turning MOSFET 320 on (switch-ON) and MOSFET 330 off (switch-OFF). When PWMA-1 is logic low, gate driver 310 generates corresponding voltages on paths 312 and 313-1 to 313-4, turning MOSFET 320 off and MOSFET 330 on. When PWMA-1 is in the Hi-Z (high impedance or middle rail voltage) state, gate driver 310 generates corresponding voltages on paths 312 and 313-1 to 313-4, turning both MOSFET 320 and MOSFET 330 off. The gate driver 310 drives the switch with an appropriate dead-time interval to ensure that the high-side and low-side switches do not conduct simultaneously, thereby preventing a shoot-through between Vin and ground, which is known in the relevant art. Figure 7 An example illustration of the implementation of the gate driver module will be provided.

[0094] Negative threshold voltage detector 340 is used to detect whether the voltage of "switch node" SW-1 (221) has reached a negative threshold (relative to ground 299). Negative threshold voltage detector 340 is connected to node SW-1 (221) and PWM-1 (211). When PWM-1 is in Hi-Z, if negative threshold voltage detector 340 detects that the voltage of node SW-1 has reached the threshold, negative threshold voltage detector 340 will output logic signal 363 (neg-volt, for example, logic high) to indicate that the voltage of node SW-1 has reached the threshold. When the voltage SW-1 has not yet reached the threshold, negative threshold voltage detector 340 will de-assert the signal neg-volt (363). When PWM-1 is not in Hi-Z state, negative threshold voltage detector 340 will keep neg-volt (363) in the de-assert state. Figure 8 This document will provide an example of how to implement a negative threshold voltage detector.

[0095] A zero-current detector 350 is used to detect whether the inductor current associated with the power supply phase is zero. The zero-current detector 350 receives the magnitude of the inductor current. When the zero-current detector 350 detects that the inductor current is zero, it outputs a logic signal 373 (zero-current, e.g., logic high); otherwise, it holds signal 373 in a deasserted state. The zero-current detector 350 can be implemented using known methods.

[0096] When HS switch 320 is turned on, current flows from Vin through HS switch 320 and inductor 225A-1 associated with SPSA-1 (220-1) to the load (connected at node Va), with the current having an increasing slope. The voltage at node SW (221) rises to Vin (201). When LS switch 330 is turned on, inductor current flows in the loop formed by LS switch 330, inductor 225A-1, and the load, with the current having a decreasing slope. The voltage at node SW (221) drops to zero volts. One cycle of the PWMA-1 signal can be referred to as the "operating cycle" of an SPS or general switching converter. Therefore, in each cycle of PWM (211), the equivalent parasitic capacitance 360 ​​charges Vin through the high-side switch 320 when it is turned on and discharges to zero volts through the low-side switch 330 when it is turned on.

[0097] Whenever the parasitic capacitance 360 ​​is charged (or discharged) through any switch, a corresponding power loss will occur, the value of which is:

[0098] , ------------------Formula (1)

[0099] Where: Cpar is the capacitance of the equivalent parasitic capacitance 360, Vc is the voltage change across the parasitic capacitance 360 ​​during charging (or discharging), and f-sw is the switching frequency of the PWM signal.

[0100] Furthermore, the charging and discharging of the equivalent parasitic capacitance 360 ​​through the switch will cause [damage / discharge] due to the on-resistance of the corresponding switch. The loss (R-ON loss) is known in the relevant art. This loss can be minimized by charging and discharging the parasitic capacitor 360 (at least partially) using an inductor (225-1) instead of a switch. This is because, all other things being equal, the core loss of the inductor is generally less than the R-ON loss caused by charging the parasitic capacitor through the switch, which is known in the relevant art.

[0101] The power losses described above lead to a decrease in the efficiency of the switching converter. Although these losses occur in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM), in DCM the load itself is smaller, so the same amount of loss represents a larger proportion of the load. Therefore, the losses become more significant in DCM.

[0102] According to an embodiment of this application, in the DCM, before the high-side switch (HS switch) 320 is turned on in each PWM cycle, the capacitor 360 is effectively charged to the required fraction of the input voltage Vin (201), rather than fully charged to Vin, to reduce losses. By charging the capacitor to the required fraction before the HS switch is turned on, the time for the HS switch to charge the capacitor 360 is reduced, thereby reducing losses. The low-side switch (LS switch) 330 is briefly turned on at the beginning of each PWM cycle (211) to achieve the above conditions, as will be further described later. Figure 4A As described herein, and refer to where applicable. Figure 3 .

[0103] 5. Reduce power stage losses in DCM mode

[0104] Figure 4A This is a timing diagram (not to scale), exemplarily showing a specific SPS (e.g., in one embodiment of this application). Figure 3 Waveforms of some signals / nodes in SPS-1. Assume SPS-1 is the only power stage operating under DCM. Figure 4A The waveform examples of the voltages of signals PWMA-1 (211), en-LS[1] (313-1), en-HS (312), node SWA-1 (221), and the current IL (290) in inductor 225A-1 are shown. The time intervals t410–t427 and t427–t437 represent two PWM cycles (i.e., the cycle of signal PWM-1 (211-1)). IL-avg represents the average inductor current over the two cycles.

[0105] In one embodiment, each PWM cycle in DCM mode includes the following time periods (in chronological order):

[0106] 1. First low-side phase (LS-phase): LS switch 330 is on, HS switch 320 is off;

[0107] 2. High-end phase (HS-phase, duration T-ON): HS switch 320 is on, LS switch 330 is off;

[0108] 3. Second LS-phase: LS switch 330 is on, HS switch 320 is off; and

[0109] 4. Idle phase: Both switches are closed, and the inductor current is zero.

[0110] As mentioned above, there are corresponding "dead-times" between switching operations: the "first dead-time interval" is between (1) and (2), and the "second dead-time interval" is between (2) and (3).

[0111] According to an embodiment of this application, the duration of the first low-end phase (hereinafter referred to as T-off-1) and the length of the first dead time interval (hereinafter referred to as T-deadtime-1) can be calculated by the phase controller 210 or the SPS 220. The length of T-off-1 is provided by the phase controller 210 to the SPS 220 via path 211. In one embodiment, this configuration information is written into the non-volatile memory (NVM) in the OTP bit of the SPS 220 (and the phase controller 210). For example, a value of "0" ("1") in the NVM bit of the SPS (phase controller) indicates that the SPS can use the PWMA signal received from the phase controller 210 to set T-off-1 and T-deadtime-1; while a value of "1" ("0") indicates that the SPS can calculate the above times itself. The phase controller 210 and the SPS 220 will read this configuration bit from their respective NVMs in a known manner and generate a PWMA / gate drive signal based on the bit.

[0112] exist Figure 4A In the illustrated example implementation (first embodiment), it is assumed that the phase controller 210 is configured to generate a PWMA signal (path 211) indicating the lengths of T-off-1 and T-deadtime-1 (and the length of T-ON). In another embodiment (second embodiment), the SPS 220 calculates the lengths of T-off-1 and T-deadtime-1, while the phase controller 210 specifies the length of T-ON. The PWMA signals generated in the first and second embodiments are respectively as follows: Figure 4A and 4B As shown. Figure 4B The PWM-local signal in the code is a signal generated internally by the SPS 220, which will be discussed later. Figure 7 Detailed explanation follows.

[0113] According to the embodiments of this application, the durations of T-off-1 and T-deadtime-1 are calculated in advance so that when the HS switch 320 is turned on (phase 2), the voltage across the capacitor 360 reaches the required fraction of Vin. Furthermore, in the first low-side phase, only a portion of the LS switches 330 are turned on to reduce losses caused by charging the gate capacitance of the LS switches. In one embodiment, only one-quarter of the LS switches 330 are turned on in the first low-side phase. A detailed explanation of how this switching method reduces losses and improves efficiency will be provided later. Figure 4A Further details are provided below.

[0114] Before time t410, PWMA-1 is in a high-impedance (Hi-Z) state. Therefore, before t410, both en-LS and en-HS are logic low, and the inductor current IL (250) is zero. (Refer to...) Figure 3 When both switches are closed and no current flows through inductor 225A-1, the voltage at node SW-1 and the voltage across capacitor 360 are Va.

[0115] At t410 (the start of a PWM cycle in DCM mode), gate driver 310 receives a logic low on path 211 and accordingly generates a logic low on path en-HS, keeping HS switch 320 in the off state. Gate driver 310 detects the PWMA-1 signal transitioning from high impedance (Hi-Z) to logic low and therefore generates a logic high on path 313-1, and on paths 313-2 to 313-4 (… Figure 4A A logic low level is generated on (not shown), thereby turning on a quarter of the LS switch 330. The time period t410–t413 corresponds to the first LS-phase mentioned above.

[0116] When LS switch 330 is turned on, the voltage at node SWA-1 drops to zero volts, and capacitor 360 begins to discharge through the LS switch. Inductor current IL begins to flow from the load (Va) to SWA-1. As previously described, phase controller 210 pre-calculates the duration of the first low-side phase (t410–t413) and accordingly sets PWMA-1 to logic low for that pre-calculated time. The pre-calculated timing is designed so that at the end of the first low-side phase, the negative inductor current reaches a predetermined magnitude, as will be explained in detail in the following sections. Therefore, at t413, the inductor current reaches the predetermined magnitude “IL-rev”.

[0117] At t413, gate driver 310 receives a high-impedance (Hi-Z) signal on path 211, thereby generating a logic low level on path en-LS[1] and turning off LS switch 330. Gate driver 310 continues to keep HS switch 320 in the off state. When LS switch is off, negative inductor current charges capacitor 360 through inductor 225A-1. Therefore, the voltage at node SWA-1 begins to rise from zero volts to Vin.

[0118] It can be observed that the charging current originates from inductor 225A-1, and within this charging interval (t413–t416), the inductor core loss may also affect the overall efficiency of the switching converter. To minimize the inductor core loss, the maximum inductor current (I-rev) in the first low-side phase should be as small as possible, while ensuring that the parasitic capacitor 360 is effectively charged so that the power loss caused by the parasitic capacitor 360 (PL1 in equation (1)) does not become the main loss. If capacitor 360 must be fully charged to Vin (instead of V-frac), the power loss due to the inductor core loss may exceed the loss reduction achieved by charging the parasitic capacitor through the HS switch.

[0119] Therefore, in the first low-side phase, the inductor current is allowed to reach only a certain magnitude (I-rev) so that when the HS switch is turned on (t416), the voltage at node SWA-1 (and the voltage across capacitor 360) reaches the required fraction of Vin, rather than the full amount of Vin. The required fraction corresponds to the voltage magnitude in... Figure 4A This is denoted as V-frac. In one embodiment, the required fraction is 0.75. Therefore, if Vin is 12 V, then V-frac is 9 V. Although the example uses a fraction value of 0.75, the V-frac value can generally be set to a range of ≥0.4 to slightly less than 1.0.

[0120] At t416, gate driver 310 receives a logic high level on path 211, thereby generating a logic high level on path en-HS, thus turning on the HS switch. Gate driver 310 keeps the LS switch off. When the HS switch is on, the voltage at node SWA-1 rises to Vin, and current flows through HS switch 320 and inductor 225A-1 to the load, increasing until it reaches IL-peak at t419. Therefore, capacitor 360 charges from V-frac voltage to Vin voltage, completing the charging through the HS switch. The time period t416–t419 corresponds to the HS phase described above.

[0121] In constant on-time control techniques, the T-ON duration of the HS phase may be a fixed value, with the PWM frequency proportional to the required regulating voltage (Va) and load current. In other embodiments employing a fixed-frequency, variable-duty-cycle signal, the T-ON duration varies depending on the magnitude of Va and the load current. For example, a higher load current demand results in a longer T-ON duration, and vice versa.

[0122] Referring to equation (1), it can be seen that charging the capacitor to V-frac before turning on the HS switch can make Vc equal to (Vin minus V-frac), thereby significantly reducing the power loss caused by charging the parasitic capacitor 360 through the HS switch.

[0123] Assumption , , If capacitor 360 is charged from zero voltage to Vin (i.e., without using this invention), the power loss is:

[0124] ,

[0125] With this invention, the capacitor is charged only from V-frac to Vin, therefore the power loss is:

[0126] ,

[0127] Therefore, the power loss caused by parasitic capacitance is reduced to 1 / 35 of that without the present invention, so that this loss is no longer the dominant loss.

[0128] At t419, gate driver 310 receives a high-impedance (Hi-Z) signal on path 211, thereby generating a logic low on path en-HS and turning off HS switch 320. During the dead-time, LS switch remains closed. When the HS switch closes, the voltage at node SWA-1 begins to drop from Vin to zero volts. Capacitor 360 begins to discharge (starting from the Vin voltage) to maintain current flow from Vin to the load in inductor 225A-1. Therefore, the inductor current decreases starting at t419.

[0129] When both switches are off, and assuming a sufficiently long dead time, capacitor 360 will fully discharge, while the inductor will attempt to maintain its current, causing the switch node voltage to become negative until the body diode of the low-side MOSFET turns on. When the SWA-1 node voltage is lower than the forward voltage of the body diode between the source and drain of the LS switch (approximately 0.7 volts in this embodiment, referred to as SW-neg), ... Figure 4A When (as shown), the inductor current will flow through the body diode. The current conduction process of the LS switch body diode will be discussed later. Figure 5 Detailed description is provided.

[0130] When the PWM is in Hi-Z and the SWA-1 voltage reaches the negative threshold, the negative threshold voltage detector 340 triggers signal 363 at t422. Figure 4A (Not shown). In response to this trigger, gate driver 310 generates a logic high level on path en-LS[1]-en-LS[4], thereby fully turning on the LS switch. For simplicity, Figure 4A Only en-LS[1] is displayed, but gate driver 310 also generates logic high for paths 313-2 to 313-4.

[0131] At t422, when the LS switch is turned on, the voltage at the SWA-1 node rises to zero volts. The inductor current flows through the LS switch and decreases until it reaches zero at t425.

[0132] In T425, the zero-current detector 350 triggers signal 373 ( Figure 4A (Not shown). In response to this trigger, gate driver 310 generates a logic low level on path en-LS[1]-en-LS[4], turning off the LS switch. The time period t422–t425 corresponds to the second LS-phase described above.

[0133] When the LS switch is off, the voltage at node SWA-1 (and the voltage across the capacitor) rises to Va and remains at Va until the next PWM cycle begins at t427. The time period t425–t427 corresponds to the idle phase described above.

[0134] Figure 4B For another embodiment of the timing diagram (not to scale), an SPS (e.g.) is exemplarily shown. Figure 3 Some signal waveforms of SPS-1 in the model. In this alternative embodiment, it is assumed that SPS 220 calculates the magnitudes of T-off-1 and T-deadtime-1, and receives the T-ON duration from phase controller 210 via path 211. SPS 220 then generates a PWM-local signal from the PWMA-1 signal received via path 211 to drive the switch.

[0135] The time intervals t440–t457 and t457–t467 represent two PWM cycles (i.e., the cycle of the PWMA-1 signal (211)). The voltage and inductor current waveforms of nodes en-LS[1], en-HS, and SW (221) are compared with... Figure 4A The display is the same, so it will not be described again. The PWM-local signal generated by the SPS 220 is the same as... Figure 4AThe PWMA-1 signal is the same (assuming the phase controller calculates T-off-1 and T-deadtime-1).

[0136] The following will continue to describe a specific implementation of the LS switch 330 in the embodiments of this application.

[0137] 6. Specific implementation method of the low-side switch

[0138] Figure 5 This is a schematic diagram illustrating the implementation of the low-side switch (LS switch) in an embodiment of this application. The structure of the LS switch 330 is detailed in the figure. The LS switch 330 is implemented as an N-type enhancement-mode multi-gate MOSFET. In one embodiment, the LS switch 330 comprises four sections, each containing 12 transistors arranged in parallel. For simplicity, only the transistor numbers (510-1 to 510-12) of the first section (topmost layer) are labeled. The drain terminals of all transistors in all sections are interconnected, and similarly, the source terminals of all transistors are interconnected. The gate terminals of all transistors in each section are interconnected, and each section is provided with an independent gate drive terminal. Although the example embodiment shows four sections, each containing 12 transistors, in other embodiments, the LS switch 330 may be designed to contain any suitable number of sections / transistors (based on chip area limitations, Vin, Va, maximum rated power of VRM 110, etc.), which can be easily understood by those skilled in the art upon reading this application.

[0139] Each part receives the corresponding gate drive signal en-LS (313). Therefore, the figure shows four drive signals en-LS[1] (313-1) to en-LS[4] (313-4). Figure 5 It also shows capacitor 360 ( Figure 3 And an effective parasitic gate capacitor 515-1. Capacitor 515-1 represents the equivalent capacitance of the parasitic capacitance between the gate and drain of transistors 510-1 to 510-12. Although not shown in the figure, similar parasitic gate capacitances exist between transistors in other parts of the circuit. Furthermore, although... Figure 5 Not shown, each transistor in the LS switch has a body diode between its source and drain.

[0140] In one embodiment, all transistors in a particular section are turned on when en-LS[x] is logic high, and all transistors in that section are turned off when en-LS[x] is logic low. Therefore, if en-LS[1] is logic high, transistors 510-1 to 510-12 are turned on; if en-LS[1] is logic low, transistors 510-1 to 510-12 are turned off.

[0141] As those skilled in the art will know, LS switches are typically quite large, and therefore, the charging of the parasitic gate capacitance each time the LS switch is turned on results in power loss. (Refer to...) Figure 4A / 4B, it can be seen that the LS switch is turned on twice in each PWM cycle, resulting in losses caused by the additional LS phase (i.e., the newly added first LS phase in this invention). Therefore, one aspect of this application points out that in the first LS phase ( Figure 4A The time period t410–t413 and Figure 4B During the time period t440–t443, only a portion of the switches are turned on, thereby proportionally reducing parasitic gate capacitance (and thus reducing the aforementioned additional losses). In one embodiment, only one-quarter of the LS switch 330 is turned on in the first low-side phase.

[0142] Understandably, because only a portion of the LS switch 330 is turned on, the on-resistance of the switch is greater than that of a fully turned-on switch (all parts conducting), thus resulting in higher I²R losses. However, the parasitic gate capacitance is smaller when the switch is partially turned on, thereby reducing switching losses. Therefore, the on-ratio of the LS switch 330 needs to be designed to achieve an optimal trade-off between I²R losses and switching losses caused by gate capacitance. Those skilled in the art can understand the design principles by reading this application.

[0143] The following will continue to describe the specific implementation methods of the phase controller in the embodiments of this application.

[0144] 7. Phase Controller

[0145] Figure 6 This is a schematic diagram showing the implementation details of the phase controller in an embodiment of this application. The phase controller 210 includes a control module 610, a mode module 615, a PWM generator 620, a phase manager 630, and a logic module 650. For ease of understanding and clarity, power stages 220-1 to 220-6 and the corresponding inductors and capacitors are also shown in the figure. For simplified explanation, Figure 6 Only the 6-phase converters containing power stages SPSA-1 (220-1) to SPSA-6 (220-6) are shown, which together generate voltage Va (240).

[0146] In addition, it should be noted that, Figure 6 Only components relevant to understanding this application are shown. The phase controller 210 may contain more or fewer modules than shown in the figures. Furthermore, for illustrative purposes, the phase controller 210 is described and illustrated as employing a current-mode control technique; however, it should be understood that the phase controller 210 may also employ other types of control techniques. The internal modules of the phase controller 210 may be powered by a power supply not shown.

[0147] Vref represents the target voltage to be provided at node Va (240). Therefore, Vref represents a stable reference DC voltage generated internally by phase controller 210 in a known manner. Control module 610 receives the reference voltage Vref (601), the output voltage Va (240) (or a fraction of Va using a voltage divider network), and generates a voltage Vc (611) representing the difference between Vref (601) and Va (240), which serves as one of the inputs to PWM generator 620. Control module 610 may internally include components such as an error amplifier and a proportional-integral-derivative (PID) controller, as known in the art. Control module 610 may be implemented in a known manner.

[0148] The mode module 615 receives load current information from path 613 and generates a signal "mode" on path 617, indicating whether the SPS should operate in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In one embodiment, the mode module 615 generates a logic high level on path 617 when the load current is less than a predetermined threshold; otherwise, it generates a logic low level. This threshold can be pre-written into the non-volatile memory (NVM) of the phase controller 210 or input by the user in a corresponding manner (not shown). In this embodiment, the predetermined threshold is less than 10% of the maximum rated current. For example, if the maximum rated current is 100 amperes (A), then the predetermined threshold is 10 A. The mode module 615 can be implemented in a known manner.

[0149] The PWM generator 620 generates signals PWM-CLK (621) and SYNC (622) based on the signal Vc (611), the load current demand on path 613, and the mode signal on path 617. Although Figure 6Not shown, the PWM generator 620 may also receive feedback signals (e.g., sensed inductor current, instantaneous value of output voltage Va, etc.) to determine the period (or frequency) and pulse width of the PWM-CLK signal, as is known in the art. Therefore, the control module 610 and the PWM generator 620 work together to maintain the output voltage Va (240) at the desired magnitude indicated by Vref (601). The PWM generator 620 also receives signals T-off-1 (653) and T-deadtime-1 (656), details of which will be described later.

[0150] PWM generator 620 generates the SYNC signal based on the mode signal (617). In one embodiment, when path 617 receives a logic high (indicating DCM), the PWM generator generates a logic low on path 622 (SYNC). In DCM mode, as previously described, the configuration bit in the NVM of phase controller 210 indicates whether phase controller 210 needs to calculate the magnitudes of T-off-1 and T-deadtime-1. PWM generator 620 reads this configuration bit in a known manner and generates a PWM-CLK signal accordingly. Alternatively, mode module 615 may read the configuration bit and send the information to PWM generator 620 via a corresponding path (not shown).

[0151] Specifically, when the configuration bit indication (e.g., a value of "0") indicates that the phase controller 210 does not need to calculate the magnitudes of T-off-1 and T-deadtime-1, the phase controller 210 ignores the inputs on paths 653 and 656 and generates PWM-CLK based solely on input 613. In this embodiment, the PWM generator 620 switches PWM-CLK between high-level (HIGH) and high-impedance (Hi-Z) states, with the high-level duration used to meet load current requirements. Therefore, the PWM generator generates PWM-CLK on path 621 for each PWM cycle ( Figure 4B The waveform generated by the PWMA-1 signal is as follows:

[0152] -Logic high, its duration is determined by input 613;

[0153] - The remaining time of the cycle is in a high impedance state (Hi-Z).

[0154] In another embodiment, when the configuration bit indication (e.g., a value of "1") requires the phase controller 210 to calculate the magnitudes of T-off-1 and T-deadtime-, the phase controller 210 generates PWM-CLK based on signals 653 and 656 in addition to input 613. In this embodiment, the PWM generator 620 switches the PWM-CLK between low, high, and high impedance (Hi-Z) states. Therefore, the PWM generator generates PWM-CLK on path 621 for each PWM cycle ( Figure 4A The waveform generated by the PWMA-1 signal is as follows:

[0155] - Logic Low, whose duration is equal to the value received by channel 653;

[0156] - High impedance state (Hi-Z), the duration of which is equal to the value received by the path 656;

[0157] - Logic high (HIGH), the duration of which is determined by input 613;

[0158] - It is in a high impedance state (Hi-Z) for the rest of the cycle.

[0159] A PWM generator may internally contain components such as a sawtooth waveform generator, a timer, and a comparator. Figure 6 (Not shown) to generate a PWM-CLK signal, as is known in the art. A PWM generator can be implemented in a known manner.

[0160] Phase manager 630 controls the increase or decrease of phase (and therefore power phase) based on values ​​received on path 623 (e.g., load current demand, Vin / Va changes, etc.) and the logic level of the SYNC signal received on path 622. In one embodiment, when path 622 receives a logic low level (i.e., DCM), the phase manager only activates a single power phase. In CCM, the phase manager sends PWM signals in stages to each active SPS. The phase manager enables power phases in a round-robin manner for wear leveling, as previously described.

[0161] The phase manager forwards the PWM-CLK signal (621) to path 211 corresponding to the power stage in operation. Therefore, in the CCM, the phase manager forwards the PWM-CLK signal to multiple paths corresponding to the power stages in operation. The phase manager also forwards the SYNC signal (622) to path 212 for all power stages (SPS-1 to SPS-6). The phase manager can be implemented in a known manner.

[0162] Logic module 650 generates signals T-off-1 (653) and T-deadtime-1 (656). Logic module 650 reads the aforementioned configuration bits from the NVM in a known manner. When the configuration bits indicate that phase controller 210 needs to calculate the magnitudes of T-off-1 and T-deadtime-1, and the mode signal (617) is at a logic high level, logic module 650 performs the corresponding calculations. The calculations of logic module 650 are based on inputs received on path 643, such as the magnitude of Va (240), the magnitude of the voltage to be generated on parasitic capacitor 360 before the HS switch is turned on (which may be a direct value or fraction of Vin), the capacitance value of parasitic capacitor 360, the inductance value of inductor 225, Vin, etc. The values ​​on path 643 may be pre-written into phase controller 210 or input by the user. How logic module 650 calculates the magnitudes of T-off-1 and T-deadtime-1 in one embodiment will be described in detail later in this application.

[0163] Referring back to Figure 3, in order for capacitor 360 to charge to V-frac at t416, the energy built up in inductor 225 during the first low-side (LS) phase duration needs to be transferred to capacitor 360 during the first dead-time interval. Therefore, logic module 650 calculates the magnitude of I-rev using the following formula:

[0164] ,---------------- Formula (2)

[0165] First dead zone time:

[0166] ,

[0167] Where: L is the inductance value of inductor 225 (acting in the active power phase in DCM mode; typically, L is the same for all VRM power phases), and I-rev corresponds to V-frac. Figure 4A The values ​​of L, Cpar, and V-frac are shown in / 4B. These are provided by path 643. Therefore, logic module 650 calculates the size of I-rev.

[0168] Referring back to Figure 4, it can be seen that in the first LS phase, the voltage at the SWA node drops from Va to zero volts, while the inductor current increases from zero to I-rev amperes. Therefore, logic module 650 uses the following formula to calculate the magnitude of T-off-1:

[0169] ------------------Formula (3),

[0170] In the first LS phase: ,

[0171] The values ​​of Va and L are provided by path 643. di equals I-rev minus 0, where I-rev has been calculated by the above formula (2). Therefore, logic module 650 calculates the size of T-off-1.

[0172] Since the voltage change and corresponding energy on capacitor 360 are known, logic module 650 can calculate the magnitude of T-deadtime-1. Another method is to turn on HS switch 320 after the first LS phase, when the SW node voltage reaches V-frac. Generally, the dead time should be long enough to charge capacitor 360 to t416 (before HS switch 320 turns on). .

[0173] As previously stated, the value of V-frac can be chosen to achieve an optimal trade-off between inductor core losses and parasitic capacitance (360) power losses, as will be apparent to those skilled in the art upon reading this application. It is understood that the value of V-frac is interdependent with the minimum peak inductor current (I-rev) required to be established in the first LS phase. If I-rev is too small, it may not provide sufficient charge to capacitor 360 to achieve the target voltage V-frac, while if I-rev is too large, it may result in the aforementioned higher inductor core losses.

[0174] This description will continue to illustrate the implementation details of the gate driver in one embodiment of this application.

[0175] 8. Gate driver block

[0176] Figure 7 shows implementation details of the power stage gate driver block in one embodiment of this application. The gate driver 310 is shown to include an inverter 702, a drive control block 715, a PWM-local generator 720, a multiplexer (MUX) 735, a PWM level converter 745, an SR-latch 750, and an OR gate 765. The PWM level converter 745 further includes a buffer 742, a resistor 743, and an inverter 744. Only the relevant components necessary for understanding this application are shown in the figure. It is understood that the gate driver 310 may include more... Figure 7 Show more or fewer blocks.

[0177] It should be noted that the figure describes the generation of drive signals en-LS [1] – en-LS [4] for LS switch 330. Gate driver 310 will generate drive signal en-HS in a known manner. Specifically, gate driver 310 will keep path en-HS logic high for the T-ON duration specified by path 211.

[0178] Drive control block 715 generates the signal "use-local" (path 717) based on the signal is-DCM received on path 704. As previously described, in DCM mode, SPS 220 can be configured to calculate the magnitudes of T-off-1 and T-deadtime-1 itself, or receive these times from phase controller 210 on path 211. Drive control block 71 reads configuration bits from the NVM of SPS 220 in a known manner and generates the use-local signal based on these configuration bits. When path 704 receives a logical LOW (i.e., CCM mode), the drive control block generates a logical LOW on path 717 (ignoring the OTP bit). When path 704 receives a logical HIGH, if the OTP bit is '1', the drive control block generates a logical HIGH on path 717; otherwise, it generates a logical LOW. Drive control block 715 can be implemented in a known manner.

[0179] The PWM-local generator 720 generates a PWM waveform (path 722, PWM-local) based on the signal PWMA on path 211 and the use-local signal on path 717. Signal 722 corresponds to... Figure 4B The PWM-local signal shown.

[0180] When the path use-local receives a logic HIGH, block 720 calculates the values ​​of T-off-1 and T-deadtime-1 as described above. Of the values ​​required to perform these calculations, the real-time values ​​of Va and Vin can be obtained from the corresponding nodes, while values ​​such as L, Cpar, and V-frac can be read from the NVM or input by the user in a non-displayed manner. Block 720 performs one calculation (e.g., the first time after power-on when use-local is HIGH), stores the result in a register (not displayed), and then uses this stored value to generate a control signal waveform on path 722. Alternatively, block 720 can employ closed-loop control, for example, by monitoring the voltage of the SW node after the first LS phase to generate a PWM-local signal. Although... Figure 7 Not shown in the text, but block 720 may contain components such as timers, counters, and comparators to generate signals on path 722. Those skilled in the art will understand this after reading this application. A functional implementation example of block 720 will be described below.

[0181] During DCM operation, if the gate driver 310 is configured to calculate T-off-1 and T-deadtime-1 locally in the SPS 220, the PWMA signal received from the phase controller 210 via path 211 switches between logic HIGH and Hi-Z states, the duration of each state being determined by the load current demand. In each cycle of PWMA (211), when path 211 receives a rising edge (T-ON start), block 720 starts the first timer for a duration of the pre-calculated T-off-1 and generates the corresponding PWM-local falling edge (logic LOW, first LS phase start). When the first timer ends (first LS phase ends), block 720 starts the second timer for a duration of the pre-calculated T-deadtime-1 and transitions the PWM-local from LOW to Hi-Z. When the second timer ends (first dead time ends), block 720 transitions the PWM-local from Hi-Z to HIGH (i.e., generates the rising edge of the PWM-local).

[0182] Understandably, block 720 will maintain a logic HIGH state on the PWM-local for the duration of T-ON (received by path 211). Therefore, a suitable logic block can be used to measure the T-ON duration, and block 720 can switch the PWM-local from HIGH to Hi-Z based on the measurement. Block 720 will maintain the Hi-Z state until it receives the rising edge (start) of the next cycle of PWMA. Therefore, the PWM-local signal generated by block 720 is related to... Figure 4AThe PWMA-1 in the DCM is the same (meaning that if the phase controller 210 calculates T-off-1 and T-deadtime-1 in the DCM, the PWM-local will be the PWMA-1 signal).

[0183] The multiplexer (MUX) 735 receives the PWMA signal on path 211 and the PWM-local signal on path 722 as inputs, and selects one of them as the output of path 737 (MUX output) based on the logic value of the selection signal 717 (use-local). In one embodiment, when use-local (717) is logic HIGH, the signal of path 722 is selected as the output of path 737; when use-local (717) is logic LOW, the signal of path 211 is selected as the output.

[0184] PWM level converter 745 generates a binary signal on path 747 based on the logic level of the tri-state signal PWMA on path 737. In one embodiment, 743 acts as a weak pull-up resistor (i.e., a very large resistance) to keep the input of inverter 744 LOW unless PWMA is forced to HIGH. Inverter 744 acts as a MOS inverter. Therefore, when path 737 receives a logic LOW, block 745 generates a logic HIGH on path 747; otherwise, it keeps the logic LOW.

[0185] The SR latch 750 receives a set input from the negative-volt (363) signal and a reset input from the zero-current (373) signal. The Q output of the SR latch 750 is provided to paths 313-2 to 313-4.

[0186] The OR gate 765 receives the signal LS-drive (747) and the Q output (753) of the SR latch, and generates an OR output that is connected to path 313-1.

[0187] During runtime, in DCM mode, path 212 (SYNC-A) receives a logical LOW, causing path 704 (is-DCM) to generate a logical HIGH. In this example embodiment, it is assumed that the configuration bit value is '0', indicating that the phase controller 210 calculates the magnitudes of T-off-1 and T-deadtime-1. Therefore, the drive control block generates a logical LOW on path 717. Consequently, the MUX 735 outputs the signal on path 211 as the output of path 737.

[0188] Referring back to Figure 4, the signal state description in each PWM cycle is as follows:

[0189] During the time period t410-t413:

[0190] PWMA (211) / 737 is logic LOW. Therefore, during this time period, signal 747 is logic HIGH, and correspondingly, en-LS [1] is logic HIGH.

[0191] Since the signals neg-volt and zero-current are logic LOW, the Q output of the SR latch is logic LOW. Accordingly, en-LS [2] to en-LS [4] are logic LOW.

[0192] Therefore, in the first LS phase, only 1 / 4 of the LS switch 330 is turned on. Understandably, if the number of LS switch portions turned on differs during the first LS duration, the output of the OR gate 765 can be connected to the corresponding gate drive signal.

[0193] During the time period t413-t416:

[0194] PWMA / 737 is in Hi-Z state. Therefore, during this period, signal 747 is logic LOW.

[0195] Since both the negative-volt and zero-current signals are logic LOW, the Q output of the SR latch is logic LOW, and correspondingly, en-LS [1] to en-LS [4] are logic LOW. Therefore, the LS switch is off.

[0196] During the time period t416-t419:

[0197] PWMA / 737 is at logic HIGH. Therefore, during this time period, signal 747 is at logic LOW.

[0198] Both the negative-volt and zero-current signals are logic LOW, therefore the Q output of the SR latch is logic LOW, and correspondingly, en-LS [1] to en-LS [4] are logic LOW. Therefore, the LS switch is off. Although Figure 7 Not shown in the diagram, but when PWMA is logic HIGH, gate driver 310 generates logic HIGH on path en-HS in a known manner.

[0199] During the time period t419-t422:

[0200] PWMA / 737 is in Hi-Z state. Therefore, during this period, signal 747 is logic LOW.

[0201] The zero-current signal is logic LOW, while the negative-volt signal is set to logic HIGH at t422. Accordingly, the Q output of the SR latch changes to logic HIGH starting from t422. Therefore, en-LS [1] to en-LS [4] are driven to logic HIGH starting from t422. Accordingly, the LS switch is fully open at t422.

[0202] In t425:

[0203] PWMA / 737 remains in Hi-Z state, so signal 747 remains at logic LOW. Signal neg-volt is at logic LOW, while signal zero-current is set to logic HIGH at t425. Accordingly, the SR latch is reset, causing en-LS [1] to en-LS [4] to be driven to logic LOW. Therefore, the LS switch is turned off at t425.

[0204] During the time period t425-t427:

[0205] PWMA / 737 remains in Hi-Z state, therefore signal 747 remains at logic LOW.

[0206] The negative-volt signal is logic LOW, while the zero-current signal remains logic HIGH. Accordingly, the Q output is logic LOW, causing en-LS [1] to en-LS [4] to remain logic LOW. Therefore, the LS switch remains off until the next cycle of PWMA begins.

[0207] While the example embodiments describe a specific technique for generating LS drive signals, other techniques can be used to generate LS drive signals with appropriate modifications to the gate driver circuitry, as will be apparent to those skilled in the art upon reading this application. For example, in another embodiment, a change in the PWMA signal from Hi-Z to logic LOW can be detected, and this change can be used to turn on a portion of the LS switch 330 in the first LS phase.

[0208] Therefore, the technology of this application can reduce losses and improve the efficiency of switching converters under light load conditions.

[0209] The following will continue to describe an example implementation of the negative threshold voltage detector block in the embodiments of this application.

[0210] 9. Negative threshold voltage detector

[0211] Figure 8This is a block diagram of a negative threshold voltage detector implemented in a power stage according to an embodiment of this application. The negative threshold voltage detector 340 includes current sources 805 and 810, resistor 820, N-channel MOSFETs 830 and 840, and inverter 850. Vcc (201) represents the supply voltage (e.g., 3.3V) from outside the SPS 220-1 (e.g., from phase controller 210). The magnitude of voltage V1 (802) is equal to the gate-source threshold voltage (Vt1) of transistor 830 plus a small voltage Vdelta1 (causing the gate voltage of transistor 830 to exceed the value of Vt1).

[0212] Due to the voltage drop Vdelta2 across resistor 820, the gate voltage V2 (804) of transistor 840 is equal to V1 (802) minus Vdelta2. Resistor 820 is sized to make V2 (804) close to the gate-source threshold voltage Vt2 of transistor 840. In one embodiment, V2 = Vt2 minus 0.7V (as shown in Figure 4, denoted as SW-neg).

[0213] Therefore, when the voltage at node SW-1 is higher than the threshold (equal to or greater than the threshold voltage), transistor 840 is turned off, and the output 363 of inverter 850 is logic LOW. However, when SW-1 (221-1) is negative and reaches the magnitude of SW-neg, transistor 840 is turned on, and the output 363 of inverter 850 becomes logic HIGH.

[0214] Although this example embodiment uses Figure 8 The circuit shown is used to detect the negative threshold voltage of the SW node, but it should be understood that alternative embodiments may use other circuits to achieve negative threshold voltage detection.

[0215] 10. Conclusion

[0216] References to "one embodiment," "another embodiment," or similar terms in this specification indicate that a feature, structure, or characteristic related to that embodiment is included in at least one embodiment of this application. Therefore, the appearance of "in one embodiment," "in another embodiment," and similar terms in this specification does not necessarily refer to the same embodiment.

[0217] Although each terminal / node is shown as "connected to" other terminals in the schematics of Figures 1, 2, 3, 5, 6, 7 and 8, it should be understood that in actual applications, the path may contain other components (depending on the specific environment), and therefore these connections can be considered as "electrically coupled" to the same terminals.

[0218] In this application, the power supply terminal and the ground terminal are considered to be constant reference potentials.

[0219] While various embodiments of this application have been described above, it should be understood that these are merely examples and not limitations. Therefore, the scope of this application should not be limited by the above embodiments, but should be defined only by the following claims and their equivalents.

Claims

1. A switching converter, comprising: a high-side switch and a low-side switch connected in series at a switching node and operating together to provide a regulated supply voltage at an output node based on an input voltage received at an input node, the input voltage having a first magnitude, the high-side switch and the low-side switch being connected in series between the input node and a ground terminal providing a constant reference potential, wherein an inductor is coupled between the switching node and the output node, the high-side switch and the low-side switch driving the inductor based on a control signal respectively; and a gate drive module to drive the high-side switch and the low-side switch to turn on or off based on a logic level of the control signal, wherein there is an effective parasitic capacitance between the switching node and the ground terminal, the gate drive module driving the high-side switch and the low-side switch such that, in a cycle of the control signal: at a first time point, the low-side switch is turned on while the high-side switch is turned off; at a second time point following the first time point, the low-side switch is turned off while the high-side switch remains turned off; and at a third time point following the second time point after a delay time, the high-side switch is turned on while the low-side switch remains turned off, wherein by the third time point, a voltage across the effective parasitic capacitance is only a fraction of the first magnitude, and when the high-side switch remains on from the third time point, the voltage across the effective parasitic capacitance further rises to the first magnitude, wherein the fraction is less than one. the cycle of the control signal starts from the first time point, wherein a time length defined by the first time point and the second time point is equal to a first pre-calculated value, such that a current in the inductor reaches a predetermined magnitude at the second time point, wherein the delay time is equal to a second pre-calculated value.

2. The switching converter of claim 1, wherein, the gate drive module is further capable of driving the high-side switch and the low-side switch such that, in the cycle of the control signal:

3. The switching converter of claim 1, wherein, at a fourth time point following the third time point, the high-side switch is turned off and the low-side switch remains turned off; at a fifth time point following the fourth time point, the low-side switch is turned on and the high-side switch remains turned off; at a sixth time point following the fifth time point, the low-side switch is turned off and the high-side switch remains turned off, wherein by the fifth time point, a voltage at the switching node (SW) reaches a first negative threshold voltage, and from the fifth time point, the voltage at the switching node rises to zero during the low-side switch remains on, wherein by the sixth time point, the current in the inductor drops to zero. the effective parasitic capacitance is an equivalent capacitance composed of a first parasitic capacitance between current terminals of the high-side switch and a second parasitic capacitance between current terminals of the low-side switch.

4. The switching converter of claim 1, wherein, ​ 5. The switching converter of claim 3, wherein, The low-side switch includes a plurality of segments configured in parallel, each segment of the plurality of segments including a corresponding plurality of transistors, wherein each transistor includes a first current terminal, a second current terminal, and a control terminal, and the control terminals of the plurality of transistors in the corresponding segment are connected to each other, wherein each segment is controllable by a corresponding common gate drive signal that drives the control terminals of the plurality of transistors in the corresponding segment, wherein when the common gate drive signal of a segment of the plurality of segments is driven to a first logic state, the corresponding plurality of transistors in the segment are turned on; and when the common gate drive signal of the segment of the plurality of segments is driven to a second logic state, the plurality of transistors in the segment are turned off, wherein during a time period between a first time point and a second time point, the common gate drive signals of a first subset of the plurality of segments are driven to the first logic state, and the remaining common gate drive signals are driven to the second logic state, wherein during a time period between the fifth time point and a sixth time point, the common gate drive signals of all segments of the plurality of segments are driven to the first logic state.

6. The switching converter of claim 5, wherein, The switch converter operates in either continuous conduction mode (CCM) or discontinuous conduction mode (DCM) only, wherein the converter operates in CCM when the load current demand exceeds a threshold current; otherwise, the converter operates in DCM, wherein the mode signal is the second logic state when the converter operates in DCM, wherein the first logic state is logic high and the second logic state is logic low.

7. The switching converter of claim 6, wherein, The switch converter further includes: a negative threshold voltage detector that receives the control signal and the switching node voltage and generates a negative threshold crossing signal of the first logic state when the switching node voltage exceeds a first negative threshold; and a zero current detector connected in the inductor current path that generates a zero current indication signal of the first logic state when the inductor current is zero.

8. The switching converter of claim 6, wherein, The switch converter includes a memory for storing a configuration bit, The gate drive module includes: a first inverter coupled to receive the mode signal and generate a first inverter output; a drive control module coupled to receive the first inverter output signal and the configuration bit and configured to generate a local indication signal, wherein the drive control module generates an output of logic high when the first inverter output is logic high and the configuration bit is logic high; a PWM-local generator module coupled to receive the control signal and the local indication signal and to receive a calculation input including the inductance value of the inductor, the size of the effective parasitic capacitance, the desired size, the fraction, and configured to generate a PWM-local signal; wherein the PWM-local generator block calculates the first pre-computed value, the first pre-set size and the second pre-computed value based on the calculated input when the local indication signal is logic high, and the PWM-local generator block generates a PWM-local signal to specify the first time point, the second time point, the third time point, the fourth time point, the fifth time point and the sixth time point; a multiplexer (MUX) coupled to receive the control signal and the PWM-local signal as inputs, and the local indication signal as a selection signal, when the local indication signal is logic low, the MUX forwards the control signal as a MUX output; when the local indication signal is logic high, the MUX forwards the PWM-local signal as the MUX output; a PWM-level converter module coupled to receive the MUX output, and used to generate a low-side drive signal (LS-drive signal), wherein the PWM-level converter generates logic high when the MUX output is logic low, otherwise generates logic low; an SR latch coupled to receive the negative threshold crossing signal at a set input, the zero current indication signal at a reset input, and generate a Q output based on the set input and the reset input; an OR gate coupled to receive the Q output and the LS-drive signal as inputs, and generate an OR output; wherein the OR output is coupled to a common gate drive signal of a first subset of the plurality of segments, and the Q output is coupled to a common gate drive signal of the remaining segments.

9. The switching converter of claim 8, wherein, The negative threshold voltage detector comprises: a resistor; a second inverter; a first current source coupled between a second constant reference potential and a first terminal of the resistor; a first transistor having a first current terminal coupled to a second terminal of the resistor, a second current terminal coupled to the first constant reference potential, and a control terminal coupled to an intersection of the first current source and the first terminal of the resistor; a second transistor having a control terminal coupled to the second terminal of the resistor, a first current terminal coupled to an input of the second inverter, and a second current terminal coupled to the SW node; and a second current source coupled between the second constant reference potential and the input of the second inverter, wherein when an output of the second inverter is logic high, it indicates that a voltage at the switching node is equal to or greater than the first negative threshold voltage; and when the output of the second inverter is logic low, it indicates the opposite.

10. A voltage regulation module (VRM) comprising: a power stage comprising: ​ a high-side switch and a low-side switch connected in series to a switching node and operating together to provide a regulated supply voltage of a desired magnitude at an output node from an input voltage received from an input node, wherein the input voltage is of a first magnitude, the high-side switch and the low-side switch being connected in series between the input node and a ground terminal providing a first constant reference potential, wherein an inductor is connected between the switching node and the output node, wherein the high-side switch and the low-side switch are respectively driven by a control signal to drive the inductor; a gate drive module for driving the high-side switch and the low-side switch to turn on or turn off according to a logic level of the control signal, wherein there is an effective parasitic capacitance between the switching node and the ground terminal, wherein the gate drive module drives the high-side switch to turn on for a first time period and drives the low-side switch to turn on for a second time period in each cycle of the control signal, wherein the first time period is of a magnitude sufficient for the regulated supply voltage to maintain the desired magnitude in steady state, and the gate drive module further drives the low-side switch and the high-side switch such that in the cycle of the control signal: at a first time point, the low-side switch is turned on and the high-side switch is turned off; at a second time point following the first time point, the low-side switch is turned off and the high-side switch remains turned off; at a third time point following the second time point after a delay time, the high-side switch is turned on and the low-side switch remains turned off, wherein by the third time point, a voltage on the effective parasitic capacitance reaches only a fraction of the first magnitude, the fraction being the fraction, and from the third time point, the voltage on the effective parasitic capacitance rises to the first magnitude during the period when the high-side switch is continuously turned on, wherein the fraction is less than one; and a phase controller providing a magnitude of the first time period in the control signal.

11. The voltage regulation module (VRM) of claim 10, wherein, the cycle of the control signal starts from the first time point, wherein a time between the first time point and the second time point is equal to a first pre-calculated value, such that a current of the inductor reaches a predetermined magnitude at the second time point, wherein the delay time is equal to a second pre-calculated value, such that the voltage on the effective parasitic capacitance reaches the fraction of the first magnitude at the third time point.

12. The voltage regulation module of claim 11, wherein, the gate drive module further drives the high-side switch and the low-side switch such that in the cycle of the control signal: at a fourth time point following the third time point, the high-side switch is turned off and the low-side switch remains turned off; at a fifth time point following the fourth time point, the low-side switch is turned on and the high-side switch remains turned off; and at a sixth time point following the fifth time point, the low-side switch is turned off and the high-side switch remains turned off, wherein by the fifth time point, a voltage of the switching node (SW) reaches a first negative threshold voltage, and from the fifth time point, the voltage of the switching node rises to zero during the period when the low-side switch is turned on, wherein by the sixth time point, the inductor current falls to zero.

13. The voltage regulation module of claim 12, wherein, the phase controller comprises: a first memory storing a first configuration bit; a control module coupled to receive the regulated supply voltage and the reference voltage of the desired size and generate an error signal based on a difference between the reference voltage and the regulated supply voltage; a mode module coupled to receive the threshold current and current load information and generate a mode signal of a logic high when the current load is less than the threshold current and a logic low otherwise; a PWM generator module coupled to receive the error signal, the mode signal and the current load information, generate an operation mode indication signal and a common control signal, wherein the PWM generator generates the operation mode indication signal of a logic low when the mode signal is of a logic high; wherein the PWM generator module generates the common control signal based on at least information including the current load; a phase management module coupled to receive the operation mode indication signal, the common control signal and phase management information including the current load, the desired size and the first size, the phase management module generating the control signal and a synchronization (SYNC) signal; and a logic module coupled to receive the mode signal and operation information including the inductance value, the effective parasitic capacitance size, the desired size, the fraction, the logic module generating a first pre-computed value and a second pre-computed value, wherein when the mode signal is of a logic high: the phase management module only operates the power stage in an active state, wherein the phase management module forwards the common control signal as the control signal of the power stage and the phase management module forwards the operation mode indication signal as a synchronization (SYNC) signal of the power stage; wherein when the first configuration bit is of a logic high: the logic module computes the first pre-computed value, the predetermined current size and the second pre-computed value based on the operation information, wherein the PWM generator module generates the common control signal based on the first pre-computed value and the second pre-computed value, wherein the control signal is used to specify the first time point, the second time point, the third time point and the fourth time point.

14. The voltage regulation module of claim 10, wherein, the effective parasitic capacitance is an equivalent capacitance of a combination of a first parasitic capacitance between the high-side switch current terminals and a second parasitic capacitance between the low-side switch current terminals.

15. The voltage regulation module of claim 13, wherein, the low-side switch includes a plurality of parallel configured segments, each segment including a corresponding plurality of transistors, wherein each transistor includes a first current terminal, a second current terminal and a control terminal, and the control terminals of the plurality of transistors in a corresponding segment are connected to each other, wherein each segment is controllable by a corresponding common gate drive signal that drives the control terminals of the plurality of transistors in the corresponding segment, wherein when the common gate drive signal of a segment is in a first logic state, the transistors of the corresponding segment are turned on, and when the signal is in a second logic state, the transistors of the corresponding segment are turned off, wherein during a time between the first time point and the second time point, the common gate drive signals of the segments in the first subset are in the first logic state and the signals of the remaining segments are in the second logic state, Wherein in the time between the fifth time point and the sixth time point, the common gate drive signals of all segments are in the first logic state.

16. The voltage regulation module of claim 15, wherein, The power stage further comprises: a negative threshold voltage detector coupled to receive the control signal and a switching node voltage and generate a logic high negative threshold crossing signal when the switching node voltage exceeds a first negative threshold; a zero current detector coupled in the path of the inductor current and generate a logic high zero current inductor signal when the magnitude of the current is zero.

17. The voltage regulation module of claim 16, wherein, The power stage comprises a second memory storing a second configuration bit, and the gate drive module comprises: a first inverter coupled to receive a synchronization signal and generate a first inverter output; a drive control module coupled to receive the first inverter output and the second configuration bit and generate a logic high local indication signal when the first inverter output is logic high and the second configuration bit is logic high; a PWM-local generator module coupled to receive the control signal, the local indication signal, and a calculation input including an inductance value, an effective parasitic capacitance magnitude, a required magnitude, and a fraction, and generate a PWM-local signal; a multiplexer (MUX) coupled to receive the control signal and the PWM-local signal as inputs and the local indication signal as a selection signal, wherein when the local indication signal is logic low, the MUX forwards the control signal as a MUX output; and when the local indication signal is logic high, the MUX forwards the PWM-local signal as the MUX output; a PWM-level converter module coupled to receive the MUX output and generate a low-side drive signal (LS-drive signal), wherein when the MUX output is logic low, the PWM-level converter generates a logic high; and otherwise generates a logic low; a SR-latch coupled to receive the negative threshold crossing signal as a set input and the zero current indication signal as a reset input and generate a Q output according to the set input and the reset input; an OR gate coupled to receive the Q output and the LS-drive as inputs and generate an OR output, wherein the OR output is connected to the common gate drive signals of a first subset of the segments; and wherein the Q output is connected to the common gate drive signals of the remaining segments of the segments; wherein when the local indication signal is logic high: the PWM-local generator module calculates a first pre-calculated value, a first predetermined magnitude, and a second pre-calculated value according to the calculation input; and wherein the PWM-local generator module generates a PWM-local signal satisfying a first time point, a second time point, a third time point, and a fourth time point. The negative threshold voltage detector comprises:

18. The voltage regulation module of claim 17, wherein, a resistor; a second inverter; a first current source coupled between a second constant reference potential and a first end of the resistor; ​ a first transistor, a first current terminal of the first transistor is coupled to a second terminal of the resistor; wherein a second current terminal of the first transistor is coupled to the first constant reference potential; wherein a control terminal of the first transistor is coupled to a connection point of the first current source and the first terminal of the resistor; a second transistor, a control terminal of the second transistor is coupled to the second terminal of the resistor, wherein a first current terminal of the second transistor is coupled to an input of the second inverter, wherein a second current terminal of the second transistor is coupled to the switching node; and a second current source, coupled between a second constant reference potential and the input of the second inverter, wherein when the output of the second inverter is logic high, it indicates that the voltage of the switching node is greater than or equal to the first negative threshold voltage, and when the output of the second inverter is logic low, it indicates the opposite case.

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