Signal synchronization method and device, equipment and storage medium

Abstract

The invention provides a signal synchronization method, apparatus and device, and a storage medium. The method comprises the steps of processing an acquired broadband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result; determining a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result; processing the first feedback gain to obtain a second carrier frequency offset estimation value, and generating a second phase-locked loop compensation result according to the second carrier frequency offset estimation value; determining a second feedback gain according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result; determining a first code loop compensation result and a first frequency-locked loop carrier compensation result according to the second feedback gain; demodulating and decoding the first code loop compensation result and the first frequency-locked loop carrier compensation result to obtain message information; the method is used for realizing high-precision phase tracking while eliminating most of frequency dynamics, effectively isolating noise through a gain adaptive mechanism, and remarkably improving the locking speed and tracking stability.

Description

Technical Field

[0001] This application relates to the field of satellite signal synchronization, and in particular to a signal synchronization method, apparatus, device and storage medium. Background Technology

[0002] Existing spread spectrum tracking algorithms are primarily designed for high-orbit or narrowband satellites and are not entirely applicable to low-orbit satellites. For low-orbit satellites, the Doppler frequency shift of the signal carrier exhibits high dynamic characteristics. Combined with carrier frequency jumps, this can trigger drastic Doppler agility, severely impacting the stability and tracking accuracy of the carrier tracking loop. Large Doppler frequency dynamic changes can lead to unstable tracking or even loss of lock in traditional carrier phase-locked loops (PLLs). Furthermore, Doppler frequency agility is equivalent to introducing a frequency step signal at the input of the carrier tracking loop, causing the loop to continuously enter the transient response process of frequency step, resulting in unstable tracking or even loss of lock.

[0003] Secondly, in the traditional fixed-loop gain design, the phase detector output is the same for different frequency domain steps. Any value between; based on the output of the phase detector, under-adjustment will occur when the signal frequency difference is large, which greatly increases the lock-in time of the loop; if the lock-in time spans the sawtooth cycles of multiple phase detector output signals, misadjustment will occur, causing the entire adjustment process to exhibit cycle slip phenomenon; based on the output of the phase detector, over-adjustment will occur when the signal frequency difference is small, causing the output signal oscillation to intensify, ultimately leading to loop lockout. Summary of the Invention

[0004] This application provides a signal synchronization method, apparatus, device, and storage medium that can achieve high-precision phase tracking while eliminating most frequency dynamics, and effectively isolate noise through a gain adaptive mechanism, significantly improving locking speed and tracking stability.

[0005] In a first aspect, this application provides a signal synchronization method, comprising: The acquired broadband radio frequency signal is processed to obtain the first carrier frequency offset estimate and the first phase-locked loop compensation result; The first feedback gain is determined based on the first carrier frequency offset estimate and the first phase-locked loop compensation result; The first feedback gain is processed to obtain a second carrier frequency offset estimate, and a second phase-locked loop compensation result is generated based on the second carrier frequency offset estimate. The second feedback gain is determined based on the second carrier frequency offset estimate and the second phase-locked loop compensation result; The first code ring compensation result and the first frequency-locked ring carrier compensation result are determined based on the second feedback gain; The first code ring compensation result and the first frequency-locked ring carrier compensation result are demodulated and decoded to obtain the message information.

[0006] In one or more possible embodiments, determining the first feedback gain based on the first carrier frequency offset estimate and the first phase-locked loop compensation result includes: The first carrier frequency offset estimate is compared with the carrier loop bandwidth to determine the first inter-frequency error; The first carrier frequency offset estimate is compared with the first phase-locked loop compensation result by sign comparison to determine the first loop feedback direction; The first feedback gain is determined based on the first inter-frequency error and the first loop feedback direction.

[0007] In one or more possible embodiments, the processing of the acquired broadband radio frequency signal to obtain a first carrier frequency offset estimate and a first phase-locked loop compensation result includes: The frequency-locked loop carrier NCO is initialized based on the initial carrier compensation results and the initial phase-locked loop compensation results; The initial demodulation signal is determined based on the broadband radio frequency signal and the first local signal generated by the frequency-locked loop carrier NCO; The first despread signal is determined based on the initial demodulation signal and the initial code ring compensation result, and the first integral clearing result is generated based on the first despread signal; Calculate the incoherent accumulation result based on the first integral clearing result, and obtain time synchronization information based on the incoherent accumulation result; The estimated value of the first carrier frequency offset and the compensation result of the first phase-locked loop are determined based on the time synchronization information.

[0008] In one or more possible embodiments, processing the first feedback gain to obtain a second carrier frequency offset estimate includes: The broadband radio frequency signal is compensated based on the first feedback gain to generate a first demodulated signal; The first feedback gain is subjected to code ring filtering, and the second code ring compensation result is determined based on the filtered first feedback gain and the unit pseudocode Doppler enhancement. The second despread signal is calculated and generated based on the first demodulated signal and the second code ring compensation result, and the second despread signal is accumulated to obtain the second integral clearing result; The second carrier frequency offset estimate is generated based on the second integral clearing result.

[0009] In one or more possible embodiments, the step of compensating the broadband radio frequency signal according to the first feedback gain to generate the first demodulated signal includes: Multiply the first feedback gain by the unit carrier Doppler boost to obtain the carrier Doppler compensation value; The carrier Doppler compensation value, the acquisition prediction Doppler frequency, and the carrier frequency fixed frequency word offset are added together to obtain the carrier compensation value. The second frequency-locked loop carrier compensation result is determined based on the carrier compensation value and the terminal operating clock frequency. The second local signal is determined based on the second frequency-locked loop carrier compensation result; The second local signal and the broadband radio frequency signal are mixed to generate a first demodulated signal.

[0010] In one or more possible embodiments, generating a second phase-locked loop compensation result based on the second carrier frequency offset estimate includes: The second integral clearing result is phase-rotated to obtain the third integral clearing result; Based on the second carrier frequency offset estimate and the third integral clearing result, a carrier phase discrimination result is generated; Phase filtering is performed on the carrier phase discrimination result to generate a second phase-locked loop compensation result.

[0011] In one or more possible embodiments, determining the first code ring compensation result and the first frequency-locked loop carrier compensation result based on the second feedback gain includes: The first code ring compensation result is generated based on the second feedback gain and the second integral clearing result; The second feedback gain is processed by the frequency-locked loop carrier NCO to generate the first frequency-locked loop carrier compensation result.

[0012] In one or more possible embodiments, determining the second feedback gain based on the second carrier frequency offset estimate and the second phase-locked loop compensation result includes: The second carrier frequency offset estimate is compared with the carrier loop bandwidth to determine the second inter-frequency error; The second carrier frequency offset estimate is compared with the second phase-locked loop compensation result by sign comparison to determine the feedback direction of the second loop; The second feedback gain is determined based on the second inter-frequency error and the second loop feedback direction.

[0013] Secondly, this application also provides a signal synchronization device, comprising: The signal processing module is used to process the acquired broadband radio frequency signal to obtain the first carrier frequency offset estimate and the first phase-locked loop compensation result; The first feedback gain determination module is used to determine the first feedback gain based on the first carrier frequency offset estimate and the first phase-locked loop compensation result; The update module is used to process the first feedback gain to obtain a second carrier frequency offset estimate, and generate a second phase-locked loop compensation result based on the second carrier frequency offset estimate. The second feedback gain determination module is used to determine the second feedback gain based on the second carrier frequency offset estimate and the second phase-locked loop compensation result. The compensation result determination module is used to determine the first code ring compensation result and the first frequency-locked loop carrier compensation result based on the second feedback gain; The message information acquisition module is used to demodulate and decode the first code ring compensation result and the first frequency-locked ring carrier compensation result to acquire message information.

[0014] Thirdly, this application also provides an electronic device, the electronic device comprising: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform any of the methods in the first aspect.

[0015] Fourthly, this application also provides a computer storage medium storing a computer program for causing a computer to perform any of the methods described in the first aspect.

[0016] According to the signal synchronization method, apparatus, device and storage medium provided in this application, high-precision phase tracking can be achieved while eliminating most frequency dynamics, and noise can be effectively isolated through gain adaptive mechanism, significantly improving locking speed and tracking stability. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0018] Figure 1 This is a diagram of a conventional signal synchronization module according to an embodiment; Figure 2 This is a flowchart of a signal synchronization method provided according to an embodiment; Figure 3 This is a block diagram of a signal synchronization method provided according to an embodiment; Figure 4 A diagram of a signal synchronization device according to an embodiment is provided; Figure 5 This is a schematic diagram of an electronic device according to an embodiment; Figure 6 This is a schematic diagram of a computer storage medium provided according to an embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0020] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0021] Furthermore, in the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0022] Low Earth Orbit (LEO) satellites are artificial satellites that operate in orbits approximately 300 to 2000 kilometers above the Earth's surface. The "low" in LEO is relative to medium Earth Orbit (MEO) and high Earth Orbit (HEO) satellites. To overcome Earth's gravity and avoid re-entering the atmosphere, LEO satellites must orbit the Earth at extremely high speeds (approximately 7.8 km / s). Relative to users on the ground, LEO satellites rapidly rise from the horizon, fly overhead, and then set back towards the horizon on the other side. This high-speed relative motion generates a significant and rapidly changing "Doppler frequency shift." For a fixed point on the ground, the "visible time" (from rise to fall) of a LEO satellite is typically only a few minutes to a dozen minutes. This means that terminal equipment must acquire and stably track the satellite signal within a very short time; otherwise, the signal will be lost.

[0023] For satellite spread spectrum signal tracking algorithms, existing solutions mainly target high-orbit or narrowband satellites for acquisition and tracking. For low-orbit satellites, Doppler frequency dynamics and Doppler frequency agility caused by carrier frequency jumps are the main factors affecting the characteristics of spread spectrum carrier tracking loops. Doppler frequency dynamics can lead to unstable tracking or even loss of lock in traditional carrier phase-locked loops. Simultaneously, Doppler frequency agility is equivalent to introducing a frequency step signal at the input of the carrier tracking loop, causing the carrier tracking loop to continuously enter the transient response process of frequency step, thus leading to unstable loop tracking or even loss of lock.

[0024] Furthermore, in traditional fixed-loop-gain designs, the phase detector output is the same for different frequency steps. Any value between these ranges. For the same phase detector output signal, under-adjustment can occur when the signal frequency difference is large, increasing the loop lock-in time. Furthermore, when the lock-in time spans multiple sawtooth cycles of the phase detector output signals, mis-adjustment will occur, resulting in cycle slippage throughout the adjustment process. For the same phase detector output signal, over-adjustment can occur when the signal frequency difference is small, causing increased oscillation in the system output signal and leading to loop lockout.

[0025] Existing typical signal synchronization methods, specifically as follows: Figure 1 As shown, a typical baseband signal tracking loop structure is illustrated. Continuous tracking of the input signal is achieved through the coordinated operation of the carrier tracking loop and the code tracking loop. In the carrier tracking loop, the carrier loop discriminator calculates the error based on the phase-rotated signal. After smoothing by the carrier loop filter, the error drives the carrier loop NCO to adjust the output frequency, forming a closed-loop control. In the code tracking loop, the code loop discriminator estimates the code phase deviation through the processed signal. The deviation is then filtered by the code loop filter and used to control the code loop NCO to adjust the code generation rate. Tracking jitter in the carrier loop is directly transmitted to the code loop through the code NCO offset, affecting code measurement accuracy. Furthermore, code loop instability reduces the input signal quality of the carrier discriminator, potentially triggering a chain reaction of track loss. Secondly, loop performance is limited by the fixed filter bandwidth setting: a wider bandwidth is needed to adapt to dynamic environments, while a narrower bandwidth is needed to suppress noise. This contradiction makes it difficult for traditional loops to maintain optimal performance in complex environments. In addition, under weak signal conditions, when correlation peaks are submerged by noise, the discriminator output error increases significantly, easily leading to track loss. Once track loss occurs, a long time is required to re-establish tracking.

[0026] To address the aforementioned problems, this application provides a signal synchronization method applied to a terminal, specifically as follows: Figure 2 As shown, it includes: Step 201: Process the acquired broadband radio frequency signal to obtain the first carrier frequency offset estimate and the first phase-locked loop compensation result; In one or more possible embodiments, this application is applied to a terminal, specifically to the signal receiving and processing module within the terminal, to achieve robust signal synchronization and demodulation under high dynamic and weak signal conditions, providing accurate baseband signals for subsequent navigation information calculation or data communication; the aforementioned broadband radio frequency signal is transmitted by a satellite, and after receiving the broadband radio frequency signal, the terminal processes it, down-converting it by the radio frequency front-end and converting it from analog to digital to a digital intermediate frequency signal S. n and the digital intermediate frequency signal S n After processing, the estimated value of the first carrier frequency offset and the compensation result of the first phase-locked loop are output.

[0027] In one or more possible embodiments, processing the acquired broadband radio frequency signal to obtain a first carrier frequency offset estimate and a first phase-locked loop (PLL) compensation result includes: initializing the frequency-locked loop carrier NCO based on the initial carrier compensation result and the initial PLL compensation result; determining an initial demodulation signal based on the broadband radio frequency signal and the first local signal generated by the frequency-locked loop carrier NCO; determining a first despreading signal based on the initial demodulation signal and the initial code ring compensation result, and generating a first integral clearing result based on the first despreading signal; calculating an incoherent accumulation result based on the first integral clearing result, and obtaining time synchronization information based on the incoherent accumulation result; determining the first carrier frequency offset estimate and the first PLL compensation result based on the time synchronization information; since the first integral clearing result is a complex signal (containing in-phase I and quadrature Q components), the phase will be randomly rotated due to the influence of the residual carrier frequency offset. In order to eliminate this phase uncertainty and extract stable signal power, it is necessary to square the modulus of each integral clearing result (i.e., calculate I² + ...). The Q² or absolute value operation is used to convert complex signals into positive real numbers representing signal energy, thus ensuring that subsequent accumulation is unaffected by phase jumps. Then, these real energy values ​​obtained over multiple code periods are accumulated to obtain an incoherent accumulation result. This accumulation process is essentially an accumulation and averaging of signal energy, effectively improving the signal-to-noise ratio and making weak synchronization characteristics stand out in a noisy background. Peak detection is then performed on the incoherent accumulation result sequence. The receiver slides along the local code phase and repeats the incoherent accumulation process at each possible phase offset point. The despreading effect is optimal and the signal energy is maximized when the phase of the local code is perfectly aligned with the phase of the spreading code of the input signal. At this point, the corresponding incoherent accumulation result will exhibit a significant peak. The location of this peak indicates the precise arrival time or frame boundary of the signal, thereby obtaining time synchronization information. Based on this time synchronization information, a first local signal and a digital intermediate frequency signal are generated. Carrier frequency identification results Carrier phase identification results The carrier frequency is identified by a frequency-locked loop filter. Filtering is performed to obtain the estimated value of the first carrier frequency offset. The carrier phase discrimination result is obtained through a phase-locked loop filter. Filtering is performed to obtain the compensation result of the first phase-locked loop. .

[0028] Step 202: Determine the first feedback gain based on the first carrier frequency offset estimate and the first phase-locked loop compensation result; In one or more possible embodiments, the first carrier frequency offset estimate is compared with the carrier loop bandwidth to determine the first inter-frequency error; the first carrier frequency offset estimate is compared with the first phase-locked loop compensation result by sign comparison to determine the first loop feedback direction; and the first feedback gain is determined based on the first inter-frequency error and the first loop feedback direction. The specific formula is as follows:

[0029] Among them, in this application Take as , Take as , Take as , where n represents the sampling time; Where sig represents the carrier loop bandwidth, and sig represents the estimated value of the first carrier frequency offset. Compensation result of the first phase-locked loop The sign comparison result, if the first carrier frequency offset estimate is... Compensation result of the first phase-locked loop If the sign comparison results are the same, then sig is positive; otherwise, it is negative. Specifically, when the estimated value of the first carrier frequency offset is determined... The absolute value is greater than The following formula will only be used if sig < 0:

[0030] As long as the first carrier frequency offset estimate is not simultaneously determined... The absolute value is greater than When sig < 0, the following formula is used:

[0031] Existing solutions, under fixed gain, suffer from insufficient loop correction capability for large frequency steps (large initial frequency offset), resulting in excessively small adjustment steps and slow convergence. This application provides a method to determine the magnitude of the generated feedback gain by comparing the estimated carrier frequency offset with a preset loop bandwidth threshold to generate inter-frequency error. When the estimated carrier frequency offset is large, the calculated feedback gain D(n) increases significantly, effectively increasing the "total open-loop gain" of the loop. This allows for a larger frequency adjustment step size of the NCO, quickly narrowing the frequency difference between the local carrier (generated by the frequency-locked loop carrier NCO) and the input signal (wideband RF signal transmitted by the satellite), effectively overcoming under-adjustment and significantly shortening the lock-in time. Existing solutions, under fixed gain, exhibit excessive gain when the frequency difference is small, causing the loop to "overshoot," resulting in damped oscillations or continuous oscillations near the equilibrium point. These oscillations degrade demodulation performance and, in severe cases, cause the loop to lose its locked state. When the frequency offset estimate decreases, the calculated feedback gain D(n) also decreases. At this time, the loop enters "fine-tuning" mode, and the frequency adjustment step size of the NCO becomes very precise, improving tracking stability and noise immunity. Cycle slips often occur when the phase detector output of the phase-locked loop crosses its linear range boundary (such as jumping from +π to -π). In the case of rapid frequency changes or noise, a fixed high gain may "push" the phase to cross the boundary quickly, causing the loop to produce an incorrect 2π phase jump. This application solves the cycle slip problem by checking whether the signs of the carrier frequency offset estimate and the phase-locked loop compensation result are consistent. If the signs are the same, it means that the directions of the frequency difference and the phase difference are consistent, and the loop is adjusting towards the correct locking direction. If the signs are opposite, it means that the directions of the frequency difference and the phase difference are inconsistent, and the loop may be in a state of "overshooting" and then correcting back, or on the edge of a cycle slip. At this time, the adaptive module will adjust the feedback gain according to the formula for calculating the feedback gain, thereby effectively avoiding the occurrence of cycle slips.

[0032] Step 203: Process the first feedback gain to obtain the second carrier frequency offset estimate, and generate the second phase-locked loop compensation result based on the second carrier frequency offset estimate; In one or more possible embodiments, the first feedback gain is first multiplied by a unit carrier Doppler boost to obtain a carrier Doppler compensation value; the carrier Doppler compensation value and the capture prediction Doppler frequency are then... and carrier frequency fixed frequency word offset The carrier compensation values ​​are added together to obtain the carrier compensation value; based on the carrier compensation value and the terminal operating clock frequency, the second frequency-locked loop carrier compensation result is calculated. According to the second frequency-locked loop carrier compensation result Determine the second local signal; then, compare the second local signal with the broadband radio frequency signal (here, the broadband radio frequency signal is essentially a processed broadband radio frequency signal, i.e., a digital intermediate frequency signal). The system performs frequency mixing to generate a first demodulated signal. Simultaneously, it performs code loop filtering on the first feedback gain and determines a second code loop compensation result based on the filtered first feedback gain and the unit pseudo-code Doppler gain. Specifically, it calculates the pseudo-code Doppler compensation value based on the filtered first feedback gain and the unit pseudo-code Doppler gain, and then generates a second code loop compensation result based on the pseudo-code Doppler compensation value, the code NCO nominal deviation, and the terminal operating clock frequency. After determining the second code loop compensation result, it calculates and generates a second despread signal based on the first demodulated signal and the second code loop compensation result, and accumulates the second despread signal to obtain a second integral clearing result.

[0033] In one or more possible embodiments, the second integral clearing result is processed by a frequency discriminator and a phase-locked loop filter to obtain a second carrier frequency offset estimate. Simultaneously, the second integral clearing result is phase-rotated to obtain a third integral clearing result. The mixed signal (first demodulated signal) is not completely zero-frequency, but has a small, slowly changing residual frequency. This residual frequency difference leads to a key problem: the direction of the phase vector represented by the second integral clearing result will slowly rotate over time. By performing a reverse mathematical rotation on the second integral clearing result through the phase rotation step, the vector rotation effect caused by the residual frequency difference can be actively canceled in the digital domain. After obtaining the above-mentioned third integral clearing result, the third integral clearing result and the second carrier frequency offset estimate are processed by a phase discriminator to obtain a carrier phase discrimination result. The carrier phase discrimination result is then filtered by a phase-locked loop filter to obtain a second phase-locked loop compensation result.

[0034] In one or more possible embodiments, the second carrier frequency offset estimate is used to assist in updating the phase-locked loop (PLL) NCO carrier generator. Specifically, the PLL NCO carrier generator is dynamically configured and driven by a real-time changing digital control signal (the second carrier frequency offset estimate) from the PLL, so that the frequency of the output signal of the PLL NCO carrier generator is close to the data intermediate frequency signal in advance.

[0035] In one or more possible embodiments, the total control word of the phase-locked loop (PLL) carrier NCO = PLL's own phase control word + (PLL frequency estimate × scaling factor); the specific auxiliary update process is as follows: the PLL continues to operate, and the PLL loop filter outputs a smoothed and denoised second carrier frequency offset estimate, representing the remaining relatively stable frequency difference between the current intermediate frequency signal and the PLL carrier NCO; then, the second carrier frequency offset estimate is converted and scaled according to the scaling factor, which is related to the phase accumulator bit width of the PLL carrier NCO and the clock frequency of the FPGA, and the specific calculation formula is as follows:

[0036] Where K represents the calculated scaling factor, and N represents the phase accumulator bit width of the frequency-locked loop carrier NCO. This represents the clock frequency of the FPGA; the scaling factor converts the second carrier frequency offset estimate (i.e., the frequency-locked loop frequency estimate) into a frequency control word increment that the PLL carrier NCO can understand; the scaled frequency-locked loop frequency control word is directly added to the phase control word output by the PLL loop filter to obtain the superimposed total control word, and then the PLL carrier NCO adjusts the frequency and phase of the output signal according to the superimposed total control word.

[0037] Step 204: Determine the second feedback gain based on the second carrier frequency offset estimate and the second phase-locked loop compensation result; In one or more possible embodiments, the second carrier frequency offset estimate is compared with the carrier loop bandwidth to determine the second inter-frequency error; the second carrier frequency offset estimate is compared with the second phase-locked loop compensation result by sign comparison to determine the second loop feedback direction; the second feedback gain is determined based on the second inter-frequency error and the second loop feedback direction; the second feedback gain is generated according to the same method as generating the first feedback gain, and the specific formula is not elaborated here.

[0038] Step 205: Determine the first code ring compensation result and the first frequency-locked ring carrier compensation result based on the second feedback gain; In one or more possible embodiments, a second pseudo-code Doppler compensation value is generated based on the second feedback gain and the second integral clearing result. Then, a first code ring compensation result is generated based on the second pseudo-code Doppler compensation value, the code NCO nominal deviation, and the terminal operating clock frequency. Simultaneously, the second feedback gain is first multiplied by the unit carrier Doppler augmentation to obtain the carrier Doppler compensation value. The carrier Doppler compensation value and the acquisition prediction Doppler frequency are then... and carrier frequency fixed frequency word offset The carrier compensation values ​​are added together to obtain the carrier compensation value; based on the carrier compensation value and the terminal operating clock frequency, the first frequency-locked loop carrier compensation result is calculated.

[0039] Step 206: Demodulate and decode the first code ring compensation result and the first frequency-locked ring carrier compensation result to obtain the message information.

[0040] In one or more possible embodiments, demodulation and decoding are performed based on the first code ring compensation result and the first frequency-locked ring carrier compensation result to generate compensated incoherent integral information and time information. Finally, the message information is decoded based on the incoherent integral information and time information.

[0041] This application also provides a structural schematic diagram of an example of a signal receiving and processing device, specifically as follows: Figure 3 As shown, it includes a phase-locked loop, a frequency-locked loop, and a feedback gain calculation module. The specific processing flow after receiving the broadband radio frequency signal transmitted by the satellite is as follows: First, the broadband radio frequency signal received by the terminal antenna is processed by the radio frequency front-end to output a digital intermediate frequency signal. Then, based on the digital intermediate frequency signal A first integral clearing result is generated; a first phase-locked loop (PLL) compensation result and a first carrier frequency offset estimate are generated based on the first integral clearing result; a first feedback gain is generated based on the first PLL compensation result and the first carrier frequency offset estimate; a carrier compensation result is generated based on the first feedback gain, the capture prediction Doppler frequency, and the carrier frequency fixed frequency word offset, thereby generating a carrier frequency offset compensated digital baseband signal integral clearing result (a second integral clearing result); a second carrier frequency offset estimate and a second PLL compensation result are generated based on the compensated digital baseband signal demodulation result; a code ring NCO compensation result is generated based on the second carrier frequency offset estimate, the second PLL compensation result, and the digital baseband signal; finally, demodulation and decoding are performed based on the carrier compensation result and the code ring compensation result to obtain message demodulation information.

[0042] According to the signal synchronization method provided in this application, a tracking structure consisting of a cascaded frequency-locked loop (FLL) and a phase-locked loop (PLL) is adopted. The FLL quickly eliminates the large dynamic Doppler frequency offset of the signal, while the PLL focuses on high-precision carrier phase tracking, effectively solving the problem of easy loss of lock-in in traditional PLLs under high-speed dynamic environments. The two loops use independent carrier generators, achieving noise isolation between the preceding and following stages and reducing mutual interference. In addition, a feedback gain adaptive adjustment module is introduced into the loop, which can dynamically optimize the loop gain according to the frequency offset and the frequency and phase discrimination symbols, significantly improving the locking speed and tracking stability of the loop. This overcomes the under-adjustment, over-adjustment, and cycle slip phenomena existing in fixed-gain designs, thereby ensuring the reliability and accuracy of signal synchronization in low-Earth orbit satellite broadband communication systems.

[0043] Corresponding to the above-mentioned signal synchronization method, the present invention also proposes a signal synchronization device, specifically as follows: Figure 4 As shown, it includes: The signal processing module 401 is used to process the acquired broadband radio frequency signal to obtain the first carrier frequency offset estimate and the first phase-locked loop compensation result. The first feedback gain determination module 402 is used to determine the first feedback gain based on the first carrier frequency offset estimate and the first phase-locked loop compensation result; The update module 403 is used to process the first feedback gain to obtain the second carrier frequency offset estimate, and generate the second phase-locked loop compensation result based on the second carrier frequency offset estimate. The second feedback gain determination module 404 is used to determine the second feedback gain based on the second carrier frequency offset estimate and the second phase-locked loop compensation result. The compensation result determination module 405 is used to determine the first code ring compensation result and the first frequency-locked ring carrier compensation result based on the second feedback gain; The message information acquisition module 406 is used to demodulate and decode the first code ring compensation result and the first frequency-locked ring carrier compensation result to acquire message information.

[0044] Since the device embodiments of the present invention correspond to the method embodiments described above, details not disclosed in the device embodiments can be referred to in the method embodiments described above, and will not be repeated in the present invention.

[0045] This application also provides an electronic device, including at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the above-described signal synchronization method.

[0046] like Figure 5 As shown, the device includes a processor 501, a memory 502, a communication interface 503, and a bus 504. The processor 501, memory 502, and communication interface 503 are interconnected via the bus 504.

[0047] Processor 501 is configured to read instructions from memory 502 and execute them, so that at least one processor can execute the signal synchronization method provided in the above embodiments.

[0048] The memory 502 is used to store various instructions and programs for the signal synchronization method provided in the above embodiments.

[0049] Bus 504 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0050] Processor 501 can be a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), or any combination of CPU, NP, and GPU. It can also be a hardware chip. The aforementioned hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0051] In addition, this application also provides a computer-readable storage medium, such as Figure 6 As shown, the computer storage medium stores a computer program that is used to cause the computer to perform any of the methods described in the above embodiments.

[0052] The memory may include readable media in the form of volatile memory, such as random access memory (RAM) 601 and / or cache memory 602, and may further include read-only memory (ROM) 603.

[0053] The memory may also include a program / utility 605 having a set (at least one) of program modules 604, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0054] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0055] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0056] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0057] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0058] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A signal synchronization method, characterized by, The method comprises: processing the acquired wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result; determining a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result; processing the first feedback gain to obtain a second carrier frequency offset estimation value, and generating a second phase-locked loop compensation result according to the second carrier frequency offset estimation value; determining a second feedback gain according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result; determining a first code loop compensation result and a first frequency-locked loop carrier compensation result according to the second feedback gain; demodulating and decoding the first code loop compensation result and the first frequency-locked loop carrier compensation result to acquire the electric text information.

2. The method of claim 1, wherein, The method of determining the first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result comprises: comparing the first carrier frequency offset estimation value with a carrier loop bandwidth to determine a first inter-frequency error; comparing the first carrier frequency offset estimation value with the first phase-locked loop compensation result in sign to determine a first loop feedback direction; determining the first feedback gain according to the first inter-frequency error and the first loop feedback direction.

3. The method according to claim 1 or 2, characterized in that, The method of processing the acquired wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result comprises: initializing a frequency-locked loop carrier NCO according to an initial carrier compensation result and an initial phase-locked loop compensation result; determining an initial demodulation signal according to the wideband radio frequency signal and a first local signal generated by the frequency-locked loop carrier NCO; determining a first despreading signal according to the initial demodulation signal and an initial code loop compensation result, and generating a first integral clean result according to the first despreading signal; calculating a non-coherent accumulation result according to the first integral clean result, and acquiring time synchronization information according to the non-coherent accumulation result; determining the first carrier frequency offset estimation value and the first phase-locked loop compensation result according to the time synchronization information.

4. The method of claim 1, wherein, The method of processing the first feedback gain to obtain a second carrier frequency offset estimation value comprises: compensating the wideband radio frequency signal according to the first feedback gain to generate a first demodulation signal; code loop filtering the first feedback gain, and determining a second code loop compensation result according to the filtered first feedback gain and a unit pseudo-code Doppler increment; calculating a second despreading signal according to the first demodulation signal and the second code loop compensation result, and accumulating the second despreading signal to obtain a second integral clean result; generating the second carrier frequency offset estimation value according to the second integral clean result.

5. The method of claim 4, wherein, The method of compensating the wideband radio frequency signal according to the first feedback gain to generate a first demodulation signal comprises: multiplying the first feedback gain by a unit carrier Doppler increment to obtain a carrier Doppler compensation value; adding the carrier Doppler compensation value, an acquisition predicted Doppler frequency and a carrier frequency fixed frequency word offset to obtain a carrier compensation value; determining a second frequency-locked loop carrier compensation result according to the carrier compensation value and a terminal working clock frequency; determining a second local signal according to the second frequency-locked loop carrier compensation result; Mixing the second local signal and the wideband radio frequency signal to generate a first demodulation signal.

6. The method of claim 4, wherein, The second phase-locked loop compensation result is generated according to the second carrier frequency offset estimation value. The second integral clear result is phase-rotated to obtain a third integral clear result. A carrier phase discrimination result is generated according to the second carrier frequency offset estimation value and the third integral clear result. The carrier phase discrimination result is phase-filtered to generate a second phase-locked loop compensation result.

7. The method of claim 4, wherein, The first code loop compensation result and the first frequency-locked loop carrier compensation result are determined according to the second feedback gain. The first code loop compensation result is generated according to the second feedback gain and the second integral clear result. The first frequency-locked loop carrier compensation result is generated by processing the second feedback gain through a frequency-locked loop carrier NCO.

8. The method of claim 1, wherein, The second feedback gain is determined according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result. The second inter-frequency error is determined by comparing the second carrier frequency offset estimation value with a carrier loop bandwidth. The second loop feedback direction is determined by symbolically comparing the second carrier frequency offset estimation value with the second phase-locked loop compensation result. The second feedback gain is determined according to the second inter-frequency error and the second loop feedback direction.

9. A signal synchronization apparatus, characterized by comprising: Comprise: The signal processing module is configured to process the acquired wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result. The first feedback gain determination module is configured to determine a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result. The update module is configured to process the first feedback gain to obtain a second carrier frequency offset estimation value, and generate a second phase-locked loop compensation result according to the second carrier frequency offset estimation value. The second feedback gain determination module is configured to determine a second feedback gain according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result. The compensation result determination module is configured to determine a first code loop compensation result and a first frequency-locked loop carrier compensation result according to the second feedback gain. The electronic text information acquisition module is configured to demodulate and decode the first code loop compensation result and the first frequency-locked loop carrier compensation result to obtain electronic text information.

10. An electronic device, comprising: The electronic device comprises: At least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any one of the methods of claims 1-8.

11. A computer storage medium, characterized in that The computer storage medium stores a computer program, and the computer program is used to enable a computer to execute any one of the methods of claims 1-8.

Images