Ethernet code stream processing method, device and network equipment

Abstract

The embodiment of the invention provides an Ethernet code stream processing method and device and network equipment, and relates to the technical field of communication, and the method comprises the steps: obtaining an Ethernet code stream and a first source port number of the Ethernet code stream; obtaining a destination port number of the Ethernet code stream from configuration information corresponding to the first source port number; if the sewer mark of the first FIFO corresponding to the destination port number is set, deleting idle code blocks included in the Ethernet code stream, and caching non-idle code blocks included in the Ethernet code stream to the first FIFO; and transmitting the Ethernet code stream in the first FIFO to a physical coding sublayer (PCS) corresponding to the destination port number. Packet loss caused by inconsistent clocks of a receiving channel and a sending channel can be avoided.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an Ethernet stream processing method, apparatus and network equipment. Background Technology

[0002] 5G networks need to provide customers with end-to-end solutions. On a unified infrastructure and network architecture, dedicated networks should be designated for different services, enabling more secure and efficient transmission of various service data within these dedicated networks. To this end, next-generation network technologies must support flexible network slicing, achieve end-to-end hard isolation, and meet deterministic low latency requirements.

[0003] Slicing Packet Networks (SPNs) introduce slice channel technology, allowing service packets to be directly interleaved at Layer 1 (L1) using time-division multiplexing (TDM) based on 66-bit code blocks. This eliminates the framing, packet assembly, table lookup, and buffering processes involved in packet forwarding, enabling transparent transmission of service packets without awareness of the service, thus achieving extremely low forwarding latency and physical isolation. Therefore, fast 66-bit Ethernet code block interleaving is the foundation for building end-to-end physically isolated slice channels in network construction.

[0004] Currently, when a switch processes 66B Ethernet streams, if the clocks of the receiving channel and the transmitting channel are inconsistent, the difference between the receiving stream rate and the transmitting stream rate will be too large, which can easily lead to serious packet loss. Summary of the Invention

[0005] The purpose of this application is to provide an Ethernet stream processing method, apparatus, and network device to solve the problem of severe packet loss caused by clock inconsistency between the receiving and transmitting channels. The specific technical solution is as follows:

[0006] In a first aspect, embodiments of this application provide an Ethernet stream processing method, including:

[0007] Obtain the Ethernet stream and the first source port number of the Ethernet stream;

[0008] Obtain the destination port number of the Ethernet stream from the configuration information corresponding to the first source port number;

[0009] If the watermark flag of the first FIFO corresponding to the destination port number is set, then the idle code blocks included in the Ethernet code stream are deleted, and the non-idle code blocks included in the Ethernet code stream are cached in the first FIFO. The watermark flag being set is used to indicate that the amount of data in the first FIFO is greater than or equal to a first preset threshold.

[0010] The Ethernet stream in the first FIFO is transmitted to the physical coding sublayer (PCS) corresponding to the destination port number.

[0011] In one possible implementation, before deleting the idle code block included in the Ethernet code stream if the drain flag of the first FIFO corresponding to the destination port number is set, the method further includes:

[0012] If the waterline flag of the first FIFO corresponding to the destination port number is set, at least one complete message included in the Ethernet stream is deleted until the waterline flag is unset, at which point the deletion of messages included in the Ethernet stream stops. The waterline flag being set indicates that the amount of data in the first FIFO is greater than or equal to a second preset threshold, and the second preset threshold is greater than the first preset threshold.

[0013] In one possible implementation, the method further includes:

[0014] If neither the upper nor lower waterline flag of the first FIFO is set, then all code blocks included in the Ethernet bitstream are cached in the first FIFO.

[0015] In one possible implementation, transmitting the Ethernet stream in the first FIFO to the physical coding sublayer (PCS) corresponding to the destination port number includes:

[0016] Read the code blocks included in the Ethernet code stream from the first FIFO, and transmit the read code blocks to the PCS;

[0017] During the process of reading the code blocks included in the Ethernet code stream, if it is detected that the empty flag of the first FIFO is set, then when a code block at the end of a message is read, the reading of code blocks from the first FIFO is stopped. The empty flag being set is used to indicate that the amount of data in the first FIFO is less than a third preset threshold, and the third preset threshold is less than the first preset threshold.

[0018] The idle code block is transmitted to the PCS corresponding to the destination port number until the empty flag of the first FIFO is deactivated. Then, the code blocks included in the Ethernet code stream are read from the first FIFO and the read code blocks are transmitted to the PCS corresponding to the destination port number.

[0019] In one possible implementation, if the drain flag of the first FIFO corresponding to the destination port number is set, then the idle code blocks included in the Ethernet stream are deleted, and the non-idle code blocks included in the Ethernet stream are cached before the first FIFO. The method further includes:

[0020] If a first message from a second source port number is currently being transmitted to the destination port identified by the destination port number, then the Ethernet stream is buffered in the second FIFO corresponding to the first source port number;

[0021] When the first message is transmitted, the second message included in the Ethernet stream is read from the second FIFO.

[0022] In one possible implementation, the configuration information further includes cross-board forwarding indication information and header information corresponding to the Ethernet stream; after obtaining the destination port number of the Ethernet stream from the configuration information corresponding to the first source port number, the method further includes:

[0023] If the cross-board forwarding indication information indicates that cross-board forwarding is required, then the preset number of code blocks included in the Ethernet code stream are concatenated, and a header is generated based on the header information to obtain a third message;

[0024] The third message is forwarded to the card containing the destination port number via the forwarding card.

[0025] In one possible implementation, obtaining the Ethernet stream and the first source port number corresponding to the Ethernet stream includes:

[0026] Obtain the Ethernet stream transmitted by the PCS and the first source port number corresponding to the Ethernet stream; or,

[0027] The system receives a fourth message transmitted by the forwarding board, the fourth message including a header and code blocks in the Ethernet code stream; it obtains the first source port number from the header of the fourth message and obtains the code blocks encapsulated in the fourth message.

[0028] Secondly, embodiments of this application provide an Ethernet stream processing apparatus, comprising:

[0029] The cross-configuration module is used to obtain the Ethernet stream and the first source port number of the Ethernet stream; and to obtain the destination port number of the Ethernet stream from the configuration information corresponding to the first source port number.

[0030] The idle code deletion module is used to delete the idle code blocks included in the Ethernet code stream and cache the non-idle code blocks included in the Ethernet code stream into the first FIFO if the waterline flag of the first FIFO corresponding to the destination port number is set. The waterline flag being set is used to indicate that the amount of data in the first FIFO is greater than or equal to a first preset threshold.

[0031] The idle code filling module is used to transmit the Ethernet code stream in the first FIFO to the physical coding sublayer PCS corresponding to the destination port number.

[0032] In one possible implementation, the device further includes:

[0033] The message deletion module is used to delete at least one complete message included in the Ethernet stream if the waterline flag of the first FIFO corresponding to the destination port number is set, until the waterline flag is unset, and then stop deleting the messages included in the Ethernet stream. The waterline flag being set indicates that the amount of data in the first FIFO is greater than or equal to a second preset threshold, and the second preset threshold is greater than the first preset threshold.

[0034] In one possible implementation, the idle code deletion module is specifically used to cache all code blocks included in the Ethernet code stream into the first FIFO if neither the upper nor lower waterline flag of the first FIFO is set.

[0035] In one possible implementation, the free code filling module is specifically used for:

[0036] Read the code blocks included in the Ethernet code stream from the first FIFO, and transmit the read code blocks to the PCS;

[0037] During the process of reading the code blocks included in the Ethernet code stream, if it is detected that the empty flag of the first FIFO is set, then when a code block at the end of a message is read, the reading of code blocks from the first FIFO is stopped. The empty flag being set is used to indicate that the amount of data in the first FIFO is less than a third preset threshold, and the third preset threshold is less than the first preset threshold.

[0038] The idle code block is transmitted to the PCS corresponding to the destination port number until the empty flag of the first FIFO is deactivated. Then, the code blocks included in the Ethernet code stream are read from the first FIFO and the read code blocks are transmitted to the PCS corresponding to the destination port number.

[0039] In one possible implementation, the device further includes:

[0040] The multi-channel forwarding scheduling module is used to buffer the Ethernet stream into the second FIFO corresponding to the first source port number if a first packet from the second source port number is currently being transmitted to the destination port identified by the destination port number; and to read the second packet included in the Ethernet stream from the second FIFO when the first packet is transmitted.

[0041] In one possible implementation, the configuration information further includes cross-board forwarding indication information and header information corresponding to the Ethernet stream; the device further includes:

[0042] The message framing module is used to, if the cross-board forwarding indication information indicates that cross-board forwarding is required, concatenate a preset number of code blocks included in the Ethernet code stream, generate a header based on the header information, and obtain a third message; and forward the third message to the board where the destination port number is located through the forwarding board.

[0043] In one possible implementation, the device further includes a message parsing module;

[0044] The cross-configuration module is used to obtain the Ethernet stream transmitted by the PCS and the first source port number corresponding to the Ethernet stream;

[0045] The message parsing module is used to receive a fourth message transmitted by the forwarding board, the fourth message including a header and code blocks in the Ethernet code stream; to obtain the first source port number from the header of the fourth message, and to obtain the code blocks encapsulated in the fourth message.

[0046] Thirdly, embodiments of this application provide a network device, including a processor and an FPGA chip, wherein the processor and the FPGA chip communicate with each other via a communication bus;

[0047] The FPGA chip includes the apparatus described in the second aspect above.

[0048] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method described in the first aspect above.

[0049] Fifthly, embodiments of this application also provide a computer program product containing instructions that, when run on a computer, cause the computer to perform the method described in the first aspect.

[0050] Using the above technical solution, after obtaining the Ethernet stream and the first source port number, the corresponding destination port number can be obtained. If the de-watering flag of the first FIFO corresponding to the destination port number is set, then after deleting the idle blocks included in the Ethernet stream, the non-idle blocks are buffered in the first FIFO, and the Ethernet stream in the first FIFO is transmitted to the PCS corresponding to the destination port number. By deleting idle blocks, write operations to the first FIFO can be reduced, which can improve the transmission rate, making the transmission rate match the reception rate, thereby reducing the buffer size in the first FIFO, avoiding memory overflow of the first FIFO due to the transmission rate being consistently lower than the reception rate, and thus avoiding packet loss.

[0051] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0053] Figure 1 This is a block diagram of a traditional switch;

[0054] Figure 2 This is a schematic diagram of the data format of a 66B code block provided in an embodiment of this application;

[0055] Figure 3 This is a schematic diagram of the message transmission format in an Ethernet stream provided in an embodiment of this application;

[0056] Figure 4 A flowchart illustrating an Ethernet stream processing method provided in this application embodiment;

[0057] Figure 5 A block diagram of an Ethernet stream processing system provided in this application embodiment;

[0058] Figure 6 This is a schematic diagram of the structure of the multi-channel forwarding and scheduling module provided in the embodiments of this application;

[0059] Figure 7 A schematic diagram of the message format of the data packets provided in the embodiments of this application;

[0060] Figure 8 This is a schematic diagram of the structure of the message framing module provided in the embodiments of this application;

[0061] Figure 9 This is a schematic diagram of the structure of the message parsing module provided in an embodiment of this application;

[0062] Figure 10 This is a schematic diagram of the structure of an Ethernet stream processing device provided in an embodiment of this application;

[0063] Figure 11 This is a schematic diagram of the structure of a network device provided in an embodiment of this application. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0065] To facilitate understanding, the relevant technical terms involved in the embodiments of this application will be introduced first.

[0066] Traditional switch block diagrams are as follows Figure 1 As shown, after receiving a message, the serializer / deserializer (SerDes) transmits the data in the message to the Physical Coding Sublayer (PCS). The PCS then sends the data to the Media Access Control (MAC) layer. The MAC layer encapsulates the data into a message and performs a Cyclic Redundancy Check (CRC). After the CRC check passes, the message is sent to the switching chip. The switching chip then queries the destination port based on the MAC table or the Virtual Local Area Network (VLAN) tag and forwards the message through the destination port.

[0067] Traditional message forwarding methods have complex processing procedures and large forwarding delays. By using Ethernet code for fast crossover, forwarding latency can be reduced.

[0068] A 66B code block is the smallest transmission unit in a high-speed Ethernet interface. The data format of a 66B code block is as follows: Figure 2 As shown, it includes a 2-bit synchronization header and a 64-bit data payload, for example, Figure 2 The synchronization header is 10, and the 64-bit data payload includes 0x1e0x00 0x000x00 0x00 0x00 0x00 0x00 0x00.

[0069] In practice, the synchronization header can be 01 or 10. When the synchronization header is 01, it means that the 66B code block is entirely composed of data; when the synchronization header is 10, it means that the 66B code block includes control information.

[0070] In an Ethernet stream, the transmission format of a message is as follows: Figure 3As shown, a complete and valid message includes a Start of Packet (SOP), an End of Packet (EOP), and valid data (Data, D) between the SOP and EOP. In the Ethernet stream, the link is idle until the next SOP arrives after the EOP, and the Ethernet stream is filled with idle codes (I).

[0071] SOP is a control block with a synchronization header of 10 and a data payload including S code, and EOP is a control block with a synchronization header of 10 and a data payload including T code.

[0072] The Ethernet stream processing method provided in the embodiments of this application is described below.

[0073] This application provides an Ethernet stream processing method, which is applied to an FPGA chip, such as... Figure 4 As shown, the method includes:

[0074] S401. Obtain the Ethernet stream and the first source port number of the Ethernet stream.

[0075] S402. Obtain the destination port number of the Ethernet stream from the configuration information corresponding to the first source port number.

[0076] S403. If the drain flag of the first first-in-first-out (FIFO) queue corresponding to the destination port number is set, then the idle blocks included in the Ethernet stream are deleted, and the non-idle blocks included in the Ethernet stream are buffered into the first FIFO. The drain flag being set indicates that the amount of data in the first FIFO is greater than a first preset threshold.

[0077] Each destination port number corresponds to a FIFO. If the dewatering flag of the first FIFO is set, it means that the amount of data in the code block cached in the first FIFO is greater than the first preset threshold. In this case, the transmission rate is less than the reception rate. The transmission rate can be improved and the forwarding latency reduced by deleting idle code blocks in the Ethernet code stream.

[0078] Understandably, after deleting the idle blocks included in the Ethernet stream, the non-idle blocks preceding the idle blocks can be concatenated with the subsequent non-idle blocks and cached in the first FIFO to ensure the continuity of the Ethernet stream.

[0079] Subsequently, when it is detected that the watermark flag of the first FIFO is deactivated, it indicates that the amount of data in the code block cached in the first FIFO is less than or equal to the first preset threshold. At this time, the deletion of the free code block included in the Ethernet code stream can be stopped, and the Ethernet code stream can continue to be cached in the first FIFO.

[0080] S404. Transmit the Ethernet stream in the first FIFO to the PCS corresponding to the destination port number.

[0081] The Ethernet stream is transmitted to the PCS corresponding to the destination port number, so that the PCS can transmit the Ethernet stream to other devices.

[0082] Using this method, after obtaining the Ethernet stream and the first source port number, the corresponding destination port number can be obtained. If the de-watering flag of the first FIFO corresponding to the destination port number is set, then after deleting the idle blocks included in the Ethernet stream, the non-idle blocks are buffered in the first FIFO, and the Ethernet stream in the first FIFO is transmitted to the PCS corresponding to the destination port number. By deleting idle blocks, write operations to the first FIFO can be reduced, thereby increasing the transmission rate and matching the transmission rate with the reception rate. This reduces the buffer size in the first FIFO, preventing the first FIFO from overflowing due to the transmission rate consistently being lower than the reception rate, and thus avoiding packet loss.

[0083] In some embodiments of this application, before deleting the free blocks included in the Ethernet stream if the drain flag of the first FIFO corresponding to the destination port number is set, the method further includes:

[0084] If the waterline flag of the first FIFO corresponding to the destination port number is set, at least one complete packet in the Ethernet stream is deleted until the waterline flag is unset, at which point the deletion of packets in the Ethernet stream stops. The waterline flag being set indicates that the amount of data in the first FIFO is greater than a second preset threshold, and the second preset threshold is greater than the first preset threshold.

[0085] When the waterline flag of the first FIFO is set, it indicates that the difference between the message transmission and reception rates is too large. Continuing to transmit the Ethernet stream in the current way is likely to cause the buffer of the first FIFO to overflow. Therefore, complete messages can be deleted in advance to avoid the loss of code blocks in subsequent different messages, which would lead to more serious packet loss.

[0086] When the waterline flag is deactivated, the deletion of Ethernet stream packets can be stopped, and then the above S403 can be executed.

[0087] Using this method, when an Ethernet stream is sent from a high-bandwidth channel to a low-bandwidth channel, and deleting idle code blocks is insufficient to address the difference in message transmission and reception rates, complete messages can be deleted to avoid serious packet loss problems later.

[0088] In the above embodiments, if neither the upper waterline flag nor the lower waterline flag of the first FIFO is set, then all code blocks included in the Ethernet bitstream are cached in the first FIFO.

[0089] In some embodiments of this application, the above-mentioned S404, transmitting the Ethernet stream in the first FIFO to the PCS corresponding to the destination port number, can be specifically implemented as follows:

[0090] Read the code blocks included in the Ethernet code stream from the first FIFO and transmit the read code blocks to the PCS; during the process of reading the code blocks included in the Ethernet code stream, if the empty flag of the first FIFO is detected to be set, then stop reading code blocks from the first FIFO when a code block at the end of a message is read; transmit idle code blocks to the PCS corresponding to the destination port number until the empty flag of the first FIFO is detected to be unset, then continue reading the code blocks included in the Ethernet code stream from the first FIFO and transmit the read code blocks to the PCS corresponding to the destination port number.

[0091] Setting the empty flag indicates that the amount of data in the first FIFO is less than a third preset threshold, which is less than a first preset threshold. If the empty flag in the first FIFO is set, it means that all code blocks in the first FIFO will be read. After reading a code block at the end of a message, reading is paused, and idle code blocks are filled in the Ethernet stream transmitted to the PSC, thus avoiding empty reads. This achieves matching of message transmission and reception rates when the Ethernet stream is sent from a small bandwidth channel to a large bandwidth channel, avoiding the problem of increased bit error rate caused by the message transmission rate exceeding the reception rate.

[0092] In some embodiments of this application, in step S403 above, if the drain flag of the first FIFO corresponding to the destination port number is set, the method further includes deleting the idle code blocks included in the Ethernet stream and caching the non-idle code blocks included in the Ethernet stream before the first FIFO:

[0093] If a first message from a second source port number is currently being transmitted to the destination port identified by the destination port number, the Ethernet stream is buffered in the second FIFO corresponding to the first source port number; when the first message is transmitted, the second message included in the Ethernet stream is read from the second FIFO.

[0094] When the Ethernet stream is received, if a message from the second source port number is currently being transmitted to the same destination port, it means that multiple Ethernet streams from different channels need to be transmitted to the same channel. For example, traffic from the first source port and the second source port need to be transmitted to the same destination port. In this case, the currently received Ethernet stream can be temporarily buffered in the second FIFO. When the first message is transmitted, the second message included in the Ethernet stream can continue to be transmitted. The subsequent transmission process can be referred to the relevant description in the above embodiment.

[0095] Using this method, under low traffic conditions, packets from different channels can be forwarded to the same destination port within the same time period, enabling multi-channel to single-channel packet forwarding with little or no delay.

[0096] In some embodiments of this application, the configuration information further includes cross-board forwarding indication information and header information corresponding to the Ethernet stream; after obtaining the destination port number of the Ethernet stream from the configuration information corresponding to the first source port number in S401 above, the method further includes:

[0097] If the cross-board forwarding indication information indicates that cross-board forwarding is required, then the preset number of code blocks included in the Ethernet stream are concatenated, and a header is generated based on the header information to obtain a third message; the third message is then forwarded to the board containing the destination port number through the forwarding board. In essence, each time the preset number of code blocks included in the Ethernet stream are received, the preset number of code blocks are concatenated into a third message, and then forwarded to the board containing the destination port number through the forwarding board.

[0098] Correspondingly, the current board may also receive messages from other boards. Based on this, the above-mentioned S404, obtaining the Ethernet stream and the first source port number corresponding to the Ethernet stream, includes the following two implementation methods:

[0099] Method 1: Obtain the Ethernet stream transmitted by the PCS and the corresponding first source port number. That is, obtain the Ethernet stream and first source port number transmitted by other devices through the PCS.

[0100] Method 2: Receive the fourth message transmitted by the forwarding board. The fourth message includes a header and an Ethernet stream. Obtain the first source port number from the header of the fourth message and obtain the Ethernet stream encapsulated in the fourth message.

[0101] Method two refers to receiving a fourth message transmitted by other boards through a forwarding board. The header of the fourth message is in a format that each board can recognize. After receiving the fourth message, the header of the fourth message can be stripped to obtain the encapsulated Ethernet stream, and then the Ethernet stream can be processed according to the method described in the above embodiments.

[0102] This method provides a way to cross-board traffic, enabling rapid cross-connection of non-Ethernet traffic services.

[0103] like Figure 5 As shown, Figure 5 This application provides a block diagram of an Ethernet stream processing system, including a forwarding board and a Field Programmable Gate Array (FPGA) chip. The forwarding board is located within other chips. Figure 5In this context, Seres+PCS refers to the hardware resources on the FPGA chip. This FPGA chip is used to implement the Ethernet stream processing method provided in this application embodiment. The method provided in this application embodiment can be mounted on various types of logic chips and is independent of the functionality of specific devices. The FPGA chip includes an X-Cross config (XC_CFG) module, a packet framing module, a multi-channel forwarding and scheduling module, a packet deletion module, a packet parsing module, an IDLE deletion module, a buffer module, and an IDLE filling module.

[0104] The buffer module includes multiple FIFOs, each with a corresponding output port. The transmit channel clock (tx_clk) and receive channel clock (rx_clk) of the buffer module are both provided by Seres+PCS. The write interface of the FIFOs in the idle code block deletion module and the buffer module both use rx_clk, while the read interface of the FIFOs in the idle code filling module and the buffer module both use tx_clk, enabling cross-clock domain forwarding of the 66B code stream.

[0105] The XC_CFG module is implemented using dual-port Random Access Memory (RAM). One port is used to update configuration information, and the other port is used to receive 66B bitstreams to perform port number matching on the 66B bitstreams. The XC_CFG module stores configuration information corresponding to each source port number. This configuration information may specifically include fast cross switch, destination port number, cross-board cross switch, cross-board cross header, message deletion threshold, idle block deletion threshold, and idle block filling threshold.

[0106] Figure 5 In the process, the XC_CFG module receives 66B bitstream data and the channel number (Ch_Num+66B_data), where the channel number is the source port number of the 66B bitstream. It then looks up the configuration information corresponding to this source port number. If the configuration information determines that the 66B bitstream data needs fast cross-connection and needs to be forwarded to the destination port, it transmits the cross-connection data (Xc_data_to_tx) to be sent to the multi-channel forwarding scheduling module. This cross-connection data is the received 66B bitstream data. If the configuration information determines that the 66B bitstream data needs cross-board cross-connection, it transmits the 66B bitstream data, the channel number, and cross-board cross-connection configuration information (Ch_Num+66B_data+pkt_cfg) to the message framing module. The cross-board cross-connection configuration information includes the cross-board cross-connection header. If the configuration information determines that the 66B bitstream does not need to be forwarded and is normally received data (Normal_data_rx), it directly transmits it to the message framing module.

[0107] The following combination Figure 5 The three crossover methods provided in the embodiments of this application will be introduced.

[0108] Method 1: Fast crossover from single channel to single channel

[0109] Step 1: The XC_CFG module receives the 66B bitstream and the source port number.

[0110] The source PORT number is the channel number (Ch_Num) of the 66B bitstream.

[0111] Step 2: The XC_CFG module reads the configuration information corresponding to the source PORT number from the CFG RAM, and determines whether fast crossover is required and the corresponding destination PORT number based on the configuration information. If fast crossover is required, the XC_CFG module passes the 66B bitstream and the destination PORT number to the multi-channel forwarding scheduling module.

[0112] Step 3: The multi-channel forwarding and scheduling module transmits the 66B bitstream and the destination PORT number to the packet deletion module.

[0113] Since it is a single-channel to single-channel forwarding, it does not involve inter-channel scheduling or caching. Therefore, the multi-channel forwarding scheduling module does not need to process the 66B bitstream and can directly pass the 66B bitstream and the destination PORT number to the packet deletion module.

[0114] Step 4: The message deletion module determines the FIFO (referred to as FIFO1) corresponding to the destination PORT number. If the water level flag (afull_high) of FIFO1 is 1, it means that the water level of the channel corresponding to FIFO1 is about to be full. Then, the complete message in the 66B bitstream is discarded until the water level flag (afull_high) of FIFO1 becomes 0, at which point the message discarding stops.

[0115] It should be noted that the waterline flag of the FIFO is set by the cross-configuration module based on the packet deletion threshold (second preset threshold) of the destination port number. When the amount of data in the FIFO corresponding to the destination port number reaches the packet deletion threshold, the waterline flag of the FIFO is set to 1. When the amount of data in the FIFO corresponding to the destination port number is lower than the packet deletion threshold, the waterline flag of the FIFO is set to 0.

[0116] The message deletion module can determine the boundary of the message by the S code and T code in the 66B code stream. After determining that afull_high of FIFO1 is set to 1, when the next S code of the 66B code stream is detected, the data valid signal is pulled low. When the afull_high of FIFO1 is set to 0, the data valid signal is kept low until the T code is detected, at which point the message deletion stops.

[0117] Understandably, the message deletion module will transmit the 66B bitstream after deleting the message to the IDLE deletion module.

[0118] Conversely, if the message deletion module receives a 66B bitstream and determines that FIFO1's afull_high is set to 0, it sends the 66B bitstream and the destination PORT number to the IDLE deletion module.

[0119] The message deletion module deletes messages based on the waterline flag, which can handle message forwarding in asymmetric bandwidth channels. When messages are sent from a large bandwidth to a small bandwidth, it can speed up the message forwarding rate and avoid a large number of packet losses.

[0120] Step 5: The IDLE deletion module determines the FIFO (called FIFO1) corresponding to the destination PORT number. If the full_low flag of FIFO1 is 1, it means that the full_low flag of the channel corresponding to FIFO1 is about to be full. Then, a portion of the free code blocks in the 66B bitstream are deleted to reduce the buffer in the FIFO.

[0121] Specifically, when the IDLE deletion module detects an idle code block, it deletes the idle code block of the current frame and concatenates the message of the next frame. By deleting idle code blocks, write operations to FIFO1 can be reduced.

[0122] Understandably, after the IDLE deletion module deletes the idle module, it caches the remaining code blocks included in the 66B bitstream into FIFO1.

[0123] It should be noted that the FIFO's dewatering flag is set by the cross-configuration module based on the idle deletion threshold (first preset threshold) of the destination port number. When the amount of data in the FIFO corresponding to the destination port number reaches the idle deletion threshold, the FIFO's dewatering flag is set to 1. When the amount of data in the FIFO corresponding to the destination port number is lower than the idle deletion threshold, the FIFO's dewatering flag is set to 0.

[0124] The IDLE deletion module deletes idle code blocks based on the dropout flag, which can correct the clock difference between the receiving and transmitting directions and avoid packet loss caused by large clock differences.

[0125] Step 6: The IDLE filling module reads the 66B bitstream from FIFO1. If the IDLE filling module detects that the aempty flag in FIFO1 is set to 1, it will stop reading packets from FIFO1 when it reaches the end of a packet in the 66B bitstream. It will then replace the subsequent data of the 66B bitstream with an empty code block and continue transmitting the 66B bitstream, so that subsequent modules can receive a continuous bitstream and avoid empty frames. This continues until aempty is set to 0, at which point it will continue reading packets from FIFO1 and transmitting them.

[0126] It should be noted that the empty flag of the FIFO is set by the cross-configuration module based on the idle fill threshold (third preset threshold) of the destination port number. When the amount of data in the FIFO corresponding to the destination port number is less than or equal to the idle fill threshold, the empty flag of the FIFO is set to 1. When the amount of data in the FIFO corresponding to the destination port number is greater than the idle fill threshold, the empty flag of the FIFO is set to 0.

[0127] Step 7: The IDLE filling module inputs the 66B bitstream into the PCS of the destination PORT.

[0128] Using this method, the FIFO in the buffer module has the function of isolating the transmit and receive clock domains, and can adjust the message transmission rate by adding or deleting idle code blocks and deleting complete messages, and can tolerate large differences in transmit and receive rates.

[0129] Method 2: Rapid Crossing from Multi-Channel to Single-Channel

[0130] Step 1: The XC_CFG module receives the 66B bitstream and the source PORT number.

[0131] Step 2: The XC_CFG module reads the configuration information corresponding to the source PORT number from RAM, and determines whether fast forwarding is needed and the corresponding destination PORT number based on the configuration information. If forwarding is needed, the XC_CFG module passes the 66B bitstream and the destination PORT number to the multi-channel forwarding scheduling module.

[0132] Step 3: The multi-channel forwarding and scheduling module receives the 66B bitstream and the destination PORT number.

[0133] like Figure 6 As shown, the multi-channel forwarding and scheduling module includes a channel polling module, a message scheduling module, and a FIFO corresponding to each source PORT number.

[0134] If there are no packets from other source PORTs currently being transmitted to the destination PORT, the multi-channel forwarding scheduling module does not need to buffer the 66B bitstream in its own FIFO. Instead, the packet scheduling module can directly transmit the 66B bitstream and the destination PORT number to the packet deletion module.

[0135] If there are currently packets from other source PORTs being transmitted to the destination PORT, the multi-channel forwarding scheduling module will buffer the 66B stream into the FIFO (called FIFO A) corresponding to the source PORT number of the 66B stream.

[0136] When the currently transmitting message is completed, the channel polling module checks the next non-empty FIFO by scheduling the empty signal of each FIFO. Assuming that the next non-empty FIFO is FIFO A, the channel polling module notifies the message scheduling module of the source PORT number corresponding to FIFO A. Then, the message scheduling module reads a message from FIFO A and transmits the message to the message deletion module.

[0137] Understandably, the multi-channel forwarding scheduling module needs to check the S and T codes in the 66B bitstream to delimit a complete message, and cannot schedule other messages while sending one message. When the traffic is low, the latency of forwarding messages in this way is in the nanosecond (ns) range, achieving fast message forwarding from multi-channel to single-channel.

[0138] Step 4: The message deletion module determines the FIFO (referred to as FIFO1) corresponding to the destination PORT number of the received 66B bitstream. If the water level flag (afull_high) of FIFO1 is 1, it means that the water level of the channel corresponding to FIFO1 is about to be full. Then, the complete message in the 66B bitstream is discarded until the water level flag (afull_high) of FIFO1 becomes 0, at which point the message discarding stops.

[0139] The message deletion module can determine the boundary of the message by the S code and T code in the 66B code stream. After determining that afull_high of FIFO1 is set to 1, when the next S code of the 66B code stream is detected, the data valid signal is pulled low. When the afull_high of FIFO1 is set to 0, the data valid signal is kept low until the T code is detected, at which point the message deletion stops.

[0140] Understandably, the message deletion module will transmit the 66B bitstream after deleting the message to the IDLE deletion module.

[0141] Conversely, if the message deletion module receives a 66B bitstream and determines that FIFO1's afull_high is set to 0, it sends the 66B bitstream and the destination PORT number to the IDLE deletion module.

[0142] Step 5: The IDLE deletion module determines the FIFO (called FIFO1) corresponding to the destination PORT number. If the full_low flag of FIFO1 is 1, it means that the full_low flag of the channel corresponding to FIFO1 is about to be full. Then, a portion of the free code blocks in the 66B bitstream are deleted to reduce the buffer in the FIFO.

[0143] Specifically, when the IDLE deletion module detects an idle code block, it deletes the idle code block of the current frame and concatenates the message of the next frame. By deleting idle code blocks, write operations to FIFO1 can be reduced.

[0144] Understandably, after the IDLE deletion module deletes the idle module, it caches the 66B bitstream in FIFO1.

[0145] Step 6: The IDLE filling module reads the 66B bitstream from FIFO1. If the IDLE filling module detects that the aempty flag in FIFO1 is set to 1, it will stop reading packets from FIFO1 when it reaches the end of a packet in the 66B bitstream. It will then replace the subsequent data of the 66B bitstream with an empty code block and continue transmitting the 66B bitstream, so that subsequent modules can receive a continuous bitstream and avoid empty frames. This continues until aempty is set to 0, at which point it will continue reading packets from FIFO1 and transmitting them.

[0146] Step 7: The IDLE filling module inputs the 66B bitstream into the PCS of the destination PORT.

[0147] This approach enables low-latency Ethernet stream forwarding with an asymmetric number of channels, making it applicable to a wider range of scenarios.

[0148] Method 3: Cross-board intersection

[0149] Step 1: The XC_CFG module receives the 66B bitstream and the source PORT number.

[0150] Step 2: The XC_CFG module reads the configuration information corresponding to the source PORT number from RAM, and determines whether cross-board forwarding is required and the corresponding destination PORT number based on the configuration information. If cross-board forwarding is required, the XC_CFG module passes the 66B bitstream and the cross-board cross-pass packet header configuration information (pkt_cfg) included in the configuration information to the packet framing module.

[0151] The header configuration information is the configuration information of the cross-board cross header. The cross-board cross header is a MAC header that the forwarding board can recognize, so that the forwarding board can forward the message carrying the MAC header to other boards based on the MAC header.

[0152] Step 3: The message framing module concatenates the cross-board cross header and consecutive 66B code blocks into a fixed-length data message. The cross-board cross header is configured by the control side into a format that the forwarding board can recognize. The message framing module transmits the data message to the forwarding board, and then the forwarding board forwards the data message to other boards based on the cross-board cross header. The other boards input the data message into the message parsing module.

[0153] The format of the data message is as follows: Figure 7 As shown, it includes a MAC header and a 66B bitstream consisting of N 66B code blocks. Optionally, a custom frame header may also be included, which includes reserved fields that can be configured later based on actual needs.

[0154] The structure of the message framing module is as follows: Figure 8 As shown, it specifically includes a code block counting module, a data splicing module, and a FIFO corresponding to each source PORT number.

[0155] The message framing module receives the 66B bitstream data, channel number, and header configuration information (Ch+66B+pkt_cfg). Based on the channel number, it caches the 66B bitstream data into the FIFO corresponding to that channel number (i.e., the source PORT number). The block counting module counts the number of blocks in each FIFO. The data splicing module polls each FIFO. When the number of blocks in a FIFO reaches a preset number, the preset number of blocks in the FIFO are then processed according to... Figure 7 The format shown is concatenated into a data packet and then sent to the forwarding board. Unlike the MAC of standard Ethernet, this packet framing module only needs to perform simple code block concatenation and does not require CRC check, which can reduce processing complexity.

[0156] The process of the forwarding board forwarding data packets to other boards is basically the same as the general Ethernet forwarding process. The difference is that in this embodiment, instead of processing Ethernet frames, it directly encapsulates the 66B bitstream of the link layer. When the forwarding board forwards packets, it does not need to be aware of the specific frame format, which makes it convenient to forward different Layer 2 frames and achieve a purpose similar to cross-board circuit simulation.

[0157] The reason for cross-board crossover is that large router devices often have multiple expansion cards to support ports with various speeds. The backplane supports packet forwarding between these expansion cards, and the network ports are all on these expansion cards. Therefore, if two peer devices are connected to different expansion cards, cross-board crossover is required, and the single-channel fast crossover in Method 1 cannot be used directly.

[0158] Step 4: The message parsing module splits the received data message into a 66B code stream and obtains the destination PORT number from the header. The 66B code stream and the destination PORT number are then input into the multi-channel forwarding scheduling module. Since the cross-board forwarding mode does not involve inter-channel scheduling and buffering, the 66B code stream and the destination PORT number are directly passed through to the message deletion module.

[0159] The structure of the message parsing module is as follows: Figure 9 As shown, the system includes a code block counting module and a code block recovery module. The code block counting module counts the code blocks in the received data packet. Each time a header is detected, the counter is reset to zero. The code block recovery module then recovers the data packet into 66B code blocks and a channel number (Ch+66B), where the channel number is the destination PORT number. The code block counting module counts the recovered 66B code blocks. When the count value of the code block counting module accumulates to a preset number, the processing of one packet is complete. By transparently processing the 66B code stream, the effect of cross-board circuit simulation can be achieved.

[0160] Step 5: The message deletion module determines the FIFO (referred to as FIFO1) corresponding to the destination PORT number of the received 66B bitstream. If the water level flag (afull_high) of FIFO1 is 1, it means that the water level of the channel corresponding to FIFO1 is about to be full. Then, the complete message in the 66B bitstream is discarded until the water level flag (afull_high) of FIFO1 becomes 0, at which point the message discarding stops.

[0161] The message deletion module can determine the boundary of the message by the S code and T code in the 66B code stream. After determining that afull_high of FIFO1 is set to 1, when the next S code of the 66B code stream is detected, the data valid signal is pulled low. When the afull_high of FIFO1 is set to 0, the data valid signal is kept low until the T code is detected, at which point the message deletion stops.

[0162] Understandably, the message deletion module will transmit the 66B bitstream after deleting the message to the IDLE deletion module.

[0163] Conversely, if the message deletion module receives a 66B bitstream and determines that FIFO1's afull_high is set to 0, it sends the 66B bitstream and the destination PORT number to the IDLE deletion module.

[0164] Step 6: The IDLE deletion module determines the FIFO (called FIFO1) corresponding to the destination PORT number. If the full_low flag of FIFO1 is 1, it means that the full_low flag of the channel corresponding to FIFO1 is about to be full. Then, a portion of the free code blocks in the 66B bitstream are deleted to reduce the buffer in the FIFO.

[0165] Specifically, when the IDLE deletion module detects an idle code block, it deletes the idle code block of the current frame and concatenates the message of the next frame. By deleting idle code blocks, write operations to FIFO1 can be reduced.

[0166] Understandably, after the IDLE deletion module deletes the idle module, it caches the 66B bitstream in FIFO1.

[0167] Step 7: The IDLE filling module reads the 66B bitstream from FIFO1. If the IDLE filling module detects that the aempty flag in FIFO1 is set to 1, it will stop reading packets from FIFO1 when it reads the end of a packet in the 66B bitstream, replace the subsequent data of the 66B bitstream with an empty code block, and continue to transmit the 66B bitstream so that subsequent modules can receive a continuous bitstream and avoid empty frames. This continues until aempty is set to 0, at which point it continues to read packets from FIFO1 and transmit them.

[0168] Step 8: The IDLE filling module inputs the 66B bitstream into the PCS of the destination PORT.

[0169] This method enables rapid cross-board Ethernet traffic exchange, providing the possibility of rapid cross-board exchange for non-Ethernet traffic services.

[0170] Corresponding to the above method embodiments, this application also provides an Ethernet stream processing device, which is applied to an FPGA chip, such as... Figure 10 As shown, the device includes:

[0171] The cross-configuration module 1001 is used to obtain the Ethernet stream and the first source port number of the Ethernet stream; and to obtain the destination port number of the Ethernet stream from the configuration information corresponding to the first source port number.

[0172] The idle code deletion module 1002 is used to delete the idle code blocks included in the Ethernet code stream and cache the non-idle code blocks included in the Ethernet code stream into the first FIFO if the bottom watermark flag of the first FIFO 1004 corresponding to the destination port number is set. The bottom watermark flag is set to indicate that the amount of data in the first FIFO 1004 is greater than or equal to the first preset threshold.

[0173] The idle code filling module 1003 is used to transmit the Ethernet code stream in the first FIFO 1004 to the physical coding sublayer PCS corresponding to the destination port number.

[0174] Optionally, the device further includes:

[0175] The message deletion module 1005 is used to delete at least one complete message included in the Ethernet stream if the waterline flag of the first FIFO 1004 corresponding to the destination port number is set, until the waterline flag is unset, and then stop deleting the messages included in the Ethernet stream. The waterline flag being set indicates that the amount of data in the first FIFO 1004 is greater than or equal to a second preset threshold, and the second preset threshold is greater than a first preset threshold.

[0176] Optionally, the idle code deletion module 1002 is used to cache all code blocks included in the Ethernet code stream into the first FIFO 1004 if neither the upper waterline flag nor the lower waterline flag of the first FIFO 1004 is set.

[0177] Optionally, the idle code filling module 1003 is specifically used for:

[0178] Read the code blocks included in the Ethernet code stream from the first FIFO1004 and transmit the read code blocks to the PCS;

[0179] During the process of reading the code blocks included in the Ethernet code stream, if it is detected that the empty flag of the first FIFO1004 is set, then when a code block at the end of a message is read, the reading of code blocks from the first FIFO1004 is stopped. The empty flag being set is used to indicate that the amount of data in the first FIFO1004 is less than the third preset threshold, and the third preset threshold is less than the first preset threshold.

[0180] The idle code block is transmitted to the PCS corresponding to the destination port number until the empty flag of the first FIFO1004 is deactivated. Then, the code blocks included in the Ethernet code stream are read from the first FIFO1004 and the read code blocks are transmitted to the PCS corresponding to the destination port number.

[0181] Optionally, the device further includes:

[0182] The multi-channel forwarding scheduling module 1006 is used to buffer the Ethernet stream into the second FIFO corresponding to the first source port number if a first message from the second source port number is being transmitted to the destination port identified by the destination port number; and to read the second message included in the Ethernet stream from the second FIFO when the first message is transmitted.

[0183] Optionally, the configuration information also includes cross-board forwarding indication information and header information corresponding to the Ethernet stream; the device also includes:

[0184] The message framing module 1007 is used to splice a preset number of code blocks included in the Ethernet code stream and generate a header based on the header information if the cross-board forwarding indication information indicates that cross-board forwarding is required, to obtain a third message; and forward the third message to the board where the destination port number is located through the forwarding board.

[0185] Optionally, the device further includes a message parsing module 1008;

[0186] The cross-configuration module 1001 is used to obtain the Ethernet stream transmitted by the PCS and the first source port number corresponding to the Ethernet stream;

[0187] The message parsing module 1008 is used to receive the fourth message transmitted by the forwarding board. The fourth message includes a header and code blocks in the Ethernet code stream. It obtains the first source port number from the header of the fourth message and the code blocks encapsulated in the fourth message.

[0188] This application also provides a network device, such as... Figure 11 As shown, it includes a processor 1101 and an FPGA chip 1102, wherein the processor 1101 and the FPGA chip 1102 communicate with each other through a communication bus 1103.

[0189] The FPGA chip 1102 includes the Ethernet stream processing device described in the above embodiments.

[0190] The aforementioned communication bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0191] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0192] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements any of the above-described Ethernet stream processing methods.

[0193] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the Ethernet stream processing methods described above.

[0194] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0195] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0196] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0197] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. An Ethernet code stream processing method, characterized in that, The method comprises: acquiring an Ethernet code stream and a first source port number of the Ethernet code stream; acquiring a destination port number of the Ethernet code stream from configuration information corresponding to the first source port number; if a low water mark flag of a first FIFO corresponding to the destination port number is set, deleting idle code blocks included in the Ethernet code stream, and buffering non-idle code blocks included in the Ethernet code stream to the first FIFO, the low water mark flag being set to indicate that a data amount in the first FIFO is greater than or equal to a first preset threshold value; transmitting the Ethernet code stream in the first FIFO to a physical coding sublayer (PCS) corresponding to the destination port number.

2. The method of claim 1, wherein, Before the step of deleting the idle code blocks included in the Ethernet code stream if the low water mark flag of the first FIFO corresponding to the destination port number is set, the method further comprises: if a high water mark flag of the first FIFO corresponding to the destination port number is set, deleting at least one complete packet included in the Ethernet code stream until the high water mark flag is unset, and stopping deleting the packets included in the Ethernet code stream, the high water mark flag being set to indicate that the data amount in the first FIFO is greater than or equal to a second preset threshold value, the second preset threshold value being greater than the first preset threshold value.

3. The method according to claim 1 or 2, characterized in that, The method further comprises: if neither the high water mark flag nor the low water mark flag of the first FIFO is set, buffering all code blocks included in the Ethernet code stream to the first FIFO.

4. The method of claim 1, wherein, The step of transmitting the Ethernet code stream in the first FIFO to the PCS corresponding to the destination port number comprises: reading the code blocks included in the Ethernet code stream from the first FIFO, and transmitting the read code blocks to the PCS; in the process of reading the code blocks included in the Ethernet code stream, if a will empty flag of the first FIFO is set, stopping reading the code blocks from the first FIFO when a code block at the end of a packet is read, the will empty flag being set to indicate that the data amount in the first FIFO is less than a third preset threshold value, the third preset threshold value being less than the first preset threshold value; transmitting idle code blocks to the PCS corresponding to the destination port number until the will empty flag of the first FIFO is unset, and then continuing to read the code blocks included in the Ethernet code stream from the first FIFO and transmitting the read code blocks to the PCS corresponding to the destination port number.

5. The method of claim 1, wherein, Before the step of deleting the idle code blocks included in the Ethernet code stream if the low water mark flag of the first FIFO corresponding to the destination port number is set, the method further comprises: if a first packet from a second source port number is currently being transmitted to a destination port identified by the destination port number, buffering the Ethernet code stream to a second FIFO corresponding to the first source port number; when the first packet is transmitted, reading a second packet included in the Ethernet code stream from the second FIFO.

6. The method of claim 1, wherein, The configuration information further comprises cross-board forwarding indication information and header information corresponding to the Ethernet code stream; after obtaining the destination port number of the Ethernet code stream from the configuration information corresponding to the first source port number, the method further comprises: If the cross-board forwarding indication information indicates that cross-board forwarding is required, splicing a preset number of code blocks included in the Ethernet code stream, and generating a header based on the header information to obtain a third packet; Forwarding the third packet to a board card where the destination port number is located through a forwarding board card.

7. The method of claim 1, wherein, The obtaining of the Ethernet code stream and the first source port number corresponding to the Ethernet code stream comprises: Obtaining the Ethernet code stream transmitted by the PCS and the first source port number corresponding to the Ethernet code stream; or Receiving a fourth packet transmitted by a forwarding board card, the fourth packet comprising a header and a code block in the Ethernet code stream; obtaining the first source port number from the header of the fourth packet, and obtaining the code block encapsulated in the fourth packet.

8. An Ethernet stream processing device, characterized by Comprise: A cross configuration module configured to obtain an Ethernet code stream and a first source port number of the Ethernet code stream; Obtaining a destination port number of the Ethernet code stream from configuration information corresponding to the first source port number; An idle code deletion module configured to, if a lower water line flag of a first FIFO corresponding to the destination port number is set, deleting idle code blocks included in the Ethernet code stream, and buffering non-idle code blocks included in the Ethernet code stream to the first FIFO, the lower water line flag being set to indicate that a data amount in the first FIFO is greater than or equal to a first preset threshold; An idle code filling module configured to transmitting the Ethernet code stream in the first FIFO to a physical coding sublayer (PCS) corresponding to the destination port number.

9. The apparatus of claim 8, wherein, The apparatus further comprises: A packet deletion module configured to, if an upper water line flag of the first FIFO corresponding to the destination port number is set, deleting at least one complete packet included in the Ethernet code stream until the upper water line flag is unset, and stopping deleting the packets included in the Ethernet code stream, the upper water line flag being set to indicate that the data amount in the first FIFO is greater than or equal to a second preset threshold, the second preset threshold being greater than the first preset threshold.

10. The apparatus of claim 8 or 9, wherein The idle code deletion module is specifically configured to, if neither the upper water line flag nor the lower water line flag of the first FIFO is set, buffering all code blocks included in the Ethernet code stream to the first FIFO.

11. The apparatus of claim 8, wherein, The idle code filling module is specifically configured to: Reading the code blocks included in the Ethernet code stream from the first FIFO, and transmitting the read code blocks to the PCS; In the process of reading the code blocks included in the Ethernet code stream, if a will empty flag of the first FIFO is set, stopping reading the code blocks from the first FIFO when a code block at a tail of a packet is read, the will empty flag being set to indicate that the data amount in the first FIFO is less than a third preset threshold, the third preset threshold being less than the first preset threshold; transmitting idle code blocks to the PCS corresponding to the destination port number until the de-setting of the empty flag of the first FIFO is identified, and then continuing to read the code blocks included in the Ethernet code stream from the first FIFO and transmitting the read code blocks to the PCS corresponding to the destination port number.

12. The apparatus of claim 8, wherein, The apparatus further comprises: a multi-channel forwarding scheduling module configured to, if a first packet from a second source port number is currently being transmitted to a destination port identified by the destination port number, cache the Ethernet code stream to a second FIFO corresponding to the first source port number, and read a second packet included in the Ethernet code stream from the second FIFO when the first packet is transmitted.

13. The apparatus of claim 8, wherein, The configuration information further comprises cross-board forwarding indication information and header information corresponding to the Ethernet code stream, and the apparatus further comprises: a packet framing module configured to, if the cross-board forwarding indication information indicates that cross-board forwarding is required, splice a preset number of code blocks included in the Ethernet code stream, generate a header based on the header information, and obtain a third packet, and forward the third packet to a board card on which the destination port number is located through a forwarding board card.

14. The apparatus of claim 8, wherein, The apparatus further comprises a packet analyzing module. The cross configuration module is configured to obtain the Ethernet code stream transmitted by the PCS and a first source port number corresponding to the Ethernet code stream. The packet analyzing module is configured to receive a fourth packet transmitted by a forwarding board card, the fourth packet comprising a header and code blocks in the Ethernet code stream, obtain the first source port number from the header of the fourth packet, and obtain the code blocks encapsulated in the fourth packet.

15. A network device, comprising: The apparatus comprises a processor and an FPGA chip, and the processor and the FPGA chip communicate with each other through a communication bus. The FPGA chip comprises the apparatus of any one of claims 8-14. The apparatus comprises a processor and an FPGA chip, and the processor and the FPGA chip communicate with each other through a communication bus. The FPGA chip comprises the apparatus of any one of claims 8-14.

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