Hybrid flash memory reading optimization method based on reliability perception

Abstract

The invention discloses a hybrid flash memory reading optimization method based on reliability perception, which is characterized in that the reading performance optimization of a high-density flash memory is realized by adopting a method of migrating data on data pages with different characteristics to flash memory pages with different reliability for reading. According to the method, a heat classifier, an original bit error rate calculator and a read-reread counter of data pages are arranged in a flash memory controller to judge the characteristics of the data pages, and corresponding migration mechanisms are designed for data on the data pages with different characteristics, so that resource allocation of different reliability pages in a flash memory is adjusted; and the overall reading performance of the flash memory equipment is optimized. Compared with the prior art, the method has the advantages that the reading performance of the high-density flash memory is improved through the reading method capable of sensing the reliability of the data pages, the operation of repeated rereading in the reading process of the high-density flash memory is optimized, the delay overhead caused by a read retry mechanism is effectively reduced, and the method is simple and convenient, good in use effect and has a certain application prospect.

Description

Technical Field

[0001] This invention relates to the field of flash memory read performance technology, and in particular to a reliability-aware hybrid flash memory read optimization method. Background Technology

[0002] With the development of 3D NAND vertical stacking technology and multi-bit technology, flash memory storage density has evolved from single-bit cell (SLC) to five-bit cell (PLC), and the number of stacking layers has increased from the initial 24 layers to as many as 280 layers currently. Among them, four-bit cell (QLC) flash memory, by storing four bits of data in each storage cell and stacking in multiple layers, has significantly improved storage density and reduced costs, and has been widely used in consumer-grade storage systems. However, the increased bit density of QLC flash memory leads to a narrower noise margin, and with the increase in the number of stacking layers, programming interference and read interference problems become increasingly serious, reducing its durability and causing a significant increase in read latency and a decline in read performance due to frequent read retries. Read retries are the process of repeatedly adjusting the read reference voltage to correct errors when error correction codes (such as LDPC) fail, which severely degrades read performance.

[0003] The read retry mechanism of QLC flash memory leads to a significant increase in read latency and a decrease in read performance for at least two reasons: First, the high-density storage characteristics result in multiple voltage states. Specifically, each QLC cell needs 15 reference voltages to distinguish 16 voltage states, and the intervals between adjacent voltage states are much narrower than those of SLC and TLC. This dense voltage distribution and high stacking layer count make it highly susceptible to programming interference, read interference, and charge leakage, leading to a significant increase in the original bit error rate. Reading four bits of QLC flash memory requires applying different combinations of reference voltages step-by-step, and each read retry requires completely repeating this multi-stage process. Second, there is the cumulative latency from multiple read reference voltage adjustments. When the initial read operation causes voltage drift exceeding the instantaneous correction capability of the error correction code, the flash controller is forced to initiate the read retry mechanism: readjusting the new read reference voltage and performing the read operation on the target cell again. However, a single voltage adjustment of QLC flash memory may not be sufficient to control the original bit error rate within the error correction code's capability. Therefore, the read retry process may require up to ten or more iterations of adjusting the read reference voltage and performing the read operation, drastically increasing the actual read time.

[0004] To reduce read retry latency in QLC flash memory, three main approaches have been adopted: The first is to suppress the number of read retry triggers through refresh operations (resetting page retention age) or reference voltage prediction. However, relying on refresh to suppress read retry requires continuous read and write operations at extremely high refresh rates, resulting in significant performance and lifespan costs. Schemes relying on machine learning to model the reference voltage and then predict it incur high computational overhead. The second approach accelerates the read retry process through pipelined retry technology or dynamically adjusting the read retry voltage table, but this only shortens the latency per retry and does not consider data access characteristics. The third approach utilizes hybrid flash architecture (Hybrid SSD) to improve performance by adding an SLC cache layer. However, mainstream research on this approach focuses excessively on write optimization, neglecting read performance bottlenecks; secondly, the migration mechanism relies solely on data access frequency, causing premature migration of too many data pages; and thirdly, most only support coarse-grained SLC-QLC dual-mode conversion, requiring a three-fold sacrifice in capacity.

[0005] In summary, existing technologies can alleviate the latency caused by the read retry mechanism of QLC and reduce the number of read retries or the latency per retrieval to some extent, but none of them can completely eliminate the read retry problem of QLC flash memory, while also incurring huge overhead in terms of lifespan, computation, or capacity. Previous work and experiments have revealed that the workloads involved in solid-state drives generally exhibit the following characteristics: most read requests concentrate on accessing a small portion of the address space, i.e., access exhibits a certain degree of skewness. This frequently read data needs to be placed on high-reliability pages; while other less frequently accessed data can be placed on lower-reliability pages. Therefore, a dynamic read optimization method combining reliability awareness and data characteristics is needed to improve flash memory read performance while reducing capacity loss. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies by providing a reliability-aware hybrid flash memory read optimization method. This method involves migrating data from data pages with different characteristics to flash memory pages with varying reliability (SLC / TLC / QLC) for reading. By analyzing factors affecting flash memory reliability, a model of the original bit error rate and read retries is established, forming a principle for mode switching and data migration. Different mode pages are matched according to the data characteristics and reliability requirements. Reading is performed on the migrated pages, avoiding repeated read retries on the original QLC pages, thereby optimizing flash memory read performance and achieving read performance optimization for high-density flash memory. This method uses a data page heat classifier, an original bit error rate calculator, and a read retries counter in the flash memory controller to identify the characteristics of data pages. Corresponding migration mechanisms are designed for data pages with different characteristics to adjust resource allocation among pages with different reliability levels within the flash memory, optimizing the overall read performance of the flash memory device. This invention identifies the hot, cold, warm, and hot characteristics of data and matches pages of different reliability based on the number of read retry attempts on the current page. This allows hot data with a high number of read retry attempts to be migrated to high-reliability pages, warm data with a high number of read retry attempts to be migrated to relatively high-reliability pages, and cold data with a low number of read retry attempts to be retained on low-reliability pages. Through dual conversion and migration metrics, the reliability of hot and warm data is improved while reducing read performance loss caused by repeated read retry operations. This improves the read performance of high-density flash memory, optimizes repeated read operations during the reading process, effectively reduces the latency overhead of the read retry mechanism, and is simple, effective, and has promising application prospects.

[0007] The technical solution for achieving the object of the present invention is: a hybrid flash read optimization method based on reliability awareness, which is characterized in that a real-time monitoring of the number of accesses to data pages, the original bit error rate (RBER), a hot read recognition mechanism, and a read retry count mechanism are added to the flash controller of a flash solid-state drive to optimize the read performance of high-density flash. The flash solid-state drive adopts a hybrid of two or more modes among SLC, MLC, TLC, and QLC; the hot read recognition mechanism is a recognition mechanism for warm / hot data based on the number of reads of the flash page where the currently accessed data is located. When the number of reads reaches or exceeds a first dynamic threshold T1 but is less than a second dynamic threshold T2, i.e., T1 < T2, it is recognized as warm data; when the number of reads reaches or exceeds the second dynamic threshold T2, it is recognized as hot read data; if it is recognized as warm data or hot data, then according to the reliability of the page where the current data is located and the read retry count, it is determined whether it is necessary to migrate to a flash page with a higher reliability mode for the read operation, and a reset mechanism is adopted for the data heat after migration; the read retry count mechanism performs dynamic calculation after reliability modeling based on the original bit error rate (RBER) of the data page and the error correction ability of the low-density parity-check (LDPC) error correction code; the original bit error rate of the data page is a model constructed by dynamically obtaining flash reliability information; the flash reliability information includes: the number of erase / write cycles, the retention time, and the number of reads of the flash; the reset mechanism, after the data is migrated to a new flash page, attenuates the data heat of the page where it is located to half of the original, and the number of reads and read retry counts of all data pages are uniformly set to zero at the beginning; The flash controller uses a flash block as the minimum management unit to perform mode conversion and data migration, and matches appropriate reliability pages for data with different characteristics, ensuring that all pages in the target block after migration are in the same flash mode of SLC, TLC, or QLC; the mode conversion is achieved by adjusting the reference voltage and programming algorithm of the flash to perform conversion between different flash modes of SLC, TLC, or QLC. When the number of free pages in the target flash block is insufficient for data page migration, the mode conversion is triggered, and then the data migration is performed; the operations of the mode conversion and data migration specifically include: 1) When it is monitored that hot data resides on a QLC page and the read retry count of this page reaches or exceeds the first dynamic threshold R1, check all pages on the block where this QLC page is located with a read retry count greater than R1. If there are sufficient free pages on the SLC block at this time, trigger the data migration operation of migrating the eligible pages on the QLC block to the SLC pages in the SLC block; if there are insufficient free pages on the SLC block at this time, trigger the mode conversion operation of converting an idle QLC block to an SLC block, and trigger the data migration operation after the mode conversion; if there is no idle QLC block at this time, no mode conversion and data migration operations are performed; similarly, perform the mode conversion and data migration operations on the hot data on the TLC page according to the above method; 2) When it is monitored that the temperature data resides on a QLC page and the read retry count of this page reaches or exceeds the second dynamic threshold R2, that is, when R1 < R2, check all the pages on the block where this QLC page is located with read retry counts greater than R2. If there are sufficient free pages on the TLC block at this time, trigger a data migration operation to migrate the eligible pages on the QLC block to the TLC block; if there are insufficient free pages on the TLC block at this time, trigger a mode conversion operation to convert an idle QLC block to a TLC block. After the mode conversion, trigger the above data migration operation; if there is no idle QLC block at this time, no mode conversion and data migration operations are performed. 3) For cold data with a low access count or a read retry count that does not reach the corresponding threshold, maintain its storage in the QLC flash block; for warm data with a general access count or a read retry count that does not reach the corresponding threshold, maintain its storage in the TLC flash block.

[0008] The flash solid-state drive adopts a hybrid of any two or three modes among SLC, MLC, TLC, QLC or PLC.

[0009] The first dynamic threshold R1 and the second dynamic threshold R2 are dynamically configured according to the requirements of the actual workload and the life stage of the flash block; the life stage of the flash block is divided into a young stage, a middle-aged stage and an old stage; the specific configuration of the first dynamic threshold R1 and the second dynamic threshold R2 is as follows: in the same flash life stage and the same workload, count the overall read performance improvement and capacity loss under different combinations of dynamic thresholds (R1, R2), and select the threshold combination with lower capacity loss and higher performance improvement as the actually adopted threshold according to the experimental results of the two.

[0010] The mode conversion and data migration include: 1) When it is monitored that the access count of the data stored in the SLC or TLC flash block drops to the cold data level and the read count is lower than the corresponding threshold at the same time, trigger an operation to migrate the data on the SLC or TLC page to the QLC page. 2) If there are insufficient QLC free pages on the QLC block, trigger an operation to convert all the pages on the SLC or TLC block to the QLC mode, so as to release the capacity of the high-performance flash block to accommodate newly generated or hot data with an increased access count.

[0011] The storage density of the high-density flash gradually increases from SLC → MLC → TLC → QLC, and its reliability and read performance gradually decrease. When the data page is currently in the QLC mode, the higher reliability modes are SLC, MLC or TLC modes; when the data page is currently in the TLC mode, the higher reliability modes are SLC or MLC modes.

[0012] The basic process of the hybrid flash memory read performance optimization method is as follows: Step 1: When a user sends an access request, the number of times the accessed data page is read will increase simultaneously. Record.

[0013] Step 2: The smallest unit of flash memory read operation is a page. Before reading each page, the data on the accessed page is identified by its hotness. If the data on QLC / TLC is identified as hot or warm data, the process proceeds to Step 3 below; if the data on SLC is identified as cold data, the process proceeds to Step 4 below; if the data on QLC / TLC is identified as cold data, or the data on SLC is identified as hot data, the process stops.

[0014] Step 3: Calculate the number of read retry attempts for the pages containing hot and warm data. If the number of read retry attempts for hot / warm data is high, then these data are matched with high reliability pages, that is, the data is migrated to high reliability pages for reading. When there are not enough high reliability free pages, necessary flash mode conversion is performed. If the number of read retry attempts for hot / warm data is low, then these data are matched with low reliability pages, that is, no data migration operation is performed.

[0015] Step 4: For cold data located on SLC, the data is migrated to low-reliability pages, while simultaneously increasing the overall capacity of the device. Finally, the data migration and conversion process during the read operation is managed at the flash memory block level. The simplified process described above mainly consists of the following three aspects: 1) Provide a data popularity identification mechanism, specifically including: A data heat identification method based on access thresholds is adopted, which has been widely used in previous work. Its basic idea is to update and record the number of read operations on the current data in real time. When the number of read accesses is higher than threshold T1 but lower than threshold T2, the data is marked as warm data; when the number of read accesses is higher than threshold T2, the data is marked as hot data; other data is marked as cold data. This heat information is reset after data migration, i.e., marked as cold data. The data heat information is used to guide the calculation of subsequent read retry counts.

[0016] 2) Provide a method for calculating the number of read retry attempts for a data page, specifically including: The raw bit error rate is modeled based on factors affecting flash memory reliability. Then, the number of page read retry attempts is modeled based on the raw bit error rate and error correction code capability. During data access, flash memory reliability information (erasure / write cycles, retention time, and read cycles) is updated and recorded in real time. The raw bit error rate is calculated, and then the number of read retry attempts is calculated. Read retry attempts are calculated for pages marked as hot or warm data on the QLC and on the TLC, providing guidance for subsequently matching pages with different reliability levels.

[0017] 3) Provide a reliability-aware hybrid flash memory read method, specifically including: Unlike previous methods, this method considers both data hotness characteristics and read retry mechanisms simultaneously, and is not limited to dual-mode SLC-QLC / SLC-TLC. This invention introduces a hotness classification module, a raw bit error rate calculation module, a read retry counting module, and a data migration and mode conversion control module into the flash translation layer (FTL) of the solid-state drive controller, realizing a joint migration and conversion strategy based on data hotness and cell reliability. This method avoids excessive data page migration caused by simple hot / cold data determination, and supports fine-grained conversion between SLC, TLC, and QLC modes. When a large number of read retries occur on QLC, hot data can be migrated to SLC, and warm data to TLC, achieving a balance between performance and capacity. Since flash memory has a limited lifespan, and its reliability gradually decreases with increasing read / write / erase cycles, the number of read retries gradually increases. Therefore, different read retry thresholds are used for flash memory with different lifecycles. From young to middle-aged to old, the lower the reliability, the higher the read retry threshold.

[0018] The solid-state drive is a flash memory solid-state drive that combines two or more of the following modes: SLC, MLC, TLC, and QLC.

[0019] The above three methods will work in the following three situations: In the first scenario, when hot data located on a QLC / TLC page is identified during the reading process, if the number of read retries for that page reaches the dynamic threshold R1, a highly reliable SLC page is matched for data migration. If there are not enough SLC free pages on the SLC block, a mode conversion from a QLC / TLC free block to an SLC block is triggered first, followed by data migration.

[0020] The second scenario is that when warm data is identified on a QLC page, if the number of read retry attempts for that page reaches the dynamic threshold R2, a TLC page with higher reliability will be matched for data migration. Whether to perform mode switching depends on the availability of TLC free pages.

[0021] The third case is that when cold data located on an SLC / TLC page is identified, if the read retry count of this page is low, a QLC page with lower reliability is matched for data migration operations, and the freed idle page continues to store other hot / warm data that meets the read retry conditions.

[0022] Compared with the prior art, the present invention has a read method that senses the reliability of data pages, realizes the improvement of the read performance of high-density flash memory, optimizes the repeated rereading operations during the reading process of high-density flash memory, effectively reduces the latency overhead brought by the read retry mechanism. This method realizes the read performance optimization of hybrid flash memory at the cost of sacrificing a small amount of device capacity. According to the characteristics and reliability requirements of data, and combined with the reliability situation of the current page where it is located, it is migrated to a matching reliability page for reading, avoiding repeated reading operations of hot data on low-reliability pages, significantly improving the read performance of the flash memory. The method is simple, has good usage effects, and has a certain application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is an architecture diagram for implementing the present invention in Embodiment 1; Figure 2 It is a schematic diagram of the reliability matching mechanism for data pages; Figure 3 It is a schematic diagram of the data migration and mode conversion control mechanism. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The present invention is applied to a solid-state flash drive that mixes two or more of SLC, MLC, TLC, and QLC modes. A mechanism for real-time monitoring of the access count of data pages, the raw bit error rate (RBER), and the read retry count is added to the flash controller of the solid-state flash drive.

[0025] The present invention adopts a hot read identification mechanism for data, based on the read count of the flash page where the currently accessed data is located. When the read count reaches or exceeds the first threshold T1 but is less than the second threshold T2 (T1 < T2), it is identified as warm data; when the read count reaches or exceeds the second threshold T2, it is identified as hot read data. If it is identified as warm data or hot data, it is determined whether to migrate to a flash page with a higher reliability mode for reading operations according to the reliability of the current data page and the read retry count.

[0026] The read retry count mechanism is dynamically calculated after reliability modeling based on the raw bit error rate (RBER) of the data page and the error correction ability of the low-density parity-check (LDPC) error correction code; the raw bit error rate of the data page is based on factors affecting the reliability of the flash memory, such as the number of erase / write cycles, retention time, read count, etc., and is calculated by dynamically obtaining this information.

[0027] This invention employs a reset mechanism for the data popularity after migration. When data is migrated to a new flash memory page, the popularity of the data on that page is reduced to half of its original value. Initially, the read count and read retries for all data pages are uniformly set to zero.

[0028] The higher reliability mode in this invention is relative, progressing from SLC to MLC to TLC, and finally to QLC mode. Storage density gradually increases, while reliability and read performance gradually decrease. If a data page is currently in QLC mode, a higher reliability mode could be SLC, MLC, or TLC mode; conversely, if a data page is currently in TLC mode, a higher reliability mode could be SLC or MLC mode.

[0029] The key to this invention lies in providing dual data migration metrics and placing data with different characteristics on flash memory pages of different reliability modes, determining whether data resides in the original flash memory page or is migrated to a flash memory page of a higher reliability mode for reading. The basic idea is to migrate data with a high number of read retries in a lower reliability mode (such as QLC) to a higher reliability mode for reading, while ensuring capacity requirements are met. For hot data with high reliability requirements, migration is made to the high-reliability SLC mode; for warm data with moderate reliability requirements, migration is made to the moderate-reliability TLC mode; and for cold data with low reliability requirements, it remains in the QLC mode to reduce capacity loss, providing appropriate reliability guarantees for different types of data, thereby optimizing the overall read performance of the device.

[0030] This invention matches suitable reliability pages to data with different characteristics. The flash memory controller uses flash memory blocks as the smallest management unit to perform mode switching and data migration, ensuring that all pages in the target block are in the same flash memory mode (SLC, TLC, or QLC) after migration. The mode switching refers to the conversion between different flash memory modes (SLC, TLC, or QLC), which is triggered when data pages need to be migrated and there are not enough free pages on the target flash memory block. Mode switching can be achieved by adjusting the reference voltage of the flash memory and the programming algorithm.

[0031] The specific operations for triggering mode switching and data migration include: 1) When hot data is detected residing on a QLC page and the number of read retries for that page reaches or exceeds the first dynamic threshold R1, check all pages in the block where the QLC page resides that have a read retries greater than R1. If there are sufficient free pages in the SLC block at this time, trigger the data migration operation to move the qualified pages in the QLC block to SLC pages in the SLC block; if there are insufficient free pages in the SLC block at this time, trigger the mode switching operation to convert an idle QLC block to an SLC block, and then trigger the above data migration operation; if there are no idle QLC blocks at this time, no mode switching and data migration operation is performed. The same applies to hot data on TLC pages.

[0032] 2) When it is detected that the warm data resides on a QLC page and the read retry count of this page reaches or exceeds the second dynamic threshold R2 (R1 < R2), check all the pages on the block where this QLC page is located with read retry counts greater than R2. If there are sufficient free pages on the TLC block at this time, trigger the data migration operation of migrating the pages that meet the requirements on the QLC block to the TLC pages in the TLC block; if there are insufficient free pages on the TLC block at this time, trigger the mode conversion operation of converting an idle QLC block to a TLC block, and then trigger the above data migration operation; if there is no idle QLC block at this time, no mode conversion and data migration operations are performed.

[0033] 3) For cold data with a low access count or a read retry count that does not reach the corresponding threshold, maintain its storage in the QLC flash block; for warm data with a general access count or a read retry count that does not reach the corresponding threshold, maintain its storage in the TLC flash block, so as to significantly improve the read performance while minimizing the capacity loss caused by mode conversion.

[0034] The flash memory mode is not limited to the three mixed flash memory modes of SLC, TLC, or QLC, and can also be extended to other high-density flash memories with multiple-bit cells, such as any two or three mixed flash memory modes of SLC, MLC, TLC, QLC, or PLC.

[0035] The first dynamic threshold R1 and the second dynamic threshold R2 are dynamically configured according to the requirements of the actual workload and the life stage of the flash block. The life stage of the flash block refers to being measured by the number of erase / write cycles of the flash block. Taking the QLC block as an example, its life is approximately 1000 P / E cycles. Then, when the P / E cycle is 0 - 333, it is marked as the young stage; when the P / E cycle is 334 - 666, it is marked as the middle-aged stage; when the P / E cycle is greater than 667, it is marked as the old stage.

[0036] The specific configuration method of the dynamic thresholds R1 and R2 is: in the same flash memory life stage and the same workload, count the overall read performance improvement and capacity loss under different combinations of dynamic thresholds (R1, R2), and select the threshold combination with lower capacity loss and higher performance improvement as the actually adopted threshold according to the experimental results of the two. Usually, under the same workload, the dynamic thresholds set for flash blocks in different life stages are usually different.

[0037] The present invention further includes: providing a reverse conversion strategy, which triggers the migration of data on the SLC or TLC pages to QLC pages when the number of accesses to data stored in the SLC or TLC flash block drops to the cold data level and the number of reads is lower than the corresponding threshold. If there are not enough QLC free pages on the QLC block, the operation of converting all pages on the SLC or TLC block to QLC mode is triggered, thereby freeing up the capacity of the high-performance flash block to accommodate newly generated or hot data with increased access frequency.

[0038] The technical solution and effects of the present invention will be further described in detail below through specific embodiments.

[0039] Example 1 See Figure 1 This invention adds a data page reliability matching mechanism and a data migration and conversion control mechanism to the solid-state drive controller. Data from data pages with different characteristics is migrated to flash memory pages (SLC / TLC / QLC) with different reliability levels for reading. By analyzing factors affecting flash memory reliability, a model of the original bit error rate and read retries is established, forming a principle for mode conversion and data migration. Different modes of pages are matched according to the characteristics and reliability requirements of the data. Reading is performed on the migrated pages, avoiding repeated read retries on the original QLC pages, thereby optimizing flash memory read performance and achieving high-density flash memory read performance optimization. The solid-state drive is a flash memory solid-state drive that combines two or more of the following modes: SLC, MLC, TLC, and QLC.

[0040] See Figure 2 Based on the data heat identification mechanism and the number of page read rereads, this invention matches and migrates different data to different reliability pages (SLC / TLC / QLC). Here, the reliability of the four types of pages on the QLC block is not distinguished.

[0041] See Figure 3 This invention migrates the hot data identified on the QLC through the principles of data migration and mode conversion; See Figures 1-3 This invention is applied to flash solid-state drives that combine two or more of the following modes: SLC, MLC, TLC, and QLC. It is implemented through the following main steps: Step 1: When the host sends a read request, the value of the data access counter is incremented and recorded. The value of the data access counter is used to determine the data's popularity (cold / warm / hot). Step 2: When hot / warm data is found on QLC or hot data on TLC, the number of read retry counts for the page containing the data is calculated. The data heat and the number of read retry counts are used to jointly determine whether the data should be migrated. Step 3: When the read retry count of the page where the hot data on the QLC / TLC reaches the dynamic threshold R1, data migration is performed on the data page. If the number of SLC free pages on the current SLC block is not enough, a conversion from QLC / TLC to SLC mode needs to be performed before data migration; Step 4: When the read retry count of the page where the warm data on the QLC reaches the dynamic threshold R2 (R1 < R2), data migration is performed on the data page. If the number of TLC free pages on the current TLC block is not enough, a conversion from QLC to TLC mode needs to be performed before data migration; Step 5: When the data is migrated to a new page, update the read retry count counter of the data page; Step 6: Check the data on the SLC / TLC. If it is identified as cold data and the read retry count of the page where it is located is low, perform mode conversion and data migration; The present invention migrates data to different reliability pages for reading according to the heat characteristics and read retry counts of the data. The heat characteristics and read retry counts of the data change with user requests. When the dynamic threshold for warm / hot data recognition is met, the read retry count is calculated. If the read retry threshold is also met, the corresponding data migration operation is executed. And the read retry threshold is adjusted according to the life cycle of the flash memory. The older the flash memory block, the larger the corresponding threshold.

[0042] The present invention reduces the excessive migration overhead caused by rapid heat changes according to the characteristics and read retry counts of the data, while meeting the reliability requirements of different data, and fully utilizes the role of the high-reliability flash memory mode in improving read performance. At the same time, previous research has shown that hot data accounts for a small proportion in the storage space. Therefore, fewer pages need to be migrated and converted, and the overall capacity loss of the device is small, and the user's usage requirements can be guaranteed.

[0043] In addition, several types of overheads are required to implement the present invention, namely storage and latency overheads. The storage overhead includes the read counter and read retry counter for each page. The size of these additional metadata is much lower than that of the data page itself, so it can be ignored in modern large-capacity solid-state drives. For the data migration cost, since the proportion of the storage space where the hot data is located is very small itself, and the read retry threshold condition needs to be met at the same time, the amount of data migrated is very small. At the same time, at high read retry counts, the read and reprogramming latency brought by migration is smaller than the latency brought by retry. Therefore, the reliability-aware hybrid flash read performance optimization method only introduces a small amount of overhead but brings a large improvement in read performance.

[0044] The above is only a further description of the present invention, and is not intended to limit this patent. All equivalent implementations of the present invention should be included within the scope of the claims of this patent.

Claims

1. A reliability-aware hybrid flash memory read optimization method, characterized in that, In the flash controller of a flash solid-state drive, a real-time monitoring mechanism for the access count of data pages, the original bit error rate, a hot read recognition mechanism, and a read retry count mechanism are added to optimize the read performance of high-density flash memory. The flash solid-state drive adopts a hybrid of two or more modes among SLC, MLC, TLC, and QLC; the hot read recognition mechanism is a mechanism for identifying warm / hot data based on the read count of the flash page where the current accessed data is located. When the read count reaches or exceeds the first dynamic threshold T1 but is less than the second dynamic threshold T2, i.e., T1 < T2, it is identified as warm data; when the read count reaches or exceeds the second dynamic threshold T2, it is identified as hot read data; if it is identified as warm data or hot data, then based on the reliability of the page where the current data is located and the read retry count, it is determined whether it is necessary to migrate to a flash page with a higher reliability mode for the read operation, and a reset mechanism is adopted for the data heat after migration; the read retry count mechanism performs dynamic calculation after reliability modeling based on the original bit error rate of the data page and the error correction ability of the low-density parity-check (LDPC) error correction code; the original bit error rate of the data page is a model constructed by dynamically obtaining flash reliability information; the flash reliability information includes: the number of erase / program cycles, the retention time, and the read count of the flash memory; the reset mechanism, after the data is migrated to a new flash page, attenuates the data heat of the page where it is located to half of the original. The read counts and read retry counts of all data pages are uniformly set to zero initially, and the read retry count of the page needs to be recalculated after the data migration.

2. The reliability-aware hybrid flash memory read optimization method according to claim 1, characterized in that, The flash controller uses flash blocks as the minimum management unit to perform mode conversion and data migration, and matches suitable reliability pages for data with different characteristics, ensuring that all pages in the target block after migration are in the same flash mode of SLC, TLC, or QLC; the mode conversion is achieved by adjusting the reference voltage and programming algorithm of the flash memory to perform the conversion between different flash modes of SLC, TLC, or QLC. When there are insufficient free pages in the target flash block during data page migration, the mode conversion is triggered, and then the data migration is performed; The operations of the mode conversion and data migration specifically include: 1) When it is monitored that hot data resides on a QLC page and the read retry count of this page reaches or exceeds the first dynamic threshold R1, check all pages on the block where this QLC page is located with a read retry count greater than R1. If there are sufficient free pages on the SLC block at this time, trigger the data migration operation to migrate the eligible pages on the QLC block to the SLC pages on the SLC block; if there are insufficient free pages on the SLC block at this time, trigger the mode conversion operation to convert an idle QLC block to an SLC block, and trigger the data migration operation after the mode conversion; if there is no idle QLC block at this time, no mode conversion and data migration operations are performed; similarly, perform the mode conversion and data migration operations on the hot data on the TLC page according to the above method. 2) When it is monitored that the warm data resides on a QLC page and the read retry count of this page reaches or exceeds the second dynamic threshold R2, that is, when R1 < R2, check all the pages on the block where the QLC page is located with read retry counts greater than R2. If there are sufficient free pages on the TLC block at this time, trigger the data migration operation of migrating the eligible pages on the QLC block to the TLC block; if there are insufficient free pages on the TLC block at this time, trigger the mode conversion operation of converting an idle QLC block to a TLC block. After the mode conversion, trigger the above data migration operation; if there is no idle QLC block at this time, no mode conversion and data migration operations are performed. 3) For cold data with a low access count or a read retry count not reaching the corresponding threshold, maintain its storage in the QLC flash block; for warm data with a general access count or a read retry count not reaching the corresponding threshold, maintain its storage in the TLC flash block.

3. The reliability-aware hybrid flash memory read optimization method according to claim 1, characterized in that, The flash solid-state drive adopts a hybrid of any two or three modes among SLC, MLC, TLC, QLC or PLC.

4. The reliability-aware hybrid flash memory read optimization method according to claims 1 and 2, characterized in that, The first dynamic threshold R1 and the second dynamic threshold R2 are dynamically configured according to the requirements of the actual workload and the life stage of the flash block; the life stage of the flash block is divided into a young stage, a middle-aged stage and an old stage; the specific configuration of the first dynamic threshold R1 and the second dynamic threshold R2 is as follows: in the same flash life stage and the same workload, count the overall read performance improvement and capacity loss under different combinations of dynamic thresholds (R1, R2), and select the threshold combination with lower capacity loss and higher performance improvement as the actually adopted threshold according to the experimental results of the two.

5. The reliability-aware hybrid flash memory read optimization method according to claims 1 and 2, characterized in that, The mode conversion and data migration include: 1) When it is monitored that the access count of the data stored in the SLC or TLC flash block drops to the cold data level and the read count is lower than the corresponding threshold, trigger the operation of migrating the data on the SLC or TLC page to the QLC page. 2) If there are insufficient QLC free pages on the QLC block, trigger the operation of converting all the pages on the SLC or TLC block to the QLC mode, so as to release the capacity of the high-performance flash block to accommodate newly generated or hot data with an increased access count.

6. The reliability-aware hybrid flash memory read optimization method according to claim 1, characterized in that, The storage density of the high-density flash gradually increases from SLC → MLC → TLC → QLC, and its reliability and read performance gradually decrease. When the data page is currently in the QLC mode, the higher reliability modes are SLC, MLC or TLC modes; when the data page is currently in the TLC mode, the higher reliability modes are SLC or MLC modes.

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