PCIe cross-version link capability mapping and transaction data reconstruction method

Abstract

The invention discloses a PCIe cross-version link capability mapping and transaction data reconstruction method, which comprises the following steps: link negotiation and physical layer opposite end simulation: a cross-generation PCIe bridging device simulates high-version equipment behavior training and establishes a first link between the cross-generation PCIe bridging device and a host, the cross-generation PCIe bridging device simulates behavior training of the low-version device and establishes a second link between the cross-generation PCIe bridging device and the low-version device; data processing and transmission: the cross-generation PCIe bridging device processes the data received from the host so as to adapt and transmit the data to the low-version device, and the cross-generation PCIe bridging device processes the data received from the low-version device so as to adapt and transmit the data to the host; when the cross-generation PCIe bridging device processes data received from low-version equipment, the method comprises the following steps that a second unpacking module carries out protocol identification on data packets of a symbol stream transmission unit received from the low-version equipment, judges whether the data packets are transaction layer data packets or link layer data packets and then unpacks the data packets respectively.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method for mapping PCIe cross-version link capabilities and reconstructing transaction data. Background Technology

[0002] In the field of high-speed interconnect and board-level system design, PCI Express (PCIe), as the mainstream high-speed serial interconnect protocol standard, is widely used in computing platforms, server motherboards, GPU accelerator cards, and high-performance data center interconnect architectures. With the continuous growth of data processing demands, the PCIe protocol has evolved from the early Gen3 (8 GT / s) to the current mainstream Gen4 (16 GT / s), Gen5 (32 GT / s), and even the latest Gen6 (64 GT / s), providing systems with higher bandwidth density and transmission efficiency. However, the incompatibility between different generations of protocol versions has gradually become apparent, especially in systems where new and old devices coexist or where scalability requirements are high. There may be mismatches between the motherboard interface and the actual devices in terms of speed, number of channels, and encoding methods. For example, on motherboard platforms using the new generation PCIe 6.0 x4 interface, connecting traditional PCIe 4.0 x16 or PCIe 5.0 x8 devices often presents the following challenges: First, there is a significant waste of physical channel resources: due to the reduced speed, the number of channels must be increased to maintain the total bandwidth, thus occupying more PCB space and trace resources; second, the link negotiation mechanism lacks flexibility: PCIe link training and negotiation are highly dependent on the hardware initialization process. Once a device is identified as an older version, the link will automatically degrade, failing to fully utilize the speed potential of the upstream interface.

[0003] Current PCIe protocol bridging and compatibility solutions primarily rely on switch chips, retimers, or bridge-type intermediate devices to perform link isolation, protocol conversion, and path selection. These chips are typically deployed on motherboards or intermediate expansion modules, acting as independent link participants connected to the host PCIe topology. During system initialization, they must participate in link training, configuration space identification, and protocol rate negotiation, thus they cannot bypass the host's standard enumeration mechanism and lack the ability to reconstruct or masquerade the protocol formats of the link and transaction layers. Furthermore, because these chips have fixed functions and are not programmable, they lack the general ability to parse, reassemble, and adapt the underlying transaction packet structure in the face of significant changes in packet structure, transaction management, encoding mechanisms (such as PAM4), and data formats (such as the difference between link-layer FLIT packets and transaction-layer TLP packets) across different generations of PCIe protocols. They are also incapable of handling cross-generational protocol bridging tasks. More importantly, when dealing with the connectivity needs of traditional devices such as PCIe 4.0 x16, these solutions typically still require full support for x16 physical channels. Although the upstream link may have adopted the more efficient PCIe 6.0 x4 interface, and the total bandwidth remains unchanged, the limited number of physical channels results in extremely low utilization of board resources and increased cabling complexity. Therefore, existing technologies still struggle to achieve transparent bridging, bandwidth matching, and physical resource compression between high- and low-generation PCIe devices without increasing hardware complexity.

[0004] The above background information is provided only to assist in understanding the inventive concept and technical solution of this invention. It does not necessarily belong to the prior art of this application, nor does it necessarily provide technical teaching. In the absence of clear evidence that the above information was disclosed before the filing date of this application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0005] The purpose of this invention is to provide a method for PCIe cross-version link capability mapping and transaction data reconstruction.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for mapping and reconstructing PCIe cross-version link capabilities includes the following steps: Link negotiation and physical layer peer simulation: The cross-generation PCIe bridging device simulates the behavior of a high-version device for training and establishes a first link between it and the host, and the cross-generation PCIe bridging device simulates the behavior of a low-version device for training and establishes a second link between it and the low-version device. Data processing and transmission: The cross-generation PCIe bridging device processes the data received from the host to adapt and transmit it to the lower version device; the cross-generation PCIe bridging device processes the data received from the lower version device to adapt and transmit it to the host. When the cross-generation PCIe bridging device processes data received from the lower version device, it includes the following steps: The second unpacking module performs protocol identification on the data packets received from the symbol stream transmission unit of the lower version device, and unpacks them respectively after determining whether the data packets are transaction layer data packets or link layer data packets. The mapping module restores the transit label to the original label according to the pre-established mapping table, and maintains the correspondence with the unpacked data packet; The second reconstruction module reconstructs the header segment of the data according to the requirements of the FLIT transmission unit, including inserting the original tag into the header segment of the corresponding data packet; The controller encapsulates data packets into FLIT transmission units, assigns transaction sequence numbers, and adds CRC check codes to generate data packets with FLIT transmission units adapted to the host. The data packets of the FLIT transmission unit are sent to the host.

[0007] In one embodiment, the higher version is the PCIe Gen6 protocol, and the lower version is the PCIe Gen5 protocol or the PCIe Gen4 protocol.

[0008] In one embodiment, the training of the first link in the link negotiation and physical layer peer simulation step includes the following steps: The first serializer supporting PAM4 encoding is electrically connected to the host. After power-on, the first physical coding sublayer, which is electrically connected to the first serializer, drives the first link training and state machine to start, and the first link training and state machine drives the first link state transition. After the first link transitions from the detection state to the polling state, the host sends an ordered set to the first physical coding sublayer; The first link training and state machine confirms the capabilities supported by the host based on the parsed content, and the first physical coding sublayer returns the ordered set to the host; The host computer confirms the capabilities supported by the cross-generation PCIe bridging device based on the parsed content. The first link enters a normal state, and the training of the first link is completed.

[0009] In one embodiment, the training of the second link in the link negotiation and physical layer peer simulation step includes the following steps: Electrically connect the second serializer, which supports NRZ encoding, to the lower-version device; After power-on, the second physical coding sublayer, which is electrically connected to the second serializer, drives the second link training and state machine startup, and the second link training and state machine drive the second link state transition. When the second link transitions from the detection state to the polling state, the second physical coding sublayer sends an ordered set to the lower version device; The lower-version device confirms the capabilities supported by the cross-generation PCIe bridging device based on the parsed content, and the lower-version device returns the ordered set to the cross-generation PCIe bridging device; The second link training and state machine confirms the capabilities supported by the lower-version device based on the parsed content. The second link enters a normal state, and the training of the second link is completed.

[0010] In one embodiment, after the first link training and the second link training are completed, the configuration module is activated. The configuration module switches the bridging working mode according to the preset configuration instructions and sends the bridging working mode to the middle protocol processing module to activate the conversion path of data packets between the FLIT transmission unit and the symbol stream transmission unit. The FLIT transmission unit corresponds to the data transmission mode of the PCIe Gen6 protocol, and the symbol stream transmission unit corresponds to the data transmission mode of the PCIe Gen5 protocol or the PCIe Gen4 protocol.

[0011] In one embodiment, the bridging operating mode includes bridging of the PCIe Gen6 protocol with the PCIe Gen5 protocol, and bridging of the PCIe Gen6 protocol with the PCIe Gen4 protocol.

[0012] In one embodiment, a state cross-sensing step is also included: The central coordination module listens to energy management link layer data packets sent by the host and the lower version device; The central coordination module, based on the transaction type of the energy management link layer data packet, causes one of the first link and the second link to switch to the corresponding state; The central coordination module causes the other of the first link and the second link to switch to the corresponding state, so as to realize the coordinated state transition of the host and the low-version device and the coordinated operation of the first link and the second link.

[0013] In one embodiment, the state cross-sensing step further includes: the central coordination module records the state transition of the first link and the second link; when at least one of the first link and the second link enters the normal state, the central protocol processing module is notified to prepare for the data processing and transmission step; when either the first link or the second link enters the recovery state or the dormant state, the central protocol processing module is notified to suspend the data processing and transmission step.

[0014] In one embodiment, the cross-generation PCIe bridging device, when processing data received from the host, includes the following steps: The first unpacking module performs protocol identification on the data packets of the FLIT transmission unit received from the host, and unpacks them according to whether the data packets are transaction layer data packets or link layer data packets. The mapping module obtains the original tag based on the transaction sequence number in the data packet and translates it into a transit tag. The mapping relationship between the original tag and the transit tag is recorded in the mapping table to prepare for the subsequent recovery of the original tag. The CRC module performs CRC verification on the data packet and generates a CRC checksum; The first reconstruction module reconstructs the header segment of the data according to the requirements of the symbol stream transmission unit and inserts the relay tag into the header segment of the corresponding data. The first reconstruction module concatenates the data packets and adds the CRC checksum to generate a data packet that is compatible with the symbol stream transmission unit of the low-version device; The data packets from the symbol stream transmission unit are sent to the scheduling module and then transmitted to the lower version device.

[0015] In one embodiment, when the reconstruction module reconstructs the header segment of the data according to the requirements of the symbol stream transmission unit, it specifically includes one or more of field rearrangement, byte alignment, bit compression, and bit extension.

[0016] In one embodiment, when the CRC module performs CRC verification on the data packet, if the verification is successful, a corresponding valid CRC checksum is generated; if the verification fails, an inversion operation is performed to generate a corresponding incorrect CRC checksum.

[0017] In one embodiment, after receiving a data packet that failed verification, the lower version device will automatically generate a resend request to guide the host to resend the data packet.

[0018] In one embodiment, after the data packets of the symbol stream transmission unit are sent to the scheduling module, the data packets of the symbol stream transmission unit are transmitted to the lower version device according to the scheduling rule that the link layer data packets take precedence over the transaction layer data packets.

[0019] In one embodiment, when the cross-generation PCIe bridging device processes data received from the lower version device, the CRC module generates a temporary CRC for the unpacked temporary data according to the CRC algorithm specified by the higher version, ensuring the reliability of subsequent data packet encapsulation for FLIT transmission units.

[0020] In one embodiment, when the reconstruction module reconstructs the header segment of the data according to the requirements of the FLIT transmission unit, it specifically includes one or more of the following: field rearrangement, byte alignment, bit compression, and bit extension.

[0021] In one embodiment, it can be applied to one or more of FPGA platforms, RISC platforms, x86 platforms, and ARM platforms.

[0022] The beneficial effects of the technical solution provided by this invention are as follows: a. Reduce the number of physical channels: While keeping the total bandwidth unchanged, the physical channel resources required by the motherboard can be significantly reduced through link capability mapping and data bandwidth compression mechanisms.

[0023] b. Implement protocol format reconstruction: Support the structural reorganization and bidirectional translation of data packets between different generations of PCIe protocols to ensure data consistency and transaction integrity in cross-version communication.

[0024] c. Bypassing fixed link configuration limitations: Simulate the target protocol capabilities during the link initialization phase to avoid forced speed reduction of the host due to device version limitations after identification, thereby maintaining the high-speed link operation.

[0025] d. High flexibility and customizability: This method can be adapted to multiple hardware platforms and PCIe versions, and can be flexibly deployed according to actual needs to achieve various cross-version interoperability and protocol adaptation scenarios. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of a cross-generation PCIe bridging device provided as an exemplary embodiment of the present invention; Figure 2 An architectural diagram of a cross-generation PCIe bridging device is provided as an exemplary embodiment of the present invention; Figure 3 An architecture diagram of a cross-generation PCIe bridging device for processing data received from a host, provided as an exemplary embodiment of the present invention; Figure 4 This is an architecture diagram of a cross-generation PCIe bridging device for processing data received from a lower version device, provided as an exemplary embodiment of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0030] like Figure 1-4 As shown, in some embodiments of the present invention, a method for PCIe cross-version link capability mapping and transaction data reconstruction is provided. Specifically, this method can be applied to one or more of FPGA platforms, RISC platforms, X86 platforms, and ARM platforms.

[0031] like Figure 1 As shown, this method is applied to a cross-generation PCIe bridging device on an FPGA platform. This cross-generation PCIe bridging device is located between the host and the lower-generation device. The host uses a new generation PCIe 6.0 x4 interface, which is suitable for the PCIe Gen6 protocol, and the lower-generation device uses a PCIe 4.0 x16 interface, which is suitable for the PCIe Gen4 protocol. In other embodiments, the lower-generation device can also use a PCIe 5.0 x8 interface, which is suitable for the PCIe Gen5 protocol.

[0032] The cross-generation PCIe bridging device includes a first physical layer, which includes a first serializer (Serdes) port for electrical connection to the host. This first serializer port supports PAM4 encoding and is a high-speed channel compliant with PCIe 6.0 PHY requirements. The first serializer port is electrically connected to the first physical coding sublayer (PCS), which handles basic signal tasks such as physical code recognition, symbol alignment, and link recovery (CDR). The first physical coding sublayer is also electrically connected to the first link training and status state machine (LTSSM), which drives the state transition of the first link, including the entire process from the detect state → polling state → configuration state → recovery state → active (L0) state. The first link refers to the link between the host and the first serializer port.

[0033] The cross-generation PCIe bridging device also includes a second physical layer. This second physical layer includes a second serializer (Serdes) port for electrical connection to lower-version devices. This second serializer port supports NRZ encoding and is a high-speed channel compliant with PCIe 4.0 PHY requirements. The second serializer port is electrically connected to the second physical coding sublayer (PCS), which handles basic signal tasks such as physical pattern recognition, symbol alignment, and link recovery (CDR). The second physical coding sublayer is also electrically connected to the second link training and status state machine (LTSSM), which drives the second link state transitions, including the entire process from the detect state → polling state → configuration state → recovery state → active (L0) state. The second physical coding sublayer also includes a built-in FM (Frame Generation) submodule to simulate host-side behavior, where the second link refers to the link between the host and the second serializer port.

[0034] The cross-generation PCIe bridging device also includes a middle protocol processing module. This module processes data of different formats between the first and second physical layers, enabling the conversion of FLIT transport unit packets received from the host into symbol stream transport unit packets for compatibility with older devices, and vice versa. The middle protocol processing module specifically includes the following sub-modules: The first unpacking module is configured to: identify the protocol structure and deconstruct the data packets (256-byte fixed format) of the FLIT transmission units received from the host; determine whether the data packet is a transaction layer (TLP-FLIT) packet or a link layer (DLLP-FLIT) packet; if it is TLP-FLIT: extract the TLP header field (such as Type, Length, Tag, Requester ID, Address, etc.); if it is DLLP-FLIT: extract the link layer control field (such as ACK / NAK / PM_Request, etc.); the header and payload segments in the data packet are decoded independently, and the original CRC32 in the data packet is stripped; each deconstructed data is added to the internal buffer and marked with the original transaction sequence number (SeqNum).

[0035] The second unpacking module is configured to: identify the protocol structure and decompose the data packets of the Symbol Stream Transmission Unit received from the lower version device; determine whether the data packet is a Transaction Layer (TLP) data packet or a Link Layer (DLLP) data packet; if it is DLLP data, no modification is required, but the packing order needs to be adjusted according to the encapsulation requirements of the PCIe 6.0 input interface; if it is TLP data, remove the field layouts incompatible with PCIe 6.0 in the PCIe 4.0 format.

[0036] The mapping module, due to the different length specifications of the tag fields in PCIe 6.0 and PCIe 4.0, needs to establish a mapping table to ensure compatibility of the data packets of the FLIT transmission unit received from the host with the lower version device, while also guaranteeing transaction matching and order consistency. Therefore, the mapping module is configured to: recover the tag field in PCIe 6.0 based on the transaction sequence number in the data packet of the FLIT transmission unit, and record it as the original tag; and translate it into the tag field of PCIe 4.0 according to the internal encoding mechanism, and record it as the transit tag; and record the mapping relationship between the original tag and the transit tag in the mapping table to prepare for the subsequent recovery of the original tag.

[0037] Similarly, to ensure that data packets of symbol stream transmission units received from lower version devices are compatible with the host and to guarantee transaction matching and order consistency, the mapping module is also configured to restore the relay label to the original label according to the pre-established mapping table and maintain the correspondence with the unpacked data packets so that the host can correctly track and match cross-generational transactions.

[0038] The CRC module's core objective is to ensure the consistency and validity of CRC checks across different link standards (PCIe 6.0 and PCIe 4.0), thereby enabling transparent forwarding and error mapping in the absence of protocol identification when acting as a relay bridging device. For data packets from FLIT transmission units (TLPs) received from the host side, the CRC module is configured to perform integrity checks on each received TLP packet, determining the success of the CRC check. Specifically, it first checks if the CRC field passes the check; if successful, it generates a valid CRC checksum; if it fails, it performs an inversion operation to generate an incorrect CRC checksum. For reconstructed PCIe 4.0 TLP packets, the TLP CRC needs to be recalculated and appended. Furthermore, older versions of the device automatically generate a retransmission request upon receiving a failed check packet, guiding the host to resend the data packet.

[0039] For data packets from Symbol Stream Transmission Units (SSTRU) originating from lower-version devices, the SSTRU data packets generated by the lower-version devices contain standard CRC checksums. However, considering the extremely short physical distance between the cross-generation PCIe bridging device and the lower-version device and the absence of error-prone links in between, no CRC check or verification processing is performed to avoid resource waste and processing delays. Instead, CRC-trusted forwarding is performed directly. The CRC module is configured to generate a temporary CRC for the unpacked temporary data packets of the Symbol Stream Transmission Units according to the CRC algorithm specified in PCIe 6.0, ensuring the reliability of subsequent FLIT transmission unit data packet encapsulation. Subsequently, the CRC module regenerates a CRC checksum conforming to the PCIe 6.0 standard for the reconstructed data packets, which is then added during FLIT transmission unit data packet encapsulation.

[0040] The first refactoring module, such as Figure 3As shown, for data packets from the FLIT transmission unit received from the host side, the core task is to reassemble the TLP data and DLLP data obtained from the host side into a format that conforms to the PCIe 4.0 protocol structure, and to supplement the relevant protocol fields (TAG, CRC, etc.) to ensure that they can be directly recognized and processed by PCIe 4.0 devices. The entire process maintains a transparent forwarding principle, without parsing the protocol semantic layer. Field mapping and structure adaptation are only performed where necessary. The first reconstruction module is configured to: firstly, temporarily store DLLP data (such as ACK / NAK, Flow Control, PM messages, etc.) from the host side into the DLLP buffer; secondly, temporarily store TLP data from the host side into the TLP buffer. The role of the DLLP buffer is to coordinate with the synchronization and arbitration scheduling of TLP data, so that DLLP can be sent first when needed (e.g., PM transactions). The TLP buffer ensures that data is not lost while waiting for TAG conversion, DLLP scheduling, etc., and can be correctly merged with DLLP in priority order. According to the requirements of the symbol stream transmission unit, the header segments of DLLP and TLP data are reconstructed, performing one or more of the following: field rearrangement, byte alignment, bit compression, and bit extension, such as reconstructing Type, Length, Requester ID, Address. Remove data packet-specific fields (such as transaction sequence reference bits) from the FLIT transmission unit, rearrange the field positions according to the data packet of the symbolic stream transmission unit, and insert the transit tag into the header segment of the corresponding data; then concatenate the data packets and add CRC check codes to generate data packets of the symbolic stream transmission unit adapted to low-version devices.

[0041] The scheduling module is configured to optimize data transmission without causing significant information changes. It primarily continues sending data in the order of unpacking to avoid excessive latency. It is configured to: upon receiving data packets from the symbol stream transmission unit adapted to the lower-version device after reconstruction by the first reconstruction module, transmit the data packets to the lower-version device according to the scheduling rule that DLLP data packets take precedence over TLP data packets. Specifically, it first determines whether the data packet is a DLLP or TLP packet, ensuring that power management or link maintenance data is prioritized; if it is a DLLP, such as PM_Enter_L1, ACK / NACK, etc., it is prioritized for transmission; if it is a regular TLP, it is scheduled according to FIFO or transaction priority sequence. All scheduled data is sent to the second serializer port of the second physical layer for transmission to the lower-version device.

[0042] The second reconstruction module, for data packets from the Symbol Stream Transmission Unit (SLT) received from lower-version devices, has the core task of adapting the protocol fields and reconstructing the headers of the unpacked TLP data packets and DLLP data packets to meet the controller's receiving requirements. This module does not involve data packet assembly, transaction sequence number allocation, or CRC insertion according to the requirements of the FLIT transmission unit; these are handled by the controller's hard core. Therefore, the logic implementation of this second reconstruction module is relatively simple, but it plays a crucial role in cross-generation protocol adaptation. The second reconstruction module is configured to perform one or more of the following on the data packet header segment: field rearrangement, byte alignment, bit compression, and bit extension. For example, rearranging the header segment of the PCIe 4.0 protocol structure to PCIe 6.0 format, arranging it according to the PCIe 6.0 protocol field order, removing or replacing PCIe 4.0 specific fields, and inserting the original label into the header segment of the corresponding data packet according to the correspondence between the transit label and the original label recorded in the mapping table.

[0043] The controller, specifically the PCIe 6.0 controller, is configured such that after the second reconstruction module completes the above reconstruction, TLP / DLLP data packets are directly sent to the PCIe 6.0 controller in a form conforming to the PCIe 6.0 interface standard. The controller then completes the encapsulation of the FLIT transmission unit, the allocation of the transaction sequence number, and the addition of the CRC checksum, generating a data packet of the FLIT transmission unit adapted to the host, and sending it to the first serializer port of the first physical layer to be sent to the host.

[0044] The cross-generation PCIe bridging device also includes a central coordination module. Since the training and state machine of the first link in the first physical layer and the training and state machine of the second link in the second physical layer do not interfere with each other, the central coordination module is set up to record the state transition of the first link and the second link, realize cross-sensing between the first link and the second link, ensure the consistency of data packet transmission rhythm, and thus avoid the occurrence of abnormal system states or link inconsistencies. The central coordination module is used to monitor the power management link layer data packets sent by the host and the lower version device. It is configured to: according to the transaction type of the power management link layer data packet, the central coordination module causes one of the first link and the second link to switch to the corresponding state; and causes the other of the first link and the second link to switch to the corresponding state, so as to realize the coordinated state transition of the host and the lower version device and the coordinated operation of the first link and the second link. It is also configured to: record the state transition of the first link and the second link; when at least one of the first link and the second link enters the normal state, the central protocol processing module is notified to prepare for the data processing and transmission steps; when either the first link or the second link enters the recovery state or the dormant state, the central protocol processing module is notified to suspend the data processing and transmission steps.

[0045] The cross-generation PCIe bridging device also includes a configuration module. After the first link training and the second link training are completed, the configuration module is activated and configured to: switch the bridging working mode according to the preset configuration instructions, and send the bridging working mode to the central protocol processing module to activate the conversion path of data packets between the FLIT transmission unit and the symbol stream transmission unit. The FLIT transmission unit corresponds to the data transmission mode of the PCIe Gen6 protocol, and the symbol stream transmission unit corresponds to the data transmission mode of the PCIe Gen5 protocol or the PCIe Gen4 protocol. The bridging working mode includes bridging the PCIe Gen6 protocol with the PCIe Gen5 protocol, and bridging the PCIe Gen6 protocol with the PCIe Gen4 protocol.

[0046] In one embodiment, the PCIe cross-version link capability mapping and transaction data reconstruction method of the present invention includes the following steps: Link negotiation and physical layer peer simulation: The cross-generation PCIe bridging device simulates the behavior of high-version devices for training and establishes the first link between it and the host; the cross-generation PCIe bridging device simulates the behavior of low-version devices for training and establishes the second link between it and the low-version devices. Data processing and transmission: The cross-generation PCIe bridging device processes the data received from the host to adapt and transmit it to the lower version device. The higher version uses the PCIe Gen6 protocol, and the lower version uses the PCIe Gen5 protocol or the PCIe Gen4 protocol.

[0047] The training of the first link in the link negotiation and physical layer peer simulation steps includes the following steps: Electrically connect the first serializer, which supports PAM4 encoding, to the host. After power-on, the first physical coding sublayer, which is electrically connected to the first serializer, drives the first link training and state machine startup, and the first link training and state machine drive the first link state transition. After the first link transitions from the detection state to the polling state, the host sends an ordered set to the first physical coding sublayer, which can be a TS1 / TS2 ordered set. The first link training and state machine confirms the host's supported capabilities based on the parsed content, and the first physical coding sublayer returns the ordered set to the host, which can specifically be a TS1 / TS2 ordered set; The host computer determines the capabilities supported by the cross-generation PCIe bridge device based on the parsed content. The first link has entered a normal state, and the training of the first link is complete.

[0048] The training of the second link in the link negotiation and physical layer peer simulation steps includes the following steps: Electrically connect the second serializer, which supports NRZ encoding, to the lower version device; After power-on, the second physical coding sublayer, which is electrically connected to the second serializer, drives the second link training and state machine startup, and the second link training and state machine drive the second link state transition. When the second link transitions from the detection state to the polling state, the second physical coding sublayer sends an ordered set to the lower version device, which can be a TS1 / TS2 ordered set. The lower version device confirms the capabilities supported by the cross-generation PCIe bridging device based on the parsed content, and the lower version device returns the ordered set to the cross-generation PCIe bridging device, which can specifically be a TS1 / TS2 ordered set; The second link training and state machine determine the capabilities supported by lower-version devices based on the parsed content. The second link has entered a normal state, and the training of the second link has been completed.

[0049] Among them, such as Figure 3 As shown, when a cross-generation PCIe bridge device processes data received from a host, it includes the following steps: The first unpacking module performs protocol identification on the data packets of the FLIT transmission unit received from the host, and unpacks them according to whether the data packets are transaction layer data packets or link layer data packets. The mapping module obtains the original tag based on the transaction sequence number in the data packet and translates it into a transit tag. It records the mapping relationship between the original tag and the transit tag in the mapping table to prepare for the subsequent recovery of the original tag. The CRC module performs CRC verification on the data packets and generates CRC checksums. The first reconstruction module reconstructs the header segment of the data according to the requirements of the symbol stream transmission unit and inserts the relay tag into the header segment of the corresponding data. The first reconstruction module concatenates data packets and adds CRC check codes to generate data packets for the symbol stream transmission unit adapted to low-version devices; The data packets from the symbol stream transmission unit are sent to the scheduling module and then transmitted to the lower version device.

[0050] Among them, such as Figure 4 As shown, when a cross-generation PCIe bridging device processes data received from a lower-version device, it includes the following steps: The second unpacking module performs protocol identification on the data packets of the symbol stream transmission unit received from the lower version device, and unpacks them according to whether the data packets are transaction layer data packets or link layer data packets. The mapping module restores the transit label to the original label according to the pre-established mapping table, and maintains the correspondence with the unpacked data packet; The second reconstruction module reconstructs the header segment of the data according to the requirements of the FLIT transmission unit, including inserting the original tag into the header segment of the corresponding data packet; The controller encapsulates data packets into FLIT transmission units, assigns transaction sequence numbers, and adds CRC check codes to generate data packets with FLIT transmission units adapted to the host. Send the data packets of the FLIT transmission unit to the host.

[0051] Therefore, this invention adopts a modular cross-generational protocol bridging method. Through bidirectional protocol adaptation, link capability mapping, and transaction layer data reconstruction, it achieves transparent compatibility of the host's high-version PCIe interface with low-version devices and efficient utilization of physical channel resources without changing the total bandwidth.

[0052] First, this method constructs a link capability negotiation process compatible with the PCIe 6.0 interface standard. By simulating the configuration space during the link initialization phase and key capability fields during the link training process, it can declare high version rates and channel capabilities, avoid link speed reduction caused by device version limitations, and ensure that the link operates in the expected high-speed state.

[0053] Secondly, this method designs a protocol conversion process between FLIT transmission unit and symbol stream transmission unit, which supports bidirectional reconstruction of transaction layer and link layer packet structure between PCIe 6.0 and PCIe 4.0, including the processing of the mapping relationship between transaction sequence and original label and relay label, and the decoupling and regeneration of CRC check mechanism, so as to accurately transmit data integrity and transaction consistency in cross-protocol transmission.

[0054] Furthermore, this method employs a dual-port hierarchical processing and link state independent control strategy, enabling separate management of host-side and device-side links without relying on traditional switch or bridge topologies. In conjunction with a central coordination module, it achieves transparent response to link state switching without the need for additional software driver intervention.

[0055] In summary, this method achieves a highly compatible, high-bandwidth-utilization, and low-resource-consumption PCIe cross-version protocol bridging scheme through the synergy of link capability mapping, protocol format reconstruction, configuration space virtualization, and physical resource compression mechanisms, providing a new implementation path for the interoperability of multi-generation protocol devices and high-speed system interconnection.

[0056] Compared with existing technologies, in one embodiment, the beneficial effects of this technical solution are as follows: 1. Significantly improves physical channel resource utilization and simplifies system architecture design: This method, through protocol parsing and bandwidth mapping mechanisms, allows the use of only four PCIe 6.0 lanes (x4) to carry the equivalent data bandwidth of a PCIe 4.0 x16 device, thereby significantly reducing the system's physical dependence on the number of lanes without reducing the total data throughput. This feature not only significantly reduces PCB board area and trace density, lowering connector and channel layout costs, but also provides greater structural flexibility and integration space for high-density system designs. 2. Seamless Reconstruction and Translation of Transaction Packets and Link Layer Data Across Multiple Protocol Generations: Addressing the differences in packet structure between the FLIT transport unit of PCIe 6.0 and the symbolic stream transport unit of PCIe 4.0, this method designs a complete protocol conversion process. This process can perform real-time parsing, reassembly, and repackaging of the content of transmitted transaction packets, covering the corresponding processing of the header r format, transaction identifiers (mapping from original label to relay label), and CRC check mechanisms. This mechanism ensures data consistency, response correctness, and flow control state integrity across generations of links, ensuring strict alignment of communication behaviors in protocol semantics. 3. Bypass link negotiation restrictions and ensure the utilization of upstream high-speed links: This method simulates the target protocol capability during the link initialization phase and declares high version rates and channel parameters in the configuration space. Combined with the link state machine response mechanism, the host always recognizes the interface as a high version device during the enumeration process, thereby keeping the high-speed link running at full speed and avoiding link speed reduction or bandwidth waste caused by the downstream actual device being a low version. 4. Enhance the system's deployment flexibility and protocol adaptation and expansion capabilities on heterogeneous platforms: This method is highly modular and scalable, and can flexibly adapt to the interoperability between various PCIe versions (such as Gen4, Gen5, and Gen6) according to actual needs. It can also be deployed on various hardware platforms and application scenarios, including motherboard bridging modules, adapter cards, server backplane channel compression systems, etc., thereby providing users with reconfigurable interface compatibility and protocol expansion capabilities, and improving the system's versatility and adaptability.

[0057] In summary, this technical solution has significant advantages in improving channel resource utilization, realizing cross-generational protocol conversion, ensuring continuous operation of high-speed links, and enhancing deployment flexibility, providing a feasible and scalable implementation path for the next generation of high-performance interconnect structures.

[0058] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for mapping PCIe cross-version link capabilities and reconstructing transaction data, characterized in that, Includes the following steps: Link negotiation and physical layer peer simulation: The cross-generation PCIe bridging device simulates the behavior of a high-version device for training and establishes a first link between it and the host, and the cross-generation PCIe bridging device simulates the behavior of a low-version device for training and establishes a second link between it and the low-version device. Data processing and transmission: The cross-generation PCIe bridging device processes the data received from the host to adapt and transmit it to the lower version device; the cross-generation PCIe bridging device processes the data received from the lower version device to adapt and transmit it to the host. When the cross-generation PCIe bridging device processes data received from the lower version device, it includes the following steps: The second unpacking module performs protocol identification on the data packets received from the symbol stream transmission unit of the lower version device, and unpacks them respectively after determining whether the data packets are transaction layer data packets or link layer data packets. The mapping module restores the transit label to the original label according to the pre-established mapping table, and maintains the correspondence with the unpacked data packet; The second reconstruction module reconstructs the header segment of the data according to the requirements of the FLIT transmission unit, including inserting the original tag into the header segment of the corresponding data packet; The controller encapsulates data packets into FLIT transmission units, assigns transaction sequence numbers, and adds CRC check codes to generate data packets with FLIT transmission units adapted to the host. The data packets of the FLIT transmission unit are sent to the host.

2. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 1, characterized in that: in, The higher version is the PCIe Gene6 protocol, and the lower version is the PCIe Gene4 protocol.

3. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 1, characterized in that: In the link negotiation and physical layer peer simulation steps, the training of the first link includes the following steps: The first serializer supporting PAM4 encoding is electrically connected to the host. After power-on, the first physical coding sublayer, which is electrically connected to the first serializer, drives the first link training and state machine to start, and the first link training and state machine drives the first link state transition. After the first link transitions from the detection state to the polling state, the host sends an ordered set to the first physical coding sublayer; The first link training and state machine confirms the capabilities supported by the host based on the parsed content, and the first physical coding sublayer returns the ordered set to the host; The host confirms the capabilities supported by the cross-generation PCIe bridging device based on the parsed content. The first link enters a normal state, and the training of the first link is completed.

4. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 3, characterized in that: In the link negotiation and physical layer peer simulation steps, the training of the second link includes the following steps: Electrically connect the second serializer, which supports NRZ encoding, to the lower-version device; After power-on, the second physical coding sublayer, which is electrically connected to the second serializer, drives the second link training and state machine startup, and the second link training and state machine drive the second link state transition. When the second link transitions from the detection state to the polling state, the second physical coding sublayer sends an ordered set to the lower version device; The lower-version device confirms the capabilities supported by the cross-generation PCIe bridging device based on the parsed content, and the lower-version device returns the ordered set to the cross-generation PCIe bridging device; The second link training and state machine confirms the capabilities supported by the lower-version device based on the parsed content. The second link enters a normal state, and the training of the second link is completed.

5. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 4, characterized in that: After the first link training and the second link training are completed, the configuration module is activated. The configuration module switches the bridging working mode according to the preset configuration instructions and sends the bridging working mode to the middle protocol processing module to activate the conversion path of data packets between the FLIT transmission unit and the symbol stream transmission unit. The FLIT transmission unit corresponds to the data transmission mode of the PCIe Gen6 protocol, and the symbol stream transmission unit corresponds to the data transmission mode of the PCIe Gen5 protocol or the PCIe Gen4 protocol.

6. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 5, characterized in that: The bridging modes mentioned above include bridging PCIe Gen6 and PCIe Gen5 protocols, and bridging PCIe Gen6 and PCIe Gen4 protocols.

7. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 4, characterized in that, It also includes the state cross-sensing step: The central coordination module listens to energy management link layer data packets sent by the host and the lower version device; The central coordination module, based on the transaction type of the energy management link layer data packet, causes one of the first link and the second link to switch to the corresponding state; The central coordination module causes the other of the first link and the second link to switch to the corresponding state, so as to realize the coordinated state transition of the host and the low-version device and the coordinated operation of the first link and the second link.

8. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 7, characterized in that: The state cross-sensing step further includes: the central coordination module records the state transition of the first link and the second link; when at least one of the first link and the second link enters the normal state, the central protocol processing module is notified to prepare for the data processing and transmission step; when either the first link or the second link enters the recovery state or the dormant state, the central protocol processing module is notified to suspend the data processing and transmission step.

9. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 1, characterized in that: When the cross-generation PCIe bridging device processes data received from the host, it includes the following steps: The first unpacking module performs protocol identification on the data packets of the FLIT transmission unit received from the host, and unpacks them according to whether the data packets are transaction layer data packets or link layer data packets. The mapping module obtains the original tag based on the transaction sequence number in the data packet and translates it into a transit tag. The mapping relationship between the original tag and the transit tag is recorded in the mapping table to prepare for the subsequent recovery of the original tag. The CRC module performs CRC verification on the data packet and generates a CRC checksum; The first reconstruction module reconstructs the header segment of the data according to the requirements of the symbol stream transmission unit and inserts the relay tag into the header segment of the corresponding data. The first reconstruction module concatenates the data packets and adds the CRC checksum to generate a data packet that is compatible with the symbol stream transmission unit of the low-version device; The data packets from the symbol stream transmission unit are sent to the scheduling module and then transmitted to the lower version device.

10. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 9, characterized in that: When the reconstruction module reconstructs the header segment of the data according to the requirements of the symbol stream transmission unit, it specifically includes one or more of the following: field rearrangement, byte alignment, bit compression, and bit extension.

11. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 9, characterized in that: When the CRC module performs CRC verification on the data packet, if the verification is successful, it generates a corresponding valid CRC checksum; if the verification fails, it performs an inversion operation to generate a corresponding incorrect CRC checksum.

12. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 11, characterized in that: Upon receiving a data packet that failed verification, the lower-version device will automatically generate a resend request to guide the host to resend the data packet.

13. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 9, characterized in that: After the data packets of the symbol stream transmission unit are sent to the scheduling module, the data packets of the symbol stream transmission unit are transmitted to the lower version device according to the scheduling rule that the link layer data packets take precedence over the transaction layer data packets.

14. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 1, characterized in that: When the cross-generation PCIe bridging device processes data received from the lower version device, the CRC module generates a temporary CRC for the unpacked temporary data according to the CRC algorithm specified by the higher version, ensuring the reliability of data packet encapsulation for subsequent FLIT transmission units.

15. The PCIe cross-version link capability mapping and transaction data reconstruction method according to claim 1, characterized in that: When the reconstruction module reconstructs the header segment of the data according to the requirements of the FLIT transmission unit, it specifically includes one or more of the following: field rearrangement, byte alignment, bit compression, and bit extension.

16. The PCIe cross-version link capability mapping and transaction data reconstruction method according to any one of claims 1-15, characterized in that: It can be applied to one or more of the following platforms: FPGA, RISC, X86, and ARM.

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