A circuit timing repair method and system for pre-post simulation

Abstract

The application discloses a circuit timing repair method and system for pre-simulation and post-simulation, and the method comprises the following steps: obtaining a path violating timing constraints in a circuit through timing analysis software; determining whether timing requirements can be met by modifying the delay of combination logic and the setup time parameter and the hold time parameter of a terminal register; if not, the clock tree delay of a starting point register or a terminal register is modified, timing information is analyzed, a path violating timing is obtained again, and then the determination is made; if yes, the setup time parameter and the hold time parameter of the combination logic and the terminal register are modified to meet the setup time constraints and the hold time constraints; finally, a netlist and a delay file meeting timing requirements after repair are extracted and provided for pre-simulation and post-simulation. The application aims at pre-simulation and post-simulation of a chip design after preliminary physical design to accelerate the timing and functional verification progress of the chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and specifically to a method and system for circuit timing repair oriented towards pre- and post-simulation. Background Technology

[0002] In the integrated circuit design flow, static timing analysis is an essential method for determining whether a circuit meets timing targets. However, many current VLSI logic chips have numerous timing exceptions and require manual judgment regarding timing constraints. Static timing analysis can only be performed on existing timing constraints; if the timing constraints are problematic, the results of static timing analysis will be biased, thus increasing the risk of tape-out. Circuit timing constraints are manually generated by designers without standardized verification processes, heavily relying on the designer's experience. Therefore, using the gate-level netlist of the completed physical design, along with delay back-annotation files, for post-annotation simulation (often called post-simulation) is a crucial method for verifying the correctness of timing constraints.

[0003] Post-simulation requires physical design netlists and delay back-annotation files that meet timing constraints. Design modules with high timing requirements may require months or even longer for timing repairs during the physical design phase to meet these constraints. Setting up and debugging the post-simulation environment also takes considerable time, and post-simulation runs very slowly. Therefore, post-simulation significantly impacts chip development and tape-out schedules. Advanced pre- and post-simulation (or super-pre-simulation) refers to performing post-simulation work before timing constraints are met during the physical design phase, enabling parallel execution of physical design and post-simulation to accelerate chip development. Therefore, for netlists and delay back-annotation files that do not meet timing requirements, special timing repairs are needed to satisfy the requirements of advanced pre- and post-simulation. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a circuit timing repair method and system for advanced forward and backward simulation, aiming to accelerate the timing and functional verification of chips by performing advanced forward and backward simulation on chip designs after the completion of preliminary physical design.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A circuit timing repair method for pre- and post-simulation includes the following steps:

[0007] S101, Obtain the netlist and delay back-annotation file of the chip circuit after completing the preliminary physical design;

[0008] S102, The timing of the circuit is analyzed using timing analysis software, and a current path that violates timing constraints is obtained;

[0009] S103, determine whether the current path can meet the establishment time constraint by modifying the combinational logic delay. If the establishment time constraint cannot be met, proceed to step S104; otherwise, proceed to step S105.

[0010] S104, determine whether the current path can meet the establishment time constraint by modifying the establishment time parameter of the endpoint register. If the establishment time constraint cannot be met, modify the clock tree delay time of the start or end register and jump to step S102; otherwise, modify the establishment time parameter of the endpoint register.

[0011] S105, determine whether the current path can meet the hold time constraint by modifying the combinational logic delay. If the hold time constraint cannot be met, proceed to step S106; otherwise, proceed to step S107.

[0012] S106, determine whether the current path can meet the hold time constraint by modifying the hold time parameter of the endpoint register. If the hold time constraint cannot be met, modify the clock tree delay time of the start or end register and jump to step S102; otherwise, modify the hold time parameter of the endpoint register.

[0013] S107, Modify the combinational logic delay of the current path to meet the establishment time constraint;

[0014] S108, Modify the combinational logic delay of the current path to meet the hold-time constraint;

[0015] S109, determine whether all paths that violate timing constraints have been repaired. If not, proceed to step S102; otherwise, output the repaired netlist and delay file that meet the timing requirements for use in pre- and post-simulation.

[0016] Optionally, the function expression for determining whether the establishment time constraint is satisfied is:

[0017] ;

[0018] in, For clock cycles, This is the delay for the clock signal to propagate from the generation point to the destination register on the current path. This is the delay for the clock signal to propagate from the generation point to the starting register on the current path. The combinational logic delay used to calculate the time constraints on the current path. The setup time parameter is the endpoint register. If the above condition is not met, it means that the setup time constraint cannot be met; otherwise, it means that the setup time constraint can be met.

[0019] Optionally, when determining whether the current path can meet the establishment time constraint by modifying the combinational logic delay in step S103, the combinational logic delay on the current path is included. If the setup time constraint is not met, set a delay for the combinational logic on the current path. Set the value to 0 and determine whether the setup time constraint can be met.

[0020] Optionally, when determining whether the current path can meet the establishment time constraint by modifying the establishment time parameter of the endpoint register in step S104, this includes setting the establishment time parameter of the endpoint register, which is non-negative by default. Let the setup time parameter of the endpoint register be... Set the value to 0 and determine whether the setup time constraint can be met.

[0021] Optionally, the functional expression for the judgment condition that satisfies the hold time constraint is:

[0022] ;

[0023] in, The combinational logic delay used when calculating hold-time constraints on the current path. The hold time parameter is the end register; if the above judgment condition is not met, it means that the hold time constraint cannot be met, otherwise it means that the hold time constraint can be met.

[0024] Optionally, when determining whether the current path can meet the hold time constraint by modifying the combinational logic delay in step S105, the combinational logic delay on the current path is included. If the hold-time constraint is not met, increase the delay of the combinational logic on the current path. And determine whether the hold time constraint can be met.

[0025] Optionally, when determining whether the current path can meet the hold time constraint by modifying the hold time parameter of the endpoint register in step S106, this includes the hold time parameter of the endpoint register, which is non-negative by default. Let the hold time parameter of the endpoint register be... Set the value to 0 and determine whether the hold time constraint can be satisfied.

[0026] Optionally, when modifying the clock tree delay time of the start or end register in step S104, it includes changing the setup time parameter of the end register. Setting it to 0 increases the delay of the clock signal propagating from the generation point to the endpoint register on the current path. To satisfy the constraints; when modifying the clock tree delay time of the start or end register in step S106, this includes setting the hold time parameter of the end register. Setting it to 0 increases the delay of the clock signal propagating from the generation point to the starting register on the current path. To satisfy the constraints.

[0027] Furthermore, the present invention also provides a circuit timing repair system for super-previous and super-future simulation, comprising a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the circuit timing repair method for super-previous and super-future simulation.

[0028] In addition, the present invention also provides a computer program product, including a computer program or instructions that are programmed or configured to execute the circuit timing repair method for super-pre- and post-simulation via a processor.

[0029] Compared with existing technologies, the present invention mainly achieves the following beneficial effects: For large-scale integrated circuit design modules, after the preliminary physical design is completed, netlists and delay back-annotation files that do not meet timing requirements are obtained. The present invention includes obtaining paths in the circuit that violate timing constraints through timing analysis software, determining whether the timing requirements can be met by modifying combinational logic delays and modifying the setup time and hold time parameters of the endpoint register. If not, the clock tree delays of the start or end registers need to be modified, and the timing information needs to be analyzed again to obtain the violated timing paths for further judgment. If they can be met, the setup time and hold time constraints can be met by modifying combinational logic delays or the setup time and hold time parameters of the endpoint register. Finally, the repaired netlists and delay back-annotation files that meet the timing requirements are extracted and provided for post-simulation. Thus, after the module completes the preliminary physical design, super-pre- and post-simulation can be performed, which can greatly accelerate the chip timing and functional verification progress. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention.

[0031] Figure 2 This is a schematic diagram of the register-to-register timing path delay in an embodiment of the present invention. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0033] like Figure 1 As shown, this embodiment provides a circuit timing repair method for pre- and post-simulation, including the following steps:

[0034] S101, Obtain the netlist and delay back-annotation file of the chip circuit after completing the preliminary physical design;

[0035] S102, The timing of the circuit is analyzed using timing analysis software, and a current path that violates timing constraints is obtained;

[0036] S103, determine whether the current path can meet the establishment time constraint by modifying the combinational logic delay. If the establishment time constraint cannot be met, proceed to step S104; otherwise, proceed to step S105.

[0037] S104, determine whether the current path can meet the establishment time constraint by modifying the establishment time parameter of the endpoint register. If the establishment time constraint cannot be met, modify the clock tree delay time of the start or end register and jump to step S102; otherwise, modify the establishment time parameter of the endpoint register.

[0038] S105, determine whether the current path can meet the hold time constraint by modifying the combinational logic delay. If the hold time constraint cannot be met, proceed to step S106; otherwise, proceed to step S107.

[0039] S106, determine whether the current path can meet the hold time constraint by modifying the hold time parameter of the endpoint register. If the hold time constraint cannot be met, modify the clock tree delay time of the start or end register and jump to step S102; otherwise, modify the hold time parameter of the endpoint register.

[0040] S107, Modify the combinational logic delay of the current path to meet the establishment time constraint;

[0041] S108, Modify the combinational logic delay of the current path to meet the hold-time constraint;

[0042] S109: Determine whether all paths that violate timing constraints have been repaired. If not, proceed to step S102; otherwise, output the repaired netlist and delay file that meet the timing requirements for post-simulation.

[0043] Figure 2 The diagram shows the delay of the register-to-register timing path in this embodiment, illustrating the timing path from the starting register to the ending register. Let the combinational logic delay from the starting register CLK terminal through the Q terminal to the ending register D terminal be... Since there may be multiple combinational logic paths between the two registers, the path logic delay used in this embodiment when calculating the setup time constraint is set to... The path logic delay used when calculating hold-time constraints is set to... Let the delay of the clock signal propagating from the generation point to the starting register be... The delay of the clock signal propagating from the generation point to the endpoint register is... Let the setup time parameter of the endpoint register be... The hold time parameter is And assume the clock period is... .

[0044] The goal of this embodiment is to simultaneously satisfy the setup time constraint and hold time constraint for each timing path. Therefore, the function expression for determining whether the setup time constraint is satisfied in this embodiment is:

[0045] (1)

[0046] in, To establish a margin for time constraints, A value greater than or equal to 0 means that the current path meets the setup time constraint. In the initial stages of physical design, the circuit may contain a large number of... Paths with a value less than 0 are those that violate the setup time constraint. In this embodiment, the various parts of the above formula (1) are adjusted by calculation to ensure that all paths meet the setup time constraint requirements.

[0047] In this embodiment, the function expression for determining whether the hold time constraint is satisfied is:

[0048] (2)

[0049] in, To maintain a margin of time constraint, A value greater than or equal to 0 means that the current path satisfies the hold-time constraint. In the initial stages of physical design, the circuit may contain a large number of... Paths with a value less than 0 are those that violate the hold-time constraint. In this embodiment, the various parts of formula (2) are adjusted by calculation to ensure that all paths meet the hold-time constraint requirements.

[0050] Equations (1) and (2) show the parameters that affect the setup time constraint and hold time constraint of the timing path. , , , , , and The values ​​of these parameters can all be obtained in time series analysis software. The design cycle cannot be changed, but other parameters can be modified in the timing analysis software.

[0051] This embodiment can combine three methods to repair paths that violate timing constraints to meet the timing constraints: (1) Modify the combinational logic delay of the current path. and (2) Modify the creation time parameter of the path endpoint. and hold time parameters (3) Modify the delay time of the clock signal arriving at the start and end points of the path. and The timing optimization of the circuit in the actual physical design stage mainly adopts the first method. Therefore, this embodiment also uses the first method first to fix timing violations. The third method will affect the timing of multiple paths and bring more computational iterations, thus significantly increasing the running time of the repair program. Therefore, in this embodiment, if the timing has not converged after using the first method, the second method is given priority to fix the timing, and the third method is considered last. However, this embodiment supports using these three methods to fix timing in different orders.

[0052] In step S101 of this embodiment, the netlist and delay back-annotation files of the chip circuit after the preliminary physical design are obtained. Since only the preliminary physical design is completed, the circuit does not yet meet timing requirements. To enable pre- and post-simulation and allow the physical design and post-simulation work to be carried out in parallel, this embodiment obtains the netlist and delay back-annotation files that do not yet meet timing requirements from the physical design software for subsequent processing.

[0053] Since the circuit does not meet timing requirements at the current stage, there are paths that violate timing constraints. In step S102 of this embodiment, timing analysis software is used to perform timing analysis on the circuit and extract a path that violates timing constraints for timing judgment and repair. There are often partial logic overlaps between paths that violate timing constraints; therefore, modifying the delay of some paths will affect the delay of other paths. To avoid over-repair, this embodiment sorts all extracted paths that violate timing constraints from low to high severity of violation and selects the path with the lowest severity for repair. Paths violating setup timing constraints are repaired first, followed by paths violating hold timing constraints. This repair method results in a smaller timing correction margin and more closely resembles the actual physical design repair result.

[0054] In this embodiment, step S103 uses timing analysis software to determine the current path and modifies the combinational logic delay. Can the setup time constraints be met? The combinational logic delay of a timing path is usually a non-negative number, which can be addressed by modifying... Repairing setup time violations involves reducing the delays of units and connections in the combinational logic path. As can be seen from formula (1), determining whether modifying the combinational logic delay can satisfy the setup time constraint is equivalent to... Does the inequality hold true when the value is reduced to 0, that is, does formula (3) hold true?

[0055] (3)

[0056] By calculating the current parameters, we can conclude that if formula (3) does not hold, we need to find a further time series optimization method and proceed to step S104; if formula (3) holds, it means that no other method is needed to satisfy the establishment of time constraints, and then proceed to step S105 to check the situation of maintaining time constraints.

[0057] In this embodiment, step S104 determines whether the current path can meet the establishment time constraint by modifying the establishment time parameter of the endpoint register. This embodiment uses non-negative values... The parameter is adjusted to 0, and then the validity of formula (3) is calculated. If it is valid for the current path, it means that the establishment time constraint can be met by modifying the combinational logic delay and the establishment time parameter of the endpoint register. At this time, the establishment time parameter of the endpoint register is modified and the process proceeds to step S105. Otherwise, the clock tree delay time of the start or end register needs to be modified and the process jumps to step S102. In this embodiment, the establishment time parameter is... The modification is calculated based on two values: (1) the current path violates the establishment time constraint. (2) The absolute value of the value; (3) The establishment time parameter to be modified The current value. In this embodiment, the minimum of the two values ​​is used as the current value. The amount of reduction should be minimized to avoid excessive timing repair.

[0058] In this embodiment, step S105 determines the current path by modifying the combinational logic delay. Can the hold-time constraint be met? Correcting hold-time violations by modifying combinational logic delays involves increasing the delays of cells and connections within the combinational logic path, which essentially increases the time constraint. ,but Excessive increases may violate the establishment time constraints of related paths; this embodiment sets a maximum value. No more than One-third. From formula (2), it can be seen that determining whether modifying the combinational logic delay can satisfy the hold-time constraint is equivalent to... Increase to Does the time inequality hold, that is, does the following formula (4) hold?

[0059] (4)

[0060] By calculating the current parameters, we can conclude that if formula (4) does not hold, we need to find a further timing optimization method and proceed to step S106; if formula (4) holds for all paths, it means that no other method is needed to satisfy the hold time constraint, and then proceed to step S107 to satisfy the setup time constraint by modifying the combinational logic delay.

[0061] In this embodiment, step S106 determines whether the current path can meet the hold time constraint by modifying the hold time parameter of the endpoint register. This embodiment uses non-negative values... Adjust the parameter to 0, and then calculate whether formula (4) is valid. If it is valid for the current path, it means that the hold time constraint can be met by modifying the combinational logic delay and the hold time parameter of the register. At this time, modify the hold time parameter of the endpoint register and go to step S107. Otherwise, it is necessary to modify the clock tree delay time of the start or end register and jump to step S102.

[0062] This embodiment specifies the holding time parameter. The modification is calculated based on two values: (1) the current path violates the hold-time constraint. (1) The absolute value of the value; (2) The current value of the hold time parameter to be modified. In this embodiment, the minimum of the two values ​​is used as the current value. The amount of reduction should be minimized to avoid excessive timing repair.

[0063] In this embodiment, steps S104 and S106 may require modification of the clock tree delay time of the start or end register. This means that for the current path, changing the combinational logic delay and the setup or hold time parameters of the end register cannot meet the timing requirements, so the clock tree delay time of the start or end register must be modified.

[0064] In this embodiment, when step S104 requires modifying the clock tree delay time of the start or end register, it indicates that a problem of violating setup time constraints needs to be resolved. At this time, the setup time parameter of the end register is adjusted. Setting it to 0, formula (3) can be transformed into the following formula (5):

[0065] (5)

[0066] The design specifications cannot be changed. The fact that formula (5) is invalid indicates... Significantly smaller than This indicates that the clock tree is unbalanced and the clock tree delay to reach the end register is less than the clock tree delay to reach the start register, meaning the clock sampling time is too early. For formula (5) to hold, the clock needs to be increased. The value or decrease The value of . Since optimization is usually achieved by increasing the clock tree delay in actual circuit physical design, this embodiment uses an increased value. The value is used to satisfy formula (5). To avoid over-fixing the timing, this embodiment adjusts... This makes formula (5) exactly true, that is... Adjusted to .

[0067] In this embodiment, when step S106 requires modifying the clock tree delay time of the start or end register, it indicates that a problem of violating the hold time constraint needs to be resolved. At this time, the hold time parameter of the end register is adjusted. Setting it to 0, formula (4) can be transformed into the following formula (6):

[0068] (6)

[0069] The design specifications cannot be changed. The fact that formula (6) is invalid indicates... Significantly smaller than In other words, the clock tree is unbalanced and the clock tree delay to the start register is less than the clock tree delay to the end register, meaning the clock sampling time is too late. For formula (6) to hold, the clock needs to be increased. The value or decrease The value of . Since optimization is usually achieved by increasing the clock tree delay in actual circuit physical design, this embodiment uses an increased value. The value is used to satisfy formula (6). To avoid over-fixing the timing, this embodiment adjusts... This makes formula (6) exactly true, that is... Adjusted to .

[0070] Since the same register can be the start of one timing path and the end of another, a start register may correspond to multiple end registers and a single end register may correspond to multiple start registers. Therefore, modifying... or The value of can change the timing of the current path and may also change the timing of other paths. Therefore, after the modification is completed, the timing needs to be re-analyzed in step S102.

[0071] In this embodiment, step S107 modifies the combinational logic delay to meet setup time constraints. In real physical design, paths that violate timing constraints are generally optimized to just meet the timing requirements without over-optimization. Therefore, this embodiment also tries to modify the delay to just meet the timing constraints when modifying the combinational logic delay to meet the setup time constraints. Since the probability of cells and lines closer to the end point in a path being shared by other paths is lower, modifying the logic delay from the end point can reduce the impact on other paths. In this embodiment, the delays of relevant cells and lines are attempted to be modified sequentially from the end point register to the start point register along the path from back to front. The value of cell and line delays is reduced to a minimum of 0. If the current delay is negative, no modification is made, the original value is maintained, and the next cell or line is processed.

[0072] In a circuit, there may be paths that violate setup time constraints and paths that violate hold time constraints passing through the same combinational logic unit. Before modifying the delay of a unit or line, this embodiment will check the status of other timing paths sharing the current unit or line. If the shared path has a hold time violation, since reducing the current delay may exacerbate the hold time violation, this embodiment will not modify the current delay; if the shared path does not have a hold time violation, the current delay can be modified. This embodiment refers to three values ​​to calculate the reduction in the current delay: (1) the current path violates the setup time constraint. (2) The absolute value of each shared path; (3) The current delay value of the unit or line to be modified. In this embodiment, the minimum value among the three values ​​is the amount of reduction in the current unit or line delay. Timing repair is performed on the basis of ensuring that the unit and line delays are non-negative and that the shared path does not violate the time constraint.

[0073] In this embodiment, step S108 modifies the combinational logic delay to meet the hold time constraint. Inserting a delayed buffer into the path that violates the hold time constraint increases the path delay and can correct the hold time violation. To match the actual physical design, this embodiment specifies that the maximum delay of each inserted buffer is 0.1ns, so one or more buffers may be inserted consecutively on a specific connection. Similar to step S107, when correcting the hold time constraint violation, this embodiment also performs the correction from the end register to the start register along the path from back to front. Since all paths that violate the setup time constraint have been corrected at this time, this embodiment refers to two values ​​to calculate the delay of the inserted unit: (1) the delay of the current path that violates the hold time constraint. (2) The absolute value of each shared path establishment time constraint; The minimum value of the two values ​​is used as the total delay of the current insertion buffer. If the second value is less than the first value, it means that increasing the delay is insufficient to meet the hold time constraint, and the next insertion point needs to be found from the end to the beginning of the path until the hold time constraint is met.

[0074] In this embodiment, step S109 determines whether all timing violation paths have been repaired. If there are still paths violating timing constraints, step S102 is initiated to extract the next path for repair; otherwise, it indicates that all timing violation paths in the circuit have been repaired. The repaired netlist and delay back-annotation files that meet timing requirements can be generated by timing analysis software and provided for post-simulation use.

[0075] In summary, this embodiment proposes a method for repairing timing violations in advanced pre- and post-simulation by adjusting the netlist and modifying various delay parameters in the circuit. Timing violation paths include not only register-to-register paths, but also input-to-register paths, register-to-output paths, and direct input-to-output paths. The above discussion only addresses register-to-register path repair methods. The repair methods for the latter types of paths are similar in principle and computation, therefore, they will not be described further. However, the method described in this embodiment covers all timing violation paths. The repair described in this embodiment is performed within timing analysis software, not in a physical sense; it is a virtual repair for advanced pre- and post-simulation. Simultaneously, physical timing repair during the physical design phase is still performed. The purpose of this embodiment is to accelerate the post-simulation progress after physical timing repair is completed. This method allows for the early acquisition of files that meet post-simulation requirements even when the module is still in the physical design phase and has not yet met timing constraints. This enables the time-consuming preparation and debugging of the post-simulation environment to be carried out ahead of schedule, significantly accelerating chip development.

[0076] Furthermore, this embodiment also provides a circuit timing repair system for super-previous and next-to-last simulation, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the circuit timing repair method for super-previous and next-to-last simulation.

[0077] Furthermore, this embodiment also provides a computer program product, including a computer program or instructions that are programmed or configured to execute the circuit timing repair method for super-pre- and post-simulation via a processor.

[0078] Those skilled in the art will understand that the technical solutions provided by this invention may take the form of a method, system, or computer program product. Therefore, this invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this invention may take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, produce an implementation of the flowchart... Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0079] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A circuit timing repair method for pre- and post-simulation, characterized in that, The method comprises the following steps: S101, obtaining a netlist and a delay file of a chip circuit after a preliminary physical design; S102, analyzing the circuit timing by using timing analysis software, and obtaining a current path that violates a timing constraint; S103, determining whether the current path can satisfy a setup time constraint by modifying the delay of the combinational logic, and if not, jumping to step S104; Otherwise, jumping to step S105; S104, determining whether the current path can satisfy the setup time constraint by modifying the setup time parameter of the end register, and if not, modifying the clock tree delay time of the start or end register, and jumping to step S102; otherwise, modifying the setup time parameter of the end register; S105, determining whether the current path can satisfy a hold time constraint by modifying the delay of the combinational logic, and if not, jumping to step S106; otherwise, jumping to step S107; S106, determining whether the current path can satisfy the hold time constraint by modifying the hold time parameter of the end register, and if not, modifying the clock tree delay time of the start or end register, and jumping to step S102; otherwise, modifying the hold time parameter of the end register; S107, modifying the delay of the combinational logic of the current path to satisfy the setup time constraint; S108, modifying the delay of the combinational logic of the current path to satisfy the hold time constraint; S109, determining whether all paths that violate the timing constraint have been repaired, and if not, jumping to step S102; Otherwise, outputting the repaired netlist and delay file that satisfy the timing requirement for pre-simulation and post-simulation; The function expression of the judgment condition for satisfying the setup time constraint is: ； wherein, is a clock period, is a delay of the clock signal from a point of generation to an end-point register on the current path, is a delay of the clock signal from a point of generation to a start-point register on the current path, is a combinational logic delay used in calculating the setup time constraint on the current path, is a setup time parameter of the end-point register; if the above condition is not met, it means that the setup time constraint cannot be met, otherwise it means that the setup time constraint can be met; The function expression of the judgment condition for satisfying the hold time constraint is: ； wherein, is a combinational logic delay used in calculating the hold time constraint on the current path, is a hold time parameter of the end point register; if the above condition is not true, it means that the hold time constraint cannot be met, otherwise it means that the hold time constraint can be met; When modifying the clock tree delay time of the start or end register in step S104, this includes changing the setup time parameter of the end register. Setting it to 0 increases the delay of the clock signal propagating from the generation point to the endpoint register on the current path. To satisfy the constraints; when modifying the clock tree delay time of the start or end register in step S106, this includes setting the hold time parameter of the end register. Setting it to 0 increases the delay of the clock signal propagating from the generation point to the starting register on the current path. To satisfy the constraints.

2. The method of claim 1, wherein, In step S103, when judging whether the current path can satisfy the setup time constraint by modifying the delay of the combinational logic included in the current path, the delay of the combinational logic included in the current path is set to 0 When the setup time constraint is not satisfied, the delay of the combinational logic included in the current path is set to 0 and it is judged whether the setup time constraint can be satisfied. When the setup time constraint is not satisfied, the delay of the combinational logic included in the current path is set to 0 and it is judged whether the setup time constraint can be satisfied.

3. The method of claim 1, wherein the method is performed for a circuit simulation that is forward or backward oriented. In step S104, when judging whether the current path can satisfy the setup time constraint by modifying the setup time parameter of the destination register, the setup time parameter of the destination register is taken as a non-negative number by default , and the setup time parameter of the destination register is set as 0 and whether the setup time constraint can be satisfied is judged. ​ 4. The circuit timing repair method for pre- and post-simulation based on claim 1, characterized in that, In step S105, when determining whether the current path can satisfy the hold time constraint by modifying the delay of the combinational logic included in the current path When the hold time constraint is not satisfied, increasing the delay of the combinational logic included in the current path and determining whether the hold time constraint is satisfied.

5. The method of claim 1, wherein the method is performed for a circuit simulation oriented to a future time or a past time. In the step S106, when judging whether the current path can satisfy the hold time constraint by modifying the hold time parameter of the end register, it includes judging whether the hold time parameter of the end register which is by default a non-negative number can satisfy the hold time constraint , assuming that the hold time parameter of the end register is 0 and judging whether the hold time constraint can be satisfied .

6. A circuit timing repair system oriented to pre- and post-simulation, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to perform the circuit timing repair method for pre-simulation and post-simulation according to any one of claims 1-5.

7. A computer program product comprising computer programs or instructions, characterized in that, The computer program or instructions are programmed or configured to perform the circuit timing repair method for pre-simulation and post-simulation by the processor according to any one of claims 1-5.

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