Parallel rapid three-dimensional global wiring method and system
By adopting a parallel fast 3D global routing method, the problems of search space and computational efficiency in the routing process of VLSI are solved, achieving efficient parallel routing and quality improvement, and reducing the cost of layout iteration.
CN121303050APending Publication Date: 2026-01-09ZHEJIANG UNIV OF TECH
View PDF 0 Cites 0 Cited by
Patent Information
- Application Number
- CN202511405479.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-29
- Publication Date
- 2026-01-09
Smart Images

Figure CN121303050A_ABST
Abstract
The invention relates to a parallel rapid three-dimensional global wiring method and system, and the method comprises the steps: obtaining chip design correlation information and wiring plane correlation information, initializing the global congestion information based on a wiring plane, and carrying out the parallel scheduling preprocessing of an input network cable; executing parallel global wiring path search to obtain a global wiring result; the system includes one or more parallel task processors connected via a bus to a memory in which is stored program instructions executable on the parallel task processors, the instructions when executed implementing a method. According to the method, for a large-scale network cable parallel wiring task, by reasonably dividing wiring batches, constructing an efficient scheduling system and combining a global congestion sensing path optimization strategy, cooperative improvement of wiring calculation efficiency and quality is realized on the premise of ensuring the wiring quality and the design rule compliance, and the iteration cost with a layout stage is remarkably reduced; and collaborative optimization of global wiring efficiency, parallel capability and a layout stage is realized.
Need to check novelty before this filing date? Find Prior Art
