A method, system, medium, and program product for detecting latent defects in chips.

Abstract

This application relates to a method, system, medium, and program product for detecting latent defects in chips. The method includes acquiring a dataset, which includes preprocessed AFM three-dimensional topographic data and electrical performance data; converting the preprocessed AFM three-dimensional topographic data and electrical performance data into a first multi-channel matrix and a second multi-channel matrix, respectively; inputting the first multi-channel matrix and the second multi-channel matrix into a feature extractor to extract topographic data features and electrical performance data features, respectively; then fusing the topographic data features and electrical performance data features to obtain joint features; processing the joint features using a multi-head attention mechanism to obtain features with enhanced global context information; inputting the features with enhanced global context information into a pre-trained defect recognition model, and outputting the defect recognition result. This application achieves accurate detection of latent defects in chips and optimization of manufacturing parameters, thereby significantly improving chip yield and manufacturing efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of implicit detection, and in particular to a chip implicit defect detection method, system, medium and program product. BACKGROUND

[0002] In advanced process chip manufacturing, implicit defect detection faces severe challenges: atomic force microscopy can only obtain surface topography features and cannot correlate electrical performance, electrical performance testing can capture parameter abnormalities but it is difficult to locate physical defects, and independent use of the two leads to a high implicit defect miss rate of surface topography without abnormalities but with abnormal electrical characteristics.

[0003] There are some chip detection schemes based on electrical properties in the prior art, for example, CN110957231A discloses an electrical failure discrimination scheme, which establishes a pattern feature comparison mechanism by analyzing the inclusion relationship between different electrical failure patterns, realizes pattern classification according to feature inclusion, effectively solves the misjudgment problem caused by pattern feature nesting, and significantly improves the accuracy of chip yield analysis. For example, CN110970085A discloses a yield analysis scheme based on electrical failure data, which converts the electrical failure data of DRAM chips into a grid graph form, and matches it with a plurality of pre-stored failure templates, thereby quickly identifying possible failure causes. The system includes a storage module, a data input module, a graphical module, an analysis module and an output module, which can automatically analyze the distribution characteristics of failure memory cells, effectively improving the efficiency and accuracy of DRAM chip yield analysis.

[0004] However, as semiconductor technology enters 7nm and more advanced processes, the defect size on the wafer surface becomes increasingly small and complex, and these implicit defect features are weak, making it difficult for traditional detection methods to identify them, and making implicit defect detection face severe challenges. SUMMARY

[0005] The purpose of the present application is to provide a chip implicit defect detection method, system, medium and program product, which partially solves or alleviates the above-mentioned deficiencies in the prior art, and can realize accurate detection of chip implicit defects and optimization of manufacturing parameters, thereby significantly improving chip yield and manufacturing efficiency.

[0006] In order to solve the above-mentioned technical problems, the present application specifically adopts the following technical solutions:

[0007] The first aspect of the present application is to provide a chip implicit defect detection method, comprising the following steps:

[0008] Obtain a data set, the data set including pre-processed AFM three-dimensional topography data and electrical performance data of a chip to be detected, the AFM three-dimensional topography data and the electrical performance data being obtained by scanning and testing the same region to be detected of the chip to be detected by an atomic force microscope and an electrical performance tester respectively;

[0009] Convert the pre-processed AFM three-dimensional topography data and the electrical performance data into a first multi-channel matrix and a second multi-channel matrix respectively, the first multi-channel matrix including a height data channel, a stiffness data channel and a surface potential data channel, and the second multi-channel matrix including a leakage current data channel, a resistance data channel and a threshold voltage data channel;

[0010] Input the first multi-channel matrix and the second multi-channel matrix into a feature extractor respectively and extract topography data features and electrical performance data features;

[0011] Fuse the topography data features and the electrical performance data features to obtain joint features;

[0012] Process the joint features by using a multi-head attention mechanism to obtain features with enhanced global context information;

[0013] Input the features with enhanced global context information into a pre-trained defect recognition model to output a defect recognition result;

[0014] The pre-trained defect recognition model includes a binary classification module and a multi-label classification module;

[0015] And the inputting the features with enhanced global context information into the pre-trained defect recognition model to output the defect recognition result includes:

[0016] Inputting the features with enhanced global context information into the binary classification module to determine whether there is a defect at each spatial position and output an initial confidence, and if the initial confidence is higher than a first threshold, calling the multi-label classification module to output defect type information;

[0017] The pre-trained defect recognition model is obtained by training the defect recognition model by using features with enhanced global context information of a sample chip and defect annotation data.

[0018] Further, the joint feature includes a joint feature sequence; and the fusing of the topography data features and the electrical performance data features to obtain joint features includes: respectively serializing the topography data features and the electrical performance data features to respectively obtain a first feature sequence and a second feature sequence, and splicing the first feature sequence and the second feature sequence in a sequence dimension to form a joint feature sequence. Further, the processing of the joint features by using the multi-head attention mechanism includes: injecting position information coding into the joint feature sequence, inputting the joint feature sequence after the position information coding into a Transformer model and processing by using the multi-head attention mechanism to obtain a deep fusion feature sequence.

[0019] Further, it further includes the steps of: reconstructing the deep fusion feature sequence into a feature map with a spatial dimension according to pre-stored spatial position information; performing an up-sampling operation on the feature map with the spatial dimension to reach a preset standard size; uniformly adjusting the feature channel number of the up-sampled feature map to a preset channel number by using a 1x1 convolution layer, and finally outputting a feature with enhanced global context information. Further, the defect recognition result includes a defect position, a defect type and a severity level.

[0020] Further, it further includes the steps of: generating a defect positioning heat map based on the defect recognition result, distinguishing the severity level by color coding, and generating a manufacturing parameter adjustment comparison map; providing an interactive operation interface to label the defect area and submit a decision opinion; issuing the confirmed optimization scheme to a manufacturing equipment control system through an industrial communication protocol, and generating a detection report in a standard format. Further, it further includes the steps of: inputting the defect recognition result into a pre-trained yield prediction model to output a yield prediction value; and generating a key process parameter adjustment scheme according to the yield prediction value.

[0021] In a second aspect, the present application also discloses a chip implicit defect detection system, which comprises:

[0022] A data set acquisition module configured to acquire a data set, wherein the data set comprises preprocessed AFM three-dimensional topography data and electrical performance data of a chip to be detected, and the AFM three-dimensional topography data and the electrical performance data are obtained by scanning and testing the same to-be-detected area of the chip to be detected by an atomic force microscope and an electrical performance tester respectively;

[0023] A conversion module configured to convert the preprocessed AFM three-dimensional topography data and the electrical performance data into a first multi-channel matrix and a second multi-channel matrix respectively, wherein the first multi-channel matrix comprises a height data channel, a stiffness data channel and a surface potential data channel, and the second multi-channel matrix comprises a leakage current data channel, a resistance data channel and a threshold voltage data channel;

[0024] The feature extraction module is configured to input the first multi-channel matrix and the second multi-channel matrix into the feature extractor and extract the morphological data features and electrical performance data features, respectively.

[0025] The fusion module is configured to fuse topographic data features and electrical performance data features to obtain joint features;

[0026] The context information enhancement module is configured to utilize a multi-head attention mechanism to process joint features to obtain features with enhanced global context information.

[0027] The defect identification module is configured to input features enhanced with global context information into a pre-trained defect identification model and output defect identification results.

[0028] The pre-trained defect recognition model includes a binary classification module and a multi-label classification module;

[0029] Furthermore, the step of inputting the features enhanced with global context information into the pre-trained defect recognition model and outputting the defect recognition result includes:

[0030] The feature enhanced with global context information is input into the binary classification module to determine whether there is a defect at each spatial location and outputs the initial confidence score. If the initial confidence score is higher than the first threshold, the multi-label classification module is called to output the defect type information.

[0031] The pre-trained defect recognition model is obtained by training the defect recognition model with features enhanced by global context information of the sample chip and defect annotation data;

[0032] Thirdly, this application also discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect.

[0033] Fourthly, this application also discloses a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0034] Beneficial technical effects:

[0035] To address the issue of latent defects in chips (e.g., particularly within the chip itself or between its multi-layered structures, where defects are easily hidden and difficult to identify), this invention provides a method for collaborative identification using AFM three-dimensional topographic data and electrical performance data.

[0036] Furthermore, the applicant noted that comprehensive chip testing, including AFM and electrical performance testing, generates a large amount of data, and analyzing this data from a single perspective is technically very challenging. Therefore, the collaborative analysis of AFM and electrical performance test results presents significant challenges in terms of data processing and data fusion.

[0037] To address this, the present invention provides a multi-step filtering mechanism to reduce the difficulty of identifying massive amounts of heterogeneous data (i.e., different types of AFM and electrical performance test data), thereby improving detection accuracy, reducing detection difficulty, and increasing detection efficiency.

[0038] The multi-step filtering mechanism can be reflected in at least the following aspects:

[0039] 1) For the AFM and electrical performance testing process, perform preliminary filtering of test data: specifically, select data that can better reflect the faults at the device level, such as height, stiffness, and surface potential data for AFM, and leakage current, resistance, and threshold voltage data for electrical performance testing.

[0040] 2) Two key stages are set up: feature extraction and feature recognition. In the feature extraction process, feature fusion is performed on the multi-channel matrix to further filter the initially filtered multi-channel data and extract the core enhanced features. In the feature recognition (i.e., defect recognition) process, initial confidence is first determined based on the enhanced features, and spatial locations with high probability of defects are filtered out based on the initial confidence. Then, the multi-label classification module is called for recognition.

[0041] Therefore, by implementing multiple collaborative filtering settings at the detection data level and the data identification level, this invention can reduce the difficulty of fusion processing of massive amounts of heterogeneous data to a certain extent, thereby improving the accuracy of defect identification. Furthermore, through preliminary filtering of the detection data, targeted identification of device-level faults within the chip can be achieved. This learning mechanism for centralized identification of device-level faults is more easily integrated with actual chip yield analysis needs, meeting user requirements from an application perspective (allowing users to directly rate the chip's usability).

[0042] Furthermore, from another perspective, this invention provides a multi-level data screening approach for the initial filtering of test data: Preferably, this invention focuses on selecting and fusing test data from multiple dimensions, including microscopic geometric features (such as microscopic morphology - height), macroscopic device electrical properties (such as current, resistance, and voltage), and mechanical properties (such as stiffness). This multi-dimensional test data covers defect causes from different levels: 1) multi-domain coverage and fusion from mechanical, geometric, electrical, and electrochemical perspectives; 2) multiple coverage and fusion from microscopic morphology to macroscopic device levels; 3) multi-stage coverage from the process execution stage, such as reflecting the front-end process through surface potential and threshold voltage, reflecting the mid-end process through height and stiffness, and reflecting the back-end process through resistance and leakage current.

[0043] Therefore, by reflecting details at different levels or stages through the aforementioned limited data channels, the accuracy of data identification can be effectively improved by synergistic use of AFM data and electrical performance data. At the same time, the fusion of limited channels can also reduce the difficulties in the fusion process of AFM data and electrical performance data.

[0044] Furthermore, the applicant noted that this feature extraction and combination of multiple data channels is conducive to establishing an interpretable correlation between the physical characterization of defects and electrical functions, providing a complete data foundation for chip manufacturing from detection to analysis and optimization. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0046] Figure 1 This is a flowchart of a chip latent defect detection method disclosed in this application.

[0047] Figure 2 This is a flowchart of a chip AFM detection sequence selection method disclosed in this application.

[0048] Figure 3 This is a flowchart of a chip AFM detection level control method disclosed in this application.

[0049] Figure 4 This is a schematic diagram of the module structure of a chip latent defect detection system according to one embodiment of this application.

[0050] Figure 5 This is a schematic diagram of the module structure of a chip latent defect detection system according to one embodiment of this application.

[0051] Figure 6 This is a schematic diagram of the module structure of a chip latent defect detection system according to one embodiment of this application. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0053] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0054] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0055] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0056] Figure 1 A flowchart of a chip latent defect detection method according to this application is shown. (Refer to...) Figure 1 The method specifically includes the following steps:

[0057] S1. Obtain the dataset, which includes preprocessed AFM three-dimensional topography data and electrical performance data. The AFM three-dimensional topography data and electrical performance data are obtained by scanning and testing the same area to be tested of the chip to be tested using an atomic force microscope and an electrical performance tester, respectively.

[0058] S2. Convert the preprocessed AFM three-dimensional topography data and electrical performance data into a first multi-channel matrix and a second multi-channel matrix, respectively. The first multi-channel matrix includes a height data channel, a stiffness data channel and a surface potential data channel. The second multi-channel matrix includes a leakage current data channel, a resistance data channel and a threshold voltage data channel.

[0059] S3. Input the first multi-channel matrix and the second multi-channel matrix into the feature extractor respectively and extract the morphological data features and electrical performance data features;

[0060] S4. Merge the morphological data features and electrical performance data features to obtain joint features;

[0061] The joint features include a joint feature sequence; and the fusion of morphological data features and electrical performance data features to obtain the joint features includes:

[0062] The morphological data features and electrical performance data features are serialized to obtain a first feature sequence and a second feature sequence, respectively. The first feature sequence and the second feature sequence are then concatenated along the sequence dimension to form a joint feature sequence.

[0063] Spatial coordinate information can be marked on the morphological data features and electrical performance data features to facilitate the splicing of sequences.

[0064] S5. Utilize multi-head attention mechanism to process joint features to obtain features enhanced with global contextual information (also known as enhanced features).

[0065] The process of using a multi-head attention mechanism to process joint features includes:

[0066] Position information is injected into the joint feature sequence, and the position information-encoded joint feature sequence is input into the Transformer model and processed using a multi-head attention mechanism to obtain a deep fusion feature sequence.

[0067] S6. Input the features enhanced with global context information into the pre-trained defect recognition model and output the defect recognition result;

[0068] The pre-trained defect recognition model includes a binary classification module and a multi-label classification module;

[0069] Furthermore, the step of inputting the features enhanced with global context information into the pre-trained defect recognition model and outputting the defect recognition result includes:

[0070] The features enhanced with global context information are input into the binary classification module to determine whether there are defects at each spatial location and output the initial confidence score. If the initial confidence score is higher than the first threshold, the multi-label classification module is called to output the defect type information.

[0071] The pre-trained defect recognition model is obtained by training the defect recognition model with features enhanced by global context information of the sample chip and defect annotation data.

[0072] For example, in some embodiments, if the initial confidence level is lower than a first threshold, the multi-label classification module is not invoked to output defect type information.

[0073] The defect identification results include defect location, defect type, and severity level.

[0074] The following disclosure provides a specific embodiment applicable to a wafer defect and yield co-prediction method of this application, which includes the following steps:

[0075] S101: Obtain the dataset

[0076] The data foundation of this application originates from the simultaneous acquisition of atomic force microscopy (AFM) scans and electrical performance tests on the chip's test area. This simultaneous acquisition process is a crucial prerequisite for ensuring the effectiveness of subsequent data fusion and analysis. The entire acquisition process aims to achieve a high-precision one-to-one correspondence between AFM data and electrical performance data in time and space.

[0077] In one specific embodiment, before physical inspection begins, the areas to be inspected must be precisely planned on the chip design drawings. These areas should preferably be the core functional units of the chip, such as the processing cores of the central processing unit, cache memory arrays, or input / output interface units. The boundaries of the areas need to be confirmed by comparing them with the design drawings using an optical calibration system to ensure that the scan does not miss any critical and problematic microstructures. After the areas are determined, a set of acquisition parameters for coordinated operation needs to be set for the AFM and electrical performance tester. Among these, the acquisition point interval is a core parameter, which determines the spatial resolution of the inspection. For advanced process chips of 7 nanometers and below, this interval is set to 5 nanometers by default to ensure that nanometer-level latent defects can be captured; for 14 nanometers or more mature processes, it can be appropriately relaxed to 10 to 20 nanometers to achieve a balance between accuracy and efficiency. Another key parameter is the acquisition frequency, which is uniformly set to 1 kHz in this scheme. This setup ensures that the time difference between the data acquisition of the AFM probe and the electrical performance test probe at the same location is controlled within 1 millisecond before they move to the next point, minimizing point misalignment caused by instrument response delay from a time perspective.

[0078] In a specific embodiment, the following is an example step:

[0079] Determine the chip area to be tested (such as core logic unit, memory unit array), and set the synchronous acquisition parameters for AFM and electrical performance testing (such as acquisition point interval of 10nm, acquisition frequency of 1kHz).

[0080] 1) Determining the detection area: Prioritize the core functional areas of the chip, including core logic units (such as CPU processing cores), memory unit arrays (such as DRAM memory matrix), and I / O interface areas. The boundaries of the areas need to be calibrated using chip design drawings to ensure that no critical areas are missed.

[0081] 2) Acquisition point interval: 10nm by default. For processes below 7nm, it can be adjusted to 5nm (to improve detection accuracy). For 14nm processes, it can be relaxed to 10nm (to improve acquisition efficiency).

[0082] 3) Acquisition frequency: uniformly set to 1kHz to ensure that the acquisition time difference between AFM and electrical performance test is ≤1ms, and to avoid misalignment of test points.

[0083] 4) Other parameters: The AFM scan mode is set to "tap mode" (to reduce damage to the chip surface), and the electrical performance test sampling time is 10ms per point to ensure data stability.

[0084] After the parameters are set and the synchronous acquisition program is started, the atomic force microscope (AFM) begins operation. Its probe performs precise line-by-line, point-by-point scanning over the selected area. The preferred scanning mode is "tapping mode," in which the probe periodically taps the sample surface, obtaining high-resolution morphological images while minimizing scratches or damage to the fragile chip structure. During this process, the AFM simultaneously acquires two types of data: first, three-dimensional morphological data, with a vertical height measurement range typically from 0 to 10 micrometers and a resolution up to 0.1 nanometers, accurately recording any minute undulations and topological structures on the chip surface; second, surface potential data, typically measured from -2V to +2V with an accuracy of 0.01V, which helps reflect differences in the work function and local charge distribution on the material surface, crucial for identifying certain insulating layer defects or doping anomalies. All this data is then streamed in real-time to a local server via a high-speed data interface.

[0085] During AFM data acquisition, electrical performance testing probes located near the AFM probes also perform synchronous measurements. When the AFM probe stops at a specific point, the electrical performance testing probes establish an electrical connection with that point and perform a series of rapid electrical measurements. These measurements include at least three key parameters: leakage current, resistance, and threshold voltage. The leakage current measurement range covers a wide range from 1 picoampere to 1 milliampere to capture leakage phenomena ranging from extremely weak to obvious; the resistance measurement range is from 1 ohm to 10 megohms; and the threshold voltage measurement range is -2V to +2V. To achieve precise correlation between the two data sources, the system assigns the same high-precision timestamp to all AFM and electrical performance data acquired at a single physical point. This timestamp serves as the core link, tightly binding spatial topography information with electrical function information.

[0086] In a specific embodiment, the following is an example step:

[0087] 1) AFM data acquisition: The target area is scanned by an atomic force microscope to simultaneously acquire three-dimensional morphology data (height range 0-10μm, resolution 0.1nm) and contact hole surface potential data (measurement range -2V~+2V, accuracy 0.01V). The data is transmitted to the local server in real time.

[0088] 2) Electrical performance data acquisition: A probe-type electrical performance tester is used to simultaneously measure leakage current (measurement range 1pA~1mA), resistance (measurement range 1Ω~10MΩ), and threshold voltage (measurement range -2V~+2V) at the same acquisition point. The data is bound to the AFM acquisition point one by one through timestamps.

[0089] 3) Data storage: Distributed database storage is used, and the single file naming rule is "chip model_test date_region number_data type.csv", which supports fast retrieval by chip batch, test region, and data type.

[0090] After data acquisition, two types of data are preprocessed to remove noise and outliers, and the electrical performance data is mapped one-to-one with the AFM acquisition points. The preprocessing includes:

[0091] Noise removal: AFM data was filtered using Gaussian filtering (standard deviation σ=0.5) to remove random noise, and electrical performance data was filtered using median filtering (window size 5 data points) to remove impulse noise;

[0092] Outlier handling: Outliers are identified using the 3σ criterion (AFM height data exceeding the mean ±3σ and electrical performance data exceeding the mean ±5σ are considered outliers). Outlier locations are filled in using interpolation (based on data from 8 adjacent locations) to ensure data integrity.

[0093] Point alignment: Based on the spatial coordinates (X / Y axis coordinates) of the AFM acquisition points, the electrical performance data is matched over time. The alignment error is ≤50nm. If the error exceeds the standard, the data for that area is reacquired.

[0094] S102: Feature Extraction and Fusion

[0095] 1) After data preprocessing and point alignment are completed, data from different physical domains (AFM and electrical performance) first need to be format converted to form standardized tensor inputs suitable for deep learning model processing.

[0096] Data format conversion: The preprocessed AFM data is converted into a 3-channel matrix (height, stiffness, surface potential), and the electrical performance data is converted into a K-channel matrix (leakage current, resistance, threshold voltage, etc.). The matrix dimensions are uniformly adjusted to 1024×1024 (zero padding for insufficient parts and block processing for excessive parts).

[0097] 2) CNN Feature Extraction:

[0098] The uniformly sized AFM three-channel matrix and electrical performance K-channel matrix are each input into a two-branch CNN structure for local feature extraction. Each CNN branch is specifically designed to capture meaningful local patterns from its respective data modality.

[0099] Each CNN branch consists of multiple stacked convolutional layers, connected by specific parameters. In a preferred embodiment, its structure is as follows:

[0100] The first convolutional layer uses 64 3×3 convolutional kernels with a stride of 1 and padding mode set to "SAME" to ensure that the spatial dimensions of the output feature map are consistent with the input (1024×1024). This layer is used to capture basic local features such as edges and gradients.

[0101] The second convolutional layer uses 128 3×3 convolutional kernels with a stride of 1. This layer combines and extracts more complex textures and structural patterns based on the lower-level features.

[0102] The third convolutional layer uses 256 convolutional kernels of size 5×5 with a stride of 1. Larger convolutional kernels allow the model to have a larger receptive field, thus enabling it to perceive and extract more macroscopically meaningful combined features and morphologies.

[0103] Activation function: Immediately after each convolutional operation, a ReLU activation function is applied. This function sets the activation of all negative neurons to zero, while leaving positive neurons unchanged. This introduces crucial nonlinear transformation capabilities into the network, enabling the model to learn and fit complex nonlinear relationships.

[0104] 3) After extracting the spatial topographic features of the AFM data and the structural features of the electrical performance data using a dual-branch CNN, these two feature streams, which come from different sources but have an inherent physical relationship, are then deeply fused. This application employs a CNN-Transformer hybrid model to achieve this goal. This structure can leverage the advantage of CNN in capturing local details while also utilizing the ability of Transformer to establish long-range global dependencies, thereby comprehensively revealing the weak signals of latent defects. Here, Transformer refers to a converter, and the corresponding Transformer model can refer to a converter model or a transformer model.

[0105] First, the high-order feature maps output from the two CNN branches are serialized. Specifically, each feature map is flattened in space, transforming a 3D tensor of size [Height, Width, Channels] into a 2D feature sequence of size [Sequence_Length, Channels]. Here, the sequence length Sequence_Length = Height * Width. Then, positional information is encoded into this sequence, since the Transformer itself does not contain positional awareness. Through sine / cosine positional encoding or learnable positional encoding, the model is ensured to know the relative or absolute position of each feature vector in the original 2D space.

[0106] 4) The two feature sequences from the AFM mode and the electrical performance mode are concatenated along the sequence dimension to form a joint feature sequence, which is then input into the Transformer encoder layer.

[0107] Utilizing multi-head attention mechanisms to obtain feature sequences enhanced with global contextual information:

[0108] The input joint sequence is linearly mapped to a query set, a key set, and a value set, respectively. An attention weight matrix is ​​obtained by calculating the dot product of the query and all keys. This weight matrix quantifies the correlation strength between any two feature points in the sequence, regardless of whether they come from AFM data or electrical performance data. For example, a tiny morphological depression (AFM feature) may be strongly correlated with a distant anomalous leakage current point (electrical performance feature); this cross-modal, long-range implicit correlation is fully captured in this step. The output of this head is a weighted sum of the value sets, with the weights being the attention scores calculated above. Finally, the outputs of all attention heads are concatenated along the feature dimension and integrated through a linear projection layer to form a feature sequence enhanced with global contextual information.

[0109] To stabilize the training process and accelerate convergence, layer normalization is introduced after each sub-layer (multi-head attention layer and feedforward network layer). Layer normalization normalizes all feature dimensions of a single sample, effectively mitigating the internal covariate bias problem. The normalized features are then passed through a feedforward neural network, which typically consists of two fully connected layers and a ReLU activation function, used to perform non-linear transformations and enhancements on the features.

[0110] 5) After processing through multiple Transformer blocks, we obtain a deep fusion feature sequence. At this point, we need to convert this sequence into a tensor with a spatial size of 1024×1024 and 512 channels to generate the final cross-modal feature matrix.

[0111] In some embodiments, the deep fusion feature sequence is reconstructed into a feature map with spatial dimension based on the pre-stored spatial location information; the feature map with spatial dimension is upsampled to reach a preset standard size; a 1×1 convolutional layer is used to uniformly adjust the number of feature channels of the upsampled feature map to a preset number of channels, and finally the feature with enhanced global context information is output.

[0112] First, the system needs to recover the spatial dimensionality information that was temporarily ignored during the early serialization process. When flattening the CNN feature map into a sequence, the system records the corresponding position coordinates (such as row and column numbers) of each feature vector in the original two-dimensional feature map. Then, based on this pre-stored position information, the system performs the inverse operation on the deep-fused feature sequence output by the Transformer. Specifically, the feature sequence of length L is rearranged according to its original spatial correspondence into a two-dimensional grid structure with a specific height H and width W, resulting in a three-dimensional tensor with dimensions [H, W, C], where C is the feature dimension output by the Transformer. This step essentially remaps the abstract word sequence into feature maps with explicit spatial meaning.

[0113] The reshaped feature map [H, W, C] typically has spatial dimensions H and W that differ from the original input (1024x1024). To match the input requirements of downstream networks and ensure consistency across all samples, spatial dimension unification is necessary.

[0114] Spatial Upsampling: Upsampling operations such as bilinear interpolation or transposed convolution are used to precisely enlarge the spatial size of the feature map to a preset standard size of 1024 pixels × 1024 pixels. Bilinear interpolation provides a smooth scaling effect, while transposed convolution can perform learnable feature optimization during this process. 2. Channel Dimension Adjustment and Fusion: The number of channels in the feature map is adjusted by using 1×1 convolution. 1×1 convolution can perform efficient linear combination and information integration between different channels, playing the role of "feature compression" and "non-linear enhancement". In this scheme, by setting the output channel number of 1×1 convolution to 512, the number of channels C of the feature map is uniformly adjusted to 512.

[0115] The final output is a cross-modal feature matrix with a uniform dimension of 1024×1024×512, which contains local features and global correlation information.

[0116] S103: Defect Identification

[0117] After obtaining the cross-modal feature matrix that integrates global and local information, this step will perform defect diagnosis and evaluation. This process is completed by a pre-trained defect recognition model, whose goal is to locate, identify and quantify latent defects on the chip from complex features.

[0118] In one specific embodiment, the pre-trained defect identification model is a semantic segmentation or dense prediction model based on a convolutional neural network. After loading, the cross-modal feature matrix with dimensions of 1024×1024×512 generated in the previous step is used as the model input. The model performs inference calculations on this matrix using forward propagation to parse the defect feature patterns contained therein.

[0119] In one specific embodiment, the pre-trained defect recognition model can adopt an encoder-decoder architecture. The encoder is based on a ResNet-50 backbone network pre-trained on a large dataset, with its first convolutional layer modified to accommodate a 512-channel cross-modal feature matrix input. It extracts abstract features with different receptive fields through multi-level convolutional downsampling. The decoder can employ a custom structure consisting of multiple sequentially stacked upsampling-convolutional modules. Its core achieves 2x upsampling through 4×4 transposed convolutions, followed by channel concatenation with shallow features from the corresponding encoder layer. Information is then fused through a feature refinement block containing two 3×3 convolutional layers (each followed by batch normalization and ReLU activation). Finally, 1×1 convolutions are used to progressively compress the number of channels, forming an expansion path symmetrical to the encoder, achieving spatial reconstruction and semantic enhancement of cross-modal features. Ultimately, multi-task prediction is achieved through the output layer.

[0120] In one specific embodiment, the task prediction employs a two-level cascaded classification strategy to balance the reliability of defect detection with the accuracy of classification:

[0121] Phase 1: Defect Existence Binary Classification

[0122] At this stage, the model independently judges each spatial point (i.e., each "pixel") corresponding to the feature matrix, performing a binary classification task: "normal" or "defective". For example, the network first generates a defect existence confidence map through a binary classification branch consisting of a 1x1 convolution and a sigmoid activation function.

[0123] The model outputs an initial confidence level between 0 and 1 for each location indicating a potential defect. The system sets a decision threshold (e.g., ≥0.8); a location is only preliminarily identified as a "potentially defective location" when its initial confidence level exceeds this threshold. This high threshold effectively filters out false alarms caused by noise, ensuring the reliability of locations sent to the next stage.

[0124] Phase Two: Multi-Label Classification of Defect Attributes

[0125] For all points identified as "potential defects" in the first stage, the system program will initiate the second stage of refined identification. This stage is a multi-label classification task used to determine which type of defect(s) the point belongs to. For example, this branch performs feature distillation through three 3×3 convolutional layers, then compresses the number of feature map channels to match the number of defect types N through a 1×1 convolutional layer. Subsequently, in the channel dimension, a sigmoid activation function is independently applied to the N-dimensional vector of each spatial location (i.e., each pixel), thereby outputting the multi-label probability distribution of the defect type.

[0126] In a specific embodiment, the two-level cascaded classification strategy can be implemented through two complementary technical paths: first, using an in-model conditional judgment layer to embed preset threshold logic into the forward propagation process, controlling the activation state of neurons in the multi-label classification branch through a gating mechanism; second, through external programmatic post-processing, first determining whether the initial confidence of the binary classification exceeds the threshold, and then deciding whether to call the multi-label classification module. The recognition results from the above two stages are then synthesized with spatial coordinate information to generate a structured diagnostic report for each identified defect location, for example:

[0127] Defect location: Based on the index of the defect in the feature matrix and the initial coordinates of the scanned area, the absolute physical coordinates (X, Y) on the chip are calculated using a coordinate inversion algorithm. Its positioning accuracy, achieved through high-resolution scan data, can reach ±10 nanometers.

[0128] Defect type: Directly derived from the results of the second-stage multi-label classification, clearly indicating the physical or electrical nature of the defect.

[0129] Severity: The system calculates a severity level from 1 to 5 based on the intensity, extent, and impact on electrical parameters of the defect characteristics. Level 1 represents the slightest anomaly requiring observation, while level 5 represents a fatal defect requiring immediate line stoppage and adjustment.

[0130] Overall confidence level: Finally, the system will combine the existence confidence level of the first stage with the type classification probability of the second stage to calculate an overall confidence level of 0% to 100%. This value fully reflects the model's grasp of the diagnostic result of this defect.

[0131] All output defect information is encapsulated into structured data objects (such as JSON format) and written to the database in real time.

[0132] In some embodiments, this application may further include the steps of: generating a defect location heatmap based on the defect identification results, distinguishing severity levels by color coding, and generating a comparison chart of manufacturing parameter adjustments;

[0133] Provide an interactive interface for marking defective areas and submitting decision-making opinions;

[0134] The confirmed optimization plan is sent to the manufacturing equipment control system via industrial communication protocol, and a standard format test report is generated.

[0135] In one specific embodiment, multi-dimensional visualization charts are generated based on defect identification results. For example, a defect location heatmap is used, and the chip physical layout is converted into a color-coded image through coordinate mapping technology. Red highlights indicate level 4-5 severe defect areas, yellow indicates level 2-3 moderate defects, and blue indicates level 1 minor defects. At the same time, a manufacturing parameter adjustment comparison chart is generated, clearly showing the current and recommended adjustment values ​​of key process parameters (such as ion implantation dose and annealing temperature) through dual-axis curves. Secondly, on the interactive visualization platform, engineers can select and mark defect clustering areas and add decision opinions (such as agreeing to the etching parameter adjustment plan or suggesting a second scan of area A7). All manual intervention records are synchronized to the distributed database in real time, forming a complete audit trail chain. Finally, the double-confirmed optimization plan is directly transmitted to the manufacturing equipment control system compatible with semiconductor equipment interface protocols (such as TCP / IP+Modbus) through a secure communication protocol, and a standard-compliant electronic inspection report is automatically generated, realizing digital closed-loop management from defect analysis to production execution.

[0136] In some embodiments, this application further includes the steps of: inputting the defect identification result into a pre-trained yield prediction model and outputting a yield prediction value; and generating a key process parameter adjustment scheme based on the yield prediction value.

[0137] In one specific embodiment, the structured data output by the defect identification module, including defect type, spatial distribution density, severity level, and corresponding confidence level, is input into a yield prediction sub-model trained on historical manufacturing data. This model employs a gradient boosting decision tree architecture, quantifying the impact weights of different defect categories on electrical performance and combining defect clustering effect analysis to output a quantitative yield prediction value for the current chip sample within the range of zero to 100%. Based on this yield prediction value, the system activates the process parameter optimization engine. First, the predicted yield is compared with the target yield threshold. When the deviation exceeds a preset tolerance, the system invokes the defect-process mapping relationship stored in the manufacturing parameter knowledge base to automatically generate specific adjustment schemes for key parameters such as ion implantation dose, annealing temperature, or etching time. This scheme not only includes the direction and magnitude of parameter adjustment but also uses Monte Carlo simulation to predict the yield improvement effect, ultimately forming a complete decision suggestion that includes executable process instructions and expected optimization effects.

[0138] The applicant noted that the dimensional differences between traditional AFM three-dimensional spatial data and electrical performance time-series data prevented traditional analysis methods from establishing an effective correlation. First, the two types of data have significant dimensional differences (AFM is three-dimensional spatial data, while electrical performance is time-series / point data), making it impossible to establish a correlation through traditional manual analysis. Second, latent defect characteristics are weak, making them difficult to identify using traditional threshold judgment methods. Third, inspection and yield optimization are disconnected; even if defects are detected, it is impossible to quickly pinpoint the direction of adjustments in the manufacturing process, resulting in a long optimization cycle.

[0139] In this regard, the present invention can alleviate the above problems to a certain extent by optimizing the above detection and identification methods.

[0140] From another perspective, the embodiments of the present invention may have the following technical advantages:

[0141] 1. By integrating nanoscale physical morphology data from atomic force microscopy with electrical performance parameters using AI, and employing a deep learning model to capture the weak nonlinear correlation between the two, we can accurately identify hidden defects with normal surface morphology but abnormal electrical properties, thus achieving precise location and diagnosis of deep-seated quality problems in chips.

[0142] 2. A CNN branch is used to extract local microscopic defect spatial features from the 3D topographic data of atomic force microscopy (AFM). Simultaneously, a Transformer branch is used to capture long-sequence dependencies in electrical performance data and their global association with spatial features. Finally, cross-modal feature interaction and fusion are performed at a deep model level, mapping physical topographic information and electrical performance information from different dimensions to a unified feature space. This provides reliable data support with both local details and global context for subsequent intelligent detection of latent defects in chips.

[0143] 3. The system can automatically associate the identified defect information with the manufacturing parameter database and output specific optimization solutions, changing the traditional situation where inspection and yield optimization are disconnected.

[0144] 4. By automatically generating high-precision defect location heatmaps and manufacturing parameter adjustment comparison charts, the complex output data results are transformed into an extremely intuitive visualization interface. The defect location heatmap overlays and renders the spatial coordinates of the chip inspection area with the severity, type, and confidence level of the defect, using a distinct color gradient for labeling. This allows engineers to instantly grasp the defect distribution of the entire chip in a single image, accurately pinpointing problem areas and changing the inefficient mode of manual inspection through massive amounts of data.

[0145] Reference Figure 2 In some embodiments, this application also discloses a chip AFM detection sequence selection method, including the following steps:

[0146] S201. Obtain the SEM image of the chip to be tested. Preferably, the chip to be tested has undergone electrical performance testing beforehand.

[0147] In some embodiments, this application is applicable to both chip locations with and without electrical performance testing anomalies. For locations where electrical performance testing has revealed anomalies, the system further analyzes their physical morphology features using SEM images to assess the severity and spatial distribution of defects. For locations where electrical performance testing is normal but SEM images show suspicious morphology, the system identifies them as potential latent defects and initiates AFM for detailed re-inspection. By establishing a correlation judgment mechanism between electrical performance and physical morphology, the system achieves accurate assessment of explicit defects and proactive discovery of latent defects, thereby comprehensively improving the coverage and accuracy of defect detection.

[0148] S202. Perform grayscale analysis on the SEM image to obtain the grayscale information of the SEM image;

[0149] In some embodiments, after acquiring the scanning electron microscope (SEM) image of the chip to be inspected, grayscale analysis processing is performed on the SEM image. This processing extracts the grayscale values ​​of each pixel or region in the image, quantifies the morphological comparison information contained in the SEM image into specific grayscale information data, thereby establishing a preliminary judgment basis for morphological anomalies based on grayscale features, and providing a data foundation for subsequent defect identification and classification.

[0150] S203. Set a grayscale preset threshold, obtain suspicious points that need to be re-examined by AFM based on grayscale information (such as grayscale feature values) and grayscale preset threshold, and generate a list of suspicious points.

[0151] After acquiring the scanning electron microscope (SEM) image of the chip under test, the system first performs professional image processing and feature analysis on the acquired SEM image. Gray-scale features are used to quantify and evaluate the degree of shadowing in each region of the image. Specifically, when the gray-scale feature value (e.g., gray value) of a specific region is lower than a preset first threshold, it is determined that there is a significant morphological anomaly, and the probability of a defect is very high, so there is no need to start atomic force microscopy (AFM) for subsequent inspection. When the gray-scale feature value of a specific region exceeds the preset first threshold, it is determined that the region has a certain probability of morphological anomaly features. The system will mark the region as a potential defect region and automatically include it in the AFM supplementary inspection queue.

[0152] S204. Assign AFM detection priorities to each location in the list of suspicious locations, including:

[0153] Obtain the detection features of suspicious locations, including the functional area, size, and distribution density of the suspicious locations;

[0154] Assign a basic weight score to the functional area;

[0155] The basic weight score is adjusted by weighting based on the location size and location distribution density;

[0156] The weighted scores are mapped to predefined AFM detection priorities;

[0157] A queue of AFM detection tasks is generated based on the AFM detection priority.

[0158] In some embodiments, suspicious points in the head queue of the AFM detection task queue can be used as recommended detection points. For example, suspicious points in the head queue refer to points with a detection priority greater than or equal to a set priority. Alternatively, suspicious points in the head queue refer to the suspicious points in the first part of the AFM detection task queue, such as when the proportion of the head queue in the AFM detection task queue is less than a preset proportion. In some embodiments, after completing the initial screening of suspicious points, the system acquires the detection features of each suspicious point, for example, based on chip design layout data, determines the functional area of ​​each suspicious point through coordinate mapping, and classifies and labels them according to a predefined functional criticality level. Secondly, the system accurately calculates the physical size parameters of each suspicious point using existing image analysis algorithms, including the projected area and equivalent diameter in the SEM image. Simultaneously, the system uses existing spatial statistical algorithms to quantitatively analyze the distribution pattern of suspicious points across the entire chip, calculating distribution density data reflecting the degree of point clustering.

[0159] In some embodiments, weighting the base weight score based on the point size and point distribution density includes:

[0160] Set a first weighting factor for the point size, and the first weighting factor gradually decreases as the point size increases;

[0161] A second weighting coefficient is set for the point distribution density, and the second weighting coefficient gradually decreases as the point distribution density increases;

[0162] The basic weight score is adjusted by weighting based on the first weighting coefficient and the second weighting coefficient.

[0163] In one specific embodiment, after extracting multi-dimensional features from suspicious locations, the system initiates an intelligent evaluation process for detection priorities. First, based on chip architecture design specifications, a critical grading system for functional areas is established, and different basic weight scores are assigned to different functional areas. Specifically, the system divides chip functional areas into three critical levels and assigns a basic weight score. For example, the first-level core functional areas (such as CPU / GPU processing cores and L1 / L2 cache arrays) are assigned a basic score of 100; the second-level important functional areas (such as memory controllers and I / O interface units) are assigned a basic score of 70; and the third-level general functional areas (such as power management units and test structures) are assigned a basic score of 40. This tiered scoring mechanism ensures that detection resources are tilted towards areas that have the greatest impact on chip performance.

[0164] Based on the initial weighted score, the system refines the score using a dual weighting factor. For example, regarding the size characteristics of the defects, the system sets a first weighting coefficient and establishes a size-coefficient mapping table: a weighting coefficient of 1.5 is assigned when the defect size is ≤10nm; a coefficient of 1.2 is assigned when the size is in the range of 10-50nm; and a coefficient of 1.0 is assigned when the size is ≥50nm. This decreasing coefficient design ensures that small defects receive priority detection. Regarding spatial distribution characteristics, the system sets a second weighting coefficient and defines a density evaluation standard. For example, within a 100μm² area, a sparse distribution is defined as having ≤3 suspected defects, and a weighting coefficient of 1.4 is assigned; a medium distribution is defined as having 4-8 defects, and a coefficient of 1.1 is assigned; and a dense distribution is defined as having ≥9 defects, and a coefficient of 1.0 is assigned.

[0165] The final priority score is then calculated using a multiplicative model: Final Priority Score = Base Weight Score × First Weighting Coefficient × Second Weighting Coefficient. For example, a 15nm defect located in the CPU core region (base score 100) with a coefficient of 1.2, in a sparsely distributed region (coefficient 1.4), will receive a final score of 100 × 1.2 × 1.4 = 168. However, a defect of the same size located in a densely distributed region (base score 40) in the power management region (coefficient 1.0) will only receive a score of 40 × 1.2 × 1.0 = 48.

[0166] Finally, the calculation results are converted into specific detection priorities through a preset score range mapping rule: points with a score ≥150 are classified as emergency priority and AFM detection is arranged immediately; points with a score between 100-149 are classified as high priority and detection is arranged after the emergency task is completed; points with a score between 50-99 are classified as medium priority; and points with a score <50 are classified as low priority.

[0167] In some embodiments, this application further includes the step of:

[0168] Suspicious locations are clustered, and a subset of suspicious locations are selected from the clustered suspicious location set according to priority for AFM detection.

[0169] After prioritizing all suspicious points, the system first employs a density-based spatial clustering algorithm (such as DBSCAN) to intelligently group suspicious points across the entire chip, merging spatially adjacent points with similar characteristics into the same defect cluster. Next, following preset cluster selection rules, the system prioritizes defect clusters containing a large number of high-priority points and exhibiting a concentrated spatial distribution as key detection targets. Based on the final determination of the clusters to be inspected, the system further implements a stratified sampling strategy according to the specific priority scores of the points within each cluster: all points in the top 20% of priority within each selected defect cluster are inspected; points in the middle priority range (20%-60%) are randomly sampled for inspection at a rate of 30%; and only 1-2 representative points from the bottom 40% of low-priority points with obvious clustering characteristics are selected for confirmatory inspection. This clustering-based targeted screening mechanism achieves an optimal balance between detection efficiency and quality assurance while ensuring a high defect capture rate.

[0170] In some embodiments, this application further includes the step of:

[0171] Acquire historical detection data, which includes historical AFM detection results and AFM detection priority information;

[0172] The AFM detection priority information is adjusted based on the AFM detection results.

[0173] In one specific embodiment, after the system completes the detection task of a preset cycle, it automatically collects a historical detection dataset. This dataset fully includes the initial AFM detection priority score for each suspicious point and the corresponding actual AFM detection results, including defect type, severity, and false alarms. By establishing a correlation model between priority scores and detection results, the system first analyzes the distribution pattern of the actual defect detection rate within each priority interval. For priority intervals with high initial scores but consistently lower actual defect detection rates than a preset threshold (e.g., <60%), the system will reduce the weight of the feature weight combination corresponding to that interval, such as adjusting the size factor weight from 0.4 to 0.3. At the same time, for feature combinations with moderate initial scores but significantly high defect detection rates (e.g., >85%), a weight enhancement strategy is implemented. Furthermore, the system dynamically optimizes the score boundaries for priority division, adjusting the score range boundaries for densely populated defect areas from a fixed 100 points to dynamic thresholds (such as the 90-120 score range in the current detection). It also establishes a feature feedback mechanism: when defects within a specific size range (e.g., 5-15nm) are missed in the core functional area, the system automatically adjusts the influence factor of that size range in the weight calculation. Through this data-driven closed-loop optimization mechanism, the model's parameters can be iterated, continuously improving the accuracy of priority assessment and ultimately achieving a systematic optimization of AFM detection resource utilization efficiency.

[0174] In other words, this embodiment provides a detection mechanism for restrictive detection of suspicious points, namely, screening the detection range and detection order of suspicious points, so as to reduce secondary damage to the chip under test while improving detection accuracy.

[0175] It should be noted that since AFM testing often requires the use of probes, it is prone to causing secondary damage to the chip being tested during the process. Furthermore, AFM testing is relatively expensive. Therefore, this invention focuses on using conventional electrical performance testing for initial screening. Subsequently, suspicious points that are difficult to determine directly are identified based on electrical performance testing. The detection priority of these suspicious points is then ranked based on their functional area, size, and distribution density, allowing for the selection of a relatively limited number of suspicious points for AFM testing. The restrictive detection mechanism proposed in this embodiment, on the one hand, improves the accuracy of defect detection and avoids missing latent defects by synergistically combining AFM testing and electrical performance testing; on the other hand, by restricting the application of AFM testing, it comprehensively controls testing costs and the potential secondary damage to the chip.

[0176] In particular, when the defect types in the chip under test have high repetition or the number of defect types is relatively limited, prioritizing the detection of suspicious points in the header sequence is beneficial to completing a relatively complete defect investigation through the detection of a limited number of suspicious points.

[0177] Reference Figure 3 In one specific embodiment, this application also discloses a method for controlling the AFM detection level of a chip, which specifically includes the following steps:

[0178] S301. Obtain the chip to be tested, wherein the chip to be tested has multiple testing areas, and the chip to be tested is preferably pre-tested for electrical performance.

[0179] In some embodiments, this application is applicable to both chip locations with and without electrical performance testing anomalies. For locations where electrical performance testing has revealed anomalies, the system can first further analyze their physical morphology features using SEM images to assess the severity and spatial distribution of defects before initiating AFM detection. Conversely, for locations with normal electrical performance testing but suspicious morphology in SEM images, the system identifies them as potential latent defects and initiates AFM for detailed re-inspection. By establishing a correlation judgment mechanism between electrical performance and physical morphology, accurate assessment of explicit defects and proactive discovery of latent defects are achieved, thereby comprehensively improving the coverage and accuracy of defect detection.

[0180] S302. Set the initial AFM detection level for the chip under test, including:

[0181] A uniform detection level is set for the chip to be tested;

[0182] Different risk levels are set for different categories of testing items;

[0183] Different risk levels are mapped to different initial adjustment coefficients, and the unified detection level is adjusted based on the different initial adjustment coefficients to obtain the AFM initial detection level.

[0184] In some embodiments, a uniform detection level is first established as a benchmark. This benchmark serves as the starting point and reference anchor for the entire adjustment process, and is typically preset based on the chip's process node (e.g., 7nm, 5nm) and industry-standard quality control criteria. For example, this uniform level can be defined as a standard detection mode, and configured with a set of universal acquisition parameters that balance efficiency and accuracy, such as a default acquisition point interval of 10nm and a default detection area defined as the core functional unit area. This enables the system to have a reliable and executable default detection scheme.

[0185] Subsequently, different risk levels are pre-defined and associated with different inspection item categories. This forms the knowledge base and decision-making basis for differentiated inspection. The system maintains an inspection item-risk level mapping database, built upon long-term accumulated process knowledge, defect analysis reports, and failure mode data. Specifically: defect types such as surface particulate matter and fatal short circuits, which can directly render a chip unusable, are classified as high-risk; while defect types such as localized doping anomalies and nanoscale oxide layer defects, which may affect the long-term reliability or performance parameters of the device, are classified as medium-risk; and statistical parameters such as surface roughness and average film thickness, primarily used to monitor process stability and consistency, are classified as low-risk.

[0186] Next, the system performs crucial mapping and adjustment calculations. In this step, different risk levels are quantified into different initial adjustment coefficients. The system applies these adjustment coefficients to the previously set uniform detection level and derives the final AFM initial detection level through mathematical calculations. Specifically, the adjustment coefficient is directly related to the detection density: for high-risk items, the system applies a coefficient greater than 1 (e.g., 1.5), which reduces the final spot interval (e.g., from the baseline 10nm to 6.7nm) or expands the detection area, thereby achieving more stringent and comprehensive detection; for low-risk items, a coefficient less than 1 (e.g., 0.7) is applied, which appropriately increases the spot interval (e.g., adjusts it to 14nm) or shrinks the detection area, thereby significantly improving detection efficiency while ensuring statistical validity.

[0187] S303. Perform AFM testing on the chip to be tested based on the initial AFM detection level, and obtain historical yield data and current yield data after the test;

[0188] In some embodiments, the system first performs atomic force microscopy (AFM) detection on the chip to be tested according to a preset initial AFM detection level. The detection process strictly follows the configuration of acquisition parameters that are dynamically adjusted based on the risk level, including but not limited to precisely set nanoscale point intervals and optimized area scanning ranges. High-precision probes are used to synchronously acquire multi-dimensional physical parameters such as the three-dimensional morphology, local potential distribution, and nanomechanical properties of the chip surface and near-surface areas.

[0189] In some embodiments, after the inspection is completed, the system automatically acquires and associates two datasets through a data interface: one is real-time yield data representing the current manufacturing status, and the other is standardized historical yield benchmark data for the same period. By establishing a dynamic comparison and analysis model between the two, the effectiveness and process stability of the current inspection strategy can be quantitatively evaluated, and core data support can be provided for building a closed-loop quality control system. This enables the inspection level of subsequent batches to be adaptively adjusted based on objective quality feedback, thereby continuously promoting the precise improvement of chip manufacturing yield and the continuous optimization of quality control processes.

[0190] S304. Compare the current yield data with the historical yield data, and based on the comparison results, verify or adjust the initial detection level of AFM.

[0191] In some embodiments, comparing current yield data with historical yield data and adjusting the initial AFM detection level based on the comparison results includes:

[0192] The current yield data is directly compared with the historical yield data;

[0193] If the current yield rate is higher than the historical yield rate, then set a lower initial detection level for AFM.

[0194] If the current yield rate is lower than the historical yield rate, then set a higher detection level for the initial AFM detection level.

[0195] In one specific embodiment, by establishing a direct comparison mechanism between the actual yield data of the current production batch and the validated historical yield benchmark data, when the system detects that the current yield is consistently and stably higher than the historical benchmark, it automatically sets a relatively low detection level for subsequent batches, such as appropriately increasing the interval between sampling points or reducing the detection area. Conversely, when the current yield is detected to be lower than the historical benchmark, an upgrade response is immediately initiated, setting a higher detection level for subsequent batches, such as reducing the interval between sampling points, expanding the detection area, or increasing the detection frequency. This achieves dynamic optimization of the detection strategy based on real-time quality feedback, effectively improving the utilization efficiency of detection resources while ensuring controllable quality.

[0196] In some embodiments, comparing current yield data with historical yield data and adjusting the initial AFM detection level based on the comparison results includes:

[0197] The yield fluctuation value for a selected time period is calculated based on the current yield data and historical yield data.

[0198] The yield fluctuation value is compared with the preset fluctuation threshold, and the initial detection level of AFM is adjusted according to the comparison result.

[0199] In one specific embodiment, the yield fluctuation value for a selected time period is first calculated using a standard deviation algorithm based on the current yield data and historical yield dataset. Then, this yield fluctuation value is compared and analyzed with multiple preset threshold ranges. When the fluctuation value exceeds the preset upper threshold, the system determines that process stability has decreased and automatically increases the AFM detection level, for example, reducing the sampling point interval from the standard 10nm to 5nm and simultaneously expanding the detection area to 150% of the original area. When the fluctuation value is within the normal threshold range, the current detection level remains unchanged. When the fluctuation value is below the lower threshold, the detection level is appropriately reduced, for example, adjusting the sampling point interval to 15nm. This achieves precise control of the detection strategy based on quantitative assessment of process stability, ensuring both controllable quality risks and optimal allocation of detection resources.

[0200] In some embodiments, this application further includes the step of:

[0201] Obtain maintenance plan information for AFM testing equipment and determine the current maintenance status based on the maintenance plan information;

[0202] Based on the current maintenance status, the initial AFM detection level will be adjusted, including:

[0203] If the AFM testing equipment is in the initial operation period after maintenance or is about to enter the final stage before planned maintenance, then a higher testing level should be set for the initial AFM testing level.

[0204] If the AFM testing equipment is in a stable operating period, the initial AFM testing level will not be adjusted.

[0205] In one specific embodiment, the system interacts with the equipment management system to obtain real-time maintenance plan information of the AFM testing equipment, including the last maintenance completion time and the next planned maintenance time, and accurately determines the current maintenance cycle of the equipment based on this information. Based on the judgment of the current maintenance status, the system adjusts the initial AFM detection level. Specifically, if the AFM testing equipment is in the initial operation period after maintenance (e.g., the first 24 hours after maintenance) or about to enter the final stage before planned maintenance (e.g., the 48 hours before the planned maintenance time), a higher detection level is set for the initial AFM detection level. For example, the sampling point interval is reduced by 30%-50% from the baseline value, and the detection area is expanded to 120%-150% of the original area to strengthen the monitoring of potential defects that may be introduced by equipment status fluctuations. If the AFM testing equipment is in a stable operation period (e.g., the period from the end of the post-maintenance operation period to the start of the maintenance period), the original initial AFM detection level is maintained without adjustment to ensure optimal allocation of testing resources.

[0206] Further reference Figure 4 As an implementation of the aforementioned chip latent defect detection method, this application provides an embodiment of a chip latent defect detection system, which is similar to... Figure 1 Corresponding to the method embodiments shown, the system can be specifically applied to various electronic devices.

[0207] refer to Figure 4 A chip latent defect detection system, comprising:

[0208] The dataset acquisition module 110 is configured to acquire a dataset, which includes preprocessed AFM three-dimensional topography data and electrical performance data of the chip under test. The AFM three-dimensional topography data and electrical performance data are obtained by scanning and testing the same area of ​​the chip under test by an atomic force microscope and an electrical performance tester, respectively.

[0209] The conversion module 120 is configured to convert the preprocessed AFM three-dimensional topography data and electrical performance data into a first multi-channel matrix and a second multi-channel matrix, respectively. The first multi-channel matrix includes a height data channel, a stiffness data channel and a surface potential data channel, and the second multi-channel matrix includes a leakage current data channel, a resistance data channel and a threshold voltage data channel.

[0210] Feature extraction module 130 is configured to input the first multi-channel matrix and the second multi-channel matrix into the feature extractor and extract the morphological data features and electrical performance data features, respectively.

[0211] The fusion module 140 is configured to fuse topographic data features and electrical performance data features to obtain joint features;

[0212] The context information enhancement module 150 is configured to process joint features using a multi-head attention mechanism to obtain features with global context information enhancement.

[0213] The defect identification module 160 is configured to input features enhanced with global context information into a pre-trained defect identification model and output defect identification results.

[0214] The pre-trained defect recognition model includes a binary classification module and a multi-label classification module;

[0215] Furthermore, the step of inputting the features enhanced with global context information into the pre-trained defect recognition model and outputting the defect recognition result includes:

[0216] The features enhanced with global context information are input into the binary classification module to determine whether there are defects at each spatial location and output the initial confidence score. If the initial confidence score is higher than the first threshold, the multi-label classification module is called to output the defect type information.

[0217] The pre-trained defect recognition model is obtained by training the defect recognition model with features enhanced by global context information of the sample chip and defect annotation data.

[0218] Further reference Figure 5 As an implementation of the above-mentioned chip AFM detection sequence selection method, this application provides an embodiment of a chip AFM detection sequence selection system, which is similar to... Figure 2 Corresponding to the method embodiments shown, the system can be specifically applied to various electronic devices.

[0219] refer to Figure 5 A chip AFM detection sequence selection system, comprising:

[0220] The data acquisition module 210 is configured to acquire SEM images of the chip under test, which has undergone electrical performance testing in advance.

[0221] The data processing module 220 is configured to perform grayscale analysis on the SEM image to obtain the grayscale information of the SEM image;

[0222] The suspicious location list acquisition module 230 is configured to set a grayscale preset threshold, acquire suspicious locations that need to be re-inspected by AFM based on the grayscale information and the grayscale preset threshold, and generate a suspicious location list.

[0223] The AFM detection priority generation module 240 is configured to assign AFM detection priorities to each location in the list of suspected locations, including:

[0224] Acquire the detection features of suspicious locations, including the functional area, size, and distribution density of the suspicious locations;

[0225] Assign a basic weight score to the functional area;

[0226] The basic weight score is adjusted by weighting based on the point size and point distribution density;

[0227] The weighted scores are mapped to predefined AFM detection priorities;

[0228] An AFM detection task queue is generated based on the AFM detection priority.

[0229] Further reference Figure 6 As an implementation of the above-mentioned chip AFM detection level control method, this application provides an embodiment of a chip AFM detection level control system, which is similar to... Figure 3 Corresponding to the method embodiments shown, the system can be specifically applied to various electronic devices.

[0230] refer to Figure 6 A chip AFM detection level control system, comprising:

[0231] The data acquisition module 310 is configured to acquire the chip to be tested, and the chip to be tested has multiple detection areas, and the chip to be tested has undergone electrical performance testing in advance.

[0232] The detection level setting module 320 is configured to set the initial AFM detection level for the chip under test, including:

[0233] A uniform detection level is set for the chip to be tested;

[0234] Different risk levels are set for different categories of testing items;

[0235] Different risk levels are mapped to different initial adjustment coefficients, and the unified detection level is adjusted based on the different initial adjustment coefficients to obtain the AFM initial detection level.

[0236] The yield data acquisition module 330 is configured to perform AFM detection on the chip to be tested based on the initial AFM detection level, and acquire current yield data and historical yield data after the detection.

[0237] The control module 340 is configured to compare the current yield data with the historical yield data, and based on the comparison results, verify or adjust the initial detection level of AFM.

[0238] In another aspect, this application also provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the following... Figure 1 The method shown.

[0239] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0240] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0241] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A method for detecting latent defects in a chip, the method comprising: The method comprises the following steps: obtaining a data set comprising pre-processed AFM three-dimensional topography data and electrical performance data of a chip to be detected, the AFM three-dimensional topography data and the electrical performance data being obtained by scanning and testing the same detection area of the chip to be detected by an atomic force microscope and an electrical performance tester respectively; converting the pre-processed AFM three-dimensional topography data and the electrical performance data into a first multi-channel matrix and a second multi-channel matrix respectively, the first multi-channel matrix comprising a height data channel, a stiffness data channel and a surface potential data channel, and the second multi-channel matrix comprising a leakage current data channel, a resistance data channel and a threshold voltage data channel; inputting the first multi-channel matrix and the second multi-channel matrix into a feature extractor to extract topography data features and electrical performance data features respectively; fusing the topography data features and the electrical performance data features to obtain joint features; processing the joint features by using a multi-head attention mechanism to obtain features with enhanced global context information; inputting the features with enhanced global context information into a pre-trained defect recognition model to output a defect recognition result; the pre-trained defect recognition model comprises a binary classification module and a multi-label classification module; and the inputting the features with enhanced global context information into the pre-trained defect recognition model to output the defect recognition result comprises: inputting the features with enhanced global context information into the binary classification module to determine whether there is a defect at each spatial position and output an initial confidence, and if the initial confidence is higher than a first threshold, calling the multi-label classification module to output defect type information; the pre-trained defect recognition model is obtained by training the defect recognition model by using features with enhanced global context information of a sample chip and defect annotation data; wherein the joint features comprise a joint feature sequence; and the fusing the topography data features and the electrical performance data features to obtain joint features comprises: serializing the topography data features and the electrical performance data features respectively to obtain a first feature sequence and a second feature sequence respectively, and splicing the first feature sequence and the second feature sequence in a sequence dimension to form a joint feature sequence; the processing the joint features by using the multi-head attention mechanism comprises: injecting position information coding into the joint feature sequence, inputting the joint feature sequence after the position information coding into a Transformer model and processing the joint feature sequence by using the multi-head attention mechanism to obtain a deep fusion feature sequence; reconstructing the deep fusion feature sequence into a feature map with spatial dimensions according to pre-stored spatial position information; performing an upsampling operation on the feature map after the upsampling to make it reach a preset standard size; uniformly adjusting the number of feature channels of the feature map after the upsampling to a preset number of channels by using a 1x1 convolutional layer, and finally outputting the features with enhanced global context information.

2. The method of claim 1, wherein the method further comprises: The defect recognition result comprises a defect position, a defect type and a severity level.

3. The method of claim 2, wherein the method further comprises: It further comprises the following steps: generating a defect positioning heat map based on the defect recognition result, distinguishing the severity levels by color coding, and generating a manufacturing parameter adjustment comparison chart. An interactive operation interface is provided to label the defect area and submit a decision opinion; The confirmed optimization scheme is sent to a manufacturing equipment control system through an industrial communication protocol, and a detection report in a standard format is generated.

4. The method of claim 2, wherein the method further comprises: Further comprising steps of: Inputting the defect recognition result into a pre-trained yield prediction model to output a yield prediction value; Generating a key process parameter adjustment scheme according to the yield prediction value.

5. A system for detecting latent defects in a chip, the system comprising: The system comprises: a data set acquisition module configured to acquire a data set, the data set comprising preprocessed AFM three-dimensional topography data and electrical performance data of a chip to be detected, the AFM three-dimensional topography data and the electrical performance data being obtained by scanning and testing the same area to be detected of the chip to be detected by an atomic force microscope and an electrical performance tester respectively; a conversion module configured to convert the preprocessed AFM three-dimensional topography data and the electrical performance data into a first multi-channel matrix and a second multi-channel matrix respectively, the first multi-channel matrix comprising a height data channel, a stiffness data channel and a surface potential data channel, and the second multi-channel matrix comprising a leakage current data channel, a resistance data channel and a threshold voltage data channel; a feature extraction module configured to input the first multi-channel matrix and the second multi-channel matrix into a feature extractor respectively and extract topography data features and electrical performance data features; a fusion module configured to fuse the topography data features and the electrical performance data features to obtain joint features; a context information enhancement module configured to process the joint features using a multi-head attention mechanism to obtain globally context information enhanced features; a defect recognition module configured to input the globally context information enhanced features into a pre-trained defect recognition model to output a defect recognition result; the pre-trained defect recognition model comprises a binary classification module and a multi-label classification module; and the inputting the globally context information enhanced features into the pre-trained defect recognition model to output the defect recognition result comprises: inputting the globally context information enhanced features into the binary classification module to determine whether there is a defect at each spatial position and output an initial confidence, and if the initial confidence is higher than a first threshold, calling the multi-label classification module to output defect type information; the pre-trained defect recognition model is trained by globally context information enhanced features of a sample chip and defect labeling data; wherein the joint features comprise a joint feature sequence; and the fusing the topography data features and the electrical performance data features to obtain the joint features comprises: serializing the topography data features and the electrical performance data features respectively to obtain a first feature sequence and a second feature sequence respectively, and splicing the first feature sequence and the second feature sequence in a sequence dimension to form a joint feature sequence; the processing the joint features using the multi-head attention mechanism comprises: injecting position information coding into the joint feature sequence, inputting the joint feature sequence after the position information coding into a Transformer model and processing it using the multi-head attention mechanism to obtain a deep fusion feature sequence; reconstruct the deep fusion feature sequence into a feature map with spatial dimensions according to the pre-stored spatial position information; perform an up-sampling operation on the feature map with spatial dimensions to make it reach a pre-set standard size; use a 1x1 convolutional layer to uniformly adjust the feature channel number of the up-sampled feature map to a pre-set channel number, and finally output a feature with enhanced global context information.

6. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method of any one of claims 1 to 4.

7. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method of any one of claims 1 to 4.

Images