P2P equal-bandwidth output method for display system and display control chip

Abstract

The invention discloses a P2P equal-bandwidth output method and device for a display system and a display control chip. The objective of the invention is to solve the problem that when TCON and COMBO TX clocks cannot be divided exactly, lossless transmission can still be realized and the FIFO area can be reduced. A shallow asynchronous FIFO is configured in the COMBO TX, the TCONPLL frequency is adjusted in a closed-loop mode through a real-time water reading line, the step length is 1 / 256 times of a reference clock, and equal bandwidth output under + / -3% spread spectrum tolerance is achieved; and the horizontal blanking interval dynamically adds and deletes + / -8 packets on the P2P data packets according to rows, and keeps the bandwidth constant. Parallel simultaneous implementation is realized, and the depth of the FIFO is 1t; 256 level, and the chip area is significantly reduced. The chip integrates waterline monitoring, frequency modulation and packet increasing and decreasing modules, supports various P2P codes of 8 / 10, 9 / 10, 8 / 9, 20 / 24 and 24 / 28, and is suitable for various high-resolution display devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving, in particular to a P2P bandwidth output method for a display system and a display control chip. BACKGROUND

[0002] The conventional TCON output bandwidth mechanism usually shares a reference clock by an internal service TCON_PLL and a TX_PLL, and the clock frequency for service operation and the clock frequency for transmission are required to be precisely divided or multiplied to ensure that the calculated clock is a divisible relationship, and if the clock frequency is not divisible, it is unusable. In addition, considering that the maximum requirement of the high-speed data signal of the TX output is to support 3% spread spectrum, the depth of the asynchronous FIFO of the COMBOTX is required to be large enough (which will increase the chip area) to solve the processing of the equal bandwidth output without data loss. The basic formula of the TCON input and output equal bandwidth is: clk_tcon*pixels (pixels) * encoding method = clk_combotx*data_bit (data bit width of each TX lane) Take 8 / 9 encoding as an example: clk_tcon*30 (one pixel)*9 / 8 = clk_combtx*20; The encoding included in P2P includes: (1) 8 / 10 encoding; (2) 9 / 10 encoding; (3) 8 / 9 encoding; (4) 20 / 24 encoding; (5) 24 / 28 encoding; The conventional TX equal bandwidth general architecture is shown in Figure 1 In order to adapt to the design requirements of the TCON system integrated equal bandwidth input and output, a new enhanced equal bandwidth input and output design architecture is required. SUMMARY

[0003] (I) Technical problems to be solved The present application aims to provide a P2P equal bandwidth output method for a display system and a display control chip to solve the following problems: 1) the dependence of the conventional equal bandwidth mechanism on the integer division of the TCON_PLL and TX_PLL frequencies; 2) the chip area and power consumption overhead caused by the large-depth FIFO; 3) still ensuring that the video data is not lost and not misaligned under the spread spectrum condition.

[0004] (II) Technical solutions To solve the above problems at the same time, the technical solution adopted by the present application is: In a first aspect, the present application provides a P2P equal bandwidth output method for a display system, comprising: An asynchronous FIFO is set inside the COMBOTX at the sending end, the write port of the asynchronous FIFO receives video data from the TCON, and the read port is connected to the parallel-to-serial converter of the COMBOTX; Setting upper and lower thresholds of the read water line of the asynchronous FIFO; Real-time monitoring of the read water line; When the read water line is greater than or equal to the upper threshold, determining that the write clock is fast, and reducing the output frequency of the TCON_PLL; When the read water line is less than or equal to the lower threshold, determining that the write clock is slow, and increasing the output frequency of the TCON_PLL; The dynamic frequency adjustment has a minimum step of 1 / 256 times the reference clock; Through the above-mentioned closed-loop frequency adjustment, the clock frequencies of the TCON_PLL and the COMBOTX_PLL do not need to satisfy an integer multiple relationship, and still maintain clk_tcon×pixels×encoding ratio = clk_combotx×data_bit, And the asynchronous FIFO neither overflows nor underflows, realizing equal-bandwidth output.

[0005] In a second aspect, the application provides a P2P equal-bandwidth output method for a display system, comprising: Setting an asynchronous FIFO inside the COMBOTX at the sending end, wherein the write port of the asynchronous FIFO receives video data from the TCON, and the read port is connected to the parallel-to-serial converter of the COMBOTX; Setting upper and lower thresholds of the read water line of the asynchronous FIFO; Real-time monitoring of the read water line; When the read water line is greater than or equal to the upper threshold, performing a deletion action on the P2P data packet output by the TCON in the horizontal blanking interval, and the deletion granularity is a certain number of packets or pixels; When the read water line is less than or equal to the lower threshold, performing a supplement action in the same horizontal blanking interval, and the supplement granularity is a certain number of packets or pixels; The supplemented or deleted data stream is sent to the COMBOTX after P2P encoding; Through dynamic increase and decrease of the data amount, the clock frequencies of the TCON_PLL and the COMBOTX_PLL do not need to satisfy an integer multiple relationship, and still realize equal-bandwidth output without data loss.

[0006] Preferably, the physical depth of the asynchronous FIFO is less than 256 levels, and still can absorb the instantaneous read-write rate difference caused by 3% spread spectrum, thereby reducing the chip area.

[0007] Preferably, the P2P encoding is selected from at least one of 8 / 10, 9 / 10, 8 / 9, 20 / 24 or 24 / 28.

[0008] In a third aspect, the application provides a display control chip configured to execute the method of the first aspect, comprising: TCON_PLL, for generating pixel clock; COMBOTX, containing asynchronous FIFO and TX_PLL; water line monitoring module, outputting read water line value of the asynchronous FIFO in real time; frequency control module, connected with TCON_PLL, for increasing or decreasing frequency of TCON_PLL by 1 / 256 reference clock step according to the water line value; wherein, depth of the asynchronous FIFO is less than 256 levels.

[0009] Frequency control step of the frequency control module is fixed as 1 / 256 reference clock, and continuous multi-level adjustment is supported.

[0010] In the fourth aspect, the application provides a display control chip configured as the method in the second aspect, comprising: TCON_PLL, for generating pixel clock; COMBOTX, containing asynchronous FIFO and TX_PLL; water line monitoring module, outputting read water line value of the asynchronous FIFO in real time; packet increasing and decreasing module, for increasing or decreasing packet in the range of ±8 packet in line to P2P packet or pixel in horizontal blanking interval; encoding module, for performing P2P encoding on the data stream after increasing and decreasing and outputting to COMBOTX; wherein, depth of the asynchronous FIFO is less than 256 levels.

[0011] The packet increasing and decreasing module supports dynamic adjustment range of-8 to +8 packet per action in horizontal action unit.

[0012] In the fifth aspect, the application further provides a display device comprising the display control chip in the third aspect or the fourth aspect.

[0013] Compared with the prior art, the application has the following beneficial effects: 1) TCON_PLL and TX_PLL are allowed to work at non-integer frequency, and resolution compatibility is improved by 100%; 2) Depth of asynchronous FIFO is reduced by more than 50%, and chip area and dynamic power consumption are correspondingly reduced; 3) There is no packet loss and no flicker in the spread spectrum ±3% range, and system robustness is enhanced; 4) Compatible with multiple P2P encoding formats such as 8 / 10, 9 / 10, 8 / 9, 20 / 24, 24 / 28, etc. 5) Clock and bandwidth frequency calculation do not need to be so accurate, and clock frequency in resolution scene that cannot be divided by an integer can also be used; 6) The depth requirement for the FIFO can be reduced, saving space. Additionally, it enhances protection against empty or full FIFOs. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a medium-bandwidth output architecture in the prior art of this invention; Figure 2 This is a block diagram of the PLL dynamic frequency modulation architecture of the first embodiment of the present invention; Figure 3 This is a flowchart illustrating the process of adding and removing packet data according to the second embodiment of the present invention. Figure 4 This is a hardware topology diagram of an embodiment of the display control chip of the present invention. Detailed Implementation

[0015] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0016] Example 1 like Figure 2 As shown, based on the upper and lower waterline depths set for the asynchronous FIFO output by TX, when the read waterline reaches the set upper and lower thresholds, the TCONPLL frequency is adjusted. When the upper waterline threshold is reached, it indicates that the write clock is too fast, and the TCONPLL clock frequency needs to be slowed down to ensure that the FIFO data does not overflow. When the lower waterline threshold is reached, it indicates that the write clock is too slow, and the TCONPLL clock frequency needs to be fastened to ensure that the FIFO data is not read empty. Through the above mechanism, equal bandwidth processing can be achieved even when the data is not divisible. like Figure 4 As shown, based on the upper and lower waterline depths set by the asynchronous FIFO outputting TX, when the waterline reaches the set upper and lower thresholds, the frequency of TCONPLL / COMBOTXPLL is adjusted. The specific diagram is as follows: Based on the upper and lower water line depth set by TX output asynchronous FIFO, when the read water line reaches the set upper and lower threshold, the frequency of TCONPLL is adjusted. When the upper water line threshold is reached on the asynchronous FIFO water line, it means that the write clock is too fast, and the clock of TCONPLL needs to be adjusted to be slow to ensure that the FIFO data is not overflowed. When the lower water line threshold is reached on the asynchronous FIFO water line, it means that the write clock is too slow, and the clock frequency of TCONPLL needs to be adjusted to be fast to ensure that the FIFO data is not read empty. Through the above mechanism, equal bandwidth processing can be realized even if the data cannot be evenly divided.

[0017] Embodiment two As shown in Figure 3 Based on the upper and lower water line depth set by TX output asynchronous FIFO, when the read water line reaches the set upper and lower threshold, the frequency of TCONPLL is adjusted. When the upper water line threshold is reached on the asynchronous FIFO water line, it means that the write clock is too fast, and the clock of TCONPLL needs to be adjusted to be slow to ensure that the FIFO data is not overflowed. When the lower water line threshold is reached on the asynchronous FIFO water line, it means that the write clock is too slow, and the clock frequency of TCONPLL needs to be adjusted to be fast to ensure that the FIFO data is not read empty. Through the above mechanism, equal bandwidth processing can be realized even if the data cannot be evenly divided.

[0018] Based on the upper and lower water line depth set by TX output asynchronous FIFO, when the read water line reaches the set upper and lower threshold, the frequency of TCONPLL is adjusted. When the upper water line threshold is reached on the asynchronous FIFO water line, it means that the write clock is too fast, and the clock of TCONPLL needs to be adjusted to be slow to ensure that the FIFO data is not overflowed. When the lower water line threshold is reached on the asynchronous FIFO water line, it means that the write clock is too slow, and the clock frequency of TCONPLL needs to be adjusted to be fast to ensure that the FIFO data is not read empty. Through the above mechanism, equal bandwidth processing can be realized even if the data cannot be evenly divided.

[0019] Based on the upper and lower water line depth set by TX output asynchronous FIFO, when the read water line reaches the set upper and lower threshold, the frequency of TCONPLL is adjusted. When the upper water line threshold is reached on the asynchronous FIFO water line, it means that the write clock is too fast, and the clock of TCONPLL needs to be adjusted to be slow to ensure that the FIFO data is not overflowed. When the lower water line threshold is reached on the asynchronous FIFO water line, it means that the write clock is too slow, and the clock frequency of TCONPLL needs to be adjusted to be fast to ensure that the FIFO data is not read empty. Through the above mechanism, equal bandwidth processing can be realized even if the data cannot be evenly divided.

[0020] Term explanation P2P: Point-to-Point, refers to the dedicated high-speed serial interface between TCON and the source driving chip in the display panel.

[0021] Asynchronous FIFO: a first-in-first-out memory with different read and write clock domains.

[0022] Spread spectrum: periodic, small modulation of the clock frequency to reduce EMI.

[0023] hblank: horizontal blanking period, the time period from the end of the active pixels in one line to the beginning of the active pixels in the next line.

[0024] It should be noted that the information interaction, execution process and the like between the above devices / units are based on the same concept as the method embodiments of the present application, and the specific functions and technical effects brought by them can be referred to the method embodiments part, which will not be described here.

[0025] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of software functional unit. In addition, the specific name of each functional unit and module is only for convenient distinction, and does not limit the protection scope of the present application. The specific working process of the unit and module in the above system can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0026] The computer program product provided in the embodiments of the present application, when running on a mobile terminal, enables the mobile terminal to implement the steps in each of the above method embodiments.

[0027] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the present application can implement all or part of the processes in the above-mentioned embodiment methods through a computer program to instruct relevant hardware to complete, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by a processor, the steps of each method embodiment described above can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms. The computer readable medium can at least include any entity or device capable of carrying the computer program code to the photographing device / terminal equipment, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium. For example, U disk, mobile hard disk, magnetic disk or optical disk, etc. In some jurisdictions, according to legislation and patent practice, the computer readable medium can not be an electrical carrier signal and a telecommunication signal.

[0028] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0029] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0030] In the embodiments provided by the present application, it should be understood that the disclosed apparatus / network device and method can be implemented in other ways. For example, the above-described apparatus / network device embodiments are merely schematic, for example, the division of the modules or units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed each other can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0031] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may also be distributed to multiple network units. Part or all of the units can be selected to achieve the purpose of the embodiment scheme according to actual needs.

[0032] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. Methods for displaying bandwidth output, such as P2P, in a display system, including: An asynchronous FIFO is set up inside the COMBOTX at the transmitting end. The write port of the asynchronous FIFO receives video data from the TCON, and the read port is connected to the parallel-to-serial converter of the COMBOTX. The asynchronous FIFO is configured with an upper and lower threshold value for the read waterline; characterized in that, Real-time monitoring of the water reading line; When the read threshold is greater than or equal to the upper threshold, the write clock is determined to be too fast, and the output frequency of TCON_PLL is reduced. When the read threshold is less than or equal to the lower threshold, the write clock is considered slow, and the output frequency of TCON_PLL is increased. The dynamic frequency modulation uses a minimum step size of 1 / 256 times the reference clock. Through the above closed-loop frequency modulation, the clock frequencies of TCON_PLL and COMBOTX_PLL do not need to satisfy an integer multiple relationship, and the clk_tcon×pixels×encoding ratio is still maintained as clk_combotx×data_bit. Furthermore, the asynchronous FIFO neither overflows nor underflows, thus achieving equal bandwidth output.

2. A method for P2P and other bandwidth output in a display system, comprising: An asynchronous FIFO is set up inside the COMBOTX at the transmitting end. The write port of the asynchronous FIFO receives video data from the TCON, and the read port is connected to the parallel-to-serial converter of the COMBOTX. The asynchronous FIFO sets upper and lower threshold values ​​for the read waterline; it monitors the read waterline in real time; characterized in that... When the reading line is greater than or equal to the upper threshold, a pruning action is performed on the P2P data packets output by TCON in the horizontal blanking interval, with the pruning granularity being several packets or pixels; When the reading line is less than or equal to the lower threshold, a supplementary action is performed in the same horizontal blanking interval, with the supplementary granularity being several packets or pixels. The data stream, after being supplemented or deleted, is sent to COMBOTX after being P2P encoded. By dynamically increasing or decreasing the data volume, the clock frequencies of TCON_PLL and COMBOTX_PLL do not need to satisfy an integer multiple relationship, yet output with equal bandwidth and no data loss is still achieved.

3. The method according to claim 1 or 2, characterized in that: The asynchronous FIFO has a physical depth of less than 256 levels and can still absorb the instantaneous read / write rate difference caused by 3% spread spectrum, thereby reducing the chip area.

4. The method according to claim 1 or 2, characterized in that: The P2P code is selected from at least one of 8 / 10, 9 / 10, 8 / 9, 20 / 24, or 24 / 28.

5. A display control chip, characterized in that, Configured to perform the method of claim 1, comprising: TCON_PLL is used to generate pixel clocks; COMBOTX contains an asynchronous FIFO and TX_PLL; The waterline monitoring module outputs the waterline value of the asynchronous FIFO in real time; The frequency modulation control module is connected to TCON_PLL and adjusts the TCON_PLL frequency up or down in steps of 1 / 256 times the reference clock according to the water line value. The asynchronous FIFO has a depth of less than 256 levels.

6. The chip according to claim 5, characterized in that: The frequency modulation control module has a fixed frequency modulation step size of 1 / 256 times the reference clock and supports continuous multi-level adjustment.

7. A display control chip, characterized in that, Configured to perform the method of claim 2, comprising: TCON_PLL is used to generate pixel clocks; COMBOTX contains an asynchronous FIFO and TX_PLL; The waterline monitoring module outputs the waterline value of the asynchronous FIFO in real time; The packet addition / reduction module is used to add or remove P2P packets or pixels within a range of ±8 packets per row in the horizontal blanking interval. The encoding module performs P2P encoding on the data stream after the addition or subtraction and outputs it to COMBOTX; The asynchronous FIFO has a depth of less than 256 levels.

8. The chip according to claim 6, characterized in that: The packet addition / reduction module operates on a horizontal row basis, supporting dynamic adjustment of each row from -8 to +8 packets.

9. A display device, characterized in that, It includes the display control chip as described in claim 5 or 6.

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