High linearity high image rejection ratio hybrid complex filter circuit based on a source follower

Abstract

The application provides a high-linearity high-image-rejection-ratio hybrid complex filter circuit based on a source follower, and belongs to the technical field of radio frequency receivers. The hybrid function of multiple signal filtering and low-pass filtering is realized by adopting the source follower structure, the linearity of the circuit is effectively improved, and the image rejection capability is significantly enhanced. Meanwhile, the AC coupling network with high-pass characteristics is introduced, the input common-mode bias is provided for the circuit, the low-pass characteristics of the complex filter are combined, the band-pass filtering effect is realized, the additional requirement of the intermediate frequency band-pass filter in the later stage is omitted, and the overall system power consumption is reduced. The application has the beneficial effect of wide application range.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency receiver technology, specifically relating to a hybrid complex filter circuit with high linearity and high image rejection ratio based on a source follower. Background Technology

[0002] In recent years, with the increasing demands on system performance from applications such as wireless communication, navigation and positioning, and the Internet of Things (IoT), receivers need to maintain high sensitivity and reliability in complex interference environments. This requires front-end modules to have a large dynamic range and low power consumption to meet the application needs of portable and embedded devices. Currently, widely used receiver architectures include zero-IF (zero-intermediate-frequency) and low-IF (low-intermediate-frequency) architectures. The low-IF architecture can effectively avoid the DC offset problem common in the zero-IF architecture and significantly reduce the impact of flicker noise under CMOS technology. However, this architecture is prone to introducing image interference during signal down-conversion. The image signal is superimposed into the target signal band, thereby reducing the output signal-to-noise ratio (SNR) and affecting the system's anti-interference capability and signal selectivity. Therefore, introducing complex filters in low-IF receivers is of great significance, as it can effectively suppress image interference and out-of-band interference, improving overall receiving performance.

[0003] In most applications, complex filters are primarily implemented using active RC and Gm-C structures. Active RC filters are limited by operational amplifier gain and bandwidth, resulting in higher power consumption at higher operating frequencies. Gm-C filters, operating in an open-loop state, offer higher operating frequencies and lower power consumption. However, their open-loop characteristics lead to a significant decrease in linearity. In contrast, using a source follower structure, replacing the transconductance (gm) unit with a single transistor, can significantly reduce power consumption. Furthermore, the source follower structure employs an internal feedback loop, reducing the overdrive voltage of the input MOSFET and improving linearity. However, currently, filters based on source follower structures can only achieve real-domain filtering and cannot suppress image signals. Summary of the Invention

[0004] In order to overcome the shortcomings of existing technologies, reduce the power consumption of active RC filters at high frequencies, and improve the linearity of Gm-C filters in open-loop characteristics, this invention provides a hybrid complex filter circuit with high linearity and high image rejection ratio based on a source follower.

[0005] A hybrid complex filter circuit based on a source follower with high linearity and high image rejection ratio includes an AC coupling circuit, a multiphase filter circuit, a first feedforward capacitor CH1, a second feedforward capacitor CH2, a third feedforward capacitor CH3, and a fourth feedforward capacitor CH4.

[0006] The AC coupling circuit has four inputs: a first input voltage terminal IIP, a second input voltage terminal IIN, a third input voltage terminal IQP, and a fourth input voltage terminal IQN. The AC coupling circuit also has four outputs: a first positive output terminal VIP_I, a first negative output terminal VIN_I, a second positive output terminal VIP_Q, and a second negative output terminal VIN_Q. The phase of the first input voltage terminal IIP is 180° different from the phase of the second input voltage terminal IIN. The phase of the third input voltage terminal IQP is 180° different from the phase of the fourth input voltage terminal IQN. The phase of the first input voltage terminal IIP is 90° different from the phase of the third input voltage terminal IQP. The phase of the second input voltage terminal IIN is 90° different from the phase of the fourth input voltage terminal IQN.

[0007] The multiphase filter circuit includes a multiphase filter I path and a multiphase filter Q path;

[0008] The inputs of the polyphase filter I path are a first polyphase input terminal and a second polyphase input terminal; the outputs of the polyphase filter I path include a first output terminal VSP_I and a second output terminal VSN_I; the first polyphase input terminal is connected to the first positive output terminal VIP_I; the second polyphase input terminal is connected to the first negative output terminal VIN_I; one end of the fourth feedforward capacitor CH4 is connected to the first output terminal VSP_I of the I path; the other end of the fourth feedforward capacitor CH4 is connected to the second negative output terminal VIN_Q;

[0009] One end of the third feedforward capacitor CH3 is connected to the second output terminal VSN_I of the I-path; the other end of the third feedforward capacitor CH3 is connected to the second positive output terminal VIP_Q.

[0010] The inputs of the Q-path of the polyphase filter are the third polyphase input terminal and the fourth polyphase input terminal; the outputs of the Q-path of the polyphase filter are the first output terminal VSP_Q and the second output terminal VSN_Q; the third polyphase input terminal is connected to the second positive output terminal VIP_Q; and the fourth polyphase input terminal is connected to the second negative output terminal VIN_Q.

[0011] One end of the first feedforward capacitor CH1 is connected to the first output terminal VSP_Q of the Q-path; the other end of the first feedforward capacitor CH1 is connected to the first positive output terminal VIP_I; one end of the second feedforward capacitor CH2 is connected to the second output terminal VSN_Q of the Q-path; the other end of the second feedforward capacitor CH2 is connected to the first negative output terminal VIN_I.

[0012] The AC coupling circuit is used to isolate the AC component of the input signal from the common-mode bias of the filter circuit's preceding stage, enabling the filter circuit to independently establish and maintain the required common-mode operating point. By connecting a capacitor in series in the signal path, the AC coupling circuit introduces a high-pass characteristic with a cutoff frequency of 1 / RC while blocking DC and extremely low-frequency components. This allows the input of the multiphase filter circuit to have the ability to suppress low-frequency and DC interference before entering the multiphase filter circuit. Since the multiphase filter itself exhibits a low-pass response, the high-pass AC coupling circuit and the low-pass multiphase filter circuit are combined to form a bandpass filter as a whole, achieving effective selection and enhancement of the target operating frequency band. This is beneficial for setting a stable bias and improving the frequency selectivity of the filter circuit.

[0013] The multiphase filter circuit utilizes the first-order low-pass performance of the multiphase filter circuit and the first-order high-pass performance of the feedforward capacitor: the multiphase filter circuit lags the phase of the input signal by 45° at the cutoff frequency, and the feedforward capacitor leads the phase of the input signal by 45° at the cutoff frequency; the multiphase filter I-path utilizes the first-order low-pass phase frequency characteristic of the signal transmission from the first positive output terminal VIP_I to the first output terminal VSP_I of the I-path and the first-order high-pass phase frequency characteristic of the signal transmission from the first output terminal VSP_Q to the first positive output terminal VIP_I of the Q-path: the first positive output terminal VIP_I to the first output terminal VSP_I of the I-path... The phase lags by 45°, and the phase of the signal from the first output terminal VSP_Q of the Q path to the first positive output terminal VIP_I leads by 45°. The Q path of the polyphase filter utilizes the first-order low-pass phase frequency characteristic of the signal transmission from the second positive output terminal VIP_Q to the first output terminal VSP_Q of the Q path and the first-order high-pass phase frequency characteristic of the signal transmission from the second output terminal VSN_I of the I path to the second positive output terminal VIP_Q: the phase lags by 45° from the second positive output terminal VIP_Q to the first output terminal VSP_Q of the Q path, and the phase leads by 45° from the second output terminal VSN_I of the I path to the second positive output terminal VIP_Q.

[0014] Furthermore, the AC coupling circuit includes an AC coupling I path and an AC coupling Q path;

[0015] The AC coupling I path includes a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2; one end of the first capacitor C1 is connected to the first input voltage terminal IIP; the other end of the first capacitor C1 is connected to one end of the first resistor R1 and the first positive output terminal VIP_I; the other end of the first resistor R1 is connected to the common-mode input voltage VCM; one end of the second capacitor C2 is connected to the second input voltage terminal IIN; the other end of the second capacitor C2 is connected to the first negative output terminal VIN_I and one end of the second resistor R2; the other end of the second resistor R2 is connected to the common-mode input voltage VCM.

[0016] The resistance of the first resistor R1 is equal to the resistance of the second resistor R2; the capacitance of the first capacitor C1 is equal to the capacitance of the second capacitor C2.

[0017] The AC coupling Q path includes a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4; one end of the third capacitor C3 is connected to the third input voltage terminal IQP; the other end of the third capacitor C3 is connected to the second positive output terminal VIP_Q and one end of the third resistor R3; the other end of the third resistor R3 is connected to the common-mode input voltage VCM; one end of the fourth capacitor C4 is connected to the fourth input voltage terminal IQN; the other end of the fourth capacitor C4 is connected to one end of the fourth capacitor R4 and the second negative output terminal VIN_Q; the other end of the fourth capacitor R4 is connected to the common-mode input voltage VCM.

[0018] The resistance of the third resistor R3 is equal to the resistance of the fourth resistor R4; the capacitance of the third capacitor C3 is equal to the capacitance of the fourth capacitor C4.

[0019] Furthermore, the multiphase filter I path includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a first bias MOSFET MVB1, a second bias MOSFET MVB2, a third bias MOSFET MVB3, a fourth bias MOSFET MVB4, a fifth bias MOSFET MVB5, a sixth bias MOSFET MVB6, a fifth capacitor C5, and a sixth capacitor C6;

[0020] The first multiphase input terminal is connected to the gate of the first MOSFET M1; the drain of the first MOSFET M1 is connected to GND; the source of the first MOSFET M1 is connected to the source of the first bias MOSFET MVB1; the connection point between the source of the first MOSFET M1 and the source of the first bias MOSFET MVB1 is the first output terminal VSP_I of the I-path; the source of the first bias MOSFET MVB1 is connected to VDD; the gate of the first bias MOSFET MVB1 is connected to the first bias voltage input terminal VB1.

[0021] The second multiphase input terminal is connected to the gate of the second MOSFET M2; the drain of the second MOSFET M2 is connected to VDD; the source of the second MOSFET M2 is connected to the drain of the second bias MOSFET MVB2; the connection point between the source of the second MOSFET M2 and the drain of the second bias MOSFET MVB2 is the second output terminal VSN_I of the I-path; the source of the second bias MOSFET MVB2 is connected to VDD; the gate of the second bias MOSFET MVB2 is connected to the first bias voltage input terminal VB1.

[0022] The source of the fifth bias MOSFET MVB5 is connected to GND; the gate of the fifth bias MOSFET MVB5 is connected to the second bias voltage input terminal VB2; the drain of the fifth bias MOSFET MVB5 is connected to the source of the third MOSFET M3; the connection point between the drain of the fifth bias MOSFET MVB5 and the source of the third MOSFET M3 is the third output terminal VOP_I of the I-path.

[0023] The gate of the third MOSFET M3 is connected to the second output terminal VSN_I of the I-path; the drain of the third MOSFET M3 is connected to the first output terminal VSP_I of the I-path; the drain of the third bias MOSFET MVB3 is connected to the first output terminal VSP_I of the I-path; the gate of the third bias MOSFET MVB3 is connected to the zero bias voltage input terminal VB; the source of the third bias MOSFET MVB3 is connected to VDD.

[0024] The source of the sixth bias MOSFET MVB6 is connected to GND; the gate of the sixth bias MOSFET MVB6 is connected to the second bias voltage input terminal VB2; the drain of the sixth bias MOSFET MVB6 is connected to the source of the fourth MOSFET M4; the connection point between the drain of the sixth bias MOSFET MVB6 and the source of the fourth MOSFET M4 is the fourth output terminal VON_I of the I-path; the gate of the fourth MOSFET M4 is connected to the first output terminal VSP_I of the I-path; the drain of the fourth MOSFET M4 is connected to the second output terminal VSN_I of the I-path; the fourth The drain of the bias MOSFET MVB4 is connected to the second output terminal VSN_I of the I-path; the gate of the fourth bias MOSFET MVB4 is connected to the zero bias voltage input terminal VB; the source of the fourth bias MOSFET MVB4 is connected to VDD; one end of the fifth capacitor C5 is connected to the first output terminal VSP_I of the I-path; the other end of the fifth capacitor C5 is connected to the second output terminal VSN_I of the I-path; one end of the sixth capacitor C6 is connected to the third output terminal VOP_I of the I-path; the other end of the sixth capacitor C6 is connected to the fourth output terminal VON_I of the I-path.

[0025] Furthermore, the first MOSFET M1, the second MOSFET M2, the first bias MOSFET MVB1, the second bias MOSFET MVB2, the third bias MOSFET MVB3, and the fourth bias MOSFET MVB4 are all P-channel MOSFETs; the third MOSFET M3, the fourth MOSFET M4, the fifth bias MOSFET MVB5, and the sixth bias MOSFET MVB6 are all N-channel MOSFETs.

[0026] Furthermore, the multiphase filter Q-path includes a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a seventh bias MOSFET MVB7, an eighth bias MOSFET MVB8, a ninth bias MOSFET MVB9, a tenth bias MOSFET MVB10, an eleventh bias MOSFET MVB11, a twelfth bias MOSFET MVB12, a seventh capacitor C7, and an eighth capacitor C8.

[0027] The gate of the fifth MOSFET M5 is connected to the third multiphase input terminal; the drain of the fifth MOSFET M5 is connected to GND; the source of the fifth MOSFET M5 is connected to the drain of the seventh bias MOSFET MVB7; the connection point between the source of the fifth MOSFET M5 and the drain of the seventh bias MOSFET MVB7 is the first output terminal VSP_Q of the Q-path; the gate of the seventh bias MOSFET MVB7 is connected to the first bias voltage input terminal VB1; the source of the seventh bias MOSFET MVB7 is connected to VDD.

[0028] The gate of the sixth MOSFET M6 is connected to the fourth multiphase input terminal; the drain of the sixth MOSFET M6 is connected to GND; the source of the sixth MOSFET M6 is connected to the drain of the eighth bias MOSFET MVB8; the connection point between the source of the sixth MOSFET M6 and the drain of the eighth bias MOSFET MVB8 is the second output terminal VSN_Q of the Q-path; the gate of the eighth bias MOSFET MVB8 is connected to the first bias voltage input terminal VB1; the source of the eighth bias MOSFET MVB8 is connected to VDD.

[0029] The source of the eleventh bias MOSFET MVB11 is connected to GND; the gate of the eleventh bias MOSFET MVB11 is connected to the second bias voltage input terminal VB2; the drain of the eleventh bias MOSFET MVB11 is connected to the source of the seventh MOSFET M7; the connection point between the drain of the eleventh bias MOSFET MVB11 and the source of the seventh MOSFET M7 is the third output terminal VOP_Q of the Q-path; the drain of the seventh MOSFET M7 is connected to the first output terminal VSP_Q of the Q-path; the gate of the seventh MOSFET M7 is connected to the second output terminal VSN_Q; the drain of the ninth bias MOSFET MVB9 is connected to the first output terminal VSP_Q of the Q-path; the source of the ninth bias MOSFET MVB9 is connected to VDD; the gate of the ninth bias MOSFET MVB9 is connected to the zero bias voltage input terminal VB.

[0030] The source of the twelfth bias MOSFET MVB12 is connected to GND; the gate of the twelfth bias MOSFET MVB12 is connected to the second bias voltage input terminal VB2; the drain of the twelfth bias MOSFET MVB12 is connected to the source of the eighth MOSFET M8; the connection point between the drain of the twelfth bias MOSFET MVB12 and the source of the eighth MOSFET M8 is the fourth output terminal VON_Q of the Q-path; the gate of the eighth MOSFET M8 is connected to the first output terminal VSP_Q of the Q-path; the drain of the eighth MOSFET M8 is connected to the second output terminal VSN_Q. Connections: The drain of the tenth bias MOSFET MVB10 is connected to the second output terminal VSN_Q; the gate of the tenth bias MOSFET MVB10 is connected to the zero bias voltage input terminal VB; the source of the tenth bias MOSFET MVB10 is connected to VDD; one end of the seventh capacitor C7 is connected to the first output terminal VSP_Q, and the other end of the seventh capacitor C7 is connected to the second output terminal VSN_Q; one end of the eighth capacitor C8 is connected to the third output terminal VOP_Q of the Q path, and the other end of the eighth capacitor C8 is connected to the fourth output terminal VON_Q of the Q path.

[0031] Furthermore, the fifth MOSFET M5, the sixth MOSFET M6, the seventh bias MOSFET MVB7, the eighth bias MOSFET MVB8, the ninth bias MOSFET MVB9, and the tenth bias MOSFET MVB10 are all P-channel MOSFETs; the seventh MOSFET M7, the eighth MOSFET M8, the eleventh bias MOSFET MVB11, and the twelfth bias MOSFET MVB12 are all N-channel MOSFETs.

[0032] The beneficial effects of this invention are as follows: By employing a source follower structure to achieve a hybrid function of multiphase and low-pass filtering, it exhibits high linearity and excellent image rejection performance, with a third-order intermodulation point (IIP3) of 18.1 dBm, approximately 165% higher than the Gm-C structure. Furthermore, this invention also achieves bandpass functionality by introducing an AC coupling circuit with high-pass characteristics to provide the input bias voltage, while simultaneously combining it with the low-pass characteristics of complex filtering. This eliminates the need for an intermediate frequency filter in subsequent circuits, reducing power consumption by approximately 30%. In addition, the hybrid complex filter based on a source follower proposed in this invention can be used in wireless communication chips, with a wide range of applications. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a hybrid complex filter circuit structure based on a source follower with high linearity and high image rejection ratio, provided by an embodiment of the present invention.

[0034] Figure 2 These are the frequency response simulation results of the hybrid complex filter circuit based on a source follower with high linearity and high image rejection ratio provided in the embodiments of the present invention;

[0035] Figure 3These are simulation results of the linearity at the center frequency of the hybrid complex filter circuit based on a source follower with high linearity and high image rejection ratio, provided in this embodiment of the invention.

[0036] Figure 4 These are simulation results of the linearity within the operating frequency of the hybrid complex filter circuit based on a source follower with high linearity and high image rejection ratio, provided in this embodiment of the invention.

[0037] CH1 - First feedforward capacitor; CH2 - Second feedforward capacitor; CH3 - Third feedforward capacitor; CH4 - Fourth feedforward capacitor; IIP - First input voltage terminal; IIN - Second input voltage terminal; IQP - Third input voltage terminal; IQN - Fourth input voltage terminal; VIP_I - First positive output terminal; VIN_I - First negative output terminal; VIP_Q - Second positive output terminal; VIN_Q - Second negative output terminal; C1 - First capacitor; C2 - Second capacitor; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; C3 - Third capacitor; C4 - Fourth capacitor; C5 - Fifth capacitor; C6 - Sixth capacitor; VSP_I - First output terminal of I-path; VSN_I - Second output terminal of I-path; M1 - First MOSFET; M2 - Second MOSFET; M3 - Third MOSFET; M4 - Fourth MOSFET; MVB1 - First bias MOSFET; MVB2 - Second bias MOSFET; MVB3 - Third bias MOSFET; M VB4 - Fourth bias MOSFET; MVB5 - Fifth bias MOSFET; MVB6 - Sixth bias MOSFET; VSP_Q-Q path first output terminal; VSN_Q-Q path second output terminal; M5 - Fifth MOSFET; M6 - Sixth MOSFET; M7 - Seventh MOSFET; M8 - Eighth MOSFET; MVB7 - Seventh bias MOSFET; MVB8 - Eighth bias MOSFET; MVB9 - Ninth bias MOSFET; MVB10 - Tenth bias MOSFET; M VB11 - Eleventh bias MOSFET; MVB12 - Twelfth bias MOSFET; C7 - Seventh capacitor; C8 - Eighth capacitor; VCM - Common-mode input voltage; VB - Zero bias voltage input terminal; VB1 - First bias voltage input terminal; VB2 - Second bias voltage input terminal; VOP_I-I path third output terminal VOP_I; VON_I-I path fourth output terminal VON_I; VOP_Q-Q path third output terminal; VON_Q-Q path fourth output terminal. Detailed Implementation

[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0039] The solution adopted in this invention is a hybrid complex filter circuit with high linearity and high image rejection ratio based on a source follower, including an AC coupling circuit, a multiphase filter circuit, a first feedforward capacitor CH1, a second feedforward capacitor CH2, a third feedforward capacitor CH3, and a fourth feedforward capacitor CH4.

[0040] The AC coupling circuit is used to isolate the AC component of the input signal from the common-mode bias of the filter circuit's preceding stage, enabling the filter circuit to independently establish and maintain the required common-mode operating point. By connecting a capacitor in series in the signal path, the AC coupling circuit introduces a high-pass characteristic with a cutoff frequency of 1 / RC while blocking DC and extremely low-frequency components. This allows the input of the multiphase filter circuit to have the ability to suppress low-frequency and DC interference before entering the multiphase filter circuit. Since the multiphase filter itself exhibits a low-pass response, the high-pass AC coupling circuit and the low-pass multiphase filter circuit are combined to form a bandpass filter as a whole, achieving effective selection and enhancement of the target operating frequency band. This is beneficial for setting a stable bias and improving the frequency selectivity of the filter circuit.

[0041] The AC coupling circuit has four inputs: a first input voltage terminal IIP, a second input voltage terminal IIN, a third input voltage terminal IQP, and a fourth input voltage terminal IQN. The AC coupling circuit also has four outputs: a first positive output terminal VIP_I, a first negative output terminal VIN_I, a second positive output terminal VIP_Q, and a second negative output terminal VIN_Q. The phase of the first input voltage terminal IIP is 180° different from the phase of the second input voltage terminal IIN. The phase of the third input voltage terminal IQP is 180° different from the phase of the fourth input voltage terminal IQN. The phase of the first input voltage terminal IIP is 90° different from the phase of the third input voltage terminal IQP. The phase of the second input voltage terminal IIN is 90° different from the phase of the fourth input voltage terminal IQN.

[0042] AC coupling circuits include AC coupling I-paths and AC coupling Q-paths;

[0043] The AC coupling I path includes a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2; one end of the first capacitor C1 is connected to the first input voltage terminal IIP; the other end of the first capacitor C1 is connected to one end of the first resistor R1 and the first positive output terminal VIP_I; the other end of the first resistor R1 is connected to the common-mode input voltage VCM; one end of the second capacitor C2 is connected to the second input voltage terminal IIN; the other end of the second capacitor C2 is connected to the first negative output terminal VIN_I and one end of the second resistor R2; the other end of the second resistor R2 is connected to the common-mode input voltage VCM.

[0044] The resistance of the first resistor R1 is equal to the resistance of the second resistor R2; the capacitance of the first capacitor C1 is equal to the capacitance of the second capacitor C2.

[0045] The AC coupling Q path includes a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4; one end of the third capacitor C3 is connected to the third input voltage terminal IQP; the other end of the third capacitor C3 is connected to the second positive output terminal VIP_Q and one end of the third resistor R3; the other end of the third resistor R3 is connected to the common-mode input voltage VCM; one end of the fourth capacitor C4 is connected to the fourth input voltage terminal IQN; the other end of the fourth capacitor C4 is connected to one end of the fourth capacitor R4 and the second negative output terminal VIN_Q; the other end of the fourth capacitor R4 is connected to the common-mode input voltage VCM.

[0046] The resistance of the third resistor R3 is equal to the resistance of the fourth resistor R4; the capacitance of the third capacitor C3 is equal to the capacitance of the fourth capacitor C4.

[0047] A polyphase filter circuit includes a polyphase filter I-path and a polyphase filter Q-path;

[0048] The polyphase filter I-path utilizes the first-order low-pass phase frequency characteristic of the signal transmission from the first positive output terminal VIP_I to the first output terminal VSP_I of the I-path and the first-order high-pass phase frequency characteristic of the signal transmission from the first output terminal VSP_Q to the first positive output terminal VIP_I of the Q-path: the phase of the signal from the first positive output terminal VIP_I to the first output terminal VSP_I of the I-path lags by 45°, and the phase of the signal from the first output terminal VSP_Q to the first positive output terminal VIP_I of the Q-path leads by 45°.

[0049] The Q-path of the polyphase filter utilizes the first-order low-pass phase frequency characteristic of the signal transmission from the second positive output terminal VIP_Q to the first output terminal VSP_Q of the Q-path and the first-order high-pass phase frequency characteristic of the signal transmission from the second output terminal VSN_I of the I-path to the second positive output terminal VIP_Q: the phase of the signal from the second positive output terminal VIP_Q to the first output terminal VSP_Q of the Q-path lags by 45°, and the phase of the signal from the second output terminal VSN_I of the I-path to the second positive output terminal VIP_Q leads by 45°.

[0050] Taking the I-path output as an example, the signals from the first positive output terminal VIP_I and the first negative output terminal VIN_I pass through the first MOSFET M1 and the second MOSFET M2 to reach the first output terminal VSP_I and the second output terminal VSN_I of the I-path, with a phase lag of 45°, resulting in a -45° phase signal. The signals from the second positive output terminal VIP_Q and the second negative output terminal VIN_Q of the Q-path pass through the third feedforward capacitor CH3 and the fourth feedforward capacitor CH4 with a phase lead of 45°. After inversion, the output signal is a useful signal of -45° and a mirror signal of 135°, which are superimposed on the signals from the first output terminal VSP_I and the second output terminal VSN_I of the I-path. The useful signal is enhanced and the mirror signal is canceled out. Then, the signals pass through the low-pass path formed by the third MOSFET M3 and the fourth MOSFET M4, finally reaching the output node, significantly improving the linearity and image suppression capability of the multiphase filter.

[0051] The inputs of the polyphase filter I path are a first polyphase input terminal and a second polyphase input terminal; the outputs of the polyphase filter I path include a first output terminal VSP_I and a second output terminal VSN_I; the first polyphase input terminal is connected to the first positive output terminal VIP_I; the second polyphase input terminal is connected to the first negative output terminal VIN_I; one end of the fourth feedforward capacitor CH4 is connected to the first output terminal VSP_I of the I path; the other end of the fourth feedforward capacitor CH4 is connected to the second negative output terminal VIN_Q;

[0052] One end of the third feedforward capacitor CH3 is connected to the second output terminal VSN_I of the I-path; the other end of the third feedforward capacitor CH3 is connected to the second positive output terminal VIP_Q.

[0053] The multiphase filter I path includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a first bias MOSFET MVB1, a second bias MOSFET MVB2, a third bias MOSFET MVB3, a fourth bias MOSFET MVB4, a fifth bias MOSFET MVB5, a sixth bias MOSFET MVB6, a fifth capacitor C5, and a sixth capacitor C6;

[0054] The first multiphase input terminal is connected to the gate of the first MOSFET M1; the drain of the first MOSFET M1 is connected to GND; the source of the first MOSFET M1 is connected to the source of the first bias MOSFET MVB1; the connection point between the source of the first MOSFET M1 and the source of the first bias MOSFET MVB1 is the first output terminal VSP_I of the I-path; the source of the first bias MOSFET MVB1 is connected to VDD; the gate of the first bias MOSFET MVB1 is connected to the first bias voltage input terminal VB1.

[0055] The second multiphase input terminal is connected to the gate of the second MOSFET M2; the drain of the second MOSFET M2 is connected to VDD; the source of the second MOSFET M2 is connected to the drain of the second bias MOSFET MVB2; the connection point between the source of the second MOSFET M2 and the drain of the second bias MOSFET MVB2 is the second output terminal VSN_I of the I-path; the source of the second bias MOSFET MVB2 is connected to VDD; the gate of the second bias MOSFET MVB2 is connected to the first bias voltage input terminal VB1.

[0056] The source of the fifth bias MOSFET MVB5 is connected to GND; the gate of the fifth bias MOSFET MVB5 is connected to the second bias voltage input terminal VB2; the drain of the fifth bias MOSFET MVB5 is connected to the source of the third MOSFET M3; the connection point between the drain of the fifth bias MOSFET MVB5 and the source of the third MOSFET M3 is the third output terminal VOP_I of the I-path.

[0057] The gate of the third MOSFET M3 is connected to the second output terminal VSN_I of the I-path; the drain of the third MOSFET M3 is connected to the first output terminal VSP_I of the I-path; the drain of the third bias MOSFET MVB3 is connected to the first output terminal VSP_I of the I-path; the gate of the third bias MOSFET MVB3 is connected to the zero bias voltage input terminal VB; the source of the third bias MOSFET MVB3 is connected to VDD.

[0058] The source of the sixth bias MOSFET MVB6 is connected to GND; the gate of the sixth bias MOSFET MVB6 is connected to the second bias voltage input terminal VB2; the drain of the sixth bias MOSFET MVB6 is connected to the source of the fourth MOSFET M4; the connection point between the drain of the sixth bias MOSFET MVB6 and the source of the fourth MOSFET M4 is the fourth output terminal VON_I of the I-path; the gate of the fourth MOSFET M4 is connected to the first output terminal VSP_I of the I-path; the drain of the fourth MOSFET M4 is connected to the second output terminal VSN_I of the I-path; the fourth The drain of bias MOSFET MVB4 is connected to the second output terminal VSN_I of the I-path; the gate of the fourth bias MOSFET MVB4 is connected to the zero bias voltage input terminal VB; the source of the fourth bias MOSFET MVB4 is connected to VDD; one end of the fifth capacitor C5 is connected to the first output terminal VSP_I of the I-path; the other end of the fifth capacitor C5 is connected to the second output terminal VSN_I of the I-path; one end of the sixth capacitor C6 is connected to the third output terminal VOP_I of the I-path; the other end of the sixth capacitor C6 is connected to the fourth output terminal VON_I of the I-path.

[0059] The first MOSFET M1, the second MOSFET M2, the first bias MOSFET MVB1, the second bias MOSFET MVB2, the third bias MOSFET MVB3, and the fourth bias MOSFET MVB4 are all P-channel MOSFETs; the third MOSFET M3, the fourth MOSFET M4, the fifth bias MOSFET MVB5, and the sixth bias MOSFET MVB6 are all N-channel MOSFETs.

[0060] The inputs of the Q-path of the multiphase filter are the third multiphase input terminal and the fourth multiphase input terminal; the outputs of the Q-path of the multiphase filter are the first output terminal VSP_Q and the second output terminal VSN_Q; the third multiphase input terminal is connected to the second positive output terminal VIP_Q; the fourth multiphase input terminal is connected to the second negative output terminal VIN_Q; one end of the first feedforward capacitor CH1 is connected to the first output terminal VSP_Q of the Q-path; the other end of the first feedforward capacitor CH1 is connected to the first positive output terminal VIP_I; one end of the second feedforward capacitor CH2 is connected to the second output terminal VSN_Q of the Q-path; the other end of the second feedforward capacitor CH2 is connected to the first negative output terminal VIN_I;

[0061] The multiphase filter Q-path includes the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, the seventh bias MOSFET MVB7, the eighth bias MOSFET MVB8, the ninth bias MOSFET MVB9, the tenth bias MOSFET MVB10, the eleventh bias MOSFET MVB11, the twelfth bias MOSFET MVB12, the seventh capacitor C7, and the eighth capacitor C8;

[0062] The gate of the fifth MOSFET M5 is connected to the third multiphase input terminal; the drain of the fifth MOSFET M5 is connected to GND; the source of the fifth MOSFET M5 is connected to the drain of the seventh bias MOSFET MVB7; the connection point between the source of the fifth MOSFET M5 and the drain of the seventh bias MOSFET MVB7 is the first output terminal VSP_Q of the Q-path; the gate of the seventh bias MOSFET MVB7 is connected to the first bias voltage input terminal VB1; the source of the seventh bias MOSFET MVB7 is connected to VDD.

[0063] The gate of the sixth MOSFET M6 is connected to the fourth multiphase input terminal; the drain of the sixth MOSFET M6 is connected to GND; the source of the sixth MOSFET M6 is connected to the drain of the eighth bias MOSFET MVB8; the connection point between the source of the sixth MOSFET M6 and the drain of the eighth bias MOSFET MVB8 is the second output terminal VSN_Q of the Q-path; the gate of the eighth bias MOSFET MVB8 is connected to the first bias voltage input terminal VB1; the source of the eighth bias MOSFET MVB8 is connected to VDD.

[0064] The source of the eleventh bias MOSFET MVB11 is connected to GND; the gate of the eleventh bias MOSFET MVB11 is connected to the second bias voltage input terminal VB2; the drain of the eleventh bias MOSFET MVB11 is connected to the source of the seventh MOSFET M7; the connection point between the drain of the eleventh bias MOSFET MVB11 and the source of the seventh MOSFET M7 is the third output terminal VOP_Q of the Q-path; the drain of the seventh MOSFET M7 is connected to the first output terminal VSP_Q of the Q-path; the gate of the seventh MOSFET M7 is connected to the second output terminal VSN_Q; the drain of the ninth bias MOSFET MVB9 is connected to the first output terminal VSP_Q of the Q-path; the source of the ninth bias MOSFET MVB9 is connected to VDD; the gate of the ninth bias MOSFET MVB9 is connected to the zero bias voltage input terminal VB.

[0065] The source of the twelfth bias MOSFET MVB12 is connected to GND; the gate of the twelfth bias MOSFET MVB12 is connected to the second bias voltage input terminal VB2; the drain of the twelfth bias MOSFET MVB12 is connected to the source of the eighth MOSFET M8; the connection point between the drain of the twelfth bias MOSFET MVB12 and the source of the eighth MOSFET M8 is the fourth output terminal VON_Q of the Q-path; the gate of the eighth MOSFET M8 is connected to the first output terminal VSP_Q of the Q-path; the drain of the eighth MOSFET M8 is connected to the second output terminal VSN_Q. Connections: The drain of the tenth bias MOSFET MVB10 is connected to the second output terminal VSN_Q; the gate of the tenth bias MOSFET MVB10 is connected to the zero bias voltage input terminal VB; the source of the tenth bias MOSFET MVB10 is connected to VDD; one end of the seventh capacitor C7 is connected to the first output terminal VSP_Q, and the other end of the seventh capacitor C7 is connected to the second output terminal VSN_Q; one end of the eighth capacitor C8 is connected to the third output terminal VOP_Q of the Q path, and the other end of the eighth capacitor C8 is connected to the fourth output terminal VON_Q of the Q path.

[0066] The fifth MOSFET M5, the sixth MOSFET M6, the seventh bias MOSFET MVB7, the eighth bias MOSFET MVB8, the ninth bias MOSFET MVB9, and the tenth bias MOSFET MVB10 are all P-channel MOSFETs; the seventh MOSFET M7, the eighth MOSFET M8, the eleventh bias MOSFET MVB11, and the twelfth bias MOSFET MVB12 are all N-channel MOSFETs.

[0067] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0068] Please see Figure 1 , Figure 1This is a schematic diagram of a hybrid complex filter circuit structure based on a source follower with high linearity and high image rejection ratio, provided by an embodiment of the present invention. It is characterized by including: an AC coupling I-path, an AC coupling Q-path, a polyphase filter I-path, a polyphase filter Q-path, a power supply voltage VDD, and ground GND.

[0069] In this embodiment, the I-path differential input voltage terminals of the AC coupling circuit include input voltage terminals IIP and IIN, with a phase difference of 180° between input voltage terminals IIP and IIN. The Q-path differential input voltage terminals include input voltage terminals IQP and IQN, with a phase difference of 180° between input voltage terminals IQP and IQN, a phase difference of 90° between input voltage terminals IIP and IQP, and a phase difference of 180° between input voltage terminals IIN and IQN. With a 90° phase difference, the differential positive output terminal VIP_I of the I-path of the AC coupling circuit is connected to the differential positive input terminal VIP_I of the I-path of the multiphase filter; the differential negative output terminal VIN_I of the I-path of the AC coupling circuit is connected to the differential negative input terminal VIN_I of the I-path of the multiphase filter; the differential positive output terminal VIP_Q of the Q-path of the AC coupling circuit is connected to the differential positive input terminal VIP_Q of the Q-path of the multiphase filter; and the differential negative output terminal VIN_Q of the Q-path of the AC coupling circuit is connected to the differential negative input terminal VIN_Q of the Q-path of the multiphase filter.

[0070] In this embodiment, the inputs of the polyphase filter I path are a first polyphase input terminal and a second polyphase input terminal; the outputs of the polyphase filter I path include a first output terminal VSP_I and a second output terminal VSN_I; the first polyphase input terminal is connected to the first positive output terminal VIP_I; the second polyphase input terminal is connected to the first negative output terminal VIN_I; one end of the fourth feedforward capacitor CH4 is connected to the first output terminal VSP_I of the I path; the other end of the fourth feedforward capacitor CH4 is connected to the second negative output terminal VIN_Q; one end of the third feedforward capacitor CH3 is connected to the second output terminal VSN_I of the I path; the other end of the third feedforward capacitor CH3 is connected to the second positive output terminal VIP_Q;

[0071] The multiphase filter I path includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a first bias MOSFET MVB1, a second bias MOSFET MVB2, a third bias MOSFET MVB3, a fourth bias MOSFET MVB4, a fifth bias MOSFET MVB5, a sixth bias MOSFET MVB6, a fifth capacitor C5, and a sixth capacitor C6;

[0072] The first multiphase input terminal is connected to the gate of the first MOSFET M1; the drain of the first MOSFET M1 is connected to GND; the source of the first MOSFET M1 is connected to the source of the first bias MOSFET MVB1; the connection point between the source of the first MOSFET M1 and the source of the first bias MOSFET MVB1 is the first output terminal VSP_I of the I-path; the source of the first bias MOSFET MVB1 is connected to VDD; the gate of the first bias MOSFET MVB1 is connected to the first bias voltage input terminal VB1.

[0073] The second multiphase input terminal is connected to the gate of the second MOSFET M2; the drain of the second MOSFET M2 is connected to VDD; the source of the second MOSFET M2 is connected to the drain of the second bias MOSFET MVB2; the connection point between the source of the second MOSFET M2 and the drain of the second bias MOSFET MVB2 is the second output terminal VSN_I of the I-path; the source of the second bias MOSFET MVB2 is connected to VDD; the gate of the second bias MOSFET MVB2 is connected to the first bias voltage input terminal VB1.

[0074] The source of the fifth bias MOSFET MVB5 is connected to GND; the gate of the fifth bias MOSFET MVB5 is connected to the second bias voltage input terminal VB2; the drain of the fifth bias MOSFET MVB5 is connected to the source of the third MOSFET M3; the connection point between the drain of the fifth bias MOSFET MVB5 and the source of the third MOSFET M3 is the third output terminal VOP_I of the I-path.

[0075] The gate of the third MOSFET M3 is connected to the second output terminal VSN_I of the I-path; the drain of the third MOSFET M3 is connected to the first output terminal VSP_I of the I-path; the drain of the third bias MOSFET MVB3 is connected to the first output terminal VSP_I of the I-path; the gate of the third bias MOSFET MVB3 is connected to the zero bias voltage input terminal VB; the source of the third bias MOSFET MVB3 is connected to VDD.

[0076] The source of the sixth bias MOSFET MVB6 is connected to GND; the gate of the sixth bias MOSFET MVB6 is connected to the second bias voltage input terminal VB2; the drain of the sixth bias MOSFET MVB6 is connected to the source of the fourth MOSFET M4; the connection point between the drain of the sixth bias MOSFET MVB6 and the source of the fourth MOSFET M4 is the fourth output terminal VON_I of the I-path; the gate of the fourth MOSFET M4 is connected to the first output terminal VSP_I of the I-path; the drain of the fourth MOSFET M4 is connected to the second output terminal VSN_I of the I-path; the fourth The drain of bias MOSFET MVB4 is connected to the second output terminal VSN_I of the I-path; the gate of the fourth bias MOSFET MVB4 is connected to the zero bias voltage input terminal VB; the source of the fourth bias MOSFET MVB4 is connected to VDD; one end of the fifth capacitor C5 is connected to the first output terminal VSP_I of the I-path; the other end of the fifth capacitor C5 is connected to the second output terminal VSN_I of the I-path; one end of the sixth capacitor C6 is connected to the third output terminal VOP_I of the I-path; the other end of the sixth capacitor C6 is connected to the fourth output terminal VON_I of the I-path.

[0077] In this embodiment, the first MOSFET M1, the second MOSFET M2, the first bias MOSFET MVB1, the second bias MOSFET MVB2, the third bias MOSFET MVB3, and the fourth bias MOSFET MVB4 are all P-channel MOSFETs; the third MOSFET M3, the fourth MOSFET M4, the fifth bias MOSFET MVB5, and the sixth bias MOSFET MVB6 are all N-channel MOSFETs.

[0078] In this embodiment, the inputs of the Q-path of the polyphase filter are the third polyphase input terminal and the fourth polyphase input terminal; the outputs of the Q-path of the polyphase filter are the first output terminal VSP_Q and the second output terminal VSN_Q; the third polyphase input terminal is connected to the second positive output terminal VIP_Q; the fourth polyphase input terminal is connected to the second negative output terminal VIN_Q; one end of the first feedforward capacitor CH1 is connected to the first output terminal VSP_Q of the Q-path; the other end of the first feedforward capacitor CH1 is connected to the first positive output terminal VIP_I; one end of the second feedforward capacitor CH2 is connected to the second output terminal VSN_Q of the Q-path; the other end of the second feedforward capacitor CH2 is connected to the first negative output terminal VIN_I;

[0079] The multiphase filter Q-path includes a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a seventh bias MOSFET MVB7, an eighth bias MOSFET MVB8, a ninth bias MOSFET MVB9, a tenth bias MOSFET MVB10, an eleventh bias MOSFET MVB11, a twelfth bias MOSFET MVB12, a seventh capacitor C7, and an eighth capacitor C8.

[0080] The gate of the fifth MOSFET M5 is connected to the third multiphase input terminal; the drain of the fifth MOSFET M5 is connected to GND; the source of the fifth MOSFET M5 is connected to the drain of the seventh bias MOSFET MVB7; the connection point between the source of the fifth MOSFET M5 and the drain of the seventh bias MOSFET MVB7 is the first output terminal VSP_Q of the Q-path; the gate of the seventh bias MOSFET MVB7 is connected to the first bias voltage input terminal VB1; the source of the seventh bias MOSFET MVB7 is connected to VDD.

[0081] The gate of the sixth MOSFET M6 is connected to the fourth multiphase input terminal; the drain of the sixth MOSFET M6 is connected to GND; the source of the sixth MOSFET M6 is connected to the drain of the eighth bias MOSFET MVB8; the connection point between the source of the sixth MOSFET M6 and the drain of the eighth bias MOSFET MVB8 is the second output terminal VSN_Q of the Q-path; the gate of the eighth bias MOSFET MVB8 is connected to the first bias voltage input terminal VB1; the source of the eighth bias MOSFET MVB8 is connected to VDD.

[0082] The source of the eleventh bias MOSFET MVB11 is connected to GND; the gate of the eleventh bias MOSFET MVB11 is connected to the second bias voltage input terminal VB2; the drain of the eleventh bias MOSFET MVB11 is connected to the source of the seventh MOSFET M7; the connection point between the drain of the eleventh bias MOSFET MVB11 and the source of the seventh MOSFET M7 is the third output terminal VOP_Q of the Q-path; the drain of the seventh MOSFET M7 is connected to the first output terminal VSP_Q of the Q-path; the gate of the seventh MOSFET M7 is connected to the second output terminal VSN_Q; the drain of the ninth bias MOSFET MVB9 is connected to the first output terminal VSP_Q of the Q-path; the source of the ninth bias MOSFET MVB9 is connected to VDD; the gate of the ninth bias MOSFET MVB9 is connected to the zero bias voltage input terminal VB.

[0083] The source of the twelfth bias MOSFET MVB12 is connected to GND; the gate of the twelfth bias MOSFET MVB12 is connected to the second bias voltage input terminal VB2; the drain of the twelfth bias MOSFET MVB12 is connected to the source of the eighth MOSFET M8; the connection point between the drain of the twelfth bias MOSFET MVB12 and the source of the eighth MOSFET M8 is the fourth output terminal VON_Q of the Q-path; the gate of the eighth MOSFET M8 is connected to the first output terminal VSP_Q of the Q-path; the drain of the eighth MOSFET M8 is connected to the second output terminal VSN_Q. Connections: The drain of the tenth bias MOSFET MVB10 is connected to the second output terminal VSN_Q; the gate of the tenth bias MOSFET MVB10 is connected to the zero bias voltage input terminal VB; the source of the tenth bias MOSFET MVB10 is connected to VDD; one end of the seventh capacitor C7 is connected to the first output terminal VSP_Q, and the other end of the seventh capacitor C7 is connected to the second output terminal VSN_Q; one end of the eighth capacitor C8 is connected to the third output terminal VOP_Q of the Q path, and the other end of the eighth capacitor C8 is connected to the fourth output terminal VON_Q of the Q path.

[0084] In this embodiment, the fifth MOSFET M5, the sixth MOSFET M6, the seventh bias MOSFET MVB7, the eighth bias MOSFET MVB8, the ninth bias MOSFET MVB9, and the tenth bias MOSFET MVB10 are all P-channel MOSFETs; the seventh MOSFET M7, the eighth MOSFET M8, the eleventh bias MOSFET MVB11, and the twelfth bias MOSFET MVB12 are all N-channel MOSFETs.

[0085] In this embodiment, the transconductance values ​​of the first MOSFET M1 and the first MOSFET M2 are... g m1 The transconductance values ​​of the fifth MOSFET M5 and the sixth MOSFET M6 are g m2 The output conductance values ​​of the first MOSFET M1 and the first MOSFET M2 are g ds1 The output conductance values ​​of the fifth MOSFET M5 and the sixth MOSFET M6 are g ds2 The output conductance of the tail current source is... g ds0 The capacitance values ​​of the fifth capacitor C5 and the seventh capacitor C7 are C. 11 The capacitance values ​​of the sixth capacitor C6 and the eighth capacitor C8 are C. 22 The capacitance values ​​of the first feedforward capacitor CH1, the second feedforward capacitor CH2, the third feedforward capacitor CH3, and the fourth feedforward capacitor CH4 are... C H Assuming the output conductance is much smaller than the transconductance, i.e. g ds0-2 <<g m1,2 The transfer function is:

[0086]

[0087] in, It is the voltage difference between the first positive output terminal VIP_I and the first negative output terminal VIN_I, or the voltage difference between the second positive output terminal VIP_Q and the second negative output terminal VIN_Q. It is the voltage difference between the third output terminal VOP_I of the I-path and the fourth output terminal VON_I of the I-path, or the voltage difference between the third output terminal VOP_Q of the Q-path and the fourth output terminal VON_Q of the Q-path. It is a complex frequency variable in the Laplace domain, reflecting the exponential decay and oscillatory characteristics of the signal as it changes over time; the symbol j represents the imaginary unit, used to express the phase and frequency characteristics of the AC signal.

[0088] Clearly, by introducing the first feedforward capacitor CH1, the second feedforward capacitor CH2, the third feedforward capacitor CH3, and the fourth feedforward capacitor CH4, the transfer function of the dual second-order filter introduces a complex notch point. Through capacitance value C H Independent adjustment And without affecting the overall performance of the filter. When g m1 and g m2 Equal and value At that time, complex trap points Low-pass cutoff frequency Quality Factor and DC gain They are respectively:

[0089]

[0090] In this embodiment, the circuit input requires common-mode bias, typically provided by... Figure 1 The AC coupling circuit provided in the circuit also introduces a high-pass characteristic with a cutoff frequency of 1 / RC. Because... Figure 1 The multiphase filter circuit in the circuit has a low-pass function, so the high-pass function of the AC coupling circuit can be cascaded with the LPF to form a band-pass filter (BPF), where the high-pass cutoff frequency is... Less than the low-pass cutoff frequency Therefore, the hybrid complex filter based on the source follower, combined with the AC coupling circuit, can not only suppress image signals but also has frequency selectivity, thereby eliminating the need for a subsequent intermediate frequency filter and offering the advantage of low power consumption.

[0091] Figure 2The figure shows the frequency response simulation results of the hybrid complex filter circuit with high linearity and high image rejection ratio based on a source follower provided in this embodiment of the invention. As can be seen from the figure, the filter not only suppresses the image signal, but also provides frequency selective filtering. The figure shows a passband gain of -1.3dB, a gain in the image band of -47.7dB, and an image rejection ratio (IRR) of 46.4dB, an improvement of approximately 24.5%.

[0092] Figure 3 The figure shows the simulation results of the linearity of the hybrid complex filter circuit based on the source follower with high linearity and high image rejection ratio provided in the embodiment of the present invention. The third-order intermodulation point IIP3 in the figure is 18.1dBm, which is an improvement of about 165%.

[0093] Figure 4 The simulation results of the linearity of the hybrid complex filter circuit based on a source follower with high linearity and high image rejection ratio within the operating frequency provided in this embodiment of the invention show that, within the entire passband of 2-25MHz, the third-order intermodulation point IIP3 first decreases and then increases with increasing frequency. In the worst case, IIP3 is 17.5dBm at a frequency of 9MHz.

[0094] In summary, this embodiment presents a hybrid complex filter circuit based on a source follower, exhibiting high linearity and high image rejection ratio. By employing a source follower structure, it achieves a hybrid function of multiphase and low-pass filtering, demonstrating high linearity and excellent image rejection performance. The third-order intermodulation point (IIP3) is 18.1 dBm, an improvement of approximately 165% compared to the Gm-C structure. Furthermore, this invention introduces an AC coupling circuit with high-pass characteristics to provide the input bias voltage, while simultaneously combining it with the low-pass characteristics of complex filtering to achieve bandpass functionality. This eliminates the need for an intermediate frequency filter in subsequent circuits, reducing power consumption by approximately 30%. Moreover, the hybrid complex filter based on a source follower proposed in this invention can be widely used in wireless communication chips, demonstrating broad applicability.

Claims

1. A source follower based high linearity high image rejection ratio hybrid complex filter circuit characterized by: The AC coupling circuit, the multi-phase filter circuit, the first feedforward capacitor, the second feedforward capacitor, the third feedforward capacitor and the fourth feedforward capacitor are included. The input of the AC coupling circuit includes a first input voltage terminal, a second input voltage terminal, a third input voltage terminal and a fourth input voltage terminal; the output of the AC coupling circuit includes a first positive output terminal, a first negative output terminal, a second positive output terminal and a second negative output terminal; the phase of the first input voltage terminal and the phase of the second input voltage terminal are 180 degrees apart; the phase of the third input voltage terminal and the phase of the fourth input voltage terminal are 180 degrees apart; the phase of the first input voltage terminal and the phase of the third input voltage terminal are 90 degrees apart; the phase of the second input voltage terminal and the phase of the fourth input voltage terminal are 90 degrees apart; The multi-phase filter circuit includes a multi-phase filter I channel and a multi-phase filter Q channel; The input of the multi-phase filter I channel is a first multi-phase input terminal and a second multi-phase input terminal; the output of the multi-phase filter I channel includes an I channel first output terminal and an I channel second output terminal; the first multi-phase input terminal is connected with the first positive output terminal; The second multi-phase input terminal is connected with the first negative output terminal; One end of the fourth feedforward capacitor is connected with the I channel first output terminal; the other end of the fourth feedforward capacitor is connected with the second negative output terminal; One end of the third feedforward capacitor is connected with the I channel second output terminal; the other end of the third feedforward capacitor is connected with the second positive output terminal; The input of the multi-phase filter Q channel is a third multi-phase input terminal and a fourth multi-phase input terminal; the output of the multi-phase filter Q channel is a Q channel first output terminal and a Q channel second output terminal; the third multi-phase input terminal is connected with the second positive output terminal; the fourth multi-phase input terminal is connected with the second negative output terminal; One end of the first feedforward capacitor is connected with the Q channel first output terminal; the other end of the first feedforward capacitor is connected with the first positive output terminal; One end of the second feedforward capacitor is connected with the Q channel second output terminal; the other end of the second feedforward capacitor is connected with the first negative output terminal; The AC coupling circuit is used to isolate the AC component of the input signal from the common mode bias of the front stage of the filter circuit, so that the filter circuit can independently establish and maintain the required common mode operating point; By connecting the capacitor in series in the signal path, the AC coupling circuit introduces a high-pass characteristic with a cut-off frequency of 1 / RC while blocking DC and very low frequency components, so that the input end of the multi-phase filter circuit already has the ability to suppress low frequency and DC interference before entering the multi-phase filter circuit; Since the multi-phase filter itself presents a low-pass response, the high-pass AC coupling circuit and the low-pass multi-phase filter circuit are combined with each other, thereby forming a band-pass filter as a whole. The polyphase filter circuit utilizes the first-order low-pass performance of the polyphase filter circuit and the first-order high-pass performance of the feedforward capacitor: the polyphase filter circuit lags the phase of the input signal by 45° at the cutoff frequency, and the feedforward capacitor leads the phase of the input signal by 45° at the cutoff frequency; the polyphase filter I channel utilizes the first-order low-pass phase-frequency characteristic of signal transmission from the first positive output end to the I channel first output end and the first-order high-pass phase-frequency characteristic of signal transmission from the Q channel first output end to the first positive output end: the phase of the signal from the first positive output end to the I channel first output end lags by 45°, and the phase of the signal from the Q channel first output end to the first positive output end leads by 45°; the polyphase filter Q channel utilizes the first-order low-pass phase-frequency characteristic of signal transmission from the second positive output end to the Q channel first output end and the first-order high-pass phase-frequency characteristic of signal transmission from the I channel second output end to the second positive output end: the phase of the signal from the second positive output end to the Q channel first output end lags by 45°, and the phase of the signal from the I channel second output end to the second positive output end leads by 45°.

2. The source follower based high linearity high image rejection ratio hybrid complex filter circuit of claim 1, wherein, The AC coupling circuit includes an AC coupling I channel and an AC coupling Q channel; The AC coupling I channel includes a first capacitor, a second capacitor, a first resistor and a second resistor; one end of the first capacitor is connected with a first input voltage terminal; the other end of the first capacitor is connected with one end of the first resistor and the first positive output end respectively; the other end of the first resistor is connected with a common-mode input voltage; one end of the second capacitor is connected with a second input voltage terminal; the other end of the second capacitor is connected with the first negative output end and one end of the second resistor respectively; The other end of the second resistor is connected with the common-mode input voltage; The resistance value of the first resistor is equal to the resistance value of the second resistor; the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor; The AC coupling Q channel includes a third capacitor, a fourth capacitor, a third resistor and a fourth resistor; one end of the third capacitor is connected with a third input voltage terminal; the other end of the third capacitor is connected with the second positive output end and one end of the third resistor respectively; The other end of the third resistor is connected with the common-mode input voltage; one end of the fourth capacitor is connected with a fourth input voltage terminal; the other end of the fourth capacitor is connected with the second negative output end and one end of the fourth capacitor respectively; the other end of the fourth capacitor is connected with the common-mode input voltage; The resistance value of the third resistor is equal to the resistance value of the fourth resistor; the capacitance value of the third capacitor is equal to the capacitance value of the fourth capacitor.

3. The source follower based high linearity high image rejection ratio hybrid complex filter circuit of claim 1, wherein, The polyphase filter I channel includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first biasing MOS transistor, a second biasing MOS transistor, a third biasing MOS transistor, a fourth biasing MOS transistor, a fifth biasing MOS transistor, a sixth biasing MOS transistor, a fifth capacitor and a sixth capacitor; The first polyphase input terminal is connected with the gate of the first MOS transistor; the drain of the first MOS transistor is connected with GND; the source of the first MOS transistor is connected with the source of the first biasing MOS transistor; The connection point of the source of the first MOS transistor and the source of the first biasing MOS transistor is the I channel first output end; The source of the first biasing MOS transistor is connected with VDD; the gate of the first biasing MOS transistor is connected with a first biasing voltage input terminal; The second polyphase input end is connected with the gate of the second MOS tube; the drain of the second MOS tube is connected with VDD; the source of the second MOS tube is connected with the drain of the second biasing MOS tube; and the connection point of the source of the second MOS tube and the drain of the second biasing MOS tube is the second output end of the I channel; The source of the second biasing MOS tube is connected with VDD; The gate of the second biasing MOS tube is connected with the first biasing voltage input end; The source of the fifth biasing MOS tube is connected with GND; The gate of the fifth biasing MOS tube is connected with the second biasing voltage input end; The drain of the fifth biasing MOS tube is connected with the source of the third MOS tube; and the connection point of the drain of the fifth biasing MOS tube and the source of the third MOS tube is the third output end of the I channel; The gate of the third MOS tube is connected with the second output end of the I channel; the drain of the third MOS tube is connected with the first output end of the I channel; the drain of the third biasing MOS tube is connected with the first output end of the I channel; the gate of the third biasing MOS tube is connected with the zero biasing voltage input end; and the source of the third biasing MOS tube is connected with VDD; The source of the sixth biasing MOS tube is connected with GND; The gate of the sixth biasing MOS tube is connected with the second biasing voltage input end; the drain of the sixth biasing MOS tube is connected with the source of the fourth MOS tube; the connection point of the drain of the sixth biasing MOS tube and the source of the fourth MOS tube is the fourth output end of the I channel; the gate of the fourth MOS tube is connected with the first output end of the I channel; the drain of the fourth MOS tube is connected with the second output end of the I channel; the drain of the fourth biasing MOS tube is connected with the second output end of the I channel; the gate of the fourth biasing MOS tube is connected with the zero biasing voltage input end; and the source of the fourth biasing MOS tube is connected with VDD; One end of the fifth capacitor is connected with the first output end of the I channel; The other end of the fifth capacitor is connected with the second output end of the I channel; one end of the sixth capacitor is connected with the third output end of the I channel; and the other end of the sixth capacitor is connected with the fourth output end of the I channel.

4. The source follower based high linearity high image rejection ratio hybrid complex filter circuit of claim 3, wherein, The first MOS tube, the second MOS tube, the first biasing MOS tube, the second biasing MOS tube, the third biasing MOS tube and the fourth biasing MOS tube are all P-channel MOS tubes; and the third MOS tube, the fourth MOS tube, the fifth biasing MOS tube and the sixth biasing MOS tube are all N-channel MOS tubes.

5. The source follower based high linearity high image rejection ratio hybrid complex filter circuit of claim 1, wherein, The polyphase filter Q channel comprises a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a seventh biasing MOS tube, an eighth biasing MOS tube, a ninth biasing MOS tube, a tenth biasing MOS tube, an eleventh biasing MOS tube, a twelfth biasing MOS tube, a seventh capacitor and an eighth capacitor; The gate of the fifth MOS tube is connected with the third polyphase input end; and the drain of the fifth MOS tube is connected with GND; The source of the fifth MOS tube is connected with the drain of the seventh biasing MOS tube; and the connection point of the source of the fifth MOS tube and the drain of the seventh biasing MOS tube is the first output end of the Q channel; The gate of the seventh biasing MOS tube is connected with the first biasing voltage input end; and the source of the seventh biasing MOS tube is connected with VDD; The gate of the seventh biasing MOS tube is connected with the first biasing voltage input end; and the source of the seventh biasing MOS tube is connected with VDD; The gate of the sixth MOS tube is connected with the fourth multiphase input end; the drain of the sixth MOS tube is connected with GND; the source of the sixth MOS tube is connected with the drain of the eighth biasing MOS tube; and the connection point of the source of the sixth MOS tube and the drain of the eighth biasing MOS tube is the second output end of the Q channel; The gate of the eighth biasing MOS tube is connected with the first biasing voltage input end; and the source of the eighth biasing MOS tube is connected with VDD. The source of the eleventh biasing MOS tube is connected with GND; the gate of the eleventh biasing MOS tube is connected with the second biasing voltage input end; the drain of the eleventh biasing MOS tube is connected with the source of the seventh MOS tube; the connection point of the drain of the eleventh biasing MOS tube and the source of the seventh MOS tube is the third output end of the Q channel; the drain of the seventh MOS tube is connected with the first output end of the Q channel; the gate of the seventh MOS tube is connected with the second output end; the drain of the ninth biasing MOS tube is connected with the first output end of the Q channel; and the source of the ninth biasing MOS tube is connected with VDD. The gate of the ninth biasing MOS tube is connected with the zeroth biasing voltage input end; The source of the twelfth biasing MOS tube is connected with GND; the gate of the twelfth biasing MOS tube is connected with the second biasing voltage input end; the drain of the twelfth biasing MOS tube is connected with the source of the eighth MOS tube; the connection point of the drain of the twelfth biasing MOS tube and the source of the eighth MOS tube is the fourth output end of the Q channel; the gate of the eighth MOS tube is connected with the first output end of the Q channel; the drain of the eighth MOS tube is connected with the second output end; the drain of the tenth biasing MOS tube is connected with the second output end; the gate of the tenth biasing MOS tube is connected with the zeroth biasing voltage input end; the source of the tenth biasing MOS tube is connected with VDD; one end of the seventh capacitor is connected with the first output end, and the other end of the seventh capacitor is connected with the second output end; one end of the eighth capacitor is connected with the third output end of the Q channel, and the other end of the eighth capacitor is connected with the fourth output end of the Q channel.

6. The source follower based high linearity high image rejection ratio hybrid complex filter circuit of claim 5, wherein, The fifth MOS tube, the sixth MOS tube, the seventh biasing MOS tube, the eighth biasing MOS tube, the ninth biasing MOS tube and the tenth biasing MOS tube are all P-channel MOS tubes; and the seventh MOS tube, the eighth MOS tube, the eleventh biasing MOS tube and the twelfth biasing MOS tube are all N-channel MOS tubes.

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