Multi-channel cameralink digital image fiber optic transmission system for airborne optoelectronic pods

Abstract

The present application relates to the technical field of photoelectric data transmission, and particularly relates to a multi-channel Cameralink digital image fiber transmission system for an aerial photoelectric pod. The system comprises an image data sending unit, a fiber slip ring and an image data receiving unit connected in sequence. The image data sending unit and the image data receiving unit both take FPGA as a core processor, and realize one-way transmission of optical signals through the fiber slip ring. The image data sending unit is used for receiving multi-channel Cameralink digital image signals, converting the signals into optical signals through serial-parallel conversion and time-division encoding, and sending the optical signals to the fiber slip ring. The image data receiving unit is used for receiving optical signals transmitted by the fiber slip ring, converting the optical signals into Cameralink digital image signals through photoelectric conversion and decoding reconstruction, and outputting the Cameralink digital image signals, so as to realize lossless and transparent transmission of multi-channel image signals. The system has the advantages of realizing lossless transmission of multi-channel Cameralink images through optical fibers, simple structure and high stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photoelectric data transmission, and in particular to a multi-channel Cameralink digital image fiber transmission system for an aerial photoelectric pod. BACKGROUND

[0002] The aerial photoelectric pod, as an important reconnaissance equipment on board, has been widely applied in the fields of target capturing, tracking, identification, etc. The tracking and identification of the aerial photoelectric pod are realized through real-time processing of high-reliability images, and thus the high-speed and reliable image transmission is one of the important factors affecting the performance index. The traditional aerial photoelectric pod mostly adopts a conductive ring to directly transmit Cameralink digital images, and has problems of low transmission bandwidth, poor anti-interference performance, complex wiring, etc. With the development of technology, a Cameralink digital image fiber transmission scheme based on MAX9295 / MAX9296 has appeared, but the flexibility is not strong and the transmission bandwidth is limited. With the continuous development of the aerial photoelectric pod technology and the requirements of multi-source image cooperative reconnaissance and other functional indexes, the aerial photoelectric pod has higher and higher requirements for the bandwidth of image data transmission. SUMMARY

[0003] The present application provides a multi-channel Cameralink digital image fiber transmission system for an aerial photoelectric pod to solve the above problems.

[0004] The present application aims to provide a multi-channel Cameralink digital image fiber transmission system for an aerial photoelectric pod, which comprises an image data sending unit, a fiber slip ring and an image data receiving unit connected in sequence; the image data sending unit and the image data receiving unit both take FPGA as the core processor, and realize one-way transmission of optical signals through the fiber slip ring.

[0005] The image data sending unit is used for receiving multi-channel Cameralink digital image signals, converting the signals into optical signals through serial-parallel conversion and time-division encoding, and sending the optical signals to the fiber slip ring.

[0006] The image data receiving unit is used for receiving the optical signals transmitted by the fiber slip ring, converting the signals into Cameralink digital image signals through photoelectric conversion and decoding reconstruction, and outputting the signals to realize lossless and transparent transmission of multi-channel image signals.

[0007] Preferably, the sending end of the image data sending unit receives multiple LVDS format CameraLink digital image signals, the FPGA calls the built-in ISERDES serial deserializer IP core, converts each serial LVDS signal into a 28-bit parallel signal, stores the multiple parallel data in the internal storage unit, encodes the multiple data in the storage unit according to the Aurora 8B / 10B protocol, and then transmits the encoded data to the sending optical module, and connects the optical signal to the receiving end of the image data receiving unit through the optical fiber slip ring.

[0008] Preferably, the 28-bit parallel signal includes 24-bit image data, 1-bit pixel clock, 1-bit frame synchronization signal and 2-bit line field synchronization signal.

[0009] Preferably, the time division encoding specifically includes: taking the frame synchronization signal of one of the CameraLink digital image signals as a reference, allocating independent time slices for the multiple parallel data in the line valid transmission phase of each image, and the time slice length is positively correlated with the number of valid pixels of the corresponding number of images, so as to avoid the transmission conflict of the multiple data.

[0010] Preferably, the optical module of the image data receiving unit receives the optical signal transmitted by the optical fiber slip ring, converts the optical signal into an electrical signal and inputs the electrical signal into the FPGA, the FPGA decodes the electrical signal according to the Aurora 8B / 10B protocol, stores the decoded multiple data in the storage unit in the FPGA, and the FPGA divides the multiple data according to the number of identification bits, and respectively reconstructs the 28-bit CameraLink parallel data. The FPGA calls the built-in OSERDES hard core IP core to convert the reconstructed 28-bit parallel data into the LVDS format CameraLink digital image signal and output the signal.

[0011] Preferably, the number of identification bits is 1-bit binary identification, which is added to the protocol frame header of each data in the time division encoding phase by the image data sending unit, and the image data receiving unit realizes the division and reconstruction of the multiple data by identifying the identification bit.

[0012] Preferably, the optical fiber slip ring is a multi-channel expanded beam photoelectric combined slip ring, which supports 360° continuous rotation transmission.

[0013] Compared with the prior art, the present application can achieve the following beneficial effects:

[0014] To meet the high reliability and high bandwidth requirements of Cameralink digital image transmission for aviation optoelectronic pods, this invention proposes a multi-channel Cameralink digital image fiber optic transmission system for aviation optoelectronic pods. It employs a fiber optic transmission scheme with an FPGA as the core processor. The FPGA's powerful reconfigurability gives this invention strong flexibility, allowing for programmatic control of the Cameralink image transmission bandwidth. Furthermore, the transmitting and receiving ends are interconnected via an optical link, improving the reliability and bandwidth of data transmission. Attached Figure Description

[0015] Figure 1 This is a structural diagram of a multi-channel Cameralink digital image fiber optic transmission system for an aviation optoelectronic pod, provided according to an embodiment of the present invention.

[0016] Figure 2 This is a transmitter test provided according to an embodiment of the present invention. Figure 1 Data transmission test results diagram.

[0017] Figure 3 This is a receiver test provided according to an embodiment of the present invention. Figure 1 Data transmission test results diagram.

[0018] Figure 4 This is a transmitter test provided according to an embodiment of the present invention. Figure 2 Data transmission test results diagram.

[0019] Figure 5 This is a receiver test provided according to an embodiment of the present invention. Figure 2 Data transmission test results diagram.

[0020] Figure 6 This is a data transmission result display diagram provided according to an embodiment of the present invention; (a) indicates the sending end test. Figure 1 (b) indicates the sending end test. Figure 2 (c) indicates receiver testing Figure 1 (d) indicates receiver testing. Figure 2 . Detailed Implementation

[0021] In the following description, embodiments of the invention will be described with reference to the accompanying drawings. In the description below, the same modules are denoted by the same reference numerals. Where the same reference numerals are used, their names and functions are also the same. Therefore, their detailed description will not be repeated.

[0022] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not constitute a limitation on the present application.

[0023] The present application provides a multi-channel Cameralink digital image fiber transmission system for an aerial optoelectronic pod, comprising: an image data sending unit, an image data receiving unit and a fiber slip ring connecting the image data sending unit and the image data receiving unit; the image data sending unit and the image data receiving unit both take FPGA as a core processor, and realize one-way transmission of optical signals through the fiber slip ring;

[0024] The image data sending unit is used for receiving multi-channel Cameralink digital image signals, converting the signals into optical signals after serial-parallel conversion and time division encoding, and sending the optical signals to the fiber slip ring; the image data receiving unit is used for receiving optical signals transmitted by the fiber slip ring, restoring the signals into Cameralink digital image signals after photoelectric conversion and decoding reconstruction, and outputting the signals, thereby realizing lossless transparent transmission of multi-channel image signals.

[0025] Specifically, the image data sending unit comprises a Cameralink signal receiving module, a serial-parallel conversion module, a time division encoding module and an optical module;

[0026] The Cameralink signal receiving module receives multi-channel LVDS format Cameralink digital image signals, and the Cameralink digital image signals comprise image data, a pixel clock signal, a frame synchronization signal and a line field synchronization signal;

[0027] The serial-parallel conversion module is an ISERDES serial deserializer built in FPGA, which converts each channel of serial Cameralink digital image signals into 28-bit parallel signals, and the 28-bit parallel signals comprise 24-bit image data, 1-bit pixel clock, 1-bit frame synchronization signal and 2-bit line field synchronization signal;

[0028] The time division encoding module is a built-in logic module of FPGA, which schedules multi-channel parallel data according to a preset time slice allocation rule based on the line field synchronization signals of each channel of images, so as to avoid transmission conflicts, and then encodes the data through an Aurora 8B / 10B protocol;

[0029] The optical module receives the encoded electrical signals and converts them into optical signals, which are sent through the fiber slip ring.

[0030] Specifically, the image data receiving unit comprises an optical module, a decoding module, an image reconstruction module and a Cameralink signal output module;

[0031] The optical module receives the optical signal transmitted by the fiber optic slip ring and converts it into an electrical signal;

[0032] The decoding module is a built-in logic module of the FPGA, decodes the electrical signal according to the Aurora 8B / 10B protocol, and buffers the decoded data to the internal storage unit of the FPGA;

[0033] The image reconstruction module is a built-in logic module of the FPGA, which reconstructs the buffered data according to the identification information of the multi-channel image, and restores it to the corresponding Cameralink parallel data.

[0034] The Cameralink signal output module is a built-in OSERDES serializer of the FPGA, which converts the parallel data into Cameralink digital image signals in LVDS format and outputs them.

[0035] Specifically, the fiber optic slip ring is a multi-channel beam expansion type photoelectric combination slip ring, which supports 360° rotation transmission and can simultaneously transmit optical signals and low-frequency electrical signals, avoiding data line winding and reducing the installation space occupation of the aerial photoelectric pod.

[0036] In some embodiments, the image data sending unit is configured to receive multi-channel Cameralink digital image signals, convert them into optical signals after serial-parallel conversion and time division encoding, and send them to the fiber optic slip ring; the specific implementation is as follows:

[0037] The sending end of the image data sending unit receives at least two Cameralink digital image signals, which are all in low-voltage differential signal (LVDS) format (in accordance with the Cameralink Base mode specification); the FPGA calls the built-in ISERDES serial deserializer IP core to convert each serial LVDS signal into a 28-bit parallel signal; the multi-channel parallel data is buffered to the internal storage unit, and the multi-channel data in the storage unit is time-division encoded according to the Aurora 8B / 10B protocol (a link layer protocol developed by Xilinx) and transmitted to the sending optical module; the optical signal is transmitted to the receiving end of the image data receiving unit through the fiber optic slip ring in the aerial pod.

[0038] The 28-bit parallel signal includes 24-bit image data, 1-bit pixel clock, 1-bit frame synchronization signal, and 2-bit line field synchronization signal.

[0039] The time-division encoding specifically includes: taking the frame synchronization signal of one of the Cameralink digital image signals as a reference, allocating independent time slices to the multi-channel parallel data during the line effective transmission phase of each frame of image, and the time slice length is positively correlated with the number of line effective pixels of the corresponding number of images, avoiding multi-channel data transmission conflicts.

[0040] In some embodiments, the image data receiving unit is used to receive the optical signal transmitted by the fiber slip ring, and after photoelectric conversion and decoding reconstruction, the Cameralink digital image signal is restored and output, realizing lossless transparent transmission of multiple image signals; the specific implementation is as follows:

[0041] Photoelectric conversion and decoding: the optical module of the image data receiving unit receives the optical signal transmitted by the fiber slip ring, converts it into an electrical signal and inputs it into the FPGA; the FPGA calls the Aurora 8B / 10B protocol to decode the electrical signal, and simultaneously realizes preliminary error detection through the CRC check function of the protocol.

[0042] Data buffering and image reconstruction: the decoded multiple data is buffered to the storage unit inside the FPGA, and the FPGA splits the two-way data according to the number of identification bits, and respectively reconstructs 28-bit Cameralink parallel data;

[0043] The number of identification bits is one binary identification bit, which is added to the protocol frame header of each way of data by the image data sending unit in the time-division encoding stage, and the image data receiving unit realizes the splitting and reconstruction of multiple data by identifying the identification bit.

[0044] Parallel-to-serial conversion and signal output: the FPGA calls the built-in output parallel-to-serial serializer (OSERDES) hard core IP core to convert the reconstructed 28-bit parallel data into Cameralink digital image signal in LVDS format and output.

[0045] Embodiment 1

[0046] Referring to Figure 1 , the embodiment provides a multi-channel Cameralink digital image fiber transmission system for an aerial optoelectronic pod, which comprises an image data sending unit, an image data receiving unit and a fiber slip ring connecting the two; both the sending end and the receiving end use FPGA as the core processor, combined with the optical module and the fiber slip ring, to realize high-speed and high-reliability transmission of multiple Cameralink digital images; wherein the optical module is integrated in the image data sending unit and the image data receiving unit respectively: the optical module of the sending end receives the encoded electrical signal output by the FPGA to complete the electrical-optical conversion; the optical module of the receiving end receives the optical signal transmitted by the fiber slip ring to complete the optical-electrical conversion, which is the core hardware for mutual conversion of optical signals and electrical signals.

[0047] The specific implementation method of the image data sending unit is as follows:

[0048] Cameralink signal receiving and serial-parallel conversion: the transmitting end receives at least two Cameralink digital image signals, which are all in low-voltage differential signal (LVDS) format (in line with the Cameralink Base mode specification); the FPGA calls the built-in ISERDES serial deserializer IP core to convert each serial LVDS signal into a 28-bit parallel signal; the 28-bit parallel signal contains 24-bit image data, 1-bit pixel clock, 1-bit frame synchronization signal, and 2-bit line field synchronization signal;

[0049] Data buffering and time-division encoding: two storage units are configured inside the FPGA to buffer two parallel data respectively, solving the cross-clock domain matching problem of multiple images.

[0050] Time-division encoding timing rules: based on the Aurora 8B / 10B protocol IP core, frame-level synchronization and line-level time slice allocation rules are adopted: (1) frame synchronization reference: taking the frame synchronization signal of the test Figure 1 as the time-division encoding reference, the time-division period of the two images is aligned with the frame period, avoiding cross-frame data disorder; (2) time slice allocation: in the line valid transmission phase of each frame image, the time slice is dynamically allocated according to the pixel amount of the two images, and the time slice length is calculated and adjusted in real time by the internal counter of the FPGA (based on the pixel clock period); (3) identification bit addition: 1-bit number identification bit is added to each data during encoding (test Figure 1 corresponds to "0", and test Figure 2 corresponds to "1"), providing a basis for the receiving end.

[0051] Conflict avoidance mechanism: in terms of timing, the line synchronization signal of the test Figure 1 is triggered, and only one-way buffered data is read in the same time slice, and the two-way transmission is completely staggered in the time axis; in terms of protocol, even if there is an extreme timing deviation, the number identification bit can avoid data confusion and eliminate transmission conflicts.

[0052] Optoelectronic conversion and transmission: the encoded electrical signal is input into the optical module to be converted into an optical signal, which is transmitted to the receiving end through the optical fiber slip ring (supporting 360° rotation transmission) in the aerial optoelectronic pod.

[0053] The specific implementation method of the image data receiving unit is as follows:

[0054] Optoelectronic conversion and decoding: the optical module of the receiving end receives the optical signal transmitted by the optical fiber slip ring, converts it into a 10 Gb / s electrical signal, and inputs it into the FPGA; the FPGA calls the Aurora 8B / 10B protocol IP core to decode the electrical signal, and simultaneously realizes preliminary error detection through the CRC check function of the protocol.

[0055] Data buffer and image reconstruction: the decoded multi-channel data is buffered to the storage unit inside the FPGA, and the FPGA splits the two channels of data according to the channel identification bit, and reconstructs them into 28-bit CameraLink parallel data respectively.

[0056] Parallel-to-serial conversion and signal output: the FPGA calls the built-in output parallel-to-serial serializer (OSERDES) hard core IP core to convert the reconstructed 28-bit parallel data into LVDS format CameraLink digital image signals, and outputs them to the image acquisition card (such as NIPCIe-1430) for display and verification.

[0057] In this embodiment, two channels of 30hz test images are generated in the FPGA inside the sending end to simulate the actual CameraLink camera, and the regular variation of the test image data is tested. Figure 1 The size is 1024 768, each pixel is composed of 8-bit RGB components. The value of each row of image pixels changes the same, and the RGB components of the first pixel of each row of image are all from 0, and the RGB components of each subsequent pixel are sequentially added by 1; test Figures 2-5 The size is 640 512, each pixel has a bit width of 8 bits, and each row of pixels changes the same as the test Figure 1 . By writing a bit error rate detection module, the data bit error rate of the receiving end is detected. Since the pixels at each position of the test image are fixed, it is only necessary to traverse whether the pixel values of each frame of image match the generated test image pixel values, and count the number of unmatched pixels to obtain the bit error rate of each frame of image. Through the integrated logic analyzer (ILA) inside the FPGA, the test image data before and after the fiber transmission is analyzed, and the experimental results as shown in Figures 2-5 are obtained. The test image data of the two-channel video receiving end is exactly the same as that of the sending end, so it can be seen that the data received by the receiving end of the system is correct, and the 2-way image data transmission can be normally carried out. Through 30 minutes of monitoring, a total of 1.4x10 12 bit data is transmitted, and the counting results of the two-way bit error rate detection modules are both 0, and no error is found. It can be known that the bit error rate of the system is lower than 10 -12 .

[0058] In the receiving end of the fiber transmission system of the present application, the image acquisition card is used to collect and display the two-way test images, and the images before and after the test image transmission are as shown in Figure 6 . It can be known from the comparison of the original images of the two-way test images and the images after the fiber transmission that the images after the transmission are clear and stable.

[0059] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps recited in the present disclosure can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present disclosure are achieved, which are not limited herein.

[0060] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A multi-lane Cameralink digital image fiber optic transmission system for an airborne electro-optical pod, comprising: The application relates to a kind of optical fiber slip rings, which are connected to image data sending units and image data receiving units in sequence. The image data sending unit is used to receive multiple Cameralink digital image signals, which are converted into optical signals after serial-parallel conversion and time-division encoding and then sent to the optical fiber slip ring. The image data receiving unit is used to receive optical signals transmitted by the optical fiber slip ring, which are converted into Cameralink digital image signals after photoelectric conversion and decoding and then outputted, so as to realize lossless and transparent transmission of multiple image signals.

2. A multi-channel Camera Link digital image fiber optic transmission system for an airborne electro-optical pod according to claim 1, characterized in that: The 28-bit parallel signal includes 24-bit image data, 1-bit pixel clock, 1-bit frame synchronization signal and 2-bit line field synchronization signal.

3. A multi-channel Camera Link digital image fiber optic transmission system for an airborne electro-optical pod according to claim 2, wherein: The optical module of the image data receiving unit receives optical signals transmitted by the optical fiber slip ring, converts them into electrical signals and inputs them into the FPGA.

4. A multi-channel Camera Link digital image fiber optic transmission system for an airborne electro-optical pod according to claim 1, wherein: The decoded multiple data are buffered in the storage unit inside the FPGA, and the FPGA divides the multiple data according to the number of channels and reconstructs them into 28-bit Cameralink parallel data. The number of channel identification bits is one binary identification bit, which is added to the protocol frame header of each channel of data by the image data sending unit in the time-division encoding stage, and the image data receiving unit realizes the division and reconstruction of the multiple data by identifying the identification bit.

5. A multi-channel Camera Link digital image fiber optic transmission system for an airborne electro-optical pod according to claim 4, wherein: ​

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