Implementation method, device and equipment for MiniOLT uplink GEM multi-chip splicing and medium
By configuring an independent FIFO storage structure for each ONU, the fragmentation status maintenance of MiniOLT devices is simplified, the problems of complex memory copying and status maintenance are solved, and low-latency, high-efficiency GEM frame splicing is achieved, which is suitable for FTTR scenarios.
Patent Information
- Application Number
- CN202511419610.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2026-01-09
AI Technical Summary
Traditional MiniOLT devices suffer from complex memory copying and fragment state maintenance issues in FTTR scenarios, resulting in extended processing time and high FPGA resource consumption.
An independent buffer splicing method is adopted, with an ONUi_GEM_FIFO configured to store the GEM frame payload for each ONU, and a smaller ONUi_PLI_FIFO allocated to each ONU to store the GEM frame length information. The parsing, storage and splicing of GEM frames are realized through FPGA.
It simplifies the maintenance of fragmentation status and achieves low-latency, high-efficiency GEM frame splicing processing, making it particularly suitable for MiniOLT devices in FTTR scenarios.
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Figure CN121310001A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of optical fiber communication, and in particular to a MiniOLT uplink GEM multi-piece splicing implementation method, device, equipment and medium. BACKGROUND
[0002] GPON (Gigabit-capable Passive Optical Networks) is a kind of bandwidth access technology based on optical fiber. The GPON transmission frame structure is GTC (GPON Transmission Convergence) frame, and the GEM (GPON Encapsulation Mode) frame is directly nested in the payload of the GTC frame to carry service data. In the current optical fiber communication field, especially in the FTTR (Fiber to the Room) scene, although there are mature special PON chips on the market, such chips have significant limitations in dealing with the flexible deployment, protocol evolution and customization needs of FTTR.
[0003] Although in the FTTR (Fiber to the Room) scene, the FPGA+ARM architecture can realize more flexible protocol processing; when the ONU uplink bandwidth is insufficient, the GEM frame needs to be fragmented for transmission, and the MiniOLT needs to splice these fragments into complete frames. The MiniOLT needs to recombine the fragmented GEM frames from the same ONU into complete data packets in order, otherwise the upper layer service cannot parse the fragmented data. The traditional recombination method has two major bottlenecks: 1) multiple memory copies: the fragmented cache is stored in different buffer areas, and needs to be moved during recombination, increasing the time delay; 2) complex fragmented state maintenance: the Gem-Port-ID, PLI, PTI fragmented state needs to be tracked during splicing, occupying a large amount of FPGA resources. Therefore, the traditional method has the problems of multiple memory copies and complex fragmented state maintenance, resulting in long processing delay and large FPGA resource occupation.
[0004] In order to solve the above technical problems, the present application provides a MiniOLT uplink GEM multi-piece splicing implementation method, device, equipment and medium. SUMMARY
[0005] Therefore, the purpose of the present application is to provide a MiniOLT uplink GEM multi-piece splicing implementation method, device, equipment and medium to solve the problems of memory copying and state maintenance complexity in the traditional method.
[0006] In order to achieve the above object, the application provides a FPGA implementation method of MiniOLT uplink GEM multi-piece splicing based on GPON protocol, which comprises the following steps:
[0007] GEM frame analysis step: GEM frame header and GEM load are parsed from the uplink GTC frame;
[0008] GEM load storage step: according to the Port-ID in the GEM frame header, the GEM load is written into the independent ONUi_GEM_FIFO corresponding to the ONU, wherein i is 1, 2, 3, …;
[0009] Frame length processing step: according to the PTI in the GEM frame header, whether it is a tail frame, if it is not a tail frame, the PLI value is latched, if it is a tail frame, the accumulated PLI value is stored in the independent ONUi_PLI_FIFO corresponding to the ONU;
[0010] Complete frame output step: polling the independent ONUi_PLI_FIFO corresponding to each ONU, if it is not empty, the PLI value is read out, and the data of corresponding length from the ONUi_GEM_FIFO corresponding to each ONU is read as a complete service package to output to the upper layer.
[0011] Preferably, in the GEM load storage step, an ONUi_GEM_FIFO is independently configured for each ONU, which is used for storing all GEM load data in the receiving order and is not affected by the fragmentation.
[0012] Preferably, the frame length processing step comprises:
[0013] If the PTI indicates that the current GEM frame is not a tail frame, the PLI value of the GEM frame is latched;
[0014] If the PTI indicates that the current GEM frame is a tail frame, the previously latched PLI value and the PLI value of the current tail frame are accumulated to obtain the total length of the complete GEM frame, and the total length value is stored in the corresponding ONUi_PLI_FIFO.
[0015] Further preferably, the depth of the ONUi_PLI_FIFO is much smaller than the depth of the ONUi_GEM_FIFO, and is only used for storing the length information of the complete GEM frame.
[0016] Preferably, the complete frame output step adopts a polling mode to check the ONUi_PLI_FIFO state of each ONU in turn, if the ONUi_PLI_FIFO is not empty, the complete frame output of the ONU is preferentially processed.
[0017] Preferably, the method is implemented in an FPGA, and the ONUi_GEM_FIFO and the ONUi_PLI_FIFO are both implemented using internal memory resources of the FPGA.
[0018] To achieve the above object, the application further provides a device for implementing the method described in any of the above, comprising:
[0019] a GEM parsing module for parsing a GEM frame header and a GEM payload from a GTC frame;
[0020] a GEM payload storage module for managing the ONUi_GEM_FIFO and the ONUi_PLI_FIFO of each ONU;
[0021] a frame length calculation module for determining whether the PTI in the GEM frame header indicates a tail frame, and if not, latching the PLI value, or if yes, storing the accumulated PLI value into the independent ONUi_PLI_FIFO corresponding to the ONU;
[0022] a frame output scheduling module for polling the independent ONUi_PLI_FIFO corresponding to each ONU, reading out the PLI value if the FIFO is not empty, and reading data of a corresponding length from the ONUi_GEM_FIFO corresponding to each ONU as a complete service packet to output to an upper layer.
[0023] To achieve the above object, a MiniOLT device is provided, comprising the device described in claim 7.
[0024] To achieve the above object, a computer readable storage medium is provided, having a computer program stored thereon, wherein the program, when executed by a processor, implements the method described in any of the above.
[0025] The application has the advantages that: the technical solution of the application adopts an independent cache splicing method, that is, only one FIFO is configured for each ONU to store GEM frames, and GEM_payload is stored in the FIFO regardless of whether it is sliced or not, and another FIFO with a smaller depth is additionally allocated to each ONU to store the length of a complete GEM frame, which not only avoids the separate storage of sliced frames as in the traditional splicing, and the need for complex judgment and copying during splicing, but also simplifies the maintenance of the sliced state, and realizes low-latency and high-efficiency GEM frame splicing processing, and is particularly suitable for MiniOLT devices in FTTR scenarios. BRIEF DESCRIPTION OF DRAWINGS
[0026] In order to make the object, technical scheme and advantages of the application clearer, the application provides the following drawings for description:
[0027] Figure 1This is a basic flowchart of the method described in an embodiment of the present invention;
[0028] Figure 2 This is a diagram of the GEM frame structure in the GTC payload of the method described.
[0029] Figure 3 This is a diagram of the GEM frame structure in the method described.
[0030] Figure 4 This is a FIFO storage diagram of the ONU in the method described.
[0031] Figure 5 A diagram illustrating the GEM frame slicing scenario in the method described above;
[0032] Figure 6 This is a basic framework diagram of the device according to another embodiment of the present invention. Detailed Implementation
[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0034] In an FTTR system, the MiniOLT allocates bandwidth to the accessing ONUs via downlink services. The ONUs then transmit uplink frames within their allocated bandwidth. If the bandwidth is insufficient to transmit a complete GEM frame, the ONU will slice the GEM frame for transmission. Upon receiving this slice, the MiniOLT needs to reassemble the sliced GEM frames into a complete frame before sending it to the upper layer. The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings. It should be noted that the method described in this invention is implemented using an FPGA. The following example, using two ONUs (ONU1 and ONU2) both exhibiting GEM frame fragmentation, is intended to clearly illustrate the technical solution of the present invention and should not be construed as a limitation thereof.
[0035] like Figure 1 As shown, this embodiment of the invention provides a method for implementing multi-piece stitching of MiniOLT uplink GEM, which includes the following steps:
[0036] GEM frame parsing steps: Parse the GEM frame header and GEM payload from the uplink GTC frame.
[0037] It should be noted that the payload of the uplink GTC frame consists of consecutive GEM frames (e.g., Figure 2(As shown). The GEM frame parsing engine in the FPGA first locates the start boundary of each GEM frame, and then parses its frame header (GEM Header). The GEM frame header structure is as follows: Figure 3 As shown, its key fields include: Payload Length Indicator (PLI, 12bit): indicating the byte length of the GEM Payload immediately following the frame header; Port-ID (12bit): uniquely identifying the service flow or logical connection to which this GEM frame belongs, used in this invention to associate it with a specific ONU; Payload Type Indicator (PTI, 3bit): where the least significant bit (LSB) is a key flag bit used to indicate whether the GEM frame is the last segment (tail frame) of a fragmented frame. PTI[0] = 0 indicates that it is not the tail frame (there are subsequent fragments), and PTI[0] = 1 indicates that it is the tail frame; the parsing engine extracts the Port-ID, PLI and PTI values and processes the GEM Payload data stream subsequently.
[0038] GEM payload storage steps: Identify the ONU to which the payload belongs based on the Port-ID in the GEM frame header, and write the GEM payload into the independent ONUi_GEM_FIFO corresponding to that ONU, where i is 1, 2, 3, ...
[0039] In this embodiment of the invention, during the GEM payload storage step, each ONU is independently configured with an ONUi_GEM_FIFO to store all its GEM payload data in the order of reception, unaffected by fragmentation. Specifically, after parsing the GEM frame, the payload data is stored in the corresponding ONU's GEM_FIFO according to the Port-ID. For example, ONU1 is configured with an ONU1_GEM_FIFO, and ONU2 with an ONU2_GEM_FIFO. Regardless of whether the GEM frame is fragmented, the payload data is directly written into the corresponding FIFO in sequence, without needing to determine the fragmentation status. Furthermore, the GEM payload is stored based on the PLI and Port-ID information in the GEM header. The PLI indicates the length of this GEM payload frame, and the Port-ID identifies which ONU the GEM frame belongs to. Then, the GEM payload of the corresponding length is stored in its respective ONU FIFO. Additionally, the depth of the ONUi_PLI_FIFO is much smaller than the depth of the ONUi_GEM_FIFO, and it is only used to store the length information of the complete GEM frame.
[0040] To elaborate further, after parsing the Port-ID, the system can determine which ONU (e.g., ONUi) the GEM frame originated from. The system will directly write the GEM payload data byte stream into the ONU's dedicated ONUi_GEM_FIFO. This process is "copy-free": data flows directly from the parsing engine into the FIFO without first storing it in a temporary buffer and then moving it. Regardless of whether the GEM frame is a complete frame, the first frame of a fragmented frame, a middle frame, or the last frame, its payload data is simply appended to the end of its respective ONU's GEM_FIFO in the order it is received. Figure 4 As shown, all fragmented data of ONU1 (GEM1_payload, GEM2_payload, GEM3_head, GEM3_tail) are stored sequentially into ONU1_GEM_FIFO, thus naturally maintaining the correct order of data in physical storage. Therefore, during storage, it is only necessary to determine the ONU-ID to which the GEM payload belongs. If it belongs to ONU-ID1, the payload is stored in the corresponding ONU1_GEM_FIFO. The GEM frame length PLI of ONU1 needs to be determined by whether the current frame is the last frame. If it is the last frame, the PLI is stored in ONU1_PLI_FIFO. If it is not the last frame, the value needs to be latched first, and when the last frame is encountered, the PLI is incremented and then stored in ONU1_PLI_FIFO.
[0041] Frame length processing steps: Based on the PTI indicator in the GEM frame header, determine whether it is the last frame. If it is not the last frame, latch the PLI value. If it is the last frame, store the accumulated PLI value in the independent ONUi_PLI_FIFO corresponding to this ONU.
[0042] Based on the PTI indication in the GEM header, it is determined whether the current GEM frame is the last frame. If it is the last frame, the PTI in the GEM header is directly written into the corresponding ONU's frame length storage FIFO. If it is not the last frame, the current PTI information is latched until the GEM last frame of the ONU is reached. Then, the latched PTI is added to the PTI of the current last frame, and then stored in the corresponding ONU's frame length storage FIFO. It should be specifically noted that the frame length processing steps include:
[0043] If the PTI determines that the current GEM frame is not the last frame (not the last fragment), then the PTI value of the GEM frame is latched.
[0044] If PTI determines that the current GEM frame is the last frame (last fragment), it adds the previously latched PLI value to the PLI value of the current last frame to obtain the total length of the complete GEM frame, and stores this total length value in the corresponding ONUi_PLI_FIFO.
[0045] For example, the GEM3 frame of ONU1 is split into two pieces:
[0046] First frame: PLI = L1, PTI indicates non-tail frame → Latch L1
[0047] Second frame: PLI = L2, PTI indicates the end frame → Calculate the total length L = L1 + L2, and store L in ONU1_PLI_FIFO;
[0048] Or the GEM3 frame of ONU1 is divided into three pieces:
[0049] First frame: PLI = L1, PTI indicates non-tail frame → Latch L1
[0050] Second frame: PLI = L2, PTI indicates non-tail frame → Latch L2
[0051] Third frame: PLI = L2, PTI indicates the end frame → Calculate the total length L = L1 + L2 + L3, and store L in ONU1_PLI_FIFO;
[0052] Therefore, the GEM3 frame of ONU1 may be divided into multiple pieces, and the total calculated length L = L1 + L2 + ... Ln.
[0053] To better understand the core of implementing "multi-chip splicing" and "simplified logic," let's elaborate a bit more. The PTI processing logic maintains an accumulated length register (e.g., ONUi_accumulated_pli) for each ONU, and its specific processing flow is as follows:
[0054] Scenario A: A non-tail frame is received (PTI indicates a fragment, and it is not the last segment). The specific operation is as follows: only the PLI value of the current GEM frame is accumulated into the ONU's cumulative length register (ONUi_accumulated_pli = ONUi_accumulated_pli + Current_PLI). No content is written to the PLI_FIFO at this time.
[0055] Scenario B: Tail frame received (PTI indicates the last segment of the fragment or a complete frame). Specific operations: Add the value of the accumulated length register to the PLI value of the current tail frame to obtain the total length of the entire fragmented GEM frame (Total_PLI = ONUi_accumulated_pli + Current_PLI); then write the calculated total length value Total_PLI into the ONUx_PLI_FIFO corresponding to this ONU; finally, clear the accumulated length register ONUi_accumulated_pli to zero, preparing for receiving the next fragmented frame.
[0056] However, if the received frame is an unfragmented complete GEM frame (PTI directly indicates the end frame), then the cumulative length register should be 0. Total_PLI = 0 + Current_PLI, meaning the PLI value of the frame is directly stored in PLI_FIFO.
[0057] In this way, each value stored in PLI_FIFO represents the total length of a fully received and stitched complete GEM frame. This completely replaces the logic in traditional solutions that require complex state machines to track "which Gem-Port-ID frame is missing which fragments", greatly saving FPGA resources.
[0058] Complete frame output steps: Poll the independent ONUi_PLI_FIFO corresponding to each ONU. If it is not empty, read the PLI value and read the data of the corresponding length from the ONUi_GEM_FIFO corresponding to each ONU as a complete service packet and output it to the upper layer.
[0059] It should be noted that the Ethernet service packets carried in the GEM payload need to be output as complete service packets to the upper layer after splicing. The output logic is as follows: First, it is necessary to determine whether there is an ONU's ONUi_GEM_FIFO currently outputting. If not, the ONUi_PLI_FIFO of the online ONUs is polled sequentially. If it is not empty, the PLI in the ONUi_PLI_FIFO is read, and then the data of the PLI length is retrieved from the ONUi_GEM_FIFO. This data structure constitutes a complete service packet. The method is implemented in the FPGA, and both ONUi_GEM_FIFO and ONUi_PLI_FIFO are implemented using the FPGA's internal memory resources.
[0060] In this embodiment of the invention, the complete frame output step uses a polling method to sequentially check the ONUi_PLI_FIFO status of each ONU. If the ONUi_PLI_FIFO is not empty, the complete frame output of that ONU is processed first. Specifically, the output scheduler polls the PLI_FIFO of each ONU: when it finds that the PLI_FIFO of a certain ONU is not empty, it reads the PLI value (such as length L); it reads data of length L from the GEM_FIFO of that ONU, and outputs this data of length L as a complete service packet to the upper layer.
[0061] Continue as Figure 4As shown, the output scheduler operates using a simple polling algorithm: it continuously checks whether the PLI_FIFOs of all online ONUs are non-empty. When it finds that the ONU1_PLI_FIFO of a certain ONU (e.g., ONU1) is not empty, the scheduler reads a PLI value (denoted as L) from it. This L represents the length of a complete service packet that has been assembled and stored in the ONU1_GEM_FIFO. The scheduler then continuously reads L bytes of data from the read port of the ONU1_GEM_FIFO. This L bytes of data is encapsulated into a complete Ethernet packet and sent to the upper-layer network processing unit (such as an ARM processor) through the HSGMII interface or a similar interface. After processing one packet, the scheduler continues to poll the PLI_FIFO of the next ONU. This output mechanism is extremely simple in logic and does not require checking the fragmentation status because the entries in the PLI_FIFO itself mean that a complete data packet is ready.
[0062] Specifically, when splicing the output, it is necessary to determine whether there is an ONUi_GEM_FIFO currently being output. If not, it is then determined whether the ONUx_PLI_FIFO is empty. If it is not empty, the PLI is read out, and then the GEM payload of the PLI length is read from the ONUx_GEM_FIFO, which is the service packet carried in a complete GEM frame.
[0063] To better understand the above-described technical solution of the present invention, such as Figure 5 As shown, this invention takes the case where two ONUs (ONU1 and ONU2) both have GEM frame fragmentation as an example, and each ONU has one GEM frame (GEM3) that is split into two pieces. The specific explanation is as follows:
[0064] In the first uplink GTC frame:
[0065] Received ONU1_burst, which contains GEM3_head (PTI = non-tail frame, PLI = L1_head).
[0066] Operation: Store the payload of GEM3_head into ONU1_GEM_FIFO.
[0067] Operation: Accumulate L1_head into the ONU1_accumulated_pli register (the value is now L1_head).
[0068] Received ONU2_burst, which contains GEM3_head (PTI = non-tail frame, PLI = L2_head).
[0069] Operation: Store the payload of GEM3_head into ONU2_GEM_FIFO.
[0070] Operation: Accumulate L2_head into the ONU2_accumulated_pli register (the value is now L2_head).
[0071] In the second uplink GTC frame:
[0072] ONU1_burst was received again, which contained GEM3_tail (PTI = tail frame, PLI = L1_tail).
[0073] Operation: Append the payload of GEM3_tail into ONU1_GEM_FIFO.
[0074] Operation: Calculate the total length L1_total = ONU1_accumulated_pli(L1_head) + L1_tail.
[0075] Operation: Write L1_total to ONU1_PLI_FIFO.
[0076] Operation: Clear the ONU1_accumulated_pli register.
[0077] ONU2_burst was received again, which contained GEM3_tail (PTI = tail frame, PLI = L2_tail).
[0078] Operation: Append the payload of GEM3_tail into ONU2_GEM_FIFO.
[0079] Operation: Calculate the total length L2_total = ONU2_accumulated_pli(L2_head) + L2_tail.
[0080] Operation: Write L2_total to ONU2_PLI_FIFO.
[0081] Operation: Clear the ONU2_accumulated_pli register.
[0082] Output process:
[0083] When the output scheduler polls, it finds an entry L1_total in ONU1_PLI_FIFO, so it reads the L1_total bytes of data (i.e., the complete packet formed by concatenating the payloads of GEM3_head and GEM3_tail) from ONU1_GEM_FIFO and outputs it.
[0084] Subsequently, the scheduler discovers an entry L2_total in ONU2_PLI_FIFO, so it reads the L2_total bytes of data from ONU2_GEM_FIFO and outputs it.
[0085] In summary, this invention addresses the issue of multiple ONU GEM slices received by the MiniOLT within an FPGA, preventing frame loss and splicing errors. It supports splicing of ONUs divided into multiple slices using only a large and a small FIFO for each ONU, and immediately begins uplink output upon receiving the last frame. The splicing output logic is simple, eliminating the need for Gem-Port-ID, PLI, and PTI slice status checks. Therefore, in the current field of fiber optic communication, especially in Fiber to the Room (FTTR) scenarios, the FPGA+ARM collaborative architecture effectively addresses the flexible deployment, protocol evolution, and customization requirements of FTTR. This invention primarily provides an FPGA implementation method for multi-slice splicing of uplink GEMs in a MiniOLT based on the GPON protocol, resolving the multi-slice GEM splicing necessary for uplink parsing in the MiniOLT when implementing the GPON data link layer protocol using an FPGA.
[0086] In the above embodiments, a method for implementing multi-chip splicing of MiniOLT uplink GEM based on the GPON protocol has been described in detail. This application also provides an embodiment corresponding to an apparatus for implementing multi-chip splicing of MiniOLT uplink GEM based on the GPON protocol. It should be noted that this application describes the apparatus embodiment from two perspectives: one based on functional modules and the other based on hardware. This invention further provides an apparatus for implementing any of the methods described above, namely, a method for implementing multi-chip splicing of MiniOLT uplink GEM based on the GPON protocol, comprising:
[0087] The GEM parsing module is used to parse the GEM frame header and GEM payload from the GTC frame;
[0088] The GEM load storage module is used to manage the ONUi_GEM_FIFO and ONUi_PLI_FIFO of each ONU;
[0089] The frame length calculation module is used to determine whether it is the last frame based on the PTI in the GEM frame header. If it is not the last frame, the PTI value is latched. If it is the last frame, the accumulated PTI value is stored in the independent ONUi_PLI_FIFO corresponding to the ONU.
[0090] The frame output scheduling module is used to poll the independent ONUi_PLI_FIFO corresponding to each ONU. If it is not empty, it reads the PLI value and reads the data of the corresponding length from the ONUi_GEM_FIFO corresponding to each ONU as a complete service packet and outputs it to the upper layer.
[0091] Preferably, the frame length calculation module is used to latch the PLI value of the GEM frame if the PTI indicates that the current GEM frame is not the tail frame; or to add the previously latched PLI value and the PLI value of the current tail frame to obtain the total length of the complete GEM frame if the PTI indicates that the current GEM frame is the tail frame, and store the total length value in the corresponding ONUi_PLI_FIFO.
[0092] Therefore, by configuring an independent FIFO storage structure for each ONU, the embodiments of the present invention avoid data copying operations, simplify fragmentation status maintenance, and achieve low-latency, high-efficiency GEM frame splicing processing, which is particularly suitable for MiniOLT devices in FTTR scenarios.
[0093] This invention also provides a MiniOLT device comprising at least an optical module, an FPGA chip, and an ARM processor. The FPGA chip is configured to include the aforementioned components and is responsible for implementing the core data link layer processing of the GPON protocol, particularly through the provision of an independent FIFO storage structure for each ONU, as described in this invention. The ARM processor runs upper-layer management software, performing configuration management and higher-layer protocol interaction.
[0094] Through the above specific implementation methods, the present invention avoids data copying operations and simplifies fragmentation status maintenance by configuring an independent FIFO storage structure for each ONU, thereby achieving low-latency and high-efficiency GEM frame splicing processing, which is particularly suitable for MiniOLT devices in FTTR scenarios.
[0095] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above method embodiments.
[0096] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0097] This embodiment provides a computer-readable storage medium. When the computer program stored therein is executed, it enables the use of an FPGA+ARM collaborative architecture to address the flexible deployment, protocol evolution, and customization needs of Fiber to the Room (FTTR) in the current fiber optic communication field, especially in FTTR scenarios. This embodiment primarily provides a method for implementing multi-chip splicing of uplink GEMs in MiniOLTs. When implementing the GPON data link layer protocol using an FPGA, it solves the problem of multi-chip splicing required for uplink parsing in MiniOLTs. Therefore, when the computer program in the computer-readable storage medium provided in this embodiment is executed, it avoids data copying operations and simplifies fragment state maintenance by configuring an independent FIFO storage structure for each ONU, achieving low-latency, high-efficiency GEM frame splicing processing, which is particularly suitable for MiniOLT devices in FTTR scenarios.
[0098] The foregoing provides a detailed description of a method, apparatus, device, and medium for implementing multi-chip stitching of uplink GEM in MiniOLT. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
[0099] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
Claims
1. A method for implementing multi-piece stitching of MiniOLT uplink GEM, characterized in that, Includes the following steps: GEM frame parsing steps: Parse the GEM frame header and GEM payload from the uplink GTC frame; GEM payload storage steps: Identify the ONU to which the payload belongs based on the Port-ID in the GEM frame header, and write the GEM payload into the independent ONUi_GEM_FIFO corresponding to that ONU, where i is 1, 2, 3, ...; Frame length processing steps: Determine whether it is the last frame based on the PTI in the GEM frame header. If it is not the last frame, latch the PLI value. If it is the last frame, store the accumulated PLI value in the independent ONUi_PLI_FIFO corresponding to this ONU. Complete frame output steps: Poll the independent ONUi_PLI_FIFO corresponding to each ONU. If it is not empty, read the PLI value and read the data of the corresponding length from the ONUi_GEM_FIFO corresponding to each ONU as a complete service packet and output it to the upper layer.
2. The method according to claim 1, characterized in that, In the GEM load storage step, each ONU is independently configured with an ONUi_GEM_FIFO to store all its GEM load data in the order of reception, unaffected by fragmentation.
3. The method according to claim 1, characterized in that, The frame length processing steps include: If the PTI determines that the current GEM frame is not the last frame, then the PTI value of the GEM frame is latched. If the PTI determines that the current GEM frame is the last frame, it adds the previously latched PLI value to the PLI value of the current last frame to obtain the total length of the complete GEM frame, and stores the total length value in the corresponding ONUi_PLI_FIFO.
4. The method according to claim 3, characterized in that, The depth of the ONUi_PLI_FIFO is much smaller than the depth of the ONUi_GEM_FIFO, and it is only used to store the length information of the complete GEM frame.
5. The method according to claim 1, characterized in that, The complete frame output step uses a polling method to check the ONUi_PLI_FIFO status of each ONU in turn. If the ONUi_PLI_FIFO is not empty, the complete frame output of that ONU is processed first.
6. The method according to claim 1, characterized in that, The method is implemented in an FPGA, and both ONUi_GEM_FIFO and ONUi_PLI_FIFO are implemented using the internal memory resources of the FPGA.
7. An apparatus for implementing the method according to any one of claims 1-6, characterized in that, include: The GEM parsing module is used to parse the GEM frame header and GEM payload from the GTC frame; The GEM load storage module is used to manage the ONUi_GEM_FIFO and ONUi_PLI_FIFO of each ONU; The frame length calculation module is used to determine whether it is the last frame based on the PTI in the GEM frame header. If it is not the last frame, the PTI value is latched. If it is the last frame, the accumulated PTI value is stored in the independent ONUi_PLI_FIFO corresponding to the ONU. The frame output scheduling module is used to poll the independent ONUi_PLI_FIFO corresponding to each ONU. If it is not empty, it reads the PLI value and reads the data of the corresponding length from the ONUi_GEM_FIFO corresponding to each ONU as a complete service packet and outputs it to the upper layer.
8. A MiniOLT device, characterized in that, Includes the apparatus as described in claim 7.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-6.