Low-power-consumption radio frequency network data integrity verification method and system

Abstract

The invention relates to the technical field of wireless network security, in particular to a low-power-consumption radio frequency network data integrity verification method and system, and the method comprises the following steps: writing a configuration parameter and an initial vector into a shift register, constructing a binary key stream, bit-by-bit XOR data, a key and a feedback bit by using a seed and a random number to calculate a feedback value, and shifting and writing a feedback value into the register, adjusting a tap state, and outputting an integrity label composed of register values. According to the method, configuration parameters and non-zero initial vectors are written into a shift register, a shared secret seed is combined to construct a binary key stream, XOR operation is performed on sensor data, the key stream and feedback bits bit by bit according to a clock period, feedback is dynamically calculated by using a true value state, and the shift of the register is adjusted. And the integrity label is synchronously generated in transmission, so that resource occupation caused by complex Hash operation is avoided, power consumption is greatly reduced, the speed is increased, and communication delay and congestion caused by limitation of low-power-consumption nodes are effectively relieved.

Description

Technical Field

[0001] This invention relates to the field of wireless network security technology, and in particular to a method and system for verifying the integrity of low-power radio frequency network data. Background Technology

[0002] The field of wireless network security technology mainly encompasses technologies that utilize encryption algorithms, authentication protocols, or digital signatures in wireless communication networks to prevent malicious tampering, forgery, or interception of data during radio frequency transmission, thereby ensuring the authenticity and consistency of data. Traditional data integrity verification methods used in low-power radio frequency networks involve the transmitting node using its built-in microcontroller to run specific hash algorithms (such as MD5 or SHA-256) or Message Authentication Code (HMAC) algorithms to perform mathematical operations on specific sensor data payloads to generate a fixed-length digest value or integrity tag. This tag is then appended to a specific field of the data frame and transmitted via the radio frequency communication module. Upon receiving the data frame, the receiving node recalculates the data payload using the exact same algorithm and compares the calculated digest value bit-by-bit with the tag carried in the data frame to verify whether the data has been altered.

[0003] Existing technologies in low-power radio frequency networks rely on microcontrollers to execute complex hash algorithms such as MD5 or SHA-256. These algorithms involve a large number of tedious mathematical operations and multiple rounds of iterative processing, resulting in excessive computational load and significantly increasing node energy consumption, severely shortening battery life. When processing continuous sensor data streams, complex software operation logic causes a significant increase in data encapsulation latency and makes it difficult to meet real-time requirements. Furthermore, frequent high-intensity computational tasks continuously compete for the limited system resources of the microcontroller, leading to a decrease in overall communication throughput and response speed. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a low-power radio frequency network data integrity verification method and system.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a low-power radio frequency network data integrity verification method, comprising the following steps: S1: Write the configuration parameters and non-zero initial vector into and initialize the shift register; load the shared secret seed and the current session random number into the pseudo-random number generation logic; construct a binary key stream based on the shared secret seed and the current session random number through the pseudo-random number generation logic. S2: Read the current data bit bit by bit from the sensor data stream according to the clock cycle, output the current key bit from the binary key stream through the pseudo-random number generation logic, and read the feedback bit from the highest bit of the shift register; S3: Perform a bitwise XOR operation on the current data bit, the current key bit, and the feedback bit, and calculate the feedback input value based on the logical truth value of the operation output; S4: Shift the value of the shift register one bit to the higher bit and write the feedback input value into the lowest bit of the shift register. Based on the position of the feedback tap, perform a bitwise XOR operation on the feedback input value and the shifted value in the target storage unit to adjust the state of the shift register. When the sensor data stream processing is completed, output an integrity tag composed of the values ​​of the shift register.

[0006] As a further embodiment of the present invention, the binary key stream includes a shared secret seed and a current session random number, the feedback bit specifically refers to the value in the highest-order storage unit of the shift register, the feedback input value includes the current data bit, the current key bit, and the feedback bit, and the integrity tag is specifically a combination of binary values ​​of all storage units in the shift register.

[0007] As a further aspect of the present invention, step S1 specifically comprises: S11: Obtain configuration parameters and a non-zero initial vector, determine the length and tap structure of the shift register based on the configuration parameters, and write the non-zero initial vector into multiple storage units of the shift register to establish an initial nonlinear state; S12: Obtain the shared secret seed and the current session random number, use the shared secret seed as a key primitive and the current session random number as an initialization variable, and load them into the internal status register of the pseudo-random number generation logic; S13: Drive the pseudo-random number generation logic to perform state iteration update, generate binary sequence bit by bit from the output port according to the preset stream cipher generation rules, and establish a binary key stream that is time-aligned with the sensor data stream.

[0008] As a further aspect of the present invention, step S2 specifically comprises: S21: Monitor the transmission clock signal of the sensor data stream, sample the bus level on the rising edge of the clock signal, and obtain the logic level value of the current time slot as the current data bit; S22: Trigger the pseudo-random number generation logic to perform a state advancement operation, extracting the currently generated binary bits from the output buffer as the current key bits; S23: Access the storage cell with the highest index value in the shift register, and read the currently latched binary value in the storage cell as a feedback bit.

[0009] As a further aspect of the present invention, step S3 specifically comprises: S31: Obtain the current data bits, the current key bits, and the feedback bits; S32: Input the current data bits and the current key bits into the first-level logic operation unit to perform a bitwise XOR operation to generate intermediate encryption mask bits; S33: Perform a bitwise XOR operation between the intermediate encryption mask bit and the feedback bit input to the second-level logic operation unit, and generate a feedback input value based on the logic high and low level states of the operation result.

[0010] As a further aspect of the present invention, step S4 specifically comprises: S41: Send a shift control signal to the shift register to move the binary value in each storage cell to the adjacent high-order storage cell and discard the original value that overflowed from the highest-order storage cell. S42: Enable the write port of the least significant bit storage unit of the shift register, and latch the feedback input value into the least significant bit storage unit; S43: Obtain the feedback tap position defined in the configuration parameters, and identify the target storage unit in the shift register corresponding to the feedback tap position; S44: Obtain the feedback input value and the shifted value in the target storage unit, perform an XOR operation, and write the result back to the target storage unit to update the shift register state; S45: When the sensor data stream transmission is detected to be finished, the values ​​of all storage units of the shift register are read in parallel to generate an integrity tag.

[0011] As a further aspect of the present invention, the process of updating the shift register state in S44 includes: The updated value of the target storage unit is calculated according to the following formula: ; in, Represents the next moment The value of each storage unit, Represents the current moment. The value of each storage unit, Representing the Tap coefficient at each position This represents the feedback input value. Represents the logical XOR operator. Represents the logical AND operator.

[0012] As a further aspect of the present invention, the process of generating the feedback input value in S33 includes: The logical state of the feedback input value is calculated according to the following formula: ; in, This represents the feedback input value. Represents the current data bits. Represents the current key bits. Represents the feedback bit. This represents the logical XOR operator.

[0013] As a further aspect of the present invention, the process of generating the integrity tag in S45 includes: S451: Monitor the data validity indication signal, and when the data validity indication signal is detected to flip to an invalid state, determine that the sensor data stream processing is complete; S452: Trigger the parallel output latch of the shift register to keep the binary state of all memory cells constant. S453: Concatenate the output values ​​of multiple storage units sequentially from the most significant bit to the least significant bit to construct a fixed-width binary sequence as the integrity tag.

[0014] A low-power radio frequency network data integrity verification system, wherein the low-power radio frequency network data integrity verification system is used to implement the above-mentioned low-power radio frequency network data integrity verification method, the system comprising: The key stream construction module is used to write configuration parameters and non-zero initial vectors into and initialize shift registers, load the shared secret seed and the current session random number into the pseudo-random number generation logic, construct a binary key stream based on the shared secret seed and the current session random number through the pseudo-random number generation logic, and pass it to the status reading module; The status reading module is used to read the current data bit bit by bit from the sensor data stream according to the clock cycle, output the current key bit from the binary key stream through the pseudo-random number generation logic, read the feedback bit from the highest bit of the shift register, and pass it to the feedback value calculation module. The feedback value calculation module is used to perform a bitwise XOR logic operation on the current data bit, the current key bit, and the feedback bit, calculate the feedback input value based on the logical truth value state of the operation output, and pass it to the tag generation module. The tag generation module is used to shift the value of the shift register by one bit to the higher bit and write the feedback input value into the lowest bit of the shift register. Based on the position of the feedback tap, the module performs a bitwise XOR operation on the feedback input value and the shifted value in the target storage unit to adjust the state of the shift register. When the sensor data stream processing is completed, the module outputs an integrity tag composed of the values ​​of the shift register.

[0015] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, configuration parameters and non-zero initial vectors are written into a shift register and combined with a shared secret seed to construct a binary key stream. Bitwise XOR logic operations are performed on the sensor data, key stream, and feedback bits according to the clock cycle. The feedback input is dynamically calculated and the register shift state is adjusted using the true value state obtained from the operation. Integrity tag generation is completed synchronously during data stream transmission, avoiding excessive consumption of computing resources by complex hash mathematical operations, significantly reducing computing power consumption and significantly improving processing speed. This effectively alleviates communication delays and congestion caused by limited computing power in low-power nodes. Attached Figure Description

[0016] Figure 1 This is the main flowchart of the low-power radio frequency network data integrity verification method of the present invention; Figure 2 This is a flowchart illustrating the initialization and key stream construction process of this invention. Figure 3 This is a flowchart of the data sampling and parameter extraction process of this invention; Figure 4 This is a flowchart of the logic calculation for the feedback input value in this invention; Figure 5 This is a flowchart of the register state update and tag generation process of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the software-based technical solution is described in detail below with reference to system architecture diagrams and embodiments. It should be understood that the specific embodiments described herein are only for explaining the technical solutions of this invention and do not constitute a limitation on the scope of protection.

[0018] In the description of this invention, the system architecture relationships or data processing flows indicated by terms such as "layer," "module," "interface," "data flow," "client," and "server" are all defined based on the architecture diagram or flowchart corresponding to the embodiments. This way of describing is only used to clearly illustrate the logical relationships between the elements in the technical solution, and not to limit the physical deployment form. The term "multiple" includes two or more technical units, including but not limited to multiple data nodes, processing threads, service instances, or functional components and other scalable elements. The specific number is determined according to the actual business scenario and needs to be specifically specified.

[0019] Please see Figure 1 and Figure 2 This invention provides a technical solution: a low-power radio frequency network data integrity verification method, comprising the following steps: S1: Write the configuration parameters and non-zero initial vector into the shift register and initialize it. Load the shared secret seed and the current session random number into the pseudo-random number generation logic. Construct a binary key stream based on the shared secret seed and the current session random number through the pseudo-random number generation logic. The binary key stream includes a shared secret seed and a current session random number; The specific steps of S1 are as follows: S11: Obtain the configuration parameters and non-zero initial vector, determine the length and tap structure of the shift register based on the configuration parameters, and write the non-zero initial vector into multiple storage units of the shift register to establish the initial nonlinear state. S12: Obtain the shared secret seed and the current session random number, use the shared secret seed as the key primitive and the current session random number as the initialization variable, and load them into the internal status register of the pseudo-random number generation logic; S13: Drive the pseudo-random number generation logic to perform iterative updates of the execution state, generate binary sequences bit by bit from the output port according to the preset stream cipher generation rules, and establish a binary key stream that is time-aligned with the sensor data stream.

[0020] After the low-power RF network communication module powers on and resets, the main control unit sends an initialization command to the encryption coprocessor via the internal bus. The main control unit reads predefined configuration parameters and a non-zero initialization vector from a specific address range of non-volatile memory, such as Flash. The configuration parameters include the bit width definition of the shift register. In this embodiment, the bit width is set to 16 bits, along with a tap position mask for the feedback polynomial. The main control unit writes the bit width parameter into the length configuration register of the shift register controller, configuring the physical storage space of the shift register as 16 consecutive D flip-flop units. Subsequently, the main control unit selects a non-zero initial vector, which in this embodiment is set to a hexadecimal value. That is, binary Write to the shift register at once via the parallel data bus to The storage unit loads the initial nonlinear state. Regarding the pseudo-random number generation logic, the system calls a shared secret seed stored in a secure area, which is a 128-bit key, for example... The random number generated by the current communication session is a 64-bit nonce, for example... These two parameters are loaded into the internal state register based on the stream cipher algorithm. The system drives the pseudo-random number generation logic to run a 64-clock-cycle warm-up phase, during which the generated output bits are discarded and used only to mix the internal state to eliminate initial bias. After the warm-up, the pseudo-random number generation logic enters the operating mode. On the falling edge of each data transmission clock, the internal state machine performs a non-linear update and latches a single binary value from the output port, forming a binary key stream that is strictly time-aligned with the sensor data stream.

[0021] The aforementioned shared secret seed refers to a fixed-length binary code that is pre-negotiated by both communicating parties and securely stored in the device's hardware security module. It serves as the root key for generating pseudo-random sequences, ensuring that both parties can generate synchronized encrypted key streams.

[0022] Please see Figure 1 and Figure 3 S2: Read the current data bit bit by bit from the sensor data stream according to the clock cycle, output the current key bit from the binary key stream through the pseudo-random number generation logic, and read the feedback bit from the highest bit of the shift register; The feedback bit specifically refers to the value in the highest-order storage unit of the shift register; The specific steps of S2 are as follows: S21: Monitor the transmission clock signal of the sensor data stream, sample the bus level on the rising edge of the clock signal, and obtain the logic level value of the current time slot as the current data bit; S22: Trigger the pseudo-random number generation logic to perform a state advance operation, extracting the currently generated binary bits from the output buffer as the current key bits; S23: Access the memory cell with the highest index value in the shift register and read the currently latched binary value in the memory cell as the feedback bit.

[0023] The demodulation circuit of the RF front-end recovers the baseband digital signal transmitted by the sensor and synchronously recovers a 1MHz data transmission clock signal. The integrity verification logic module uses this clock signal as a trigger source, connecting it to the clock terminal of the input sampling circuit. Upon detecting the rising edge of the data transmission clock signal, the input sampling circuit activates the bus driver to sample the level state of the data bus pins. The sampling window duration is set to 50ns. If the level remains above 2.0V during the sampling period, for a 3.3V system, the logic level of the current time slot is determined to be 1; if the level remains below 0.8V, it is determined to be 0. This logic value is latched into the input buffer register and defined as the current data bit. For example, in the first The sampled logic level is high within one clock cycle, i.e. Simultaneously, the rising edge signal synchronously triggers the output enable terminal of the pseudo-random number generation logic, and the control logic pops a bit from the current binary key stream queue. If the current output buffer value of the pseudo-random number generator is low, the extracted current key bit... Next, the read / write control logic sends an address read instruction to the shift register, addressing to index 15, which corresponds to the most significant bit. The memory cell internally reads the currently latched charge state through a sensing amplifier and outputs the corresponding digital logic value. In this embodiment, the current state of the shift register is... Its highest bit, the 15th bit, is in binary. If the first bit is 1, then the feedback bit read is... At this point, the integrity verification logic module has prepared three input components within the same clock cycle: , , It awaits entry into the next level of logical operation.

[0024] The aforementioned sensing amplifier refers to an analog comparator circuit integrated into a memory circuit, used to detect and amplify the weak voltage difference on the bit lines of the memory cell, converting it into a standard digital logic level output to ensure the accuracy of data reading.

[0025] Please see Figure 1 and Figure 4 S3: Perform a bitwise XOR operation on the current data bit, the current key bit, and the feedback bit, and calculate the feedback input value based on the logical truth value of the operation output. The feedback input values ​​include the current data bits, the current key bits, and the feedback bits; The specific steps for S3 are as follows: S31: Obtain the current data bits, current key bits, and feedback bits; S32: Input the current data bits and the current key bits into the first-level logic operation unit to perform a bitwise XOR operation to generate intermediate encryption mask bits; S33: Input the intermediate encryption mask bit and the feedback bit into the second-level logic operation unit to perform a bitwise XOR operation, and generate a feedback input value based on the logic high and low level state of the operation result; The process of generating feedback input values ​​in S33 includes: The logical state of the feedback input value is calculated based on the following formula: ; in, This represents the feedback input value. Represents the current data bits. Represents the current key bits. Represents the feedback bit. This represents the logical XOR operator.

[0026] The arithmetic logic unit within the integrity verification logic module receives three binary inputs obtained from step S2: the current data bit. Current key bits and feedback bits The arithmetic logic unit internally contains two cascaded XOR logic gates. The first-stage XOR gate receives... and The first stage performs a bitwise XOR operation to generate the intermediate encryption mask bits. The second-stage XOR gate receives the intermediate encryption mask bits and... Based on the level-flipping characteristics of the logic circuit, the final feedback input value is output. .

[0027] The aforementioned arithmetic logic unit refers to the core component of combinational logic circuits in digital circuits used to perform arithmetic and logical operations. In this scheme, it specifically refers to the hardware logic module used to perform multi-level XOR operations to generate feedback input values.

[0028] The formula used to generate the feedback input value in this step is: ; In the formula, This represents the feedback input value. Represents the current data bits. Represents the current key bits. Represents the feedback bit. This represents the logical XOR operator.

[0029] Calculations are performed using the actual values ​​obtained from S2: (Given) , , The first level of operation is The second level of operation, that is, the final calculation, is... That is, the calculated feedback input value. This result indicates that, after combining the current data bits with the historical state and keystream, the new information bit injected into the shift register input is logic 0. This value will determine the perturbation direction for the next shift register state update.

[0030] Please see Figure 1 and Figure 5 S4: Shift the value of the shift register one bit to the high bit and write the feedback input value to the lowest bit of the shift register. Based on the position of the feedback tap, perform a bitwise XOR operation on the feedback input value and the shifted value in the target storage unit to adjust the state of the shift register. When the sensor data stream processing is completed, output an integrity tag composed of the shift register values. The integrity tag is specifically a combination of binary values ​​from all memory locations in the shift register; The specific steps for S4 are as follows: S41: Send a shift control signal to the shift register to move the binary value in each memory cell to the adjacent higher memory cell and discard the original value that overflowed from the highest memory cell. S42: Enable the write port of the least significant bit of the shift register and latch the feedback input value into the least significant bit. S43: Obtain the feedback tap position defined in the configuration parameters and identify the target storage unit in the shift register corresponding to the feedback tap position; S44: Obtain the feedback input value and the shifted value in the target memory unit, perform an XOR operation, and write the result back to the target memory unit to update the shift register state; The process of updating the shift register state in S44 includes: The updated value of the target storage unit is calculated using the following formula: ; in, Represents the next moment The value of each storage unit, Represents the current moment. The value of each storage unit, Representing the Tap coefficient at each position This represents the feedback input value. Represents the logical XOR operator. Represents the logical AND operator; S45: When the sensor data stream transmission is detected to be finished, the values ​​of all storage units in the shift register are read in parallel to generate an integrity tag; The process of generating integrity labels in S45 includes: S451: Monitor the data validity indicator signal. When the data validity indicator signal is detected to flip to an invalid state, it is determined that the sensor data stream processing is complete. S452: Triggers the parallel output latch of the shift register to keep the binary state of all current memory cells constant; S453: Concatenate the output values ​​of multiple memory units in order from the most significant bit to the least significant bit to construct a fixed-width binary sequence as an integrity tag.

[0031] The verification logic controller sends a synchronous shift pulse signal to the shift register. On the rising edge of the pulse, the values ​​in storage cells 0 to 14 of the register are transferred in parallel to storage cells 1 to 15. The original value in storage cell 15, i.e., the feedback bit, is shifted out and discarded. Simultaneously, the input latch of the least significant bit, i.e., storage cell 0, is enabled, and the feedback input value calculated in step S3 is... The information is written to this location. Next, the controller reads the feedback tap position information defined in the configuration parameters. This embodiment assumes the configured tap position sequence is as follows: The corresponding tap coefficient exist When the value is 1, the rest are 0. The logic circuit performs a state update operation for each memory cell, and in particular, for target memory cells with taps, it performs an XOR feedback operation.

[0032] The process of updating the shift register state in this step is based on the formula: ; In the formula, Represents the next moment The value of each storage unit, Represents the current moment. The value of each storage unit, Representing the Tap coefficient at each position This represents the feedback input value. Represents the logical XOR operator. Represents the logical AND operator.

[0033] The advantage of this formula is that it calculates the feedback value. By distributing the tap coefficients in parallel to multiple intermediate positions in the register, the system's nonlinearity and avalanche effect are increased. This ensures that any alteration to a single bit of data will rapidly propagate to the entire register state in subsequent clock cycles, thereby improving the sensitivity of integrity checks. Implementation data is shown in Table 1.

[0034] ; As shown in Table 1, based on the data in Table 1, for the third storage unit, i.e. Perform the update calculation: Substitute the data into the formula: For the 4th storage unit, i.e. Perform update calculations, assuming Substitute the data into the formula: Therefore, it can be seen that when At this point, the third bit with a tap undergoes a data flip, changing from 0 to 1 as expected from a simple shift, while the fourth bit without a tap only performs a shift operation. When the data stream transmission end flag is set high, the state machine enters the termination state. At this time, the shift register clock stops, the parallel output port opens, and the controller reads data in bit-width order. to All values. For example, the final state is hexadecimal This 16-bit binary sequence is then output as a data integrity tag for this communication. This integrity tag is appended to the end of the data packet and sent. The receiving end will perform the same generation process and compare the tag to verify whether the data has been tampered with.

[0035] The aforementioned data integrity tag refers to a unique verification code generated based on the original data content and a preset algorithm during data communication. It is used at the receiving end to verify whether the data has been accidentally tampered with or erroneous during transmission.

[0036] A low-power radio frequency network data integrity verification system, used to execute the aforementioned low-power radio frequency network data integrity verification method, the system comprising: The key stream construction module is used to write configuration parameters and non-zero initial vectors into and initialize shift registers, load the shared secret seed and the current session random number into the pseudo-random number generation logic, construct a binary key stream based on the shared secret seed and the current session random number through the pseudo-random number generation logic, and pass it to the status reading module; The status reading module is used to read the current data bits bit by bit from the sensor data stream according to the clock cycle, output the current key bits from the binary key stream through the pseudo-random number generation logic, read the feedback bit from the highest bit of the shift register, and pass it to the feedback value calculation module. The feedback value calculation module is used to perform bitwise XOR logic operations on the current data bits, the current key bits, and the feedback bits, calculate the feedback input value based on the logical truth value of the operation output, and pass it to the tag generation module. The tag generation module is used to shift the value of the shift register one bit to the high bit and write the feedback input value to the lowest bit of the shift register. Based on the position of the feedback tap, it performs a bitwise XOR operation on the feedback input value and the shifted value in the target storage unit to adjust the state of the shift register. When the sensor data stream processing is completed, it outputs an integrity tag composed of the shift register values.

[0037] The above embodiments illustrate preferred embodiments of the present invention. Any equivalent adjustments to the technical solution based on software engineering methods are within the scope of protection, including but not limited to: implementing algorithm logic using different programming languages, refactoring functional modules into services, adjusting data interaction protocols, and optimizing resource scheduling strategies. Any implementation scheme derived from reasonable modifications to the data processing flow, service call chain, or system architecture layer without departing from the core technology of the present invention should be considered within the scope of protection defined by the claims of the present invention.

Claims

1. A method for verifying data integrity in low-power radio frequency networks, characterized in that, Includes the following steps: S1: Write the configuration parameters and non-zero initial vector into and initialize the shift register; load the shared secret seed and the current session random number into the pseudo-random number generation logic; construct a binary key stream based on the shared secret seed and the current session random number through the pseudo-random number generation logic. S2: Read the current data bit bit by bit from the sensor data stream according to the clock cycle, output the current key bit from the binary key stream through the pseudo-random number generation logic, and read the feedback bit from the highest bit of the shift register; S3: Perform a bitwise XOR operation on the current data bit, the current key bit, and the feedback bit, and calculate the feedback input value based on the logical truth value of the operation output; S4: Shift the value of the shift register one bit to the higher bit and write the feedback input value into the lowest bit of the shift register. Based on the position of the feedback tap, perform a bitwise XOR operation on the feedback input value and the shifted value in the target storage unit to adjust the state of the shift register. When the sensor data stream processing is completed, output an integrity tag composed of the values ​​of the shift register.

2. The low-power radio frequency network data integrity verification method according to claim 1, characterized in that, The binary key stream includes a shared secret seed and a current session random number. The feedback bit specifically refers to the value in the highest-order storage unit of the shift register. The feedback input value includes the current data bit, the current key bit, and the feedback bit. The integrity tag is specifically a combination of the binary values ​​of all storage units in the shift register.

3. The low-power radio frequency network data integrity verification method according to claim 2, characterized in that, The specific steps of S1 are as follows: S11: Obtain configuration parameters and a non-zero initial vector, determine the length and tap structure of the shift register based on the configuration parameters, and write the non-zero initial vector into multiple storage units of the shift register to establish an initial nonlinear state; S12: Obtain the shared secret seed and the current session random number, use the shared secret seed as a key primitive and the current session random number as an initialization variable, and load them into the internal status register of the pseudo-random number generation logic; S13: Drive the pseudo-random number generation logic to perform state iteration update, generate binary sequence bit by bit from the output port according to the preset stream cipher generation rules, and establish a binary key stream that is time-aligned with the sensor data stream.

4. The low-power radio frequency network data integrity verification method according to claim 3, characterized in that, The specific steps of S2 are as follows: S21: Monitor the transmission clock signal of the sensor data stream, sample the bus level on the rising edge of the clock signal, and obtain the logic level value of the current time slot as the current data bit; S22: Trigger the pseudo-random number generation logic to perform a state advancement operation, extracting the currently generated binary bits from the output buffer as the current key bits; S23: Access the storage cell with the highest index value in the shift register, and read the currently latched binary value in the storage cell as a feedback bit.

5. The low-power radio frequency network data integrity verification method according to claim 4, characterized in that, The specific steps in S3 are as follows: S31: Obtain the current data bits, the current key bits, and the feedback bits; S32: Input the current data bits and the current key bits into the first-level logic operation unit to perform a bitwise XOR operation to generate intermediate encryption mask bits; S33: Perform a bitwise XOR operation between the intermediate encryption mask bit and the feedback bit input to the second-level logic operation unit, and generate a feedback input value based on the logic high and low level states of the operation result.

6. The low-power radio frequency network data integrity verification method according to claim 5, characterized in that, The specific steps of S4 are as follows: S41: Send a shift control signal to the shift register to move the binary value in each storage cell to the adjacent high-order storage cell and discard the original value that overflowed from the highest-order storage cell. S42: Enable the write port of the least significant bit storage unit of the shift register, and latch the feedback input value into the least significant bit storage unit; S43: Obtain the feedback tap position defined in the configuration parameters, and identify the target storage unit in the shift register corresponding to the feedback tap position; S44: Obtain the feedback input value and the shifted value in the target storage unit, perform an XOR operation, and write the result back to the target storage unit to update the shift register state; S45: When the sensor data stream transmission is detected to be finished, the values ​​of all storage units of the shift register are read in parallel to generate an integrity tag.

7. The low-power radio frequency network data integrity verification method according to claim 6, characterized in that, The process of updating the shift register state in S44 includes: The updated value of the target storage unit is calculated according to the following formula: ； in, Representing the next moment The value of each storage unit, Represents the current moment. The value of each storage unit, Representing the Tap coefficient at each position This represents the feedback input value. Represents the logical XOR operator. Represents the logical AND operator.

8. The low-power radio frequency network data integrity verification method according to claim 7, characterized in that, The process of generating the feedback input value in S33 includes: The logical state of the feedback input value is calculated according to the following formula: ； in, This represents the feedback input value. Represents the current data bits. Represents the current key bits. Represents the feedback bit. This represents the logical XOR operator.

9. The low-power radio frequency network data integrity verification method according to claim 8, characterized in that, The process of generating the integrity tag in S45 includes: S451: Monitor the data validity indication signal, and when the data validity indication signal is detected to flip to an invalid state, determine that the sensor data stream processing is complete; S452: Trigger the parallel output latch of the shift register to keep the binary state of all memory cells constant. S453: Concatenate the output values ​​of multiple storage units sequentially from the most significant bit to the least significant bit to construct a fixed-width binary sequence as the integrity tag.

10. A low-power radio frequency network data integrity verification system, characterized in that, The system is used to implement the low-power radio frequency network data integrity verification method according to any one of claims 1-9, and the system includes: The key stream construction module is used to write configuration parameters and non-zero initial vectors into and initialize shift registers, load the shared secret seed and the current session random number into the pseudo-random number generation logic, construct a binary key stream based on the shared secret seed and the current session random number through the pseudo-random number generation logic, and pass it to the status reading module; The status reading module is used to read the current data bit bit by bit from the sensor data stream according to the clock cycle, output the current key bit from the binary key stream through the pseudo-random number generation logic, read the feedback bit from the highest bit of the shift register, and pass it to the feedback value calculation module. The feedback value calculation module is used to perform a bitwise XOR logic operation on the current data bit, the current key bit, and the feedback bit, calculate the feedback input value based on the logical truth value state of the operation output, and pass it to the tag generation module. The tag generation module is used to shift the value of the shift register by one bit to the higher bit and write the feedback input value into the lowest bit of the shift register. Based on the position of the feedback tap, the module performs a bitwise XOR operation on the feedback input value and the shifted value in the target storage unit to adjust the state of the shift register. When the sensor data stream processing is completed, the module outputs an integrity tag composed of the values ​​of the shift register.

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