A semiconductor structure and a method of fabricating the same

Abstract

This application relates to a semiconductor structure and its fabrication method, comprising: a substrate, a grating structure, and a filter unit. The substrate includes a plurality of pixel units spaced apart and arranged in an array. The grating structure is located above the substrate and includes a plurality of grating openings and a grating frame surrounding the grating openings. A total internal reflection portion is disposed within the grating frame, and the orthographic projection of the grating openings onto the substrate coincides with the orthographic projection of the pixel units onto the substrate. The filter unit is located above the substrate and within the grating openings. The semiconductor structure and its fabrication method of this application reduce optical crosstalk without sacrificing photosensitivity, improving the imaging clarity and signal-to-noise ratio of the image sensor, and also exhibit high structural stability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In image sensors, metal grids are often introduced between the filters of pixels to improve color reproduction and reduce optical crosstalk. While metal grids absorb visible light to some extent, suppressing photon crosstalk, this also significantly reduces the overall light sensitivity of the image sensor. However, decreased light sensitivity can lead to insufficient light intake when pixels are scaled down, thus affecting imaging performance and image signal-to-noise ratio.

[0003] Therefore, there is an urgent need for a grid structure design that can effectively suppress photonic crosstalk in image sensors while ensuring light sensitivity. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem that metal grids in the prior art affect the light sensitivity of image sensors.

[0005] To achieve the above objectives, this application provides a semiconductor structure, comprising:

[0006] The substrate comprises multiple pixel units spaced apart and arranged in an array;

[0007] A grid structure is located above the substrate. The grid structure includes multiple grid openings and a grid frame surrounding the grid openings. A total reflection part is provided in the grid frame, and the orthographic projection of the grid openings on the substrate coincides with the orthographic projection of the pixel unit on the substrate.

[0008] A filter unit is located above the substrate and within the grid opening.

[0009] In one embodiment, the grid frame includes a first portion spaced apart in a first direction and a second portion spaced apart in a second direction, the first portion and the second portion being intersected on a plane formed by the first direction and the second direction, the first direction intersecting the second direction.

[0010] In one embodiment, the total reflection portions are located in the first portion and the second portion respectively, and the total reflection portions located in the first portion and the total reflection portions located in the second portion are cross-connected.

[0011] In one embodiment, the total reflection portion located within the first portion includes a plurality of total reflection portions, and the plurality of total reflection portions extend in the first direction and are spaced apart in the second direction.

[0012] And / or, the total reflection portion located within the second portion includes a plurality of total reflection portions, and the plurality of total reflection portions extend in the second direction and are spaced apart in the first direction.

[0013] In one embodiment, the total reflector includes a sealed air cavity.

[0014] This application also provides a method for fabricating a semiconductor structure, comprising the following steps:

[0015] A substrate is provided, the substrate comprising a plurality of pixel units spaced apart and arranged in an array;

[0016] A grid structure is formed above the substrate. The grid structure includes a plurality of grid openings and a grid frame surrounding the grid openings. A total reflection part is provided in the grid frame, and the orthographic projection of the grid openings on the substrate coincides with the orthographic projection of the pixel unit on the substrate.

[0017] A filter unit is formed in the grid opening above the substrate.

[0018] In one embodiment, forming a grid structure above the substrate includes:

[0019] A grid material layer is formed on the substrate;

[0020] A grid groove is formed in the grid material layer, and the grid groove is located above the area of ​​the substrate where the pixel unit is not disposed;

[0021] A filling layer is formed to fill the grooves of the grid;

[0022] A first cover layer is formed covering the grid material layer and the filler layer;

[0023] A grid opening is formed in the first cover layer and the grid material layer, the orthographic projection of the grid opening on the substrate coincides with the orthographic projection of the pixel unit on the substrate, and the remaining first cover layer and the grid material layer after the grid opening is formed are connected in a grid pattern.

[0024] Remove the filler layer located within the grid groove;

[0025] A second covering layer is formed above the first covering layer to seal the grid grooves, wherein the grid material layer, the first covering layer and the second covering layer, which are connected in a grid pattern, constitute the grid frame, and the grid grooves sealed in the grid frame constitute the total reflective portion.

[0026] In one embodiment, removing the filler layer located within the grid trench includes:

[0027] An opening is formed at the intersection of the remaining first covering layer after the formation of the grid opening, and the bottom of the opening exposes at least the upper surface of the filling layer;

[0028] The filling layer is removed based on the opening.

[0029] In one embodiment, the filler layer is made of an organic polymer, wherein removing the filler layer based on the opening includes:

[0030] The filling layer is removed from the opening using an ashing process.

[0031] In one embodiment, after forming a second cover layer sealing the grille trench over the first cover layer, the method further includes:

[0032] Thin the second cover layer.

[0033] The semiconductor structure and its fabrication method described in this application have the following beneficial effects: By setting a grating structure including multiple grating openings and a grating frame surrounding the grating openings, with a total internal reflection portion disposed within the grating frame, and the filter unit located above the substrate and within the grating opening, the total internal reflection effect of the total internal reflection portion can be utilized to effectively suppress the lateral propagation of light between adjacent filter units without reducing the light incident efficiency, ensuring that light accurately passes through the filter unit of the corresponding color, thereby reducing light crosstalk. Furthermore, it can improve the imaging clarity and signal-to-noise ratio of the image sensor without sacrificing photosensitivity. Moreover, the grating openings in the grating structure are located on the substrate. The orthographic projection of the light source coincides with the orthographic projection of the pixel unit on the substrate, thereby ensuring that the light can be accurately guided to the target pixel unit. This reduces light crosstalk and also helps to achieve a compact design, which is particularly suitable for next-generation image sensors with further reduced pixel size. It helps to promote the miniaturization of image sensors and provides technical support. In addition, the grid frame surrounding the grid opening can achieve a cross-connection design, which makes the corresponding grid structure and the total reflection part inside the grid structure have high structural stability. This can avoid the problem of structural collapse in subsequent process technology, and significantly improve the overall device reliability and manufacturing yield. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in one embodiment;

[0036] Figure 2 Provided in one embodiment Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure along the AA' direction;

[0037] Figure 3 Provided in one embodiment Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure along the BB' direction;

[0038] Figure 4 This is a schematic diagram of the fabrication process of a semiconductor structure provided in one embodiment;

[0039] Figure 5 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after the formation of the first mask layer along the AA' direction;

[0040] Figure 6 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after forming grid trenches along the AA' direction;

[0041] Figure 7 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after the filling material layer is formed along the AA' direction;

[0042] Figure 8 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after the filling layer is formed along the AA' direction;

[0043] Figure 9 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after the formation of the first capping layer along the AA' direction;

[0044] Figure 10 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after the formation of the grid opening along the AA' direction;

[0045] Figure 11 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after the formation of the second mask layer along the BB' direction;

[0046] Figure 12 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A top view of the semiconductor structure after the opening is formed;

[0047] Figure 13 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after the opening is formed along the BB' direction;

[0048] Figure 14 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor structure after the filler layer has been removed along the AA' direction;

[0049] Figure 15 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor structure after the filler layer has been removed along the BB' direction;

[0050] Figure 16 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after the formation of the second capping layer along the AA' direction;

[0051] Figure 17 The semiconductor structure was prepared by the method provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure after the formation of the second capping layer along the BB' direction.

[0052] Explanation of reference numerals in the attached figures:

[0053] 1-Substrate, 11-Pixel unit, 12-Isolation unit, 121-Isolation trench, 122-First isolation layer, 123-Second isolation layer, 124-Air gap structure, 2-Grid structure, 21-Grid opening, 22-Grid frame, 221-First part, 222-Second part, 3-Total reflection part, 4-Grid material layer, 41-Grid trench, 5-First mask layer, 6-Filling layer, 61-Filling material layer, 7-First cover layer, 71-Opening, 8-Second cover layer, 9-Second mask layer. Detailed Implementation

[0054] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0056] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0057] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0058] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0059] Please see Figures 1 to 3 The present invention provides a semiconductor structure, comprising: a substrate 1, a grid structure 2, and a filter unit, wherein the substrate 1 includes a plurality of pixel units 11 spaced apart and arranged in an array; the grid structure 2 is located above the substrate 1, the grid structure 2 includes a plurality of grid openings 21 and a grid frame 22 surrounding the grid openings 21, a total reflection portion 3 is provided in the grid frame 22, and the orthographic projection of the grid openings 21 on the substrate 1 coincides with the orthographic projection of the pixel units 11 on the substrate 1; the filter unit (not shown) is located above the substrate 1 and is located in the grid openings 21.

[0060] It should be noted that Figure 1 The term "total reflection part 3" in this context refers to the overall structure of the total reflection part 3, and does not simply mean that the number of total reflection parts 3 is one.

[0061] In the above example, by setting the grating structure 2 to include multiple grating openings 21 and a grating frame 22 surrounding the grating openings 21, and by providing a total internal reflection part 3 within the grating frame 22, and the filter unit being located above the substrate 1 and within the grating opening 21, the total internal reflection effect of the total internal reflection part 3 can be utilized to effectively suppress the lateral propagation of light between adjacent filter units without reducing the light incident efficiency, ensuring that light accurately passes through the filter unit of the corresponding color, thereby reducing light crosstalk, and also improving the imaging clarity and signal-to-noise ratio of the image sensor without sacrificing photosensitivity. Furthermore, the grating openings 21 in the grating structure 2 are projected onto the substrate 1. The shadow and the orthographic projection of the pixel unit 11 on the substrate 1 coincide, thereby ensuring that the light can be accurately guided to the target pixel unit 11. This reduces light crosstalk and also helps to achieve a compact design, which is particularly suitable for next-generation image sensors with further reduced pixel size, and helps to promote the miniaturization of image sensors. In addition, the grid frame 22 surrounding the grid opening 21 can achieve a cross-connection design, so that the corresponding grid structure 2 and the total reflection part 3 inside the grid structure 2 have high structural stability, which can avoid the problem of structural collapse in subsequent process technology, and significantly improve the overall device reliability and manufacturing yield.

[0062] For example, the substrate 1 includes a plurality of pixel units 11 spaced apart and arranged in an array. The pixel units 11 are used to receive external incident light and generate corresponding electrical signals. The pixel units 11 form a two-dimensional pixel array in the substrate 1 according to a predetermined arrangement rule to achieve high-resolution image acquisition.

[0063] The substrate 1 also includes an isolation unit 12, which isolates adjacent pixel units 11. The isolation unit 12 is used to reduce electrical interference, light leakage and crosstalk between pixel units 11. The isolation unit 12 is used to form electrical and optical isolation between adjacent pixel units 11, thereby improving the imaging quality.

[0064] The isolation unit 12 includes an isolation trench 121 formed in the substrate 1 and located between adjacent pixel units 11. The bottom of the isolation trench 121 is spaced apart from the bottom of the substrate 1. The isolation unit 12 also includes a first isolation layer 122 and a second isolation layer 123 stacked sequentially. The first isolation layer 122 covers the sidewalls of the isolation trench 121 and the upper surface of the substrate 1. The second isolation layer 123 fills the isolation trench 121 and covers the first isolation layer 122. The second isolation layer 123 also has an air gap structure 124. The first isolation layer 122 is made of a high-k metal layer, such as aluminum nitride, tantalum oxide, or other suitable high-k dielectric materials, to improve the dielectric properties of the isolation unit and enhance the electric field shielding capability. The second isolation layer 123 is made of silicon oxide or other suitable materials. The air gap structure 124 is used to further reduce the dielectric constant and effectively improve the isolation effect of the pixel. The isolation unit 12 is designed with isolation trench 121, first isolation layer 122, second isolation layer 123 and embedded air gap structure 124. It achieves excellent electrical insulation performance and parasitic capacitance control capability in a limited space, so as to effectively block the carrier diffusion path and reduce crosstalk effect, which is especially suitable for high-density pixel array environment.

[0065] Furthermore, the substrate 1 also includes a metal interconnect layer (not shown) and an image signal processor (not shown). The image signal processor comprises a substrate and a conductive layer stacked sequentially. The metal interconnect layer is used to realize the horizontal and vertical transmission of pixel electrical signals, and to transmit the electrical signals acquired by the pixel unit 11 to the image signal processor. The metal interconnect layer may include a multilayer metal wiring structure, using copper (Cu), tungsten (W), or aluminum (Al) as the main conductive material, and is insulated by a dielectric layer (such as SiO2 or SiN).

[0066] Image signal processors (ISPs) are used to perform in-situ image processing, improving data processing efficiency and reducing signal transmission power consumption. An ISP includes a substrate and conductive layers stacked sequentially. The substrate forms the basic structure supporting the entire ISP and can be a high-resistivity silicon substrate or other suitable semiconductor material. The conductive layers form logic circuits, memory cells, or arithmetic modules and are connected to the pixel array via metal interconnect layers. The conductive layers include a first metal layer and a second metal layer stacked sequentially. The first metal layer is made of copper or other suitable conductive materials to achieve high-speed, high-density data interconnection. The second metal layer is made of aluminum or other suitable conductive materials to provide low-cost, easy-to-manufacture electrical connections and distributed power paths.

[0067] For example, the grid structure 2 is disposed above the substrate 1 and is used for optical isolation and light guiding control among multiple filter units to improve the imaging clarity and color reproduction of the image sensor.

[0068] For example, the grid structure 2 includes a grid opening 21 and a grid frame 22 surrounding the grid opening 21. The cross-connection design of the grid frame 22 enables the corresponding grid structure 2 and the total reflection part 3 inside the grid structure 2 to have high structural stability, which can avoid the problem of structural collapse in subsequent process technology, and significantly improve the overall device reliability and manufacturing yield. Among them, the orthographic projection of the grid opening 21 on the substrate 1 corresponds one-to-one with the orthographic projection area of ​​the pixel unit 11 on the substrate 1 and completely overlaps, thereby ensuring that the incident light can be accurately guided to the target pixel unit 11 and reducing light crosstalk. It also helps to achieve a compact design of the structure, which is particularly suitable for next-generation image sensors with further reduced pixel size, and helps to promote the miniaturization of image sensors and provide technical support.

[0069] For example, the material of the grid frame 22 may include silicon oxide or other suitable materials with a low refractive index, such as lower than the refractive index of the filter unit, which can play a certain role in suppressing optical crosstalk.

[0070] In one embodiment, the grid frame 22 includes a plurality of first parts 221 spaced apart in a first direction and a plurality of second parts 222 spaced apart in a second direction. The plurality of first parts 221 and the plurality of second parts 222 are intersected and connected in the plane formed by the first direction and the second direction, thereby forming a stable grid structure of the grid frame 22, which significantly improves the structural stability of the grid structure 2. The first direction and the second direction intersect, and exemplarily, the first direction and the second direction are perpendicular to each other.

[0071] In one embodiment, to further enhance the optical isolation effect, a total internal reflection section 3 is provided within the grating frame 22. The total internal reflection section 3 reflects stray light from non-target paths through the internal total internal reflection effect, guiding it away from the pixel area, and can effectively improve the signal-to-noise ratio and contrast of the image sensor without sacrificing photosensitivity.

[0072] In one embodiment, the total reflection portion 3 is located in the first portion 221 and the second portion 222 respectively, and the total reflection portion 3 located in the first portion 221 and the total reflection portion 3 located in the second portion 222 are cross-connected. That is, the total reflection portion 3 is provided in both the first portion 221 and the second portion 222 to form a cross-shaped optical reflection network structure, which can effectively suppress photon crosstalk.

[0073] In one embodiment, the total reflection portion 3 in the first part 221 includes a plurality of total reflection portions 3, which extend in a first direction and are spaced apart in a second direction, and / or the total reflection portion 3 in the second part 222 includes a plurality of total reflection portions 3, which extend in a second direction and are spaced apart in a first direction. That is, the performance of suppressing optical crosstalk is enhanced by the flexible structural design of the total reflection portion 3.

[0074] In one embodiment, the total reflection part 3 includes a sealed air cavity, that is, the total reflection part 3 is suspended in the grid frame 22, forming an air medium layer with extremely low internal refractive index, thereby achieving effective isolation and reflection guidance of light through the total reflection effect. By utilizing the total internal reflection effect of air, photon crosstalk can be controlled without reducing light sensitivity.

[0075] Furthermore, the total reflection part 3 is located in the grating frame 22 and is spaced apart from the air gap structure 124, so as to further ensure the stability of the grating frame 22 while ensuring the light crosstalk suppression performance of the total reflection part 3.

[0076] It should be noted that when the total reflection part 3 is a closed air cavity, the thickness of the grid frame 22 located above the total reflection part 3 needs to be designed as the target thickness to meet the light crosstalk suppression performance of the total reflection part 3. No specific limit is made on this value.

[0077] The filter units are disposed in the grating opening 21, that is, the grating structure 2 is used to isolate adjacent filter units. The filter units and pixel units 11 are correspondingly disposed in the third direction, which intersects with the first direction and the second direction respectively. The filter units include color filtering materials, such as dye layers or pigment-dispersed polymer layers for achieving red (R), green (G) and blue (B) filtering; or spectrally selective elements such as infrared cut-off filters and bandpass filters. The filter units directly fill and cover the grating opening 21 of the grating structure, which can achieve higher precision alignment during the patterning process, avoid color mixing caused by filter misalignment, and effectively reduce the packaging height, making it suitable for thickness-sensitive mobile terminal applications. The filter units are constrained by the geometric boundaries of the grating opening 21, which can obtain better film thickness uniformity and physical support, which helps to improve the process yield. The grating frame 22 isolates the filter units from each other, and together with the internal total reflection part, it can effectively block the stray light incident path between adjacent filter units, further reducing crosstalk. Therefore, by placing the filter unit in the grating opening 21, process compatibility and system integration can be optimized while ensuring optical filtering performance, making it particularly suitable for high-pixel, narrow-pixel-pitch image sensor chips.

[0078] For example, the upper surface of the filter unit has a flat structure to form a uniform light incident surface, thereby improving the microlens matching efficiency.

[0079] Furthermore, the total reflection section 3 may also include other low refractive index materials suitable for total reflection applications, such as silica aerogel, fluorinated polymers, hollow microspheres, etc., to replace or supplement the sealed air cavity structure, thereby flexibly achieving low-loss optical isolation effects under different process conditions or application scenarios.

[0080] Exemplarily, the semiconductor structure also includes a microarray structure (not shown), located above the filter unit and the grid structure 2, for collimating and focusing external incident light, guiding it efficiently into the corresponding pixel unit 11, thereby improving photoelectric conversion efficiency and sensor sensitivity. The microarray structure includes a microlens array, comprising multiple microlens units arranged in a two-dimensional array, each microlens unit corresponding one-to-one with the bottom pixel unit 11 in the vertical direction. Exemplarily, the microlens units have spherical or aspherical contour structures; for example, the microlens units are in the form of convex lenses to achieve focusing of incident light. The material of the microlens array may include transparent polymer materials, such as photosensitive resins, acrylics, polyimides, or inorganic transparent materials such as silicon oxides, fluorides, etc. Furthermore, to improve the imaging consistency of the microarray structure, the radius of curvature, diameter, and spacing of the microlens array can be locally optimized according to different wavelengths (such as RGB) or different pixel sizes, thereby balancing color imaging and luminous flux efficiency.

[0081] Secondly, the microlens array directly covers the top of the grating structure 2, located at the top layer of the light incident path of the pixel unit 11, forming a composite optical channel with layer-by-layer light guiding and level-by-level focusing functions. The semiconductor structure of this application includes a microarray structure, a filter unit, a grating structure 2 containing a total reflection part 3, and a pixel unit 11. It can simultaneously achieve light restriction, filtering, and focusing at multiple levels, effectively improving the light incident efficiency per pixel and enhancing the system's anti-stray light capability. This structure is particularly important given the trend towards miniaturized pixel sizes and higher resolutions. The semiconductor structure provided above, suitable for image sensors, especially back-illuminated image sensors, achieves excellent light collection efficiency and pixel imaging accuracy while ensuring precise optical path guidance. It is particularly suitable for scenarios requiring high sensitivity and low-noise imaging, such as night photography, face recognition, and security monitoring.

[0082] Please see Figure 4 In one embodiment, this application also provides a method for fabricating a semiconductor structure, comprising the following steps:

[0083] Step S1: Provide a substrate 1, which includes a plurality of pixel units 11 spaced apart and arranged in an array;

[0084] Step S2: A grid structure 2 is formed on the substrate 1. The grid structure 2 includes a plurality of grid openings 21 and a grid frame 22 surrounding the grid openings 21. A total reflection part 3 is provided in the grid frame 22, and the orthographic projection of the grid openings 21 on the substrate 1 coincides with the orthographic projection of the pixel unit 11 on the substrate 1.

[0085] Step S3: Form a filter unit in the grid opening 21 above the substrate 1.

[0086] The semiconductor structure fabrication method in the above example produces a grid structure 2 with high mechanical stability, overcoming the problems of easy collapse and structural instability of the total reflection part 3 in the form of a closed air cavity in the prior art. This significantly improves the overall device reliability and manufacturing yield, and has excellent process controllability and structural stability.

[0087] Specifically, please refer to Figures 5 to 17 Steps S1 to S2 are executed, a substrate 1 is provided, the substrate 1 includes a plurality of pixel units 11 spaced apart and arranged in an array; a grid structure 2 is formed above the substrate 1, the grid structure 2 includes a plurality of grid openings 21 and a grid frame 22 surrounding the grid openings 21, a total reflection part 3 is provided in the grid frame 22, and the orthographic projection of the grid openings 21 on the substrate 1 coincides with the orthographic projection of the pixel units 11 on the substrate 1.

[0088] For example, the substrate 1 is further provided with an isolation unit 12, which isolates adjacent pixel units 11. The isolation unit 12 includes an isolation trench 121 formed in the substrate 1 and located between adjacent pixel units 11. The bottom of the isolation trench 121 is spaced apart from the bottom of the substrate 1. The isolation unit 12 also includes a first isolation layer 122 and a second isolation layer 123 stacked in sequence. The first isolation layer 122 covers the sidewall of the isolation trench 121 and the upper surface of the substrate 1. The second isolation layer 123 fills the isolation trench 121 and covers the first isolation layer 122. The second isolation layer 123 is also provided with an air gap structure 124.

[0089] The substrate 1 also includes a metal interconnect layer (not shown) and an image signal processor (not shown).

[0090] For detailed information on the structure of the isolation unit 12, the metal interconnect layer, and the image signal processor, please refer to the description of the relevant embodiments of the semiconductor structure described above. The method of forming the structure of the isolation unit 12, the metal interconnect layer, and the image signal processor is a conventional technique and will not be described in detail here.

[0091] In one embodiment, forming a grid structure 2 over a substrate 1 includes steps S21 to S27:

[0092] Step S21: Form a grid material layer 4 on the substrate 1; wherein, the method for forming the grid material layer 4 includes physical vapor deposition, chemical vapor deposition or other suitable methods; the material of the grid material layer 4 includes silicon oxide or other suitable materials; in this embodiment, the grid material layer 4 is formed on the second isolation layer 123 in the isolation unit 12 of the substrate 1, and the grid material layer 4 is the base material for forming the grid frame 22.

[0093] Step S22: A grid groove 41 is formed in the grid material layer 4. The grid groove 41 is located above the area of ​​the substrate 1 where no pixel unit 11 is provided. The grid groove 41 is the basic groove for the total reflection part 3. Therefore, the number of grid grooves 41 formed can be set according to the required number of total reflection parts 3. In this embodiment, the number of grid grooves 41 formed is multiple and they are spaced apart. Regarding the depth design of the grid groove 41, while satisfying the performance of the subsequent total reflection part 3 formed through the grid groove 41, the bottom of the grid groove 41 is spaced apart from the air gap structure 124 of the isolation unit 12. That is, the grid groove 41 does not penetrate the second isolation layer 123 located above the air gap structure 124. Therefore, the grid groove 41 can penetrate the grid material layer 4 and extend to the second isolation layer 123 at the bottom, or it can not penetrate the grid material layer 4. It can be selected according to the actual situation.

[0094] Then, please refer to Figures 5 to 6Forming grid grooves 41 in the grid material layer 4 includes steps S221 to S223:

[0095] Step S221: A patterned first mask layer 5 is formed on the upper surface of the grid material layer 4;

[0096] Step S222: Based on the patterned first mask layer 5, a grid trench 41 is formed on the grid material layer 4; wherein, the first mask layer 5 includes a photoresist layer; the method of forming the grid trench 41 includes dry etching, wet etching or other suitable methods. In this embodiment, the method of forming the grid trench 41 is dry etching, such as plasma etching, which can form a grid trench 41 with a high aspect ratio and steep sidewalls, thereby ensuring the performance of the corresponding total reflection part 3;

[0097] Step S223: Remove the patterned first mask layer 5;

[0098] Step S23: Forming a filling layer 6 for filling the grid trench 41; the filling layer 6 is used to ensure the smooth progress of subsequent processes and to provide support for subsequent processes. The material of the filling layer 6 includes organic polymers, which have good fluidity and are easy to fill into various small parts of the grid trench 41. It can adapt well to the shape and structure of the grid trench 41, thereby ensuring the integrity and uniformity of the filling and facilitating the formation of a continuous and dense filling layer 6.

[0099] Then, please refer to Figures 7 to 8 The process of forming a filling layer for filling the grid groove 41 includes steps S231 to S232:

[0100] Step S231: Form a filling material layer 61 on the upper surface of the grid material layer 4 to fill the grid groove 41; the method of forming the filling material layer 61 includes chemical vapor deposition, inkjet printing, screen printing or other suitable methods;

[0101] Step S232: Remove the filler material layer 61 located on the upper surface of the grid material layer 4 to form the filler layer 6. Methods for removing the filler material layer located on the upper surface of the grid material layer 4 include dry etching, wet etching, or other suitable methods;

[0102] Step S24: Please refer to Figure 9 A first cover layer 7 is formed to cover the grid material layer 4 and the filler layer 6. The first cover layer 7 is used to ensure that the subsequent process of forming the grid opening 21 does not damage the filler layer 6, and to ensure the stability of the process. The method of forming the first cover layer 7 includes chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the first cover layer 7 includes silicon oxide or other suitable materials.

[0103] Step S25: Please refer to Figure 10 A grid opening 21 is formed in the first cover layer 7 and the grid material layer 4, and the orthographic projection of the grid opening 21 on the substrate 1 coincides with the orthographic projection of the pixel unit 11 on the substrate 1. After the grid opening 21 is formed, the remaining first cover layer 7 and the grid material layer 4 are connected in a grid-like cross-connection. The grid opening 21 is formed by dry etching, wet etching or other suitable methods using a patterned mask layer. Therefore, after the grid opening 21 is formed, the remaining first cover layer 7 and the grid material layer 4 are connected in a grid-like cross-connection. The bottom of the grid opening 21 exposes the second isolation layer 123, and the opening size of the grid opening 21 is set according to the size of the pixel unit 11 and the isolation unit 12, which is not limited here.

[0104] Step S26: Remove the filler layer 6 located in the grid groove 41; the method for removing the filler layer 6 includes an ashing process or other suitable methods;

[0105] The removal of the filling layer 6 located in the grid groove 41 includes steps S261 to S262:

[0106] Step S261: An opening 71 is formed at the intersection of the remaining first cover layer 7 after the formation of the grid opening 21, and the bottom of the opening 71 exposes at least the upper surface of the filler layer 6; the bottom of the opening 71 exposes the filler layer 6 to facilitate the subsequent removal of the filler layer 6, wherein the method of forming the opening 71 includes dry etching, wet etching or other suitable methods.

[0107] Then, please refer to Figures 11 to 13 The process of forming an opening 71 in the first cover layer 7 and the grid material layer 4 includes: forming a patterned second mask layer 9 above the first cover layer 7; forming the opening 71 on the first cover layer 7 based on the patterned second mask layer 9; and removing the second mask layer 9.

[0108] Step S262: Remove the filler layer 6 based on the opening 71; where, please refer to Figures 14 to 15 Removing the filler layer 6 based on the opening 71 includes:

[0109] The ashing process is used to remove the filling layer 6 based on the opening 71. The ashing process is a dry etching technology that usually uses plasma or reactive gas to remove the organic material filling layer 6 through chemical reaction and ion bombardment. The ashing process has a high etching rate for the filling layer 6 made of organic polymer, but has little impact on silicon oxide. It can efficiently remove the filling layer 6 without affecting the grid material layer 4 and the first cover layer 7.

[0110] Step S27: Please refer to Figures 16 to 17A second covering layer 8 is formed above the first covering layer 7, creating sealed grid grooves 41. The grid material layer 4, the first covering layer 7, and the second covering layer 8, connected in a grid pattern, constitute a grid frame 22. The sealed grid grooves 41 within the grid frame 22 constitute a total reflection portion 3. The second covering layer 8 covers the sidewalls of the grid material layer 4 after the filler layer 6 has been removed and the upper surface of the first covering layer 7, thus sealing the air cavity formed by the grid grooves 41, which is the total reflection portion 3, forming a final closed total reflection cavity. Therefore, the grid material layer 4, the first covering layer 7, and the second covering layer 8 constitute a connected grid frame 22 to ensure the stability of the grid structure 2. For example, the material of the second covering layer 8 may include silicon oxide or other suitable materials.

[0111] In this structure, the grid frames 22 spaced apart in the first direction constitute multiple first parts 221, and the grid frames 22 spaced apart in the second direction constitute multiple second parts 222. The multiple first parts 221 and the multiple second parts 222 are intersected and connected in the plane formed by the first direction and the second direction, thereby forming a stable grid frame 22 mesh structure, which significantly improves the structural stability of the grid structure 2.

[0112] The above-described method for forming the grid structure 2, by combining a controllable filling layer 6 with a closed first covering layer 7 and a second covering layer 8, can produce a grid frame 22 with a high aspect ratio and high mechanical stability, as well as a total reflection part 3 located within the grid frame 22. This overcomes the problems of easy collapse and structural instability of the total reflection part 3, which is in a closed air cavity state in the prior art, and significantly improves the overall reliability and manufacturing yield of the device. It possesses excellent process controllability and structural stability.

[0113] In one embodiment, please refer to... Figures 2 to 3 After forming a second cover layer 8 with a top opening of a sealing grid groove 41 above the first cover layer 7, the process further includes step S28: thinning the second cover layer 8 to reduce the optical path difference problem and enhance the flatness of the structure. The method for thinning the second cover layer 8 includes chemical mechanical masking, dry etching, wet etching, or other suitable methods. It should be noted that the amount of thinning of the second cover layer 8 should ensure the stability of the grid frame. The specific value is not limited here and can be selected according to the actual situation.

[0114] Specifically, step S3 is performed to form a filter unit in the grid opening 21 above the substrate 1.

[0115] For example, the material of the filter unit can be deposited and patterned by inkjet printing, spin coating, exposure and development, etc. For example, the upper surface of the filter unit has a flat structure to form a uniform light incident surface, thereby improving the efficiency of subsequent microlens matching.

[0116] In one embodiment, the method for fabricating the semiconductor structure further includes forming a microlens array or other optical structure above the filter unit. The microlens array can be fabricated by methods such as thermal reflow forming, photolithography reflow, nanoimprinting, or molding.

[0117] It should be understood that, although Figure 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 4 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0118] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0119] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate comprising a plurality of pixel units spaced apart and arranged in an array; A grid structure is formed above the substrate. The grid structure includes a plurality of grid openings and a grid frame surrounding the grid openings. A total reflection part is provided in the grid frame, and the orthographic projection of the grid openings on the substrate coincides with the orthographic projection of the pixel unit on the substrate. The formation of a grid structure above the substrate includes: A grid material layer is formed on the substrate; A grid groove is formed in the grid material layer, and the grid groove is located above the area of ​​the substrate where the pixel unit is not disposed; A filling layer is formed to fill the grooves of the grid; A first cover layer is formed covering the grid material layer and the filler layer; A grid opening is formed in the first cover layer and the grid material layer, the orthographic projection of the grid opening on the substrate coincides with the orthographic projection of the pixel unit on the substrate, and the remaining first cover layer and the grid material layer after the grid opening is formed are connected in a grid pattern. Remove the filler layer located within the grid groove; A second covering layer is formed above the first covering layer to seal the grid grooves, wherein the grid material layer, the first covering layer and the second covering layer, which are connected in a grid pattern, constitute the grid frame, and the grid grooves sealed in the grid frame constitute the total reflective portion; The removal of the filler layer located within the grid trench includes: An opening is formed at the intersection of the remaining first covering layer after the formation of the grid opening, and the bottom of the opening exposes at least the upper surface of the filling layer; Remove the filling layer based on the opening; The filler layer is made of an organic polymer, wherein removing the filler layer based on the opening includes: The filling layer is removed through an ashing process based on the opening. A filter unit is formed in the grid opening above the substrate.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming a second cover layer that seals the grid trench over the first cover layer, the method further includes: Thin the second cover layer.

3. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method for preparing a semiconductor structure as described in any one of claims 1 to 2, and the semiconductor structure comprises: The substrate comprises multiple pixel units spaced apart and arranged in an array; A grid structure is located above the substrate. The grid structure includes multiple grid openings and a grid frame surrounding the grid openings. A total reflection part is provided in the grid frame, and the orthographic projection of the grid openings on the substrate coincides with the orthographic projection of the pixel unit on the substrate. A filter unit is located above the substrate and within the grid opening.

4. The semiconductor structure according to claim 3, characterized in that, The grid frame includes a first part and a second part spaced apart in a second direction. The first part and the second part are intersected and connected on a plane formed by the first direction and the second direction, and the first direction intersects the second direction.

5. The semiconductor structure according to claim 4, characterized in that, The total reflection portions are located in the first part and the second part respectively, and the total reflection portions located in the first part and the total reflection portions located in the second part are cross-connected.

6. The semiconductor structure according to claim 5, characterized in that, The total reflection portion located within the first part includes a plurality of such portions, and the plurality of total reflection portions extend in the first direction and are spaced apart in the second direction. And / or, the total reflection portion located within the second portion includes a plurality of total reflection portions, and the plurality of total reflection portions extend in the second direction and are spaced apart in the first direction.

7. The semiconductor structure according to claim 3, characterized in that, The total reflection part includes a sealed air cavity.

Images