Active mixer with enhanced image rejection ratio (IRR)

Abstract

A communication system comprising a passive quadrature generator directly connected to an in-phase (I) mixer and a quadrature (Q) mixer; an I-LO amplitude detection circuit connected to the passive quadrature generator and connected to the I-mixer, and a Q-LO amplitude detection circuit connected to the passive quadrature generator and connected to the Q-mixer, the I-LO amplitude detection circuit configured to detect an I-LO amplitude, and the Q-LO amplitude detection circuit configured to detect a Q-LO amplitude; and a combining and integrating circuit configured to receive the detected I-LO amplitude and the detected Q-LO amplitude, and to generate an I-LO DC bias voltage for biasing the I mixer and a Q-LO DC bias voltage for biasing the Q mixer.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to mixers for transceivers. Background Technology

[0002] Wireless communication devices and technologies are becoming increasingly prevalent, including those operating at millimeter-wave (mmW) and sub-terahertz (subTHz) frequencies. Wireless communication devices typically transmit and / or receive communication signals. In radio frequency (RF) transceivers, the communication signal is typically amplified and transmitted by the transmitting section, and the received communication signal is amplified and processed by the receiving section. Transceivers used for communication in 5G and 6G applications can communicate using millimeter-wave (mmW) frequency signals and sub-THz frequencies, and can utilize so-called zero-IF (ZIF) or low-IF architectures.

[0003] The ZIF architecture is an architecture that directly upconverts baseband information signals into radio frequency (RF) signals for transmission and directly downconverts received RF signals back into baseband.

[0004] Spectrum-efficient modulation schemes (such as 16-QAM and 64-QAM) use in-phase (I) and quadrature (Q) (IQ) mixers and local oscillator (LO) generation circuitry to modulate and up-convert / down-convert communication signals.

[0005] The ZIF architecture offers numerous advantages at millimeter-wave and sub-THz frequencies, particularly when handling multiple RF frequencies. However, it also has drawbacks, including a lower image rejection ratio (IRR) that can degrade signal quality and a higher error vector magnitude (EVM) caused by IQ errors in the mixer and LO generation circuitry. For example, at sub-THz frequencies, the factory-calibrated IRR of a ZIF receiver is... cal The specification can be greater than 40dB. This is to achieve such an IRR at frequencies below THz. cal The specification, for example, a pre-calibrated IRR (IRR0) specification can be at least 25 dB. Such an IRR specification may be difficult to achieve at millimeter waves and sub-THz frequencies. Summary of the Invention

[0006] The various embodiments of the systems, methods, and apparatuses within the scope of the appended claims each have several aspects, none of which individually fully encompasses the desired properties described herein. Certain prominent features are described herein without limiting the scope of the appended claims.

[0007] Details of one or more specific embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. It should be noted that the relative dimensions in the following drawings are not to scale.

[0008] One aspect of this disclosure provides a communication system comprising a passive quadrature generator directly connected to an in-phase (I) mixer and a quadrature (Q) mixer; an ILO amplitude detection circuit connected to the passive quadrature generator and the I mixer; a QLO amplitude detection circuit connected to the passive quadrature generator and the Q mixer, the ILO amplitude detection circuit being configured to detect ILO amplitude and the QLO amplitude detection circuit being configured to detect QLO amplitude; and a combination and integration circuit configured to receive the detected ILO amplitude and the detected QLO amplitude, and to generate an ILO DC bias voltage for biasing the I mixer and a QLO DC bias voltage for biasing the Q mixer.

[0009] Another aspect of this disclosure provides a method for mixing a signal, the method comprising detecting the in-phase (I) LO amplitude and the quadrature (Q) LO amplitude; generating an I LO DC bias voltage based on the I LO amplitude; generating a Q LO DC bias voltage based on the Q LO amplitude; and applying the I LO DC bias voltage to an I mixer and the Q LO DC bias voltage to a Q mixer to improve the image rejection ratio (IRR) of the I mixer and the Q mixer.

[0010] Another aspect of this disclosure provides an apparatus for mixing signals, the apparatus including components for detecting the in-phase (I) LO amplitude and the quadrature (Q) LO amplitude; components for generating an I LO DC bias voltage based on the I LO amplitude; components for generating a Q LO DC bias voltage based on the Q LO amplitude; and components for applying the I LO DC bias voltage to an I mixer and for applying the Q LO DC bias voltage to a Q mixer to improve the image rejection ratio (IRR) of the I mixer and the Q mixer. Attached Figure Description

[0011] In the accompanying drawings, unless otherwise indicated, similar reference numerals are used throughout the various views to refer to similar parts. For reference numerals with letter characters, such as "102a" or "102b", the letter characters distinguish two similar parts or elements in the same drawing. When the aim is to have the reference numerals cover all parts with the same reference numerals in all drawings, the letter characters of the reference numerals may be omitted.

[0012] Figure 1 This is a diagram illustrating communication between a wireless device and a wireless communication system.

[0013] Figure 2A This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented.

[0014] Figure 2B This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented.

[0015] Figure 2C This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented.

[0016] Figure 3 This is a block diagram of a mixer circuit according to an exemplary embodiment of the present disclosure.

[0017] Figure 4A This is based on an exemplary embodiment of the present disclosure. Figure 3 A block diagram of an LO amplitude detection circuit, which has independent bias loops for each of I and Q.

[0018] Figure 4B This is based on an exemplary embodiment of the present disclosure. Figure 3 A block diagram of an alternative exemplary embodiment of an LO amplitude detection circuit having independent bias loops for each of I and Q.

[0019] Figure 4C This is based on an exemplary embodiment of the present disclosure. Figure 3 A block diagram of an alternative exemplary embodiment of an LO amplitude detection circuit having independent bias loops for each of I and Q.

[0020] Figure 5A This is a block diagram of a mixer core according to an exemplary embodiment of the present disclosure.

[0021] Figure 5B This is a block diagram of an alternative exemplary embodiment of the mixer core according to the exemplary embodiment of this disclosure.

[0022] Figure 6 yes Figure 3A diagram illustrating an exemplary embodiment of an arithmetic combination element.

[0023] Figure 7 yes Figure 3 A diagram illustrating an exemplary embodiment of an arithmetic combination element.

[0024] Figure 8 yes Figure 3 mixer circuit and Figure 5B A diagram showing an alternative exemplary implementation of the mixer core portion.

[0025] Figure 9 This is a flowchart illustrating an example of the operation of a method for mixing signals.

[0026] Figure 10 This is a functional block diagram of a device used for mixing signals.

[0027] Figure 11 This is a flowchart illustrating an example of the operation of a method for mixing signals.

[0028] Figure 12 This is a functional block diagram of a device used for mixing signals. Detailed Implementation

[0029] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred or superior to other aspects.

[0030] In a communication transceiver, a local oscillator (LO) signal can be used to up-convert or down-convert one or more mmW frequency signals and sub-THz frequency signals.

[0031] In millimeter-wave and sub-THz communication frequencies, high-efficiency IQ LO generation circuits can be used at carrier frequencies f 载波 A voltage-controlled oscillator (VCO) operating at / N, in conjunction with an xN frequency multiplier and a passive 0° / 90° phase shifter, generates I and Q LO signals. Typical values ​​for the frequency multiplier N are 3, 4, 6, 8, and 9.

[0032] In communication transceivers, signal up-conversion and down-conversion can occur using a direct conversion architecture, such as a low-IF (LIF) or zero-IF (ZIF) architecture. In communication transceivers using a direct conversion architecture (e.g., employing low-IF (LIF) or zero-IF (ZIF)) and operating at millimeter-wave (mmW) frequencies or below THz, the local oscillator (LO) signal used for signal up-conversion and down-conversion occurs at extremely high frequencies, ranging from tens of gigahertz (GHz) to 300 GHz. At these RF frequencies, it is difficult to provide the mixer conversion gain and phase matching to meet the desired image rejection allocated in the error vector magnitude (EVM) budget. This error vector magnitude (EVM) budget determines the maximum spectral efficiency of the communication signal.

[0033] The exemplary embodiments of this disclosure enhance the mixer's suppression of IQ LO imbalance in the presence of IQ LO imbalance, thereby improving the pre-calibration IRR0.

[0034] The exemplary embodiments of this disclosure achieve the IRR0 level required for calibration-free 16QAM modulation at frequencies below THz. 64QAM can be supported with calibration. If 64QAM is not typically used in the sub-THz frequency band, the exemplary embodiments of this disclosure can omit mixer IRR calibration.

[0035] Exemplary embodiments of this disclosure reduce the total silicon area (area of ​​the mixer and LO paths) by allowing the quadrature mixer (QH) to be directly connected to the mixer switching core without impedance matching or the use of an inductor to resonate the FET capacitor.

[0036] Exemplary embodiments of this disclosure limit quadrature mixing phase imbalance by using termination resistors to reduce the sensitivity of the quadrature mixer to reactive loads that may be caused by mixer FET capacitance.

[0037] Exemplary embodiments of this disclosure provide independent in-phase and quadrature signal feedback loops to reduce the variation in FET capacitance under large LO swing voltages by generating a fixed average drain current on the mixer FET.

[0038] In an exemplary embodiment, a real-time simulation technique is disclosed for compensating for local oscillator IQ errors in a ZIF receiver, resulting in an uncalibrated IRR of approximately 25 dB for millimeter-wave and sub-THz communication systems.

[0039] Exemplary embodiments of this disclosure control the bias current to keep the operating point of the IQ mixer constant over the LO frequency range; and use a passive IQ LO quadrature mixing structure to suppress the inherent imbalance between the LO signals transmitted to the I and Q sides of the mixer.

[0040] Figure 1 This diagram illustrates communication between wireless device 110 and wireless communication system 120. Wireless communication system 120 can be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G NR (New Radio) system, or some other wireless system. The CDMA system can implement Wideband CDMA (WCDMA), CDMA 1X, Evolved Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, Figure 1 A wireless communication system 120 is shown, comprising two base stations 130 and 132 and a system controller 140. Generally, a wireless communication system may include any number of base stations and any set of network entities.

[0041] Wireless device 110 may also be referred to as user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 may be a cellular phone, smartphone, tablet device, wireless modem, personal digital assistant (PDA), handheld device, laptop computer, smartbook, netbook, tablet computer, cordless phone, medical device, automobile, device configured to connect to one or more other devices (e.g., via the Internet of Things), wireless local loop (WLL) station, Bluetooth device, etc. Wireless device 110 may communicate with wireless communication system 120. Wireless device 110 may also receive signals from broadcast stations (e.g., broadcast station 134) and / or may communicate with satellites (e.g., one or more satellites 150 in a Global Navigation Satellite System (GNSS) or satellites capable of receiving signals from wireless device 110, etc. Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 802.15, 5G, Sub6 5G, 6G, UWB, etc.

[0042] Wireless device 110 may support carrier aggregation, such as that described in one or more LTE or 5G standards. In some implementations, carrier aggregation is used to transmit a single data stream on multiple carriers, as opposed to separate carriers used for each data stream. Wireless device 110 is capable of operating in a variety of communication frequency bands, including those used by LTE, WiFi, 5G, or other communication frequency bands within a wide frequency range. Wireless device 110 is also capable of communicating directly with other wireless devices without communicating through a network.

[0043] Generally, carrier aggregation (CA) can be classified into two types: intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same frequency band. Inter-band CA refers to operation on multiple carriers in different frequency bands.

[0044] Figure 2A This is a block diagram illustrating a wireless device 200 in which exemplary technologies of the present disclosure may be implemented. The wireless device 200 may be, for example, Figure 1 The illustrated implementation scheme of wireless device 110.

[0045] Figure 2A An example of a transceiver 220 with a transmitter 230 and a receiver 250 is shown. Generally, the conditioning of the signals in the transmitter 230 and receiver 250 can be performed by one or more stages such as amplifiers, filters, up-converters, down-converters, etc. These circuit blocks are based on... Figure 2A The configurations shown are arranged differently. Furthermore, Figure 2A Other circuit blocks, not shown, can also be used to regulate the signals in transmitter 230 and receiver 250. Unless otherwise indicated, Figure 2A Any signal in any of the other diagrams in the attached figures may be single-ended or differential. Figure 2A Some circuit blocks in the code can also be omitted.

[0046] exist Figure 2A In the example shown, wireless device 200 typically includes transceiver 220 and data processor 210. Data processor 210 may include processor 296 operatively coupled to memory 298. Memory 298 may be configured to store data and program code generally shown using reference numeral 299, and may typically include analog and / or digital processing components. Processor 296 and memory 298 may cooperate to control, configure, program, or otherwise fully or partially control some or all of the operation of embodiments of the TX LO leakage calibration circuit described herein.

[0047] Transceiver 220 includes a transmitter 230 and a receiver 250 supporting bidirectional communication. Generally, wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0048] Transmitters or receivers can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multiple stages of frequency conversion between radio frequency (RF) and baseband; for example, for a receiver, this might involve switching from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can utilize different circuit blocks and / or have different requirements. Figure 2A In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0049] In the transmission path, data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting digital signals generated by data processor 210 into I analog output signals and Q analog output signals (e.g., I analog output signals and Q analog output signals) for further processing. In other embodiments, DACs 214a and 214b are included in transceiver 220, and data processor 210 provides data (e.g., for I and Q) digitally to transceiver 220.

[0050] Within transmitter 230, baseband (e.g., low-pass) filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove unwanted image frequencies (sometimes also called mirrors) caused by the preceding digital-to-analog conversion. Amplifiers (Amps) 234a and 234b amplify the signals from baseband filters 232a and 232b, respectively, and provide the I and Q baseband signals. Upconverter 240, with upconverters 241a and 241b, uses the I TXLO and Q TXLO signals from transmit (TX) local oscillator (LO) signal generator 290 to upconvert the I and Q baseband signals, and provides the upconverted signals. Filter 242 filters the upconverted signals to remove unwanted mixing products and noise in the receive band caused by frequency upconversion. Power amplifier (PA) 244 amplifies the signal from filter 242 to obtain the desired output power level and provide the transmit RF signal. The transmitted RF signal can be routed through a duplexer or switch 246 and transmitted via antenna 248. Although the examples discussed herein utilize I and Q signals, those skilled in the art will understand that components of the transceiver can be configured to utilize polarity modulation.

[0051] In the receiving path, antenna 248 receives communication signals and provides the received RF signal, which can be routed through duplexer or switch 246 and provided to low-noise amplifier (LNA) 252. Duplexer 246 is designed to operate with specific RX and TX duplexer frequencies, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signal.

[0052] Downconverter mixers 261a and 261b in downconverter 260 mix the output of filter 254 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from receive (RX) LO signal generator 280 to generate I baseband and Q baseband signals. The I baseband and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by baseband (e.g., low-pass) filters 264a and 264b to obtain I analog input signals and Q analog input signals, which are provided to data processor 210. In the illustrated exemplary embodiment, data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signals into digital signals to be further processed by data processor 210. In some embodiments, ADCs 216a and 216b are included in transceiver 220 and provide data digitally to data processor 210.

[0053] exist Figure 2A In this configuration, TX LO signal generator 290 generates I TX LO and Q TX LO signals for up-conversion, while RX LO signal generator 280 generates I RX LO and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from LO signal generator 280.

[0054] The wireless device 200 may support carrier aggregation (CA) and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies, and / or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. However, those skilled in the art will understand that the aspects described herein may be implemented in systems, devices, and / or architectures that do not support carrier aggregation.

[0055] Figure 2AThe transceiver 220 is functionally illustrated in the document, and the illustrated configuration may or may not represent the physical device configuration in certain specific implementations. For example, as described above, the transceiver 220 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver 220 is implemented on a substrate or board (such as a printed circuit board (PCB)) having various modules, chips, and / or components. For example, the power amplifier 244, filter 242, and duplexer 246 may be implemented in separate modules or as discrete components, while the remaining components illustrated in the transceiver 220 may be implemented in a single transceiver chip.

[0056] Power amplifier 244 may include one or more stages, such as driver stages, power amplifier stages, or other components that may be configured to amplify communication signals at one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, power amplifier 244 may be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0057] In exemplary implementations of the superheterodyne architecture, PA 244 and LNA 252 (and in some examples, filters 242 and 254) may be implemented separately from other components in transmitter 230 and receiver 250 (e.g., on a millimeter-wave integrated circuit). Figure 2B The example superheterodyne architecture is illustrated in the figure.

[0058] Figure 2B This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented. Figure 2B Certain components of the wireless device 200a (e.g., those indicated by the same reference numerals) may be similar to... Figure 2A Configure those components in the wireless device 200 shown, and for Figure 2B Descriptions of items with the same number will not be repeated.

[0059] Wireless device 200a is an example of a heterodyne (or superheterodyne) architecture, in which upconverter 240 and downconverter 260 are configured to process communication signals between baseband and intermediate frequency (IF). The IF signal may be a low IF (LIF) signal. For example, upconverter 240 may be configured to provide an IF signal to upconverter 275. In an exemplary embodiment, upconverter 275 may include upconverter mixer 276. Summation function 278 of upconverter 240 combines the I and Q outputs of upconverter 240 and provides a non-quadrature signal to mixer 276. The combined signal may be single-ended or differential. Mixer 276 is configured to receive the IF signal from upconverter 240 and the TX RF LO signal from TX RF LO signal generator 277, and provide the upconverted RF signal to phase shift circuit 281. Although PLL 292 is in Figure 2B The PLL is exemplified as being shared by signal generators 290 and 277, but a corresponding PLL can be implemented for each signal generator.

[0060] In an exemplary embodiment, the components in the phase shift circuit 281 may include one or more adjustable or variable phased array elements, and may receive one or more control signals from the data processor 210 via connection 294, and operate the adjustable or variable phased array elements based on the received control signals.

[0061] In an exemplary embodiment, phase shift circuit 281 includes phase shifters 283 and phased array elements 287. Although three phase shifters 283 and three phased array elements 287 are shown for illustrative purposes, phase shift circuit 281 may include more or fewer phase shifters 283 and phased array elements 287. For example, one or two arrays of four or five antennas and corresponding phase shifters / phased array elements may be implemented.

[0062] Each phase shifter 283 can be configured to receive an RF transmit signal from the upconverter 275, change its phase by a certain amount, and provide an RF signal to a corresponding phased array element 287. Each phased array element 287 may include transmit and receive circuitry, including one or more filters, amplifiers, drive amplifiers, and / or power amplifiers. In some embodiments, the phase shifter 283 may be integrated into the corresponding phased array element 287.

[0063] The output of phase shift circuit 281 is provided to antenna array 248. In an exemplary embodiment, antenna array 248 includes a plurality of antennas, typically corresponding to the number of phase shifters 283 and phased array elements 287, such that each antenna element is coupled to a corresponding phased array element 287. In an exemplary embodiment, phase shift circuit 281 and antenna array 248 may be referred to as a phased array.

[0064] In the receiving direction, the output of phase shift circuit 281 is provided to downconverter 285. In an exemplary embodiment, downconverter 285 may include downconverter mixer 286. In an exemplary embodiment, mixer 286 downconverts the received RF signal provided by phase shift circuit 281 to an IF signal based on the RX RF LO signal provided by RX RF LO signal generator 279. I / Q generation function 291 of downconverter 260 receives the IF signal from mixer 286 and generates I and Q signals in downconverter 260, which downconverts the IF signal to baseband, as described above. Although PLL 282 is in Figure 2B The PLL is exemplified as being shared by signal generators 280 and 279, but a corresponding PLL can be implemented for each signal generator.

[0065] In some embodiments, the upconverter 275, downconverter 285, and phase shift circuit 281 are implemented on a common IC. In some embodiments, although the summation function 278 and the I / Q generation function 291 are implemented separately from mixers 276 and 286, such that mixers 276, 286, and phase shift circuit 281 are implemented on a common IC, the summation function 278 and the I / Q generation function 291 are not implemented on the common IC (e.g., the summation function 278 and the I / Q generation function 291 are implemented in another IC coupled to the IC having mixers 276, 286). In some embodiments, LO signal generators 277, 279 are included in a common IC. In some embodiments where the phase shift circuit is implemented on a common IC having 276, 286, 277, 278, 279, and / or 291, the common IC and antenna array 248 are included in a module that can be coupled to other components of transceiver 220 via connectors. In some implementations, the phase shift circuit 281 (e.g., a chip on which the phase shift circuit 281 is implemented) is coupled to the antenna array 248 via interconnects. For example, components of the antenna array 248 may be implemented on a substrate and coupled to an integrated circuit implementing the phase shift circuit 281 via flexible printed circuitry, or the integrated circuit may be mounted on the other side of the substrate.

[0066] In some implementation schemes, Figure 2A The illustrated architecture and Figure 2B The illustrated architecture is implemented within the same device. For example, wireless devices 110 or 200 can be configured to use... Figure 2A The illustrated architecture communicates with signals having frequencies below approximately 7 GHz (e.g., the FR1 band) and uses... Figure 2B The illustrated architecture communicates with signals at frequencies higher than approximately 24 GHz. In devices implementing these two architectures, Figure 2A and Figure 2BOne or more components with the same number can be shared between the two architectures. For example, a signal that has been directly down-converted from RF to baseband and a signal that has been down-converted from RF to baseband by an IF stage can both be filtered by the same baseband filter 264. In other embodiments, a first version of filter 264 is included in the device implementation. Figure 2A In the architecture section, and the second version of filter 264 is included in the device implementation. Figure 2B The architecture is described in this document. While certain example frequencies are described herein, other specific implementations are possible. For example, a direct conversion architecture can be used to transmit and / or receive signals with frequencies higher than approximately 20 GHz (e.g., with mmW frequencies). In such implementations, for example, a phased array can be implemented within the direct conversion architecture.

[0067] Figure 2C This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented. Figure 2C Some components of the wireless device 200b (e.g., indicated by the same reference numerals) may be similar to Figure 2A The wireless device 200 and / or shown Figure 2B Configure those components in the wireless device 200a shown, and... Figure 2C Descriptions of items with the same number will not be repeated.

[0068] Figure 2C The wireless device 200b incorporates a phase shift circuit 281 in its direct conversion architecture. Figure 2B As shown in the diagram, the mmW transmitted signal undergoes up-conversion and down-conversion between baseband and RF without the need for intermediate frequency (IF) signal conversion. For example, Figure 2C The LO signal in the architecture can include signals with frequencies of tens of GHz or above 100 GHz.

[0069] In some embodiments, the upconverter 240, downconverter 260, and phase shift circuit 281 are implemented on a common IC. In some embodiments, LO signal generators 280 and 290 are included in the common IC. In some embodiments, the common IC and antenna array 248 are included in a module that can be coupled to other components of transceiver 220 via connectors. In some embodiments, phase shift circuit 281 (e.g., a chip on which phase shift circuit 281 is implemented) is coupled to antenna array 248 via interconnects, or both are mounted on a substrate. For example, components of antenna array 248 may be implemented on the substrate and coupled to the integrated circuit implementing phase shift circuit 281 via flexible printed circuitry, or the integrated circuit may be mounted on the other side of the substrate.

[0070] Figure 3This is a block diagram of a mixer circuit 300 according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the mixer circuit 300 may be configured as an active mixer circuit. In an exemplary embodiment, the mixer circuit 300 may include a passive quadrature generator 304, a Q mixer 312, an I mixer 322, a Q LO amplitude detection circuit 330, an I LO amplitude detection circuit 340, and a combination and integrator element 350. In an exemplary embodiment, the combination and integrator element 350 may be an arithmetic combination and integrator circuit. An exemplary embodiment of the passive quadrature generator 304 is a quadrature mixing circuit.

[0071] The passive quadrature generator 304 is derived from, for example, the RX LO signal generator 280 or the TX LO signal generator 290 ( Figure 2C The mixer 312 receives the LO input signal LO_in and provides quadrature LO signals. For example, a differential quadrature (Q) LO signal LO_Q is provided on connections 351 and 352; and a differential in-phase (I) LO signal LO_I is provided on connections 353 and 354. The Q mixer 312 receives the Q LO input signal through nodes 356 and 357; and the I mixer 322 receives the I LO input signal through nodes 358 and 359.

[0072] Q mixer 312 receives the differential RF input signal RFin_Q via connections 313 and 314, and provides the differential baseband output signal BBout_Q via connections 316 and 317. I mixer 322 receives the differential RF input signal RFin_I via connections 323 and 324, and provides the differential baseband output signal BBout_I via connections 326 and 327.

[0073] In an exemplary embodiment, the Q LO amplitude detection circuit 330 is connected to the quadrature LO_Q signal at nodes 356 and 357; and the I LO amplitude detection circuit 340 is connected to the in-phase LO_I signal and the vLOin_m signal at nodes 358 and 359. An output referred to as xQ is provided from the Q LO amplitude detection circuit 330 to the arithmetic combination and integration element 350; and an output referred to as xI is provided from the I LO amplitude detection circuit 340 to the arithmetic combination and integration element 350. The output xQ indicates the Q LO amplitude detected by the Q LO amplitude detection circuit 330, and the output xI indicates the I LO amplitude detected by the I LO amplitude detection circuit 340.

[0074] In an exemplary embodiment, the arithmetic combination and integrator 350 receives the detected Q LO amplitude (xQ) and the detected I LO amplitude (xI), and provides a weighted time-averaged value yQ_bar to the Q mixer 312 via connection 366 (e.g., via a first differential termination resistor connected to the passive quadrature generator 304), and provides a weighted time-averaged value yI_bar to the I mixer 322 via connection 368 (e.g., via a second differential termination resistor connected to the passive quadrature generator 304). The weighted time-averaged value yQ_bar is also provided back to the Q LO amplitude detection circuit 330, and the weighted time-averaged value yI_bar is also provided back to the I LO amplitude detection circuit 340. In an exemplary embodiment, the arithmetic combination and integrator 350 performs integration over time to produce time-averaged values ​​yI_bar and yQ_bar. The value yQ_bar may be referred to as the Q LO DC bias voltage, and the value yI_bar may be referred to as the I LO DC bias voltage.

[0075] In an exemplary embodiment, the arithmetic combination and integrator element 350 combines the outputs (xQ and xI) of the Q LO amplitude detection circuit 330 and the I LO amplitude detection circuit 340 to provide control voltages yQ_bar and yI_bar. These control voltages represent DC biases that can be applied to the Q mixer 312 and I mixer 322 via differential termination resistors connected to the passive quadrature generator 304, respectively, to optimize the image rejection ratio (IRR) of the IQ mixer comprising the Q mixer 312 and the I mixer 322. Thus, the mixer core's suppression of LO imbalance is enhanced without needing to directly improve the LO imbalance at the passive quadrature generator 304. Reference Figure 4A Further description of the differential termination resistor.

[0076] Figure 4A It has Figure 3 LO amplitude detection circuit 330 and Figure 3 A block diagram of the bias circuit 400 for a portion of the arithmetic combination and integrator element 350. The QLO amplitude detection circuit 330 and portion 350a of the arithmetic combination and integrator element 350 are configured to process the Q signal. The bias circuit 400 shows a separate bias loop 435 for the Q signal; however, the bias circuit and separate bias loop for the I signal will be similar.

[0077] In an exemplary embodiment, the bias circuit 400 is Figure 3 A detailed version of a portion of the mixer circuit 300, which includes additional details of the QLO amplitude detection circuit 330 and portions of the arithmetic combination and integrator element 350; however, another iteration of the bias circuit 400 ( Figure 4A(Not shown in the image) can be operated as part of the I LO amplitude detection circuit 340 and the arithmetic combination and integration element 350 capable of processing I signals.

[0078] In an exemplary embodiment, bias circuit 400 includes a current source 402 connected to a supply voltage VDDx at node 437. Voltage VDDx is a supply voltage higher than the supply voltage VDD. In an exemplary embodiment, the values ​​of VDD and VDDx may vary depending on the specific implementation and semiconductor process. In an exemplary embodiment, bias circuit 400 is used to maintain the point (node ​​362) connected to current source 402 at a value equal to the main mixer core supply voltage value VDD, such that node 362 has a voltage equal to VDD. Bias circuit 400 also includes transistors 404, 406, 408, and 410. In an exemplary embodiment, transistors 404 and 406 may be P-type devices, and transistors 408 and 410 may be N-type devices. In an exemplary embodiment, the source of transistor 404 and the source of transistor 406 may be connected to node 362, which in this exemplary embodiment represents the value xQ ( Figure 3 In this example, the voltage value (xQ) at node 362 is driven by bias circuit 400 to match the supply voltage VDD at node 427. The drain and gate of transistor 404 are connected together, and the drain and gate of transistor 406 are connected together to simulate... Figure 5A The corresponding connections of transistors 504 and 506 are shown. The drain of transistor 404 is connected to the drain of transistor 408. The drain of transistor 406 is connected to the drain of transistor 410. The sources of transistors 408 and 410 are grounded.

[0079] The differential LO_Q signals are at nodes 356 and 357 respectively. Figure 3 The LO_Q signal is provided at 356 and 357, and is supplied to nodes 436 and 438 via capacitors 428 and 434. The positive and negative terminals of LO_Q are labeled vLOin_p and vLOin_m at nodes 356 and 357, respectively. Capacitors 428 and 438 are series-coupled capacitors that allow only extremely high-frequency LO signals to pass through, and they are also used to reduce the load applied to the passive quadrature generator 304. Figure 3 The effective shunt capacitive load on the passive quadrature generator 304 is reduced, thereby reducing the load phase imbalance of the passive quadrature generator 304. The gate of transistor 408 is connected to node 436, and the gate of transistor 410 is connected to node 438.

[0080] Resistor 426 is also connected between nodes 436 and 443, and resistor 432 is connected between nodes 438 and 443. Capacitor 446 connected between node 447 and system ground and resistor 448 connected between node 447 and node 443 form a low-pass filter. In an alternative exemplary embodiment, resistors 426 and 432 and capacitors 428 and 434 can be omitted, and the LO_Q signals vLOin_p and vLOin_m can be directly connected to nodes 436 and 438, respectively. This alternative exemplary embodiment in Figure 4B As shown in the image.

[0081] In an exemplary embodiment, resistor 442 is connected between nodes 356 and 447, and resistor 444 is connected between nodes 357 and 447. In an exemplary embodiment, resistors 442 and 444 form a so-called differential termination resistor. In an exemplary embodiment, the approximately 100-ohm values ​​of resistors 442 and 444 limit the passive quadrature generator 304 ( Figure 3 The quadrature mixing phase imbalance may be caused by the direct capacitive load of mixers 312 and 322. In an exemplary embodiment, the phase imbalance is located at ports 356 (vLOin_p) and 357 (vLOin_m) (LO_Q of passive quadrature generator 304). Figure 3 The differential termination resistors 442 and 444 at nodes 356 and 357 (and nodes 358 and 359) allow the passive quadrature generator 304 to be directly connected to the mixer cores (mixers 312 and 322) at nodes 356 and 357 (and nodes 358 and 359) without any impedance matching or buffering circuitry. This minimizes the area occupied by the integrated circuit (IC) because the impedance matching circuitry between the passive quadrature generator 304 and mixers 312 and 322 is eliminated. This setup also avoids the need for I / Q mismatch calibration of the impedance matching elements that would otherwise be used between the passive quadrature generator 304 and mixers 312 and 322. This setup also limits the phase imbalance caused by the direct capacitive loads of mixers 312 and 322, such as through the capacitance associated with the gates of mixer transistors 508, 510, 520, and 522, which will reference... Figure 5A This will be discussed further. In an exemplary embodiment, the value of the differential termination resistor is twice the characteristic impedance of the passive quadrature generator.

[0082] In an exemplary embodiment, the arithmetic combination and integration element 350a includes an amplifier 422 and a capacitor 424. This is achieved with independent I and Q amplitude detection circuits (…). Figure 3In an exemplary embodiment (330 and 340) of the amplifier, amplifier 422 includes an inverting input terminal connected to the voltage VDD at node 427 and a non-inverting input terminal connected to node 362. A bypass capacitor 425 is connected between node 427 and ground. Node 362 represents the value xQ, which is related to... Figure 3 The exemplary embodiment shown has the same value yQ with independent I and Q amplitude detection circuitry. In the exemplary embodiment, amplifier 422 may be referred to as a bias loop error amplifier, and capacitor 424 may be referred to as a compensation capacitor. In the exemplary embodiment, bias loop 435 includes error amplifier 422, compensation capacitor 424, bias resistors 426 and 432, common-source transistors 408 and 410, and load transistors 404 and 406. Bias loop 435 adjusts the DC voltage at node 423 connected to node 443 so that the voltage at node 362 (also labeled xQ) is close to the supply voltage VDD by controlling the time-averaged current (also referred to as DC bias current) of transistors 408 and 410, regardless of the amplitudes of vLOin_p and vLOin_m. Figure 3 and Figure 4A The changes in LO_Q in the data.

[0083] In an exemplary embodiment, the Q LO amplitude detection circuit 330 detects the amplitude of the quadrature LO signal as a DC voltage level (xQ), and the I LO amplitude detection circuit 340 detects the amplitude of the in-phase LO signal as a DC voltage level (xQ). Figure 3 xI in (the middle).

[0084] In an exemplary embodiment, arithmetic combination and integrator element 350 ( Figure 3 This generates an ILO DC bias voltage that varies only with the amplitude of ILO, and a QLO DC bias voltage that varies only with the amplitude of QLO. For example, in... Figure 4A In circuit 400, the value of xQ (at node 362) is directly applied to the inverting input of amplifier 422. Amplifier 422 and capacitor 424 perform integration and generate the value yQ_bar at node 366 based solely on xQ. The value yQ_bar is then applied as the QLO DC bias voltage to mixer 312 ( Figure 3 A similar circuit can generate the ILO DC bias voltage yI_bar using only the detected ILO amplitude xI. In this example, where the QLO DC bias voltage (yQ_bar) varies only with the QLO amplitude, Figure 3 The coefficients in the matrix shown can be represented by αII=αQQ=1 and αIQ=αQI=0.

[0085] In an alternative exemplary embodiment, the arithmetic combination and integrator 350 generates the QLO DC bias voltage based on the weighted sum of the Q(xQ) and I(xI)LO amplitude voltages. In matrix form, this is represented by yQ = αQI XI + αQQ XQ.

[0086] In an alternative exemplary embodiment, the arithmetic combination and integrator 350 generates the ILO DC bias voltage based on the weighted sum of the Q(xQ) and I(xI)LO amplitude voltages. In matrix form, this is represented by yI = αII XI + αIQ XQ.

[0087] In an alternative exemplary implementation, the Q(xQ) and I(xI)LO amplitude voltages are weighted with equal weights.

[0088] The output of amplifier 422 is provided to node 366 via connection 423. Figure 3 This forms the output yQ_bar. The output yQ_bar also represents the gate-source voltage (Vgs) of transistors 404 and 406, and is an integral (time-averaged) version of yQ.

[0089] In an exemplary embodiment, differential termination resistors 442 and 444 limit the LO I and LO Q phase imbalance as described above, while the amplitude imbalance of the passive quadrature generator 304 is suppressed by the Q LO amplitude detection circuit 330 and the ILO amplitude detection circuit 340 in the Q and I paths, respectively.

[0090] In an exemplary embodiment, the output (Vgs) of the differential amplifier 422 at node 423 is applied to the common-mode point (node ​​447) of vLOin_p and vLOin_m via resistor 448. The voltage Vgs is applied to node 447 via resistor 448, which is the center node terminating resistors 442 and 444.

[0091] Figure 4B This is based on an exemplary embodiment of the present disclosure. Figure 3 A block diagram of an alternative exemplary embodiment of the LO amplitude detection circuit, which has independent bias loops for each of I and Q. In the exemplary embodiment, Figure 4B The bias circuit 450 is similar to Figure 4A The bias circuit is 400. However, in Figure 4B In this example, bias circuit 450 omits resistors 426 and 432, and capacitors 428 and 434, making node 356 directly connected to node 436, and node 357 directly connected to node 438. In this alternative exemplary embodiment, terminating resistors 442 and 444 are included in bias loop 435. In this exemplary embodiment, even if the phase imbalance is due to the passive quadrature generator (Figure 3 The capacitance load of (304) increases and slightly worsens the problem, but the bias circuit 450 can still enhance the mixer's suppression of amplitude imbalance. In an exemplary embodiment, the bias circuit 450 can be used to implement a quadrature generator that inherently has poor amplitude balance but excellent phase balance when each port is terminated only with its characteristic impedance.

[0092] Figure 4C This is based on an exemplary embodiment of the present disclosure. Figure 3 A block diagram of an alternative exemplary embodiment of the LO amplitude detection circuit, which has independent bias loops for each of I and Q. In the exemplary embodiment, Figure 4C The bias circuit 470 is similar to Figure 4B The bias circuit is 450. However, in Figure 4C In the bias circuit 470, transistors 404 and 406 are omitted. Figure 4C In the diagram, current source 402 is represented as current source transistor 472. The source of transistor 472 is connected to the system voltage VDDx, and the drain of transistor 472 is connected to node 362, which is connected to the drains of transistor 408 and transistor 410. The gate of transistor 472 is connected to a voltage that, when the drain voltage of transistor 472 is equal to VDD, causes the drain-source current of transistor 472 to equal Ibias. Figure 4C The exemplary implementation shown enables better compatibility with transimpedance amplifiers that have a current-mode input at the baseband port. Figure 4C The exemplary embodiments shown can also be increased Figure 5B The drain-source voltages of transistors 408 and 410, and the corresponding mixer transistors 508, 510, 520, and 522, can improve mixer linearity. Figure 4C The alternative implementations shown may also include, for example: Figure 4A Resistors 426 and 432 and capacitors 428 and 434 are shown without changing Figure 4C Any other element of the implementation scheme.

[0093] Figure 5A This is a block diagram of a mixer core according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the mixer core 500 may be... Figure 3 Examples of mixers 312 or 322. Figure 5A In the description, the mixer core 500 is Figure 3An example of mixer 312. In an exemplary embodiment, mixer core 500 includes transistors 504, 506, 508, 520, 522, and 510. In an exemplary embodiment, transistors 504 and 506 may be P-type devices, and transistors 508, 520, 522, and 510 may be N-type devices. In an exemplary embodiment, the source of transistor 504 and the source of transistor 506 may be connected to a power supply voltage VDD. The drain and gate of transistor 504 are connected together, and the drain and gate of transistor 506 are connected together. The drain of transistor 504 is connected to the drain of transistor 508. The drain of transistor 506 is connected to the drain of transistor 510. The drain of transistor 504 is also connected to the drain of transistor 522; and the drain of transistor 506 is connected to the drain of transistor 520. Figure 5A In the illustrated embodiment, transistors 504 and 506 are diode-connected load transistors.

[0094] In another alternative exemplary embodiment, the QLO amplitude detection circuit 330 can be replaced by a common-mode sensing circuit with a resistor connected between the drains of transistors 504 and 506. In this embodiment, the common-mode voltage indicates the LO amplitude and is connected to the non-inverting input of the error amplifier 422. This alternative embodiment will... Figure 8 As described in the text.

[0095] The sources of transistors 508 and 520 are connected to node 313, which is the RF input signal RFin_p. The sources of transistors 522 and 510 are connected to node 314, which is the RF input signal RFin_m. The sources of transistors 508, 520, 522, and 510 may have a DC voltage equal to system ground, and the RFin_p and RFin_m signals may be provided by a matching network (not shown) that transmits signals from LNA 252 via nodes 313 and 314. Figure 2A ) or phase shifter array 281 ( Figure 2B or Figure 2C The RF signal is coupled to the mixer core 500. The matching network (not shown) can be a transformer-based matching network.

[0096] The quadrature vLOin_p portion of the LO_Q signal on connection 356 is provided to the gates of transistors 508 and 510. The quadrature vLOin_m portion of the LO_Q signal on connection 357 is provided to the gates of transistors 520 and 522.

[0097] The BBout_Q signal Vout_p is provided through node 316, and the BBout_Q signal Vout_m is provided through node 317.

[0098] In an exemplary embodiment, the LO amplitude detection circuit 330 ( Figure 4A Transistors 404 and 406 in the circuit provide replicas of transistors 504 and 506, while the LO amplitude detection circuit 330 ( Figure 4A Transistor 408 in the circuit provides a replica of transistors 508 and 510, and the LO amplitude detection circuit 330 ( Figure 4A Transistor 410 in the mixer core 500 provides a copy of transistors 520 and 522 in the mixer core 500.

[0099] In an exemplary embodiment, the QLO amplitude detection circuit 330 and the ILO amplitude detection circuit 340 serve as replicas of the switching devices (transistors 508, 520, 522, and 510) and load devices (transistors 504 and 506) in the mixer core 500. The QLO amplitude detection circuit 330 and the ILO amplitude detection circuit 340 each include the aforementioned bias circuit ( Figure 4A (435 in the middle), so that the average drain current in the mixer core 500 is equal to the Ibias of the current source 402 ( Figure 4A The Ibias is scaled according to the ratio of the width of transistor 408 / 410 to the width of transistors 508 / 522 and 510 / 520.

[0100] Through nodes 356 and 357 ( Figure 4A Feeding into nodes 436 and 438 ( Figure 4A The LO signal of ) passes through capacitors 428 and 434 ( Figure 4A This allows transistors 408 and 410 within the bias circuit 400 to replicate the change in the DC operating point of transistors 508 and 520 (or transistors 522 and 510) in the mixer core 500 relative to the LO signal strength. Bias circuit 435 ( Figure 4A ) is used to control the time-averaged voltage at nodes 436 and 438 to control node 362 ( Figure 4A The time-averaged voltage at nodes 456 and 457 is adjusted to VDD. Bias circuit 435 counteracts self-biasing behavior, which would otherwise modify the average drain current of transistors 408 and 410 in the presence of AC or DC coupled LO signal swings at nodes 436 and 438. Therefore, bias circuit 435 is used to provide controlled time-averaged voltages at nodes 356 and 357 that maintain a fixed average drain current in transistors 508 and 520 (and in transistors 522 and 510).

[0101] As the LO signal swing (voltage swing) increases, transistors 408 and 410 self-bias to higher DC operating currents because they lack tail bias currents at the common-source connections (nodes 313 and 314) to control the DC operating current. It is desirable to keep the average DC current flowing through the mixer devices (transistors 508 and 520, and transistors 522 and 510) constant and equal to the Ibias current scaled according to the transistor width ratio as described above (current source 402, ...). Figure 4A The source voltages of transistors 404 and 406 are kept constant equal to the reference VDD by error amplifier 422. Bias circuit 435 controls the average gate voltages of replicating devices 408 and 410, thereby controlling switching devices 508, 510, 520, and 522 in mixer core 500 to eliminate I and Q amplitude imbalance. It is desirable to adjust the gate voltages of transistors 408 and 410 so that the gate voltages decrease when the current through transistors 408 and 410 increases instantaneously. In this way, the time-averaged current through transistors 404, 406, 408, and 410 remains constant and does not change with the LO signal strength.

[0102] Figure 5B This is a block diagram of an alternative exemplary embodiment of the mixer core 570 according to an exemplary embodiment of the present disclosure. Figure 5B The mixer core 570 is similar to Figure 5A The mixer core is 500. However, in Figure 5B In this configuration, diode-connected transistor 504 is replaced by current-source transistor 574; and diode-connected transistor 506 is replaced by current-source transistor 576. The source terminals of current-source transistors 574 and 576 are connected to node 437, which has a supply voltage VDDx. Transistors 574 and 576 correspond to... Figure 4C Transistor 472. In Figure 4C In the alternative embodiment shown, the gate bias voltages of transistors 574 and 576 are... Figure 4C The gate bias voltage of the Ibias current source transistor 472 is the same.

[0103] Figure 6 yes Figure 3 A diagram illustrating an exemplary embodiment of the arithmetic combination and integrator elements. In an exemplary embodiment, the arithmetic combination and integrator circuit 600 may be implemented in a specific implementation. Figure 3The arithmetic combination and integrator element 350 functions such that the QLO DC bias voltage is generated based on the weighted sum of the Q(xQ) and I(xI)LO amplitude voltages, and the ILO DC bias voltage is generated based on the weighted sum of the Q(xQ) and I(xI)LO amplitude voltages. Circuit 600 is an example of the arithmetic combination and integrator element 350, which uses a common weighting method on the outputs of the QLO amplitude detection circuit 330 and the ILO amplitude detection circuit 340 to generate control voltages yQ and yI. For example, circuit 610 shows an arithmetic combination and integrator element 350b that can be used to control the bias of an in-phase mixer, and circuit 620 shows an arithmetic combination and integrator element 350c that can be used to control the bias of a quadrature mixer.

[0104] In an exemplary embodiment, the arithmetic combination and integration element 350b may include an amplifier 612b and resistors 614b, 616b, and 618b. Amplifier 612b may include a high-gain operational amplifier. In this example, resistor 614b may have a value R. Furthermore, resistor 616b may have a value R / αI1, and resistor 618b may have a value R / αIQ. In an exemplary embodiment, the output of amplifier 612b is a signal yI, which is provided to the inverting input of error amplifier 422b. The output of error amplifier 422b at node 368b is a control signal yI_bar, which may be applied directly or via terminating resistor circuitry to mixer 322 or nodes 358 and 359.

[0105] In an exemplary embodiment, the arithmetic combination and integrator element 350c may include an amplifier 612c and resistors 614c, 616c, and 618c. Amplifier 612c may include a high-gain operational amplifier. In this example, resistor 614c may have a value R. Furthermore, resistor 616c may have a value R / αQI, and resistor 618c may have a value R / αQQ. In an exemplary embodiment, the output of amplifier 612c is a signal yQ, which is provided to the inverting input of error amplifier 422c. The output of error amplifier 422c at node 366c is a control signal yQ_bar, which may be applied directly or via terminating resistor circuitry to mixer 312 or nodes 356 and 357.

[0106] Figure 7 yes Figure 3 A diagram illustrating an exemplary embodiment of an arithmetic combination and integrator element. In an exemplary embodiment, the arithmetic combination and integrator circuit 700 may implement... Figure 3The function of the arithmetic combination and integrator 350 is described in circuit 700. Circuit 700 is an example of the arithmetic combination and integrator 350, which averages the outputs of the Q LO amplitude detection circuit 330 and the I LO amplitude detection circuit 340 to generate control voltages yQ_bar and yI_bar.

[0107] In an exemplary embodiment, the arithmetic combination and integration element 350d may include an amplifier 612d and resistors 614d, 616d, and 618d. Amplifier 612d may include a high-gain operational amplifier. In this example, resistor 614d may have a value R. Furthermore, resistor 616d may have a value of 2R, and resistor 618d may have a value of 2R. In an exemplary embodiment, the output of amplifier 612d is a signal yI or yQ, which is provided to the inverting input of error amplifier 422d. The output of error amplifier 422d at node 366d is a control signal yQ_bar, which may be applied directly or via a terminating resistor circuit to mixer 312 or nodes 356 and 357, and the output of error amplifier 422d at node 368d is a control signal yI_bar, which may be applied directly or via a terminating resistor circuit to mixer 322 or nodes 358 and 359.

[0108] Figure 8 yes Figure 3 mixer circuit and Figure 5B The figure shows an alternative exemplary embodiment of the mixer core. In an exemplary embodiment, circuit 800 may include mixer core 805, arithmetic combination and integrator element 350 (…). Figure 3 Part 350a and terminating resistor circuit 825.

[0109] In an exemplary embodiment, the mixer core 805 is similar to Figure 5B The mixer core 570, and will not be described in detail with Figure 5B The components with the same number Figure 8 The components in the mixer. In an exemplary embodiment, the mixer core 805 includes a current source reference transistor 572 having a source connected to the system voltage VDDx at node 437 and a drain connected to a current source 807. The gates of transistors 572, 574, and 576 are connected together and biased by the current source 807. In an exemplary embodiment, Figure 3 and Figure 4A , Figure 4B and Figure 4CThe QLO amplitude detection circuit 330 can be approximated by the common-mode sensing circuit 830. During normal operation of the transceiver, because the biases of transistors 508, 520, 522, and 510 vary with both the LO amplitude and the RF signal amplitude, the RF input signal at nodes 313 and 314 in the main mixer core 805 may degrade the continuous bias loop ( Figure 4A , Figure 4B and Figure 4C The accuracy of (435) in the model. This is related to the replication bias circuit 400 ( Figure 4A ), 450 ( Figure 4B ) and 470 ( Figure 4C Unlike other bias circuits, in a replication bias circuit, the bias of the transistors in the bias loop varies only with the LO amplitude. In an exemplary embodiment, the common-mode sensing circuit 830 may include resistors 832 and 834 forming a resistive voltage divider. Resistor 832 may be connected between nodes 833 and 835 at the drain of transistor 574. Resistor 834 may be connected between node 835 and node 837 at the drain of transistor 576.

[0110] In an exemplary embodiment, resistors 832 and 834 sense the common-mode voltage at node 835. The common-mode voltage at node 835 indicates the LO amplitude and is connected to the non-inverting input of error amplifier 422. The bias voltage output yQ_bar of error amplifier 422 at node 366 is provided to node 447 between resistors 442 and 444, and is also provided to nodes 356 and 357, as described above.

[0111] The example described above illustrates how the combination and integration element 350 and the corresponding matrix coefficients (αII, αQQ, αIQ, and αQI) and bias loop are implemented using analog circuitry. In other examples, the combination and integration element 350 may be implemented using mixed-signal functions for arithmetic combination and integration. For example, the analog (bias) control loop described above may be replaced by a mixed-signal control loop utilizing an ADC, DAC, and digital logic, which may include software. In some such examples, the LO detector output is sensed using an analog-to-digital converter (ADC), and all subsequent mathematical operations are performed using digital circuitry or software, firmware, etc. For example, the matrix coefficients and operations (e.g., [αII αIQ, αQI αQQ][xI xQ]) may be stored and applied using digital computation and circuitry and / or software. Storage and computation may be performed by, for example, a data processor 210 (e.g., by memory 298 and processor 296), a controller (not shown) in transceiver 220, or a combination of both. Additional or alternative methods may be used to calculate or determine yI, yQ, yI_bar, yQ_bar, and / or other forms of bias. The calculated digital values ​​can be converted into (DC) bias voltages using a digital-to-analog converter (DAC) to apply bias control to mixers 312 and 322 (e.g., via appropriate termination resistor pairs).

[0112] Figure 9 This is a flowchart 900 illustrating an example of the operation of a method for mixing signals. The blocks in method 900 may be performed in the order shown or not, and in some embodiments, they may be performed at least partially in parallel.

[0113] In block 902, the Q LO amplitude and I LO amplitude are detected. For example, the Q LO amplitude detection circuit 330 detects the amplitude of the quadrature LO signal as DC level (xQ), and the I LO amplitude detection circuit 340 detects the amplitude of the in-phase LO signal as DC level (xI).

[0114] In block 904, the QLO DC bias voltage is generated. For example, the arithmetic combination and integrator 350 generates the QLO DC bias voltage solely based on the QLO amplitude. This can be achieved through... Figure 3 The coefficients in the matrix shown are used to achieve this, and these coefficients are... 1 and 0 represents.

[0115] In block 906, the ILO DC bias voltage is generated. For example, the arithmetic combination element 350 generates the ILO DC bias voltage based solely on the QLO amplitude. This can be achieved through... Figure 3 The coefficients in the matrix shown are used to achieve this, and these coefficients are determined by α. II =α QQ =1 and αIQ =α QI =0 indicates that...

[0116] In block 908, ILO DC bias voltage and QLO DC bias voltage are applied to the mixer to improve the mixer's IRR. For example, the output of amplifier 422 is provided to node 366 via connection 423. Figure 3 This forms the output yQ_bar. Similarly, the yI_bar output is provided to mixer 322.

[0117] Figure 10 This is a functional block diagram of an apparatus 1000 for mixing signals. The apparatus 1000 includes a component 1002 for detecting the ILO amplitude and QLO amplitude. In some embodiments, the component 1002 for detecting the ILO amplitude and QLO amplitude may be configured to perform method 900. Figure 9 The function described in operation block 902 is one or more of the functions described in the example implementation. In an exemplary embodiment, component 1002 for detecting I LO amplitude and Q LO amplitude may include Q LO amplitude detection circuit 330 that detects the amplitude of quadrature LO signals as DC level (xQ) and I LO amplitude detection circuit 340 that detects the amplitude of in-phase LO signals as DC level (xI).

[0118] The apparatus 1000 also includes a component 1004 for generating a QLO DC bias voltage. In some embodiments, the component 1004 for generating the QLO DC bias voltage may be configured to perform method 900. Figure 9 This refers to one or more of the functions described in operation block 904. In an exemplary embodiment, component 1004 for generating the QLO DC bias voltage may include an arithmetic combination and integrator 350 that generates the QLO DC bias voltage solely based on the QLO amplitude. This can be achieved through... Figure 3 The coefficients in the matrix shown are used to implement this, and these coefficients are represented by αII=αQQ=1 and αIQ=αQI=0.

[0119] The apparatus 1000 may further include a component 1006 for generating an ILO DC bias voltage. In some embodiments, the component 1006 for generating the ILO DC bias voltage may be configured to perform method 900. Figure 9 This refers to one or more of the functions described in operation block 906. In an exemplary embodiment, component 1006 for generating the ILO DC bias voltage may include an arithmetic combination element 350 that generates the ILO DC bias voltage solely based on the ILO amplitude. This can be achieved through... Figure 3The coefficients in the matrix shown are used to implement this, and these coefficients are represented by αII=αQQ=1 and αIQ=αQI=0.

[0120] The apparatus 1000 may further include a component 1008 for applying an ILO DC bias voltage and a QLO DC bias voltage to the mixer to improve the mixer's IRR. In some embodiments, the component 1008 for applying the ILO DC bias voltage and the QLO DC bias voltage to the mixer to improve the mixer's IRR may be configured to perform method 900. Figure 9 One or more functions are described in operation block 908. In an exemplary embodiment, component 1008 for applying ILO DC bias voltage and QLO DC bias voltage to the mixer to improve the mixer's IRR may include providing the output of amplifier 422 to node 366 via connection 423. Figure 3 This forms the output yQ_bar. Similarly, the yI_bar output is provided to mixer 322.

[0121] Figure 11 This is a flowchart 1100 illustrating an example of the operation of a method for mixing signals. The blocks in method 1100 may be performed in the order shown or not, and in some embodiments, they may be performed at least partially in parallel.

[0122] In block 1102, the Q LO amplitude and I LO amplitude are detected. For example, the Q LO amplitude detection circuit 330 detects the amplitude of the quadrature LO signal as DC level (xQ), and the I LO amplitude detection circuit 340 detects the amplitude of the in-phase LO signal as DC level (xI).

[0123] In block 1104, the QLO DC bias voltage is generated. For example, the arithmetic combination and integrator 350 generates the QLO DC bias voltage based on the weighted sum of the I(xI) and Q(xQ)LO amplitude voltages. In matrix form, this can be represented by yQ = αQI xI + αQQ xQ.

[0124] In block 1106, the ILO DC bias voltage is generated. For example, arithmetic combination element 350 generates the ILO DC bias voltage based on a weighted sum of the Q(xQ) and I(xI)LO amplitude voltages. In matrix form, this is represented by yI = αII xI + αIQ xQ. In other example methods, IQ and QI have zero weights, and the ILO and QLO DC bias voltages can be calculated independently.

[0125] In block 1108, the ILO DC bias voltage and QLO DC bias voltage are applied to the mixer (e.g., to improve the mixer's IRR). For example, the output of amplifier 422 is provided to node 366 via connection 423. Figure 3 This forms the output yQ_bar. Similarly, the yI_bar output is provided to mixer 322.

[0126] Figure 12 This is a functional block diagram of an apparatus 1200 for mixing signals. Apparatus 1200 includes a component 1202 for detecting the QLO amplitude and ILO amplitude. In some embodiments, the component 1202 for detecting the QLO amplitude and ILO amplitude may be configured to perform method 1100. Figure 11 The functions described in operation block 1102 are one or more of the functions described in the example implementation. In an exemplary embodiment, component 1202 for detecting Q LO amplitude and I LO amplitude may include a Q LO amplitude detection circuit 330 configured to detect the amplitude of the quadrature LO signal as a DC level (xQ) and an I LO amplitude detection circuit 340 configured to detect the amplitude of the in-phase LO signal as a DC level (xI).

[0127] The apparatus 1200 also includes a component 1204 for generating a QLO DC bias voltage. In some embodiments, the component 1204 for generating the QLO DC bias voltage may be configured to perform method 1100. Figure 11 This refers to one or more of the functions described in operation block 1104. In an exemplary embodiment, component 1204 for generating the QLO DC bias voltage may include an arithmetic combination and integrator 350 configured to generate the QLO DC bias voltage based on a weighted sum of the I(xI) and Q(xQ)LO amplitude voltages. In matrix form, this is represented by yQ = αQI xI + αQQ xQ.

[0128] The apparatus 1200 may further include a component 1206 for generating an ILO DC bias voltage. In some embodiments, the component 1206 for generating the ILO DC bias voltage may be configured to perform method 1100. Figure 11This refers to one or more of the functions described in operation block 1106. In an exemplary embodiment, component 1206 for generating the ILO DC bias voltage may include an arithmetic combination element 350 configured to generate the ILO DC bias voltage based on a weighted sum of the Q(xQ) and I(xI)LO amplitude voltages. In matrix form, this is represented by yI = αII xI + αIQ xQ. In other example devices, IQ and QI have zero weights, and the ILO and QLO DC bias voltages can be calculated independently, for example, by separate components or in separate bias loops within a shared component.

[0129] The apparatus 1200 may further include a component 1208 for applying an ILO DC bias voltage and a QLO DC bias voltage to the mixer (e.g., to improve the mixer's IRR). In some embodiments, the component 1208 for applying the ILO DC bias voltage and the QLO DC bias voltage to the mixer to improve the mixer's IRR may be configured to perform method 1100. Figure 11 One or more functions are described in operation block 1108. In an exemplary embodiment, component 1208 for applying the ILO DC bias voltage and QLO DC bias voltage to the mixer may include amplifier 422, which is configured to provide an output to node 366 via connection 423. Figure 3 This forms the output yQ_bar. Similarly, the yI_bar output is provided to mixer 322.

[0130] Specific implementation examples are described in the following numbered clauses:

[0131] 1. A communication system comprising: a passive quadrature generator directly connected to an in-phase (I) mixer and a quadrature (Q) mixer; an ILO amplitude detection circuit connected to the passive quadrature generator and connected to the I mixer; a QLO amplitude detection circuit connected to the passive quadrature generator and connected to the Q mixer, the ILO amplitude detection circuit being configured to detect ILO amplitude and the QLO amplitude detection circuit being configured to detect QLO amplitude; and a combination and integration circuit configured to receive the detected ILO amplitude and the detected QLO amplitude, and to generate an ILO DC bias voltage for biasing the I mixer and a QLO DC bias voltage for biasing the Q mixer.

[0132] 2. The communication system according to Clause 1, wherein the I LO DC bias voltage varies with the I LO amplitude but not with the Q LO amplitude, and the Q LO DC bias voltage varies with the Q LO amplitude but not with the I LO amplitude.

[0133] 3. The communication system according to Clause 1 or 2, wherein the I LO DC bias voltage and the Q LO DC bias voltage are a weighted sum of the I LO amplitude and the Q LO amplitude.

[0134] 4. The communication system according to Clause 3, wherein the I LO amplitude and the Q LO amplitude are weighted with equal weights.

[0135] 5. The communication system according to any one of clauses 2 to 4, wherein the I LO DC bias voltage controls the current through the I mixer, and the Q LO DC bias voltage controls the current through the Q mixer.

[0136] 6. The communication system according to any one of clauses 2 to 5, wherein the I LO amplitude detection circuit comprises a transistor as a replica of a switching transistor in the I mixer, and the Q LO amplitude detection circuit comprises a transistor as a replica of a switching transistor in the Q mixer.

[0137] 7. The communication system according to any one of Clauses 2 to 6, the communication system further comprising differential termination resistors in the I LO amplitude detection circuit and the Q LO amplitude detection circuit, the differential termination resistors being configured to allow the I mixer and the Q mixer to be directly connected to the passive quadrature generator.

[0138] 8. The communication system according to Clause 7, wherein the value of the differential termination resistor is twice the characteristic impedance of the passive quadrature generator.

[0139] 9. The communication system according to any one of Clauses 2 to 8, wherein the ILO amplitude detection circuit and the QLO amplitude detection circuit include a common-mode sensing circuit.

[0140] 10. The communication system according to any one of clauses 2 to 9, wherein the common-mode sensing circuit includes a resistor divider.

[0141] 11. The communication system according to any one of Clauses 2 to 10, wherein the I LO amplitude detection circuit includes a separate bias circuit for the signal processed by the I mixer, and the Q LO amplitude detection circuit includes a separate bias circuit for the signal processed by the Q mixer.

[0142] 12. The communication system according to any one of Clauses 2 to 11, wherein the I mixer and the Q mixer are configured to process signals in one or more of the millimeter-wave (mmW) communication band and the sub-terahertz (THz) communication band.

[0143] 13. The communication system according to Clause 12, wherein the I mixer and the Q mixer are configured to down-convert frequencies below mmW or THz to baseband.

[0144] 14. A method for mixing a signal, the method comprising: detecting an in-phase (I) LO amplitude and a quadrature (Q) LO amplitude; generating an I LO DC bias voltage based on the I LO amplitude; generating a Q LO DC bias voltage based on the Q LO amplitude; and...

[0145] The I LO DC bias voltage is applied to the I mixer, and the Q LO DC bias voltage is applied to the Q mixer to improve the image rejection ratio (IRR) of the I mixer and the Q mixer.

[0146] 15. The method according to Clause 14, wherein the I LO DC bias voltage is not generated based on the Q LO amplitude, and the Q LO DC bias voltage is not generated based on the I LO amplitude.

[0147] 16. The method according to Clause 14 or 15, wherein the I LO DC bias voltage and the Q LO DC bias voltage are a weighted sum of the I LO amplitude and the Q LO amplitude.

[0148] 17. The method according to Clause 16, wherein the I LO magnitude and the Q LO magnitude are weighted with equal weights.

[0149] 18. The method according to any one of clauses 14 to 17, wherein applying the I LO DC bias voltage to the I mixer and applying the Q LO DC bias voltage to the Q mixer enhances the suppression of local oscillator (LO) signal imbalance by the I mixer and the Q mixer.

[0150] 19. The method according to any one of clauses 14 to 18, wherein the I LO DC bias voltage and the Q LO DC bias voltage are generated using separate bias circuits.

[0151] 20. The method according to any one of clauses 14 to 19, the method further comprising using the I mixer and the Q mixer to process signals in one or more of the millimeter-wave (mmW) communication band and the sub-terahertz (THz) communication band.

[0152] 21. The method according to Clause 20, wherein the processing includes downconverting the I mixer signal and the Q mixer signal to baseband.

[0153] 22. An apparatus for signal mixing, the apparatus comprising: components for detecting in-phase (I) LO amplitude and quadrature (Q) LO amplitude; components for generating an I LO DC bias voltage based on the I LO amplitude; components for generating a Q LO DC bias voltage based on the Q LO amplitude; and components for applying the I LO DC bias voltage to an I mixer and for applying the Q LO DC bias voltage to a Q mixer to improve the image rejection ratio (IRR) of the mixers.

[0154] 23. The device according to Clause 22, wherein the I LO DC bias voltage does not change with the Q LO amplitude, and the Q LO DC bias voltage does not change with the I LO amplitude.

[0155] 24. The device according to clause 22 or 23, wherein the I LO DC bias voltage and the Q LO DC bias voltage are a weighted sum of the I LO amplitude and the Q LO amplitude.

[0156] 25. The device according to Clause 24, wherein the I LO amplitude and the Q LO amplitude are weighted with equal weights.

[0157] 26. The apparatus according to any one of clauses 22 to 25, wherein the components for applying the I LO DC bias voltage to the I mixer and the Q LO DC bias voltage to the Q mixer enhance the suppression of local oscillator (LO) signal imbalance by the I mixer and the Q mixer.

[0158] 27. The apparatus according to any one of clauses 22 to 26, the apparatus further comprising components for processing I mixer signals using a separate I bias circuit and for processing Q mixer signals using a separate Q bias circuit.

[0159] 28. The device according to any one of clauses 22 to 27, the device further comprising components for processing I-mixer signals and Q-mixer signals in one or more of the millimeter-wave (mmW) communication band and the sub-terahertz (THz) communication band.

[0160] 29. The apparatus according to Clause 28, further comprising components for downconverting the I mixer signal and the Q mixer signal to baseband.

[0161] The circuit architecture described in this article can be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described in this article can also be manufactured using various IC process technologies, such as complementary metal-oxide-semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0162] The apparatus for implementing the circuit described herein may be a standalone device or part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs that may include memory ICs for storing data and / or instructions, (iii) an RF IC such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a mobile phone or mobile unit, (vii) and so on.

[0163] While selected aspects have been illustrated and described in detail, it should be understood that various substitutions and modifications may be made therein without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims

1. A communication system, the communication system comprising: A passive quadrature generator, which is directly connected to an in-phase (I) mixer and a quadrature (Q) mixer; An ILO amplitude detection circuit, the ILO amplitude detection circuit being connected to the passive quadrature generator and connected to the I mixer, and a QLO amplitude detection circuit, the QLO amplitude detection circuit being connected to the passive quadrature generator and connected to the Q mixer, wherein the ILO amplitude detection circuit is configured to detect the ILO amplitude, and the QLO amplitude detection circuit is configured to detect the QLO amplitude; and A combination and integration circuit is configured to receive the detected ILO amplitude and the detected QLO amplitude, and to generate an ILO DC bias voltage for biasing the I mixer and a QLO DC bias voltage for biasing the Q mixer.

2. The communication system according to claim 1, wherein the I LO DC bias voltage varies with the I LO amplitude but not with the Q LO amplitude, and the Q LO DC bias voltage varies with the Q LO amplitude but not with the I LO amplitude.

3. The communication system according to claim 1, wherein the ILO DC bias voltage and the QLO DC bias voltage are a weighted sum of the ILO amplitude and the QLO amplitude.

4. The communication system according to claim 3, wherein the ILO amplitude and the QLO amplitude are weighted with equal weights.

5. The communication system according to claim 1, wherein the I LO DC bias voltage controls the current through the I mixer, and the Q LO DC bias voltage controls the current through the Q mixer.

6. The communication system of claim 1, wherein the I LO amplitude detection circuit comprises a transistor as a replica of the switching transistor in the I mixer, and the Q LO amplitude detection circuit comprises a transistor as a replica of the switching transistor in the Q mixer.

7. The communication system of claim 1, further comprising differential termination resistors in the I LO amplitude detection circuit and the Q LO amplitude detection circuit, the differential termination resistors being configured to allow the I mixer and the Q mixer to be directly connected to the passive quadrature generator.

8. The communication system according to claim 7, wherein the value of the differential termination resistor is twice the characteristic impedance of the passive quadrature generator.

9. The communication system according to claim 1, wherein the ILO amplitude detection circuit and the QLO amplitude detection circuit include a common-mode sensing circuit.

10. The communication system of claim 9, wherein the common-mode sensing circuit includes a resistor divider.

11. The communication system of claim 1, wherein the I LO amplitude detection circuit includes a separate bias circuit for the signal processed by the I mixer, and the Q LO amplitude detection circuit includes a separate bias circuit for the signal processed by the Q mixer.

12. The communication system of claim 1, wherein the I mixer and the Q mixer are configured to process signals in one or more of the millimeter-wave (mmW) communication band and the sub-terahertz (THz) communication band.

13. The communication system of claim 12, wherein the I mixer and the Q mixer are configured to downconvert frequencies below mmW or THz to baseband.

14. A method for mixing a signal, the method comprising: Detect the amplitude of in-phase (I) LO and quadrature (Q) LO; A DC bias voltage ILO is generated based on the ILO amplitude; A QLO DC bias voltage is generated based on the QLO amplitude; as well as The I LO DC bias voltage is applied to the I mixer, and the Q LO DC bias voltage is applied to the Q mixer to improve the image rejection ratio (IRR) of the I mixer and the Q mixer.

15. The method of claim 14, wherein the I LO DC bias voltage is not generated based on the Q LO amplitude, and the Q LO DC bias voltage is not generated based on the I LO amplitude.

16. The method of claim 14, wherein the ILO DC bias voltage and the QLO DC bias voltage are a weighted sum of the ILO amplitude and the QLO amplitude.

17. The method of claim 16, wherein the I LO amplitude and the Q LO amplitude are weighted with equal weights.

18. The method of claim 14, wherein applying the I LO DC bias voltage to the I mixer and applying the Q LO DC bias voltage to the Q mixer enhances the suppression of local oscillator (LO) signal imbalance by the I mixer and the Q mixer.

19. The method of claim 14, wherein the I LO DC bias voltage and the Q LO DC bias voltage are generated using separate bias circuits.

20. The method of claim 14, further comprising using the I mixer and the Q mixer to process signals in one or more of the millimeter-wave (mmW) communication band and the sub-terahertz (THz) communication band.

21. The method of claim 20, wherein the processing includes downconverting the I-mixer signal and the Q-mixer signal to baseband.

22. An apparatus for signal mixing, the apparatus comprising: Components used to detect the amplitude of in-phase (I) LO and quadrature (Q) LO; A component for generating an ILO DC bias voltage based on the ILO amplitude; A component for generating a QLO DC bias voltage based on the QLO amplitude; and Components for applying the I LO DC bias voltage to the I mixer and for applying the Q LO DC bias voltage to the Q mixer to improve the image rejection ratio (IRR) of the mixer.

23. The device of claim 22, wherein the I LO DC bias voltage does not change with the Q LO amplitude, and the Q LO DC bias voltage does not change with the I LO amplitude.

24. The device of claim 22, wherein the I LO DC bias voltage and the Q LO DC bias voltage are a weighted sum of the I LO amplitude and the Q LO amplitude.

25. The device of claim 24, wherein the I LO amplitude and the Q LO amplitude are weighted with equal weights.

26. The device of claim 22, wherein the components for applying the I LO DC bias voltage to the I mixer and the Q LO DC bias voltage to the Q mixer enhance the suppression of local oscillator (LO) signal imbalance by the I mixer and the Q mixer.

27. The apparatus of claim 22, further comprising components for processing I mixer signals using a separate I bias circuit and processing Q mixer signals using a separate Q bias circuit.

28. The apparatus of claim 22, further comprising components for processing I-mixer signals and Q-mixer signals in one or more of the millimeter-wave (mmW) communication band and the sub-terahertz (THz) communication band.

29. The apparatus of claim 28, further comprising a component for downconverting the I mixer signal and the Q mixer signal to baseband.

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