Narrow pulse signal processing method of transistor in vehicle, storage medium and vehicle

Abstract

The invention discloses a narrow pulse signal processing method of a transistor in a vehicle, a storage medium and the vehicle. The vehicle comprises a permanent magnet synchronous motor, and the method comprises the steps that current information and position information of the permanent magnet synchronous motor are obtained, the current information is used for representing the state of current in the permanent magnet synchronous motor, and the position information is used for representing the state of the position where the permanent magnet synchronous motor is located in the rotating process; on the basis of the current information and the position information, duty ratio information of the transistor is determined, and the duty ratio information is used for representing the ratio of the duration of driving the permanent magnet synchronous motor by the transistor in response to the initial driving signal to the signal period of the initial driving signal; processing a narrow pulse in the initial driving signal based on the duty ratio information; and obtaining a target driving signal after the narrow pulse processing is completed, controlling the transistor to respond to the target driving signal, and re-driving the permanent magnet synchronous motor to operate. The technical problem that narrow pulse signals cannot be effectively processed is solved.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and more specifically, to a narrow pulse signal processing method for transistors in a vehicle, a storage medium, and a vehicle. Background Technology

[0002] Currently, in vehicle motor control systems, the Insulated Gate Bipolar Transistor (IGBT) is the core power electronic device, and its performance directly affects drive efficiency and stability. Motor control algorithms typically drive the IGBT by generating Pulse Width Modulation (PWM) signals to achieve precise control of motor speed and torque. However, when the pulse width (duty cycle) in the PWM signal is less than the minimum turn-on and turn-off time required by the IGBT, a phenomenon known as the narrow pulse phenomenon occurs. Narrow pulses cause the IGBT to be frequently switched before it has fully entered the on or off state, significantly increasing energy loss during switching and distorting the PWM output waveform, further impacting motor operating efficiency and overall system stability.

[0003] Current motor control strategies often overlook the negative impact of narrow pulses and lack effective suppression methods. Therefore, the technical problem of effectively processing narrow pulse signals remains.

[0004] There is currently no effective solution to the aforementioned technical problems. Summary of the Invention

[0005] This application provides a method for processing narrow pulse signals of transistors in a vehicle, a storage medium, and a vehicle, to at least solve the technical problem of the inability to effectively process narrow pulse signals.

[0006] According to one aspect of the embodiments of this application, a method for processing narrow pulse signals of transistors in a vehicle is provided. The vehicle includes a permanent magnet synchronous motor (PMSM), and the transistor is used to drive the PMSM in response to an initial drive signal. The method may include: acquiring current information and position information of the PMSM, wherein the current information is used to represent the state of the current in the PMSM, and the position information is used to represent the state of the position of the PMSM during rotation; determining the duty cycle information of the transistor based on the current information and the position information, wherein the duty cycle information is used to represent the duration for which the transistor drives the PMSM in response to the initial drive signal, and the ratio of this duration to the signal period of the initial drive signal; processing narrow pulses in the initial drive signal based on the duty cycle information; acquiring a target drive signal after the narrow pulse processing is completed; and controlling the transistor to respond to the target drive signal and re-drive the PMSM.

[0007] Optionally, the method further includes: obtaining the proportion of the lower bridge high-level time of the transistor and the proportion of the upper bridge high-level time of the transistor; processing the narrow pulse in the initial drive signal based on the duty cycle information, including: determining the interval where the duty cycle information is located; and processing the narrow pulse based on the interval, the proportion of the lower bridge high-level time, and the proportion of the upper bridge high-level time.

[0008] Optionally, the duty cycle information includes the duty cycle information of the current cycle and the duty cycle information of the next cycle. Based on the interval, the proportion of the high-level time of the lower bridge, and the proportion of the high-level time of the upper bridge, the narrow pulse is processed, including: in response to the duty cycle information of the current cycle being in the first interval, the duty cycle information of the next cycle being in the first interval, and half of the sum of the proportion of the high-level time of the lower bridge and the proportion of the high-level time of the upper bridge being less than the proportion of the narrow pulse time, the waveform of the narrow pulse of the current cycle and the waveform of the narrow pulse of the next cycle are adjusted; the method further includes: pulling the lower bridge small pulse corresponding to the transistor to a low level.

[0009] Optionally, the duty cycle information includes the duty cycle information of the current cycle and the duty cycle information of the next cycle. Based on the interval, the proportion of the high-level time of the lower bridge, and the proportion of the high-level time of the upper bridge, the narrow pulse is processed, including: in response to the duty cycle information of the current cycle being in the first interval, the duty cycle information of the next cycle being in the second interval, and half of the sum of the proportion of the high-level time of the lower bridge and the proportion of the high-level time of the upper bridge being less than the proportion of the narrow pulse time, the waveform of the narrow pulse of the current cycle is adjusted; the method further includes: pulling the lower bridge small pulse corresponding to the transistor to a low level.

[0010] Optionally, the duty cycle information includes the duty cycle information of the current cycle and the duty cycle information of the next cycle. Based on the interval, the proportion of the high-level time of the lower bridge, and the proportion of the high-level time of the upper bridge, the narrow pulse is processed, including: in response to the duty cycle information of the current cycle being in the third interval, the duty cycle information of the next cycle being in the first interval, and half of the sum of the proportion of the high-level time of the lower bridge and the proportion of the high-level time of the upper bridge being less than the proportion of the narrow pulse time, the waveform of the narrow pulse of the next cycle is adjusted; the method further includes: pulling the lower bridge small pulse corresponding to the transistor to a low level.

[0011] Optionally, the duty cycle information includes the duty cycle information of the current cycle and the duty cycle information of the next cycle. Based on the interval, the proportion of the high-level time of the lower bridge, and the proportion of the high-level time of the upper bridge, the narrow pulse is processed, including: in response to the duty cycle information of the current cycle being in the second interval, the duty cycle information of the next cycle being in the third interval, and half of the sum of the proportion of the high-level time of the lower bridge and the proportion of the high-level time of the upper bridge being less than the proportion of the narrow pulse time, the waveform of the narrow pulse of the current cycle is adjusted; the method further includes: pulling the upper bridge small pulse corresponding to the transistor to a high level.

[0012] Optionally, the duty cycle information includes the duty cycle information of the current cycle and the duty cycle information of the next cycle. Based on the interval, the proportion of the high-level time of the lower bridge, and the proportion of the high-level time of the upper bridge, the narrow pulse is processed, including: in response to the duty cycle information of the current cycle being in the second interval, the duty cycle of the next cycle being in the second device, and half of the sum of the proportion of the high-level time of the lower bridge and the proportion of the high-level time of the upper bridge being less than the proportion of the narrow pulse time, adjusting the waveform of the narrow pulse of the current cycle and the waveform of the narrow pulse of the next cycle; the method further includes: pulling the upper bridge small pulse corresponding to the transistor to a high level.

[0013] Optionally, the method further includes: during the process of adjusting the waveform of the narrow pulse in the current cycle, the register data determined by the waveform adjustment task of the current cycle is moved to the first register through the routing unit corresponding to the transistor, and the waveform is adjusted after the movement is completed; during the process of adjusting the waveform of the narrow pulse in the next cycle, the register data determined by the waveform adjustment task of the next cycle is moved to the second register through the routing unit, and the waveform is adjusted after the movement is completed.

[0014] According to another aspect of the embodiments of this application, a narrow pulse signal processing device for a transistor in a vehicle is also provided. The device may include: an acquisition unit for acquiring current information and position information of a permanent magnet synchronous motor (PMSM), wherein the current information represents the state of the current in the PMSM, and the position information represents the state of the position of the PMSM during rotation; a determination unit for determining the duty cycle information of the transistor based on the current information and position information, wherein the duty cycle information represents the duration for which the transistor drives the PMSM in response to an initial drive signal, and is the ratio of this duration to the signal period of the initial drive signal; a processing unit for processing the narrow pulse in the initial drive signal based on the duty cycle information; and a driving unit for acquiring a target drive signal after the narrow pulse processing is completed, and controlling the transistor to respond to the target drive signal and re-drive the PMSM.

[0015] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided. The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device where the computer-readable storage medium is located to perform the narrow pulse signal processing method for transistors in a vehicle according to the embodiments of this application.

[0016] According to another aspect of the embodiments of this application, a processor is also provided. The processor is used to run a program, wherein the program, when running, executes the narrow pulse signal processing method for transistors in a vehicle according to the embodiments of this application.

[0017] According to another aspect of the embodiments of this application, a computer program product is also provided. This computer program product includes a computer program that, when executed by a processor, implements the narrow pulse signal processing method for transistors in a vehicle as described in the embodiments of this application.

[0018] According to another aspect of the embodiments of this application, a vehicle is also provided. The vehicle may include a memory and a processor. The memory stores an executable program. The processor can be used to run the program, wherein, when the program runs, it executes the narrow pulse signal processing method for transistors in the vehicle described in the embodiments of this application.

[0019] In this embodiment, current and position information of a permanent magnet synchronous motor (PMSM) are acquired. The current information represents the state of the current in the PMSM, and the position information represents the position of the PMSM during rotation. Based on the current and position information, the duty cycle information of a transistor is determined. The duty cycle information represents the duration of the transistor's response to the initial drive signal to drive the PMSM, and is the ratio of this duration to the signal period of the initial drive signal. Based on the duty cycle information, narrow pulses in the initial drive signal are processed. The target drive signal after narrow pulse processing is acquired, and the transistor is controlled to respond to the target drive signal to re-drive the PMSM. In other words, in this embodiment, by real-time acquisition of the PMSM's current and position information, the duty cycle information of the IGBT is accurately calculated, thereby intelligently identifying and correcting narrow pulses. Possible narrow pulses are predicted and eliminated, avoiding repeated switching of the IGBT in an incompletely conducting state, thus reducing switching losses and improving PWM waveform quality. This method fills a gap in related technologies regarding narrow pulse processing, significantly improving motor control accuracy and overall system operating efficiency. By integrating narrow pulse signal processing into the motor control process, the embodiments of this application achieve effective management of narrow pulses, ensuring that the motor can operate stably and efficiently under various operating conditions, reducing energy waste, thereby achieving the technical effect of effectively processing narrow pulse signals and solving the technical problem of not being able to effectively process narrow pulse signals. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0021] Figure 1 This is a flowchart of a narrow pulse signal processing method for a transistor in a vehicle according to an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of a five-segment pulse width modulation signal waveform according to an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of narrow pulse processing for signal switching from interval 3 to interval 3 according to an embodiment of this application;

[0024] Figure 4 This is a schematic diagram of narrow pulse processing for signal switching between interval 3 and interval 4 according to an embodiment of this application;

[0025] Figure 5 This is a schematic diagram of narrow pulse processing for signal switching from interval 5 to interval 3 according to an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of narrow pulse processing for signal switching in interval 4 to interval 5 according to an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of narrow pulse processing for signal switching from interval 4 to interval 4 according to an embodiment of this application;

[0028] Figure 8 This is a schematic diagram of the device structure of a hardware operating environment for a narrow pulse suppression method based on a general-purpose timer module-multi-channel sequencer coprocessor according to an embodiment of this application;

[0029] Figure 9 This is a schematic diagram of a narrow pulse signal processing device for a transistor in a vehicle according to an embodiment of this application. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] According to an embodiment of this application, an embodiment of a narrow pulse signal processing method for transistors in a vehicle is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0033] Figure 1This is a flowchart of a narrow pulse signal processing method for a transistor in a vehicle according to an embodiment of this application, as shown below. Figure 1 As shown, the method may include the following steps:

[0034] Step S102: Obtain the current and position information of the permanent magnet synchronous motor.

[0035] In the technical solution provided in step S102 of this application, the current information can be used to represent the state of the current in the permanent magnet synchronous motor. The position information can be used to represent the position of the permanent magnet synchronous motor during rotation. The vehicle includes a permanent magnet synchronous motor. The transistor is used to respond to the initial drive signal and drive the permanent magnet synchronous motor to run.

[0036] Optionally, a permanent magnet synchronous motor (PMSM) can be a commonly used type of electric motor. In this type of motor, the rotating magnetic field generated by the stator windings rotates synchronously with the permanent magnets on the rotor. It is highly favored in applications such as new energy vehicles and industrial control due to its high efficiency, high power density, and excellent dynamic response characteristics. The working principle of a PMSM relies on precisely controlling the current in the stator windings to generate a magnetic field synchronized with the rotor poles, thereby achieving precise speed and torque control of the motor.

[0037] Alternatively, a transistor can be a solid-state semiconductor device capable of amplifying and switching electronic signals, and is a cornerstone of modern electronic technology. In the field of motor control, especially in the drive systems of new energy vehicles, transistors such as IGBTs can be widely used as key components for power conversion, responsible for converting the DC power from the battery into the AC power required to drive the motor, and regulating the motor's drive power by controlling its on and off states.

[0038] Optionally, the current information can refer to the magnitude and direction of the current flowing through the phase windings of the motor. For permanent magnet synchronous motors, this current information can be three-phase current (U-phase, V-phase, and W-phase). This current information can be an important input to the motor control algorithm, used to monitor the motor's operating status in real time and ensure that the motor operates at optimal efficiency. By collecting and analyzing the three-phase current information, the controller can determine the motor's load, operating status, and faults, and then adjust the control strategy to optimize motor performance.

[0039] Optionally, in a permanent magnet synchronous motor, position information can refer to the rotor's position information, specifically the physical position of the rotor's magnetic poles relative to the stator. Rotor position is a key parameter in the motor control system for achieving precise speed and position control. During motor operation, the controller needs to acquire the rotor position in real time to determine the optimal current phase and achieve synchronous drive of the motor. Rotor position information is typically acquired through position sensors (such as Hall effect sensors or encoders) and is an indispensable part of the motor control algorithm, directly affecting the motor's operating efficiency and accuracy.

[0040] Optionally, the initial drive signal can be a PWM signal.

[0041] In this embodiment, the current information and position information of the permanent magnet synchronous motor can be obtained.

[0042] Optionally, ensure that the current sensor and position sensor (such as an encoder) are correctly connected to the control system interface. Initialize the sensors, including setting parameters such as sampling frequency and sensor range, to ensure the accuracy and real-time performance of data acquisition. Read the current (U, V, W phases) flowing through the three-phase windings of the permanent magnet synchronous motor in real time using a current sensor (such as a current transformer or shunt resistor). Amplify and filter the analog signal output from the sensors using a signal conditioning circuit to eliminate noise interference and improve signal quality. Use an analog-to-digital converter (ADC) to convert the conditioned analog current signal into a digital signal for subsequent digital signal processing. In a microcontroller or digital signal processor (DSP), process the digital current signal, for example, by filtering and averaging, to obtain a more accurate current state.

[0043] Optionally, a position sensor (such as an absolute or incremental encoder) can be used to read the real-time position of the permanent magnet synchronous motor rotor. The pulse signals or coded information output by the position sensor are decoded and converted into angular or linear position data of the rotor. It is ensured that the sampling of position information and current information are synchronized in time to accurately reflect the real-time operating status of the motor. Based on the characteristics of the motor, the position information is transformed from physical coordinates to the motor coordinate system, facilitating the use of motor control algorithms.

[0044] Step S104: Determine the duty cycle information of the transistor based on the current information and the position information.

[0045] In the technical solution provided in step S104 of this application, the duty cycle information is used to represent the duration of the transistor responding to the initial drive signal to drive the permanent magnet synchronous motor, which is the ratio of the duration of the initial drive signal to the signal period of the initial drive signal.

[0046] Optionally, duty cycle information can refer to the proportion of time a control signal (e.g., PWM) is active (e.g., high-level state, representing the time a transistor is on) within a complete cycle. This proportion is obtained by dividing the active time of the signal by the entire signal cycle and can be expressed as a percentage (e.g., a 50% duty cycle means the signal is high for 50% of the time within a cycle). Duty cycle information (also called duty cycle command) is calculated based on real-time current and position information and is used to guide the IGBT's turn-on and turn-off times, thereby controlling the motor's torque and speed. The duty cycle command determines the IGBT's on-time, which directly affects the current distribution in the motor windings, thus affecting the motor's mechanical output characteristics.

[0047] In this embodiment, during the process of acquiring the current information and position information of the permanent magnet synchronous motor, the duty cycle information of the transistor can be determined based on the current information and position information.

[0048] Optionally, current data for the three-phase windings (U, V, and W phases) are acquired from the ADC. Rotor position information is read from a position sensor (such as an encoder). The current and position data are ensured to be synchronized in time to reflect the motor's operating status at a specific point in time. The magnitude, direction, and trend of the three-phase currents are evaluated to determine if the motor is overloaded or close to overload. Based on the rotor position information, the motor's operating speed, acceleration, and position status are determined to identify whether the motor is in a specific operating phase or position.

[0049] Optionally, a mathematical model of a permanent magnet synchronous motor (PMSM) is used to calculate the motor's back electromotive force and inductance based on the current and position information. The motor's dynamic characteristics, such as the relationship between electromagnetic torque and current, and the influence of the electromagnetic field on motor performance, are considered.

[0050] Optionally, the duty cycle is adjusted based on the motor's current state to maintain the current near the desired value, ensuring stable torque output from the motor. Combined with the motor's position information, the duty cycle is adjusted to control the motor speed, enabling it to reach or maintain the target speed. A more advanced control strategy is used to decouple the motor's current and magnetic flux, independently controlling the motor's magnetic field and current to achieve optimal motor performance. Based on the calculation results of the above control algorithm, a suitable duty cycle ratio for the current motor state is determined, ensuring an appropriate ratio between the transistor's on-time and the signal period. The specific pulse width is calculated, i.e., the length of time the transistor should be on within the signal period, which directly determines the duty cycle of the PWM (Pulse Width Modulation) signal.

[0051] Step S106: Based on the duty cycle information, process the narrow pulse in the initial drive signal.

[0052] In the technical solution of step S106 of this application, a narrow pulse can refer to a pulse signal with a very short duration, less than the switching delay time of a transistor (such as an IGBT). A PWM signal consists of a series of repetitive pulses, and by changing the pulse width (i.e., duty cycle), the average value of the output voltage is controlled, thereby adjusting parameters such as the speed and torque of the motor.

[0053] In this embodiment, after determining the transistor's duty cycle information based on current and position information, the narrow pulse in the initial drive signal can be processed based on the duty cycle information.

[0054] Optionally, the latest duty cycle information Dm calculated by the motor control algorithm is received, reflecting the required drive strength and direction of the motor. The state of the current PWM cycle is analyzed to determine the operating interval (interval 1 to interval 5) where the duty cycle command Dm1 is located, which is the basis for processing narrow pulses. Based on the prediction mechanism of the motor control algorithm, or by observing the trend of duty cycle changes, the duty cycle command Dm2 for the next PWM cycle is estimated.

[0055] Step S108: Obtain the target drive signal after the narrow pulse processing is completed, and control the transistor to respond to the target drive signal to restart the permanent magnet synchronous motor.

[0056] In the technical solution of step S108 of this application, the target drive signal can refer to the PWM signal that is finally used to drive the motor after a series of processing (including but not limited to narrow pulse suppression processing). The target drive signal is a key output in the motor control system, which determines the real-time operating status and performance of the motor.

[0057] In this embodiment, after processing the narrow pulses in the initial drive signal based on duty cycle information, the target drive signal after the narrow pulse processing can be obtained. The transistor can then be controlled to respond to the target drive signal and restart the permanent magnet synchronous motor.

[0058] Optionally, after processing the narrow pulse, the Multi-Channel Sequencer (MCS) transmits the corrected PWM information, i.e., the target drive signal, back to the main controller or directly writes it into the register used for PWM output. The main controller or register is ready to receive this data and, once received, is immediately ready to execute it. After receiving the target drive signal, it is converted into a level signal that can be used to drive transistors (such as IGBTs). The above process may include converting the digital PWM signal into an appropriate analog signal or ensuring that the signal format is compatible with the power electronics module.

[0059] Optionally, after receiving the target drive signal, the IGBT responds according to the signal's duty cycle information, that is, it turns on and off in a timely manner according to the high and low level periods of the signal. The on and off times strictly follow the high-level time proportion defined in the PWM signal to ensure that the voltage and current on the motor windings change according to a predetermined pattern. When the IGBT operates according to the target drive signal, it begins to deliver precisely controlled current to the permanent magnet synchronous motor, restarting the motor operation according to the currently set duty cycle information. The motor's operating status (such as speed and torque) will be adjusted according to the new PWM signal mode to achieve more efficient power output and smoother operation.

[0060] Optionally, during motor operation, the control unit continuously monitors key parameters such as motor current and rotor position to verify the effectiveness of the target drive signal. The collected motor operation data is fed back to the motor control algorithm as input for subsequent duty cycle calculation and narrow pulse processing, forming a closed-loop control system to ensure the accuracy and timeliness of the system response. If the monitored motor operating state does not meet expectations, or a new narrow pulse signal is detected, the system will re-enter step S104 to calculate new duty cycle information. The narrow pulse processing and target drive signal generation and application process will be executed again to adapt to constantly changing operating conditions and requirements.

[0061] In steps S102 to S108 of this application, current and position information of the permanent magnet synchronous motor are acquired. The current information represents the state of the current in the permanent magnet synchronous motor, and the position information represents the position of the permanent magnet synchronous motor during rotation. Based on the current and position information, the duty cycle information of the transistor is determined. The duty cycle information represents the duration of the transistor's response to the initial drive signal to drive the permanent magnet synchronous motor, and is the ratio of this duration to the signal period of the initial drive signal. Based on the duty cycle information, narrow pulses in the initial drive signal are processed. The target drive signal after narrow pulse processing is acquired, and the transistor is controlled to respond to the target drive signal to re-drive the permanent magnet synchronous motor. In other words, in this embodiment, by real-time acquisition of the current and position information of the permanent magnet synchronous motor, the duty cycle information of the IGBT is accurately calculated, thereby intelligently identifying and correcting narrow pulses, predicting and eliminating potential narrow pulses, avoiding repeated switching of the IGBT in an incompletely conducting state, thus reducing switching losses and improving the PWM waveform quality. This method fills the gap in related technologies for narrow pulse processing, significantly improving motor control accuracy and overall system operating efficiency. By integrating narrow pulse signal processing into the motor control process, the embodiments of this application achieve effective management of narrow pulses, ensuring that the motor can operate stably and efficiently under various operating conditions, reducing energy waste, thereby achieving the technical effect of effectively processing narrow pulse signals and solving the technical problem of not being able to effectively process narrow pulse signals.

[0062] The method described in this embodiment will be further described below.

[0063] As an optional embodiment, the method further includes: obtaining the percentage of the lower bridge high-level time of the transistor and the percentage of the upper bridge high-level time of the transistor; step 106, processing the narrow pulse in the initial drive signal based on the duty cycle information, including: determining the interval where the duty cycle information is located; processing the narrow pulse based on the interval, the percentage of the lower bridge high-level time, and the percentage of the upper bridge high-level time.

[0064] In this embodiment, the lower bridge high-level time percentage Db refers to the percentage of the total time that the IGBT of the lower bridge arm is in the on state (i.e., outputting a high-level signal) within a complete PWM signal cycle. A larger Db indicates a longer IGBT on-time in the lower bridge arm, which is typically used to provide negative current to the motor windings (i.e., to draw current from the motor windings). Adjusting Db is crucial for controlling motor deceleration, braking, and energy recovery. In the motor control logic, if half of the sum of the lower bridge high-level time percentages in two consecutive PWM cycles is less than the preset narrow pulse time percentage Dn, a narrow pulse in the lower bridge arm may occur, requiring processing to avoid additional losses in the IGBT's incomplete on-state.

[0065] Optionally, the high-level time percentage Dt can refer to the percentage of the total time that the IGBT of the upper bridge arm is in the on state (i.e., outputting a high-level signal) within a complete PWM signal cycle. Increasing Dt means that the IGBT on time of the upper bridge arm increases, which is usually to provide positive current to the motor windings (i.e., inject current into the motor windings). Adjusting Dt also has a significant impact on the motor's acceleration, forward rotation, and other operations. Similarly, if half of the sum of the high-level time percentages of the upper bridge arm in two consecutive PWM cycles is less than the preset narrow pulse time percentage Dn, narrow pulses of the upper bridge arm may be generated, requiring corresponding suppression measures to ensure the stability of the PWM signal and the reliable operation of the IGBT.

[0066] Optionally, in obtaining the proportion of the lower bridge high-level time and the proportion of the upper bridge high-level time of the transistor, in motor control systems, the H-bridge inverter is a common structure, consisting of four IGBTs (Insulated Gate Bipolar Transistors), divided into upper and lower bridge arms. The IGBTs of the upper and lower bridge arms alternately conduct to generate PWM (Pulse Width Modulation) signals to control the current of the motor windings. The lower bridge high-level time proportion Db refers to the ratio of the time the lower bridge arm IGBT is in the conducting state to the entire cycle time in a certain PWM cycle. The upper bridge high-level time proportion Dt correspondingly represents the proportion of the upper bridge arm IGBT's conducting time in the same cycle. The above two time proportions reflect the motor control algorithm's immediate requirements for the direction and magnitude of the motor winding current, and are key factors determining the motor torque and speed.

[0067] Optionally, during the processing of narrow pulses in the initial drive signal based on the duty cycle information, it can be determined which predefined working interval the current duty cycle command Dm falls within, such as intervals 1 to 5 as mentioned above. This helps determine the shape of the PWM signal and the potential risk of narrow pulses. The interval division is based on preset narrow pulse time proportions Dn and dead time proportions Dd. By considering different ranges of Dm values, the system can predict and identify whether narrow pulses may occur. For example, when the Dm value falls within interval 3, due to the special nature of this interval, the system needs to be extra careful to avoid the generation of narrow pulses.

[0068] Optionally, during the narrow pulse processing based on the interval, the proportion of high-level time of the lower bridge, and the proportion of high-level time of the upper bridge, the duty cycle instructions Dm1 and Dm2 of the current PWM cycle and the next cycle, as well as the corresponding high-level time proportions Db and Dt of the lower and upper bridges, can be analyzed to determine whether a narrow pulse will form. If a narrow pulse risk is detected, the system adopts corresponding processing strategies according to the intervals in which Dm1 and Dm2 are located. For each type of interval switching, there are specific processing logic and methods, such as extending the conduction time of adjacent cycles or adjusting the duty cycle information of the PWM signal through the calculation of the MCS coprocessor to ensure that the PWM output does not trigger a narrow pulse.

[0069] Optionally, the key to handling narrow pulses lies in adjusting the width of the PWM signal to ensure that the IGBT has sufficient time to fully turn on or off, even with rapid changes in the duty cycle. If the calculated narrow pulse time percentage is too small, intervention can be implemented to prevent the IGBT from frequently switching in an incompletely on state. By using the MCS coprocessor to perform complex logic judgments and data operations, the narrow pulse suppression task is offloaded from the Central Processing Unit (CPU), reducing the computational burden and avoiding impact on real-time performance. This can include directly modifying the PWM signal of the current cycle or preprocessing the PWM signal of the next cycle, writing it into specific registers to achieve immediate or pre-scheduled narrow pulse suppression. The processed PWM signal is called the target drive signal. This signal, while avoiding narrow pulses, can more effectively control the IGBT, thereby precisely driving the permanent magnet synchronous motor and improving the efficiency and reliability of motor control.

[0070] As an optional embodiment, the duty cycle information includes the duty cycle information of the current cycle and the duty cycle information of the next cycle. Based on the interval, the proportion of the high-level time of the lower bridge, and the proportion of the high-level time of the upper bridge, the narrow pulse is processed, including: in response to the duty cycle information of the current cycle being in the first interval, the duty cycle information of the next cycle being in the first interval, and half of the sum of the proportion of the high-level time of the lower bridge and the proportion of the high-level time of the upper bridge being less than the proportion of the narrow pulse time, adjusting the waveform of the narrow pulse of the current cycle and the waveform of the narrow pulse of the next cycle; the method further includes: pulling the lower bridge small pulse corresponding to the transistor to a low level.

[0071] In this embodiment, the duty cycle information Dm1 for the current cycle refers to the duty cycle information of the PWM signal calculated by the motor control algorithm in the current control loop, that is, the percentage of the high-level signal in the entire signal cycle within the current cycle. Dm1 directly affects the magnitude and direction of the current in the motor windings within the current cycle. Dm1 is used to adjust the motor's operating state in real time to ensure that the motor operates according to the predetermined torque and speed requirements. The duty cycle information Dm2 for the next cycle refers to the duty cycle information of the PWM signal that will be used in the next control loop. The aforementioned Dm1 is calculated based on motor operation prediction or the dynamic adjustment strategy of the motor control algorithm. By predicting Dm2, narrow pulse problems that may occur in the next cycle can be identified and handled in advance, ensuring the smoothness and continuity of motor control.

[0072] Optionally, the first interval may refer to a specific duty cycle range defined in motor control. In this embodiment, the first interval may be Interval 3, which represents a specific area in duty cycle control where narrow pulses may occur and require special attention. Identifying whether Dm1 and Dm2 are within the first interval (such as Interval 3) is a key step in determining whether narrow pulse processing is needed. The narrow pulse time ratio Dn is a preset threshold used to determine whether there are narrow pulses in the PWM signal, that is, whether the duration of a pulse is less than the minimum stable switching time of the IGBT (Insulated Gate Bipolar Transistor). Dn is used to identify the narrow pulse conditions that need to be processed. When (Db + Dt) / 2 is less than Dn, it indicates that there may be narrow pulses in the current and next cycle PWM signals, and waveform adjustment is required.

[0073] Optionally, the lower-bridge small pulse may refer to a narrow high-level pulse received by the lower-bridge arm IGBT in the PWM signal. If the pulse width is too small, it may not be able to fully turn on or off the IGBT, resulting in additional switching losses. Identifying and processing the lower-bridge small pulse helps to avoid unnecessary losses of the IGBT in the motor drive circuit and ensure the efficiency and stability of motor operation. The low level can represent a 0 potential or a potential close to the negative pole of the power supply, corresponding to the off state of the IGBT. At this time, the motor winding is disconnected from the power supply and does not receive current input or output. Pulling the lower-bridge small pulse to the low level means eliminating the narrow pulse and fully turning off the lower-bridge arm IGBT, avoiding the switching losses and inaccurate motor control problems caused by narrow pulses.

[0074] Optionally, obtain the duty cycle information Dm1 of the current cycle and the duty cycle information Dm2 of the next cycle. The duty cycle information indicates the relative time ratio of the high level to the low level in the PWM signal and directly determines the magnitude and direction of the current in the motor winding. Check whether both Dm1 and Dm2 are within a predefined first interval (such as Interval 3). The interval division is based on the special requirements of motor control and the understanding of potential narrow pulse problems, aiming to identify high-risk operating conditions for targeted measures. Further calculate the sum of half of the high-level time ratio Db of the lower bridge and the high-level time ratio Dt of the upper bridge. This step is used to evaluate whether there is a narrow pulse risk in the current and next cycle PWM signals. If (Db + Dt) / 2 < Dn (narrow pulse time ratio), it indicates that in the current and next cycles, due to the rapid switching of the upper and lower bridge arm IGBTs, narrow pulses may occur and waveform adjustment is required.

[0075] Optionally, if the above conditions are met, that is, both Dm1 and Dm2 are in the first interval, and (Db + Dt) / 2 < Dn, the system will adjust the narrow pulses of the PWM signal in this period and the next period. The adjustment can be achieved by modifying the duty cycle of the PWM waveform or extending the width of some pulses. The purpose is to ensure that the IGBT has enough time to fully conduct or turn off during switching, avoiding the additional energy consumption and system instability caused by narrow pulses.

[0076] Optionally, the small pulses that the lower-arm IGBT may encounter will be processed. The specific operation is to pull them to the low level, that is, to ensure that the lower arm is always in the off state under narrow pulse conditions. By keeping the lower arm off during narrow pulses, unnecessary energy loss and electromagnetic interference caused by incomplete conduction of the IGBT can be effectively avoided. At the same time, the short-circuit risk when the upper and lower arms conduct simultaneously is prevented, improving the stability and safety of the system.

[0077] In the embodiment of the present application, the above method describes a refined motor control process, especially focusing on how to optimize the motor drive efficiency through PWM waveform adjustment in the high duty cycle change rate and narrow pulse sensitive interval. Specifically, the system evaluates the duty cycle information of the next period within each control period, and combines the actual situation of the current signal to pre-judge whether narrow pulses will occur. If there is a narrow pulse risk, the system will adopt a waveform adjustment strategy, focusing on eliminating the narrow pulses of the lower arm to protect the IGBT from excessive loss and ensure the smoothness and accuracy of motor control.

ID=7

[0078] As an optional embodiment, the duty cycle information includes the duty cycle information of this period and the duty cycle information of the next period. Based on the interval, the ratio of the high-level time of the lower arm, and the ratio of the high-level time of the upper arm, the narrow pulses are processed, including: in response to the duty cycle information of this period being in the first interval, the duty cycle information of the next period being in the second interval, and half of the sum of the ratio of the high-level time of the lower arm and the ratio of the high-level time of the upper arm being less than the narrow pulse time ratio, adjusting the waveform of the narrow pulse in this period; the method further includes: pulling the small pulses of the lower bridge corresponding to the transistor to the low level. <{

[0079] In this embodiment, the second interval can be interval 4, which is a specific region defined according to the motor control requirements and the characteristics of the PWM signal. Interval 4 can be defined as a high-duty-cycle region, that is, the duty-cycle command Dm is close to 1 but slightly less than 1. This means that the high-level duration in the PWM signal is very long, almost covering the entire signal cycle, while the low-level duration is very short, only for the dead time to avoid the short-circuit phenomenon of simultaneous conduction of the upper and lower bridge arms. When the motor needs high torque output or requires maximizing power utilization efficiency in a specific operation mode, the setting of interval 4 is particularly important. A higher duty cycle means a larger current flowing through the motor winding, thereby generating a greater electromagnetic force to drive the motor to produce high torque.

[0080] Optionally, in the process of obtaining and evaluating the duty-cycle information, for the current-cycle duty-cycle information Dm1, the duty-cycle information of the current cycle can be obtained, which is used to reflect the ratio of the high-level time to the low-level time in the current PWM signal. For the next-cycle duty-cycle information Dm2, the duty-cycle information of the next control cycle can be estimated or calculated. The first interval is interval 3, representing a relatively stable PWM signal range in motor control, but still needs to be vigilant about the generation of narrow pulses. The second interval is interval 4, meaning an interval with a higher duty cycle, where the motor may require greater torque or be in a higher power output state. The narrow-pulse time ratio Dn can be a preset threshold used to identify whether there is a possibility of forming narrow pulses in the current command change. If the sum of half of the high-level time ratio Dt of the upper bridge and the high-level time ratio Db of the lower bridge is less than Dn, the system identifies the narrow-pulse risk.

[0081] Optionally, when it is detected that Dm1 is in the first interval (such as interval 3), Dm2 will jump to the second interval (such as interval 4), and when (Db + Dt) / 2 < Dn, it means that there is a risk of narrow-pulse generation during the signal switching process, that is, the transition from the current cycle to the next cycle. Immediately adjust the PWM waveform within the current cycle to eliminate or mitigate the impact of narrow pulses. This may involve changing the duty cycle of the PWM signal, extending or shortening the duration of a certain level, to ensure the stability of the PWM signal and the normal operation of the IGBT (Insulated Gate Bipolar Transistor).

[0082] Optionally, pulling the lower-bridge small pulse to the low level is essentially to modify the PWM signal to ensure that when the narrow-pulse risk appears, the IGBT of the lower bridge arm remains in the off state, avoiding additional losses and electromagnetic interference caused by unstable IGBT switching states. By eliminating narrow pulses, the system can avoid the IGBT from switching when it is not fully turned on or off, reducing the switching loss and improving the efficiency and reliability of motor control.

[0083] In this embodiment, the above method, by introducing the prediction and evaluation of duty cycle information for the current and next cycles into the motor control algorithm, can identify the potential risk of narrow pulse formation in advance. By adjusting the PWM waveform and handling the low-level lower bridge pulse, the system not only avoids the negative impact of narrow pulses but also optimizes the motor drive signal, ensuring the smoothness and efficiency of motor operation. When the duty cycle command jumps from the first interval (e.g., interval 3) to the second interval (e.g., interval 4), the system checks the proportion of high-level time between the lower and upper bridges to determine whether waveform adjustment is necessary. This mechanism reflects the intelligent response of the motor control system to duty cycle changes. Through the intervention of the MCS coprocessor, the computational burden of the CPU is effectively shared, improving the system's real-time performance and response speed. Furthermore, the strategy of pulling the lower bridge pulse to a low level further ensures the accuracy of motor control and the safe operation of the IGBT under high duty cycles.

[0084] As an optional embodiment, the duty cycle information includes the duty cycle information of the current cycle and the duty cycle information of the next cycle. Based on the interval, the proportion of the high-level time of the lower bridge, and the proportion of the high-level time of the upper bridge, the narrow pulse is processed, including: in response to the duty cycle information of the current cycle being in the third interval, the duty cycle information of the next cycle being in the first interval, and half of the sum of the proportion of the high-level time of the lower bridge and the proportion of the high-level time of the upper bridge being less than the proportion of the narrow pulse time, the waveform of the narrow pulse of the next cycle is adjusted; the method further includes: pulling the lower bridge small pulse corresponding to the transistor to a low level.

[0085] In this embodiment, the third interval (interval 5) can represent a special operating state where the motor drive signal is in a range close to or equal to the maximum duty cycle. This third interval corresponds to the case where the PWM signal is at its longest high-level duration or remains completely high, and is therefore also referred to as the full-conduction state or saturation state. Interval 5 can be defined as the case where the duty cycle command Dm equals 1, meaning that the PWM signal remains almost or completely high throughout the entire control cycle, and the motor windings continuously receive the maximum possible current supply. In motor control, especially when the vehicle needs to accelerate urgently, overcome steep slopes, or otherwise require extremely high torque, the system will automatically or manually enter interval 5 to utilize the motor's maximum power output capability. However, prolonged or frequent entry into saturation state can also affect the lifespan of the motor and drive circuitry, as it increases thermal load and mechanical stress.

[0086] Optionally, in the narrow pulse suppression method based on the Generic Timer Module-MultiChannel Sequencer (GTM-MCS) coprocessor, specific processing strategies are designed for the switching between different duty cycle information intervals to ensure the stability and efficiency of the motor control signal.

[0087] Optionally, the third interval (such as interval 5) can represent a fully-conducted state, that is, the duty cycle command Dm1 equals 1, meaning the PWM signal is almost always in the high-level state within this cycle. In this case, the motor winding almost continuously obtains the maximum current to achieve the highest torque or power output. Compared with the third interval, the first interval (such as interval 3) represents an interval where the duty cycle command Dm2 is within the normal control range, and the high and low level switching of the motor control signal is more frequent to adapt to different torque and speed control requirements. When Dm1 is in the third interval (fully-conducted state) and Dm2 is about to enter the first interval, the system needs to pay special attention to the generation of narrow pulses. Because when quickly switching from the fully-conducted state to a lower duty cycle, short narrow pulses may occur, which can increase the switching loss of the IGBT and even lead to control instability. The narrow pulse time ratio Dn is a predefined threshold used to determine whether the pulses in the PWM signal belong to narrow pulses. Narrow pulses easily cause the IGBT to switch in a non-fully stable state, increasing the loss.

[0088] Optionally, if it is detected that Dm1 is in the third interval and Dm2 is about to enter the first interval, and (Db + Dt) / 2 < Dn, it means that the system predicts that narrow pulses may be generated during the next cycle signal switching, and it becomes necessary to adjust the PWM waveform of the next cycle. During the process of adjusting the waveform of the narrow pulse in the next cycle, when the narrow pulse risk is predicted, the MCS coprocessor will be used to adjust the PWM signal of the next cycle to eliminate or weaken the influence of the narrow pulse. The adjustment may include modifying the specific waveform of the PWM signal, such as by extending the conduction time of the lower or upper bridge arm to ensure that the IGBT completes the switch conversion in a stable state.

[0089] Optionally, the processing strategy of pulling the lower-bridge small pulse to the low level is specifically for the IGBT of the lower bridge arm. By forcibly pulling the lower-bridge small pulse that may form a narrow pulse to the low level, it can be ensured that the IGBT of the lower bridge arm will not attempt to switch from the fully-conducted state to the low-conducted state in too short a time during the next cycle signal switching, avoiding the occurrence of narrow pulses, thereby reducing the switching loss and improving the efficiency and stability of motor control.

[0090] In this embodiment, the method emphasizes how to prevent and resolve narrow pulse problems during the switching process from one extreme (fully on state) to another normal range (first range) through proactive PWM waveform adjustment and intelligent circuit control strategies. With the intervention of the MCS coprocessor, the system can effectively handle narrow pulses without affecting the overall real-time control performance, reducing reliance on the CPU while ensuring the accuracy of motor control signals and the safe operation of the IGBT. This method fully demonstrates the advantages of advanced control logic working in tandem with hardware in a motor control system, improving the intelligence level of motor control through precise duty cycle management and signal adjustment.

[0091] As an optional embodiment, the duty cycle information includes the duty cycle information of the current cycle and the duty cycle information of the next cycle. Based on the interval, the proportion of the high-level time of the lower bridge, and the proportion of the high-level time of the upper bridge, the narrow pulse is processed, including: in response to the duty cycle information of the current cycle being in the second interval, the duty cycle information of the next cycle being in the third interval, and half of the sum of the proportion of the high-level time of the lower bridge and the proportion of the high-level time of the upper bridge being less than the proportion of the narrow pulse time, the waveform of the narrow pulse of the current cycle is adjusted; the method further includes: pulling the small pulse of the upper bridge corresponding to the transistor to a high level.

[0092] In this embodiment, in the narrow pulse suppression method based on the GTM-MCS coprocessor, the dynamic response to the duty cycle information of the current cycle and the waveform adjustment strategy are the key to ensuring the stability and efficiency of the power electronic system.

[0093] Optionally, when Dm1 is in the second interval, about to reach the edge of the fully on state, and Dm2 enters the third interval, meaning the signal will become fully on in the next cycle, the system will assess the risk of narrow pulses during signal switching. If the average of the calculated proportions of the lower bridge high-level time Db and the upper bridge high-level time Dt (i.e., (Db+Dt) / 2) is less than the proportion of narrow pulse time Dn, it indicates the possibility of narrow pulses during rapid signal changes. To eliminate or mitigate the impact of narrow pulses, the system will adjust the PWM waveform within the current cycle to ensure a smooth transition to the fully on state, preventing the IGBT from experiencing additional switching shocks, thereby reducing system switching losses and improving stability.

[0094] Optionally, the upper bridge pulse is pulled high, and in motor control, the IGBTs of the upper and lower bridge arms are alternately turned on to achieve PWM modulation. When the system detects that the switching from the second to the third interval may generate a narrow pulse, it will take measures to force the level of the upper bridge pulse to a high level. The purpose of this is to eliminate any narrow pulses that may cause the IGBT to switch in a non-ideal state before the signal becomes fully on in the next cycle (i.e., when Dm2 is in the third interval), ensuring that the IGBT can smoothly and completely enter the fully on state.

[0095] In this embodiment, the method described above, by proactively adjusting the PWM waveform within the current cycle, effectively avoids narrow pulses during the transition from near-full conduction to full conduction. By pulling the upper bridge pulse to a high level, the signal changes are ensured to be smooth and controllable, avoiding the additional stress on the IGBT due to narrow pulses. This optimizes the overall performance of motor control, reduces switching losses, improves energy efficiency, and extends the lifespan of power electronic devices.

[0096] As an optional embodiment, the duty cycle information includes the duty cycle information of the current cycle and the duty cycle information of the next cycle. Based on the interval, the proportion of the high-level time of the lower bridge, and the proportion of the high-level time of the upper bridge, the narrow pulse is processed, including: in response to the duty cycle information of the current cycle being in the second interval, the duty cycle of the next cycle being in the second device, and half of the sum of the proportion of the high-level time of the lower bridge and the proportion of the high-level time of the upper bridge being less than the proportion of the narrow pulse time, adjusting the waveform of the narrow pulse of the current cycle and the waveform of the narrow pulse of the next cycle; the method further includes: pulling the upper bridge small pulse corresponding to the transistor to a high level.

[0097] In this embodiment, in the narrow pulse suppression method based on the GTM-MCS coprocessor, continuous evaluation of the duty cycle information of the current cycle and the next cycle, as well as fine adjustment of the PWM waveform, are the key to ensuring the stability and efficiency of the motor control system.

[0098] Optionally, during the adjustment of the waveform of narrow pulses in the current and next cycles, if a risk of narrow pulses is detected, the MCS coprocessor will execute a waveform adjustment program to adjust the PWM waveform of the current and upcoming cycles in real time to eliminate narrow pulses. This adjustment may include extending the duration of a certain level to ensure that the IGBT has sufficient time to complete a stable transition from off to on or from on to off, thereby reducing switching losses and improving the smoothness of the output waveform.

[0099] Optionally, the upper bridge pulse can be pulled high. During narrow pulse suppression, to further optimize signal stability, the system will take measures to pull the upper bridge pulse high, even when the duty cycle command Dm is within the normal range. Specifically, this means the system will automatically adjust the PWM signal to ensure that the IGBT of the upper bridge arm does not experience unnecessary narrow pulses during signal switching, even if these narrow pulses may be generated due to minor fluctuations in the duty cycle command.

[0100] In this embodiment, the narrow pulse suppression method still plays a crucial role even when the duty cycle information is in a relatively stable second interval. By adjusting the PWM waveforms of the current and next cycles, and by specifically processing the high-level pulses of the upper bridge, not only can potential narrow pulses be eliminated, but the smoothness and accuracy of the motor control signal can also be further optimized. This forward-looking adjustment strategy reflects a high degree of attention to the integrity of the motor control signal and the health status of the IGBT. Through intelligent monitoring and dynamic adjustment, the efficient operation of the motor control system under various operating conditions is ensured.

[0101] As an optional embodiment, the method further includes: during the process of adjusting the waveform of the narrow pulse in the current cycle, the register data determined by the waveform adjustment task of the current cycle is moved to the first register through the routing unit corresponding to the transistor, and the waveform is adjusted after the movement is completed; during the process of adjusting the waveform of the narrow pulse in the next cycle, the register data determined by the waveform adjustment task of the next cycle is moved to the second register through the routing unit, and the waveform is adjusted after the movement is completed.

[0102] In this embodiment, the routing unit can be an Advanced Routing Unit (ARU), which is an advanced data routing and control mechanism and an important component of the GTM. The ARU is responsible for the rapid transfer of data and control signals between different GTM modules, such as the MCS and the Analog Timer Output Module (ATOM), Basic Timer Module (TIM), and Timer Output Management Module (TOM), supporting complex signal processing and event response. In the narrow pulse suppression method, the ARU is used to efficiently transfer the register data calculated by the MCS task from the MCS's Random Access Memory (RAM) to the target register. The target register can be the ATOM's Compare Match Register (CM), such as CM0 / CM1, or the Shadow Register (SR), such as SR0 / SR1, to update the PWM waveform in real time or prepare the signal output for the next cycle. The presence of ARU greatly improves the system's response speed and flexibility, enabling the calculation results of the MCS task to be quickly applied to waveform adjustment, thus ensuring the real-time performance and accuracy of motor control.

[0103] Optionally, the waveform adjustment task can be an MCS task, referring to the timing and control logic executed by the MCS. The aforementioned MCS task can refer to the algorithm and processing flow used for narrow pulse suppression, capable of analyzing and determining the PWM waveform to be adjusted based on the input duty cycle information, and how to perform the adjustment. Based on the given duty cycle instruction and the current state of the system, the MCS task calculates new parameters of the PWM signal to be adjusted, such as the time proportions of high and low levels, and then generates corresponding register data to guide the waveform adjustment. By executing these tasks in the MCS, the bottleneck of the CPU can be overcome, enabling real-time signal processing and optimization, thereby improving the efficiency of motor control and reducing switching losses.

[0104] Optionally, register data can refer to values ​​stored in hardware registers after a specific computational task is performed. In the narrow pulse suppression method, this data includes adjusted PWM waveform parameters, such as high-level duration and low-level duration, which are used to configure the timer module to generate a new PWM signal. The register data, as the output of the MCS task, is transferred by the ARU to the designated register to update the PWM signal parameters and achieve waveform adjustment.

[0105] Optionally, the first register can be the ATOM CM0 / CM1 register. The ATOM CM0 / CM1 register can be part of the ATOM in the general-purpose timer module (GTM) and is used to store parameters required for PWM waveform adjustment in the current cycle, such as comparison matching values, which directly affect the generation of the PWM signal. During waveform adjustment, the register data for the current cycle determined by the MCS task will be moved to the CM0 or CM1 register via the ARU to immediately update the PWM waveform and ensure the correct output of the signal in this cycle.

[0106] Optionally, the second register can be the ATOM SR0 / SR1 register. SR0 and SR1 are also registers in the ATOM module, used to store the parameters required for adjusting the PWM waveform in the next cycle, i.e., the preset signal output parameters, ensuring that the PWM signal can be output according to the pre-calculated parameters at the start of the next cycle. When adjusting the PWM waveform in the next cycle, the register data determined by the MCS task will be moved to the SR0 or SR1 register. This data will take effect at the start of the next cycle, thus achieving seamless switching and adjustment of the PWM waveform.

[0107] Optionally, this embodiment illustrates the technical details of how to adjust the PWM signal waveform of the current cycle and the next cycle through an Advanced Routing Unit (ARU) in a narrow pulse suppression method based on a GTM-MCS coprocessor. The core of these steps lies in using the ARU to efficiently transfer data between the MCS and ATOM modules, thereby achieving real-time and preset adjustments to the PWM waveform and ensuring the stability and efficiency of the motor control signal.

[0108] Optionally, when a narrow pulse is detected in the current cycle, the MCS begins to execute a waveform adjustment task. This task calculates the required register data based on the current duty cycle instruction and system configuration parameters (such as the narrow pulse time percentage Dn and dead time percentage Dd). This register data can be used to adjust the PWM waveform to avoid problems caused by narrow pulses. After determining the adjustment strategy, the register data generated by the MCS needs to take effect immediately to adjust the waveform of the current cycle. The ARU, as the high-level routing unit in the GTM module, is responsible for quickly moving the above register data from the MCS's RAM to the CM0 or CM1 register in the ATOM module. The CM0 / CM1 register controls the high-level duration of the PWM signal in the current cycle; therefore, the moved data directly affects the shape of the PWM waveform in the current cycle.

[0109] Optionally, after the register data is moved to CM0 / CM1, the timer begins monitoring the signal count value within the current cycle and triggers a high-level or low-level switch of the PWM signal when the comparison match value in CM0 / CM1 is reached. Through the calculations of the MCS and the data movement of the ARU, real-time suppression of narrow pulses in the PWM signal of the current cycle is achieved. To seamlessly adjust the PWM signal, the MCS can perform waveform adjustment tasks in advance based on the duty cycle instruction and system parameters of the next cycle, calculating the register data for waveform adjustment in the next cycle. Unlike the CM0 / CM1 registers, the SR0 and SR1 registers serve as "preset" registers, used to store the register data required for the PWM waveform adjustment in the next cycle. The ARU moves the data calculated by the MCS task to SR0 or SR1 to prepare for waveform adjustment in the next cycle.

[0110] Optionally, when the current cycle ends and the next cycle begins, the data in SR0 / SR1 is copied to CM0 / CM1, thereby updating the PWM waveform parameters in real time. The timer also monitors the signal count value in the next cycle and triggers a high-level or low-level switch of the PWM signal when a new comparison match value is reached, thus suppressing the narrow pulse in the next cycle.

[0111] In this embodiment, the above steps effectively suppress narrow pulses, avoiding the additional losses and waveform distortion that may occur in power electronic components such as IGBTs under narrow pulses, thus improving the efficiency and stability of motor control. The parallel processing capability of the MCS and the efficient data routing mechanism of the ARU are key to achieving the above objectives. Together, they ensure real-time adjustment and preset adjustment of the PWM signal, enabling rapid response to changes in control requirements, while reducing the CPU load and local RAM usage, thus optimizing overall system performance.

[0112] The technical solutions of the embodiments of this application will be illustrated below with reference to preferred embodiments.

[0113] IGBTs are the core power electronic devices in permanent magnet synchronous motor control. IGBTs respond to pulse drive signals output by the controller, thereby driving the motor. When the width of the drive pulse is less than the sum of the IGBT's turn-on and turn-off delay times, the pulse is called a narrow pulse. Narrow pulses cause the IGBT to turn off again before it is fully turned on, increasing switching losses and output waveform distortion.

[0114] The MCS is the core programmable controller of the GTM, featuring a built-in microcontroller-like instruction set that supports conditional jumps, loops, register operations, and more. It can execute complex control logic and is configured with dedicated RAM to store instructions and data, supporting in-circuit program updates. It connects to other GTM modules (such as TIM, TOM, and ATOM) via the ARU, enabling real-time responses to input signal changes. Through hardware and software collaboration, the MCS significantly reduces CPU load and local RAM usage.

[0115] In this embodiment, the motor control task has high real-time requirements and is generally executed through an MCU interrupt service routine. The execution flow is as follows: obtain the three-phase current and rotor position; execute the motor control algorithm; perform narrow pulse processing based on the duty cycle instruction output by the algorithm and output PWM. Generally, the interrupt service routine executing the above process is deployed in Local RAM close to the CPU to improve program execution efficiency.

[0116] When domestically produced MCU chips control motors, the limited CPU computing power leads to excessive CPU load for narrow pulse suppression tasks, and the small amount of local RAM space prevents the deployment of complete interrupt service routines. This invention provides a narrow pulse suppression method based on the GTM-MCS coprocessor, effectively reducing CPU load and local RAM usage.

[0117] The embodiments of this application will be further described below.

[0118] In this embodiment of the application, in order to achieve the above objective, the narrow pulse suppression method based on the GTM-MCS coprocessor mainly includes the following parts: copying the narrow pulse suppression task program into the MCS RAM, the CPU moving the duty cycle data into the MCS RAM, the MCS executing the narrow pulse suppression task to process the duty cycle instruction, and writing the MCS calculation result into the ATOM register to execute PWM output.

[0119] Figure 2 This is a schematic diagram of a five-segment pulse width modulation signal waveform according to an embodiment of this application, as shown below. Figure 2 As shown, five PWM signals are constructed based on the set narrow pulse time proportion (Dn), dead time proportion (Dd), and current duty cycle instruction (Dm). Interval 1 is [0, 0.5*Dn]; interval 2 is (0.5*Dn, Dd+Dn]; interval 3 is (Dd+Dn, 1-Dd]; interval 4 is Dm∈(1-Dd, 1); and interval 5 is Dm=1. Based on this, the lower bridge high-level time proportion Db and the upper bridge high-level time proportion Dt are calculated using the current cycle duty cycle instruction Dm1 and the next cycle duty cycle instruction Dm2, and special processing is applied to narrow pulses appearing during waveform switching.

[0120] Figure 3 It is a schematic diagram of narrow pulse processing for signal switching from interval 3 to interval 3 according to an embodiment of the present application. As Figure 3 shown, when Dm1 ∈ interval 3 and Dm2 ∈ interval 3, if (Db1 + Db2) / 2 < Dn, modify the PWM waveforms of this cycle and the next cycle, and pull the small pulse of the lower bridge to the low level.

[0121] Figure 4 It is a schematic diagram of narrow pulse processing for signal switching from interval 3 to interval 4 according to an embodiment of the present application. As Figure 4 shown, when Dm1 ∈ interval 3 and Dm2 ∈ interval 4, if (Db1 + Db2) / 2 < Dn, modify the PWM waveform of this cycle and pull the small pulse of the lower bridge to the low level.

[0122] Figure 5 It is a schematic diagram of narrow pulse processing for signal switching from interval 5 to interval 3 according to an embodiment of the present application. As Figure 5 shown, when Dm1 ∈ interval 5 and Dm2 ∈ interval 3, if (Db1 + Db2) / 2 < Dn, modify the PWM waveform of the next cycle and pull the small pulse of the lower bridge to the low level.

[0123] Figure 6 It is a schematic diagram of narrow pulse processing for signal switching from interval 4 to interval 5 according to an embodiment of the present application. As Figure 6 shown, when Dm1 ∈ interval 4 and Dm2 ∈ interval 5, if (Dt1 + Dt2) / 2 < Dn, modify the PWM waveform of this cycle and pull the small pulse of the upper bridge to the high level.

[0124] Figure 7 It is a schematic diagram of narrow pulse processing for signal switching from interval 4 to interval 4 according to an embodiment of the present application. As [[ID=??]] Figure 7 shown, when Dm1 ∈ interval 4 and Dm2 ∈ interval 4, if (Dt1 + Dt2) / 2 < Dn, modify the PWM waveforms of this cycle and the next cycle, and pull the small pulse of the upper bridge to the high level.

[0125] Optionally, to modify the PWM waveform of this cycle, use the ARU to transfer the register data calculated by the MCS task to the ATOMCM0 / CM1 registers to achieve immediate modification of the PWM waveform; to modify the PWM waveform of the next cycle, use the ARU to transfer the register data calculated by the MCS task to the ATOM SR0 / SR1 registers, and directly output the required PWM waveform in the next cycle.

[0126] It should be noted that there seems to be an error in the original text where the tag in line 27 is incorrect. It should probably be Figure 7 instead of

[0125] as used in the original. This has been noted in the translation for reference.In this embodiment, a narrow pulse suppression method based on a GTM-MCS coprocessor is provided. The method utilizes a GTM-MCS coprocessor to perform narrow pulse suppression, with multiple MCS channels executing in parallel to improve the processing efficiency of the narrow pulse suppression task. Five PWM signals are constructed based on the set narrow pulse time percentage (Dn), dead time percentage (Dd), and current duty cycle instruction (Dm). The narrow pulse conditions occurring during the switching of the five PWM signals are analyzed and suppressed one by one.

[0127] Figure 8 This is a schematic diagram of the device structure of a hardware operating environment for a narrow pulse suppression method based on a general-purpose timer module-multi-channel sequencer coprocessor according to an embodiment of this application, as shown below. Figure 8 As shown, this can be a multiprocessor system architecture including a CPU, read-only memory (ROM), a GTM module, local RAM, RAM, ROM, and an interface module. These components are connected via a bus to form a complete hardware platform designed to optimize the execution efficiency of narrow pulse suppression and other related functions. CPU 0, CPU 1, and CPU 2 can be central processing units, each with its own cache and local RAM (Local RAM0, Local RAM1, Local RAM2) for executing the main control program and storing temporary data. In motor control applications, the CPU is responsible for receiving sensor data and executing complex tasks such as motor control algorithms. The GTM can contain an MCS and MCS RAM. The MCS is a built-in controller that can execute complex timing and control logic. The GTM also includes multiple timers (such as ATOM, TOM, TIM) for generating timing signals and control outputs. The interface module can include input / output (I / O) interfaces, communication interfaces, and other analog acquisition interfaces for inputting and outputting external signals, such as motor current feedback and rotor position information. RAM is used to store runtime data and program code in execution.

[0128] Interaction between components is primarily via a bus, allowing for rapid data and instruction transfer between different parts of the system. The MCS and ARU are designed to improve the efficiency of PWM signal generation and enable real-time processing of narrow pulse suppression tasks without impacting CPU operation. The MCS executes tasks in its own RAM, while the ARU is responsible for moving data between the MCS and ATOM modules. By transferring the task results (i.e., register data) from the MCS to the CM0 / CM1 or SR0 / SR1 registers of the ATOM, the PWM signal can be modified in real-time or pre-set to achieve narrow pulse suppression. The advantages of this architecture are a significant reduction in CPU load, as the narrow pulse suppression task, originally executed in the CPU interrupt service routine, is now processed in parallel by the MCS. It also reduces the need for local RAM, as the MCS has its own RAM for task execution, eliminating the need to deploy a complete interrupt service routine in the CPU's local RAM. Furthermore, the efficient data transfer by the ARU ensures the real-time performance and accuracy of the PWM signal, optimizing the overall performance of motor control.

[0129] According to an embodiment of this application, a narrow pulse signal processing device for transistors in a vehicle is also provided. It should be noted that this narrow pulse signal processing device for transistors in a vehicle can be used to execute the narrow pulse signal processing method for transistors in a vehicle described in the above embodiments.

[0130] Figure 9 This is a schematic diagram of a narrow pulse signal processing device for a transistor in a vehicle according to an embodiment of this application, as shown below. Figure 9 As shown, the narrow pulse signal processing device 900 for transistors in the vehicle may include: an acquisition unit 902, a determination unit 904, a processing unit 906, and a driving unit 908. The acquisition unit 902 is used to acquire the current and position information of the permanent magnet synchronous motor. The determination unit 904 is used to determine the duty cycle information of the transistor based on the current and position information. The processing unit 906 is used to process the narrow pulse in the initial drive signal based on the duty cycle information. The driving unit 908 is used to acquire the target drive signal after the narrow pulse processing is completed, and to control the transistor to respond to the target drive signal and restart the permanent magnet synchronous motor.

[0131] According to an embodiment of this application, a computer-readable storage medium is also provided, the storage medium including a stored program, wherein the program executes the narrow pulse signal processing method for transistors in a vehicle as described in the above embodiments.

[0132] According to an embodiment of this application, a processor is also provided for running a program, wherein the program executes the narrow pulse signal processing method for transistors in a vehicle as described in the above embodiments.

[0133] According to another aspect of the embodiments of this application, a vehicle is also provided. The vehicle may include a memory and a processor. The memory stores an executable program. The processor can be used to run the program, wherein, when the program runs, it executes the narrow pulse signal processing method for transistors in the vehicle described in the embodiments of this application.

[0134] Embodiments of this application also provide a computer program product. Optionally, in this embodiment, the computer program product may include a computer program that, when executed by a processor, implements the narrow pulse signal processing method for transistors in a vehicle according to the embodiments of this application.

[0135] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0136] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between units or modules may be electrical or other forms.

[0137] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0138] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0139] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, ROM, RAM, portable hard drives, magnetic disks, or optical disks.

[0140] The above are merely preferred embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method of narrow pulse signal processing of a transistor in a vehicle, characterized by, The vehicle includes a permanent magnet synchronous motor, and the transistor is used to drive the permanent magnet synchronous motor to operate in response to an initial driving signal. The method comprises: obtaining current information and position information of the permanent magnet synchronous motor, wherein the current information is used to represent the state of the current in the permanent magnet synchronous motor, and the position information is used to represent the state of the position of the permanent magnet synchronous motor in the rotating process; based on the current information and the position information, determining the duty cycle information of the transistor, wherein the duty cycle information is used to represent the time length of the transistor driving the permanent magnet synchronous motor in response to the initial driving signal, and the ratio of the signal period of the initial driving signal; based on the duty cycle information, processing the narrow pulse in the initial driving signal; obtaining a target driving signal after the narrow pulse processing is completed, and controlling the transistor to drive the permanent magnet synchronous motor to operate in response to the target driving signal.

2. The method of claim 1, wherein, The method further comprises: obtaining the lower bridge high level time ratio of the transistor and the upper bridge high level time ratio of the transistor; based on the duty cycle information, processing the narrow pulse in the initial driving signal, comprising: determining the interval of the duty cycle information; based on the interval, the lower bridge high level time ratio and the upper bridge high level time ratio, processing the narrow pulse.

3. The method of claim 2, wherein, The duty cycle information includes the current cycle duty cycle information and the next cycle duty cycle information, and based on the interval, the lower bridge high level time ratio and the upper bridge high level time ratio, processing the narrow pulse, comprising: in response to the current cycle duty cycle information being in the first interval, the next cycle duty cycle information being in the first interval, and the half of the sum of the lower bridge high level time ratio and the upper bridge high level time ratio being less than the narrow pulse time ratio, adjusting the waveform of the narrow pulse in the current cycle and the waveform of the narrow pulse in the next cycle; The method further comprises: pulling the lower bridge small pulse corresponding to the transistor to low level.

4. The method of claim 2, wherein, The duty cycle information includes the current cycle duty cycle information and the next cycle duty cycle information, and based on the interval, the lower bridge high level time ratio and the upper bridge high level time ratio, processing the narrow pulse, comprising: in response to the current cycle duty cycle information being in the first interval, the next cycle duty cycle information being in the second interval, and the half of the sum of the lower bridge high level time ratio and the upper bridge high level time ratio being less than the narrow pulse time ratio, adjusting the waveform of the narrow pulse in the current cycle; The method further comprises: pulling the lower bridge small pulse corresponding to the transistor to low level.

5. The method of claim 2, wherein, The duty cycle information includes the current cycle duty cycle information and the next cycle duty cycle information, and based on the interval, the lower bridge high level time ratio and the upper bridge high level time ratio, processing the narrow pulse, comprising: In response to the current cycle duty cycle information being in the third interval, the next cycle duty cycle information being in the first interval, and the half of the sum of the next bridge high level time duty cycle and the upper bridge high level time duty cycle being less than the narrow pulse time duty cycle, the waveform of the narrow pulse of the next cycle is adjusted. The method further includes: The lower bridge small pulse corresponding to the transistor is pulled to a low level.

6. The method of claim 2, wherein, The duty cycle information includes current cycle duty cycle information and next cycle duty cycle information, and the narrow pulse is processed based on the interval, the next bridge high level time duty cycle, and the upper bridge high level time duty cycle, including: In response to the current cycle duty cycle information being in the second interval, the next cycle duty cycle information being in the third interval, and the half of the sum of the next bridge high level time duty cycle and the upper bridge high level time duty cycle being less than the narrow pulse time duty cycle, the waveform of the narrow pulse of the current cycle is adjusted. The method further includes: The upper bridge small pulse corresponding to the transistor is pulled to a high level.

7. The method as claimed in claim 2, wherein, The duty cycle information includes current cycle duty cycle information and next cycle duty cycle information, and the narrow pulse is processed based on the interval, the next bridge high level time duty cycle, and the upper bridge high level time duty cycle, including: In response to the current cycle duty cycle information being in the second interval, the next cycle duty cycle information being in the second interval, and the half of the sum of the next bridge high level time duty cycle and the upper bridge high level time duty cycle being less than the narrow pulse time duty cycle, the waveform of the narrow pulse of the current cycle and the waveform of the narrow pulse of the next cycle are adjusted. The method further includes: The upper bridge small pulse corresponding to the transistor is pulled to a high level.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: In the process of adjusting the waveform of the narrow pulse of the current cycle, the register data determined by the waveform adjustment task of the current cycle is moved to a first register through a routing unit corresponding to the transistor, and the waveform is adjusted after the movement is completed. In the process of adjusting the waveform of the narrow pulse of the next cycle, the register data determined by the waveform adjustment task of the next cycle is moved to a second register through the routing unit, and the waveform is adjusted after the movement is completed.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium includes a stored executable program, wherein the executable program controls the device where the storage medium is located to execute the method of any one of claims 1 to 8 when the executable program is running.

10. A vehicle characterized by comprising: including: a memory storing an executable program; a processor configured to execute the program, wherein the program executes the method of any one of claims 1 to 8 when the program is executed.

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