Wafer parameter calibration method, system and storage medium

Abstract

The present application relates to the field of wafers, in particular to a wafer parameter calibration method and system and storage medium, comprising: obtaining historical performance test MAP graphs of multiple same type target wafers; superimposing multiple historical performance test MAP graphs, classifying and iterating to obtain a performance parameter distribution graph of the target wafer, the performance parameter distribution graph comprising several regions; screening several target chips in each region, performing parameter calibration on the screened target chips to generate calibration codes; and collecting the calibration codes of each region to form a batch calibration code set covering the wafer, and performing parameter calibration on all chips in the wafer according to the batch calibration code set. The present application can reduce the test duration and test cost.

Description

Technical Field

[0001] This invention relates to the field of wafer fabrication, and more specifically to a method, system, and storage medium for calibrating wafer parameters. Background Technology

[0002] Compared to chip probe testing for ordinary semiconductor products, probe testing for Flash products has significant unique characteristics: its core requirement is to determine the chip's performance margin, that is, to determine the appropriate read / write window. This window directly determines the stability and reliability of Flash chip read / write operations and is a key indicator for judging whether the chip's performance meets the standards.

[0003] In actual mass production, due to fluctuations in manufacturing processes such as photolithography and etching, there is often a significant difference in the performance margin between the chips in the center and edge regions (C / E) of a wafer. If this difference exceeds the design tolerance range, it will directly cause some chips in the edge or center regions to be judged as failures due to insufficient performance margin, ultimately leading to a decrease in product yield and even serious yield loss.

[0004] Currently, the mainstream improvement solutions in the industry for the aforementioned wafer center-edge in-plane uniformity difference issue are as follows: Per-die trim: This involves adjusting key parameters such as the chip's temperature coefficient, bias voltage, and pump pressure to generate configuration data for precise chip performance calibration. The core logic of this solution is to compensate for process fluctuations generated during the manufacturing process of each chip through one-to-one parameter compensation, thereby ensuring that the performance of a single chip meets design specifications and ultimately effectively improving the difference between the wafer center and edge regions, thus enhancing chip performance consistency. However, because the calibration and calibration code generation process needs to be performed individually for each chip on the wafer, it significantly increases probe testing time. For example, in a 110nm process node, on a 12-inch wafer, with a chip size of 2×2mm... 2 In mass production scenarios, probe testing time increases by at least 30%, which not only directly increases testing costs but also reduces overall production efficiency, making it difficult to adapt to the needs of large-scale mass production. Summary of the Invention

[0005] The purpose of this invention is to provide a method, system, and storage medium for calibrating wafer parameters, which can reduce testing time and reduce testing costs.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention provides a method for calibrating parameters of a wafer, comprising:

[0008] Obtain historical performance test MAPs for multiple target wafers of the same type;

[0009] Multiple historical performance test MAP maps are overlaid, classified, and iterated to obtain a performance parameter distribution map of the target wafer, which includes several regions.

[0010] In each region, select several target chips, calibrate the parameters of the selected target chips, and generate calibration codes;

[0011] The calibration codes of each region are aggregated to form a batch calibration code set covering the wafer. The parameters of all chips in the wafer are calibrated based on the batch calibration code set.

[0012] Furthermore, the generation of the calibration code includes:

[0013] Multiple chips are randomly selected on the wafer in the target area, and the performance parameters of the selected chips are tested to screen out several target chips with moderate performance.

[0014] The selected target chips are connected to a tester. The configuration pins of the selected target chips are contacted by probes, calibration parameters are written, and the parameters of the target chips are adjusted until the calibration target is reached, thus obtaining the initial calibration code.

[0015] Verify whether the initial calibration code is compatible with other chips in this area. If so, use the obtained initial calibration code as the calibration code for this area; otherwise, select a new chip, adjust the parameters, and regenerate the initial calibration code.

[0016] Furthermore, verifying whether the initial calibration code is compatible with other chips in the area specifically includes: writing the initial calibration code into multiple randomly selected chips other than the target chip, and retesting the performance parameters of the chips; if the performance parameters are within the preset range, the chip is deemed to meet the standard, otherwise it is deemed to fail to meet the standard.

[0017] The pass rate of multiple randomly selected chips other than the target chip is calculated. If the pass rate is greater than the first preset value, the initial calibration code verification is deemed to have passed; otherwise, the verification is deemed to have failed.

[0018] Furthermore, after the initial calibration code verification is successful, it also includes:

[0019] Set the process fluctuation parameters and corresponding fluctuation range in the testing machine;

[0020] Under process fluctuations, the performance parameters of the selected target chips are retested. If the performance parameters are within the preset range, the obtained initial calibration code is used as the batch calibration code for that region. If the performance parameters are not within the preset range, the parameters of the selected target chips are readjusted to obtain an optimized initial calibration code.

[0021] Furthermore, when there is only one target chip, the parameters of the selected target chip are directly calibrated to generate a calibration code;

[0022] When there are two or more target chips, the parameters of the selected target chips are adjusted to generate two or more sets of basic calibration codes.

[0023] Regional coverage testing was conducted by writing the generated basic calibration codes into multiple randomly selected chips (excluding the target chip) and retesting the chip performance parameters. If the performance parameters were within the preset range, the chip was deemed to have met the standard; otherwise, it was deemed to have failed the standard. The pass rate corresponding to each set of basic calibration codes was calculated.

[0024] If the pass rate fluctuation value corresponding to two or more sets of basic calibration codes is greater than the second preset value, the basic calibration code with the highest pass rate will be used as the calibration code.

[0025] If the compliance rate fluctuation value corresponding to two or more sets of basic calibration codes is not greater than the second preset value, an environmental stability test is conducted, and one set of basic calibration codes is selected as the calibration code based on the environmental stability test results.

[0026] Furthermore, environmental stability testing is conducted, and based on the results, one set of basic calibration codes is selected as the calibration code, including:

[0027] Retest the performance parameters of the target chip under process fluctuations;

[0028] If the performance parameters of the target chip are within the preset range, the basic calibration code is retained; if the performance parameters of the target chip are not within the preset range, the basic calibration code is removed.

[0029] Identify the performance parameter fluctuation range of the target chip corresponding to several sets of retained basic calibration codes, and select the set of basic calibration codes with the smallest fluctuation range as the calibration code.

[0030] Furthermore, when there are two or more target chips, the parameters of the selected target chips are adjusted to generate two or more sets of basic calibration codes, and the average value of the two or more sets of basic calibration codes is used as the calibration code.

[0031] Furthermore, after calibrating the parameters of all chips within the wafer according to the batch calibration code set, the target wafer is retested, and the performance test MAP is included in the historical sample library as a new sample.

[0032] Secondly, the present invention discloses a wafer parameter calibration system, comprising:

[0033] The acquisition module is used to acquire historical performance test MAPs of multiple target wafers of the same type;

[0034] The classification module is used to overlay multiple historical performance test MAP maps, perform classification iterations, and obtain a performance parameter distribution map of the target wafer, which includes several regions.

[0035] The generation module is used to select several target chips in each region, perform parameter calibration on the selected target chips, and generate calibration codes.

[0036] The calibration module is used to aggregate the calibration codes of each region to form a batch calibration code set covering the wafer, and to perform parameter calibration on all chips in the wafer based on the batch calibration code set.

[0037] Thirdly, the present invention discloses a computer-readable storage medium storing computer instructions, which, when executed by a processor, implement the steps in the above-described wafer parameter calibration method.

[0038] The unexpected beneficial effects of this invention are as follows:

[0039] The wafer parameter calibration method of this invention first classifies and iterates multiple historical performance test MAP maps to obtain a performance parameter distribution map of the target wafer, which includes several regions. Then, calibration is performed only on a small number of target chips within each region, significantly reducing the total number of calibration operations. The generated batch calibration code set can directly cover all chips on the entire wafer, eliminating the need to repeatedly generate calibration codes for individual chips, thus significantly shortening the overall calibration cycle. Simultaneously, the reduction in calibration operations also reduces the occupancy pressure and wear risk of test equipment, reduces resource consumption for data storage and processing, and lowers production costs from multiple dimensions, including equipment usage and manual maintenance. Attached Figure Description

[0040] Figure 1 A schematic flowchart of the wafer parameter calibration method according to an embodiment of the present invention is shown.

[0041] Figure 2 The diagram shows the performance parameter distribution of the target wafer according to an embodiment of the present invention.

[0042] Figure 3 A schematic diagram of the process for generating calibration codes according to an embodiment of the present invention is shown.

[0043] Figure 4 A schematic diagram of the wafer parameter calibration system according to an embodiment of the present invention is shown. Detailed Implementation

[0044] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0045] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] In one embodiment, the present invention discloses a method for calibrating wafer parameters, see [link to relevant documentation]. Figure 1 As shown, the method includes:

[0047] Obtain historical performance test MAPs for multiple target wafers of the same type;

[0048] Multiple historical performance test MAP maps are overlaid, classified, and iterated to obtain a performance parameter distribution map of the target wafer, which includes several regions.

[0049] In each region, select several target chips, calibrate the parameters of the selected target chips, and generate calibration codes;

[0050] The calibration codes of each region are aggregated to form a batch calibration code set covering the wafer. The parameters of all chips in the wafer are calibrated based on the batch calibration code set.

[0051] The wafer parameter calibration method of this invention first classifies and iterates multiple historical performance test MAP maps to obtain a performance parameter distribution map of the target wafer, which includes several regions. Then, calibration is performed only on a small number of target chips within each region, significantly reducing the total number of calibration operations. The generated batch calibration code set can directly cover all chips on the entire wafer, eliminating the need to repeatedly generate calibration codes for individual chips, thus significantly shortening the overall calibration cycle. Simultaneously, the reduction in calibration operations also reduces the occupancy pressure and wear risk of test equipment, reduces resource consumption for data storage and processing, and lowers production costs from multiple dimensions, including equipment usage and manual maintenance.

[0052] Traditional methods, failing to consider performance differences across wafer regions (such as parameter deviations between center and edge chips), are prone to over- or under-calibration issues, leading to substandard performance in some chips. This invention, based on the overlay and iterative classification of multiple historical performance test MAP maps, objectively presents the common performance characteristics of different regions within the same type of wafer, ensuring that region division aligns with the performance patterns of actual mass production processes. Each region's calibration code is customized to address performance deviations within that region, accurately compensating for process fluctuations in the chips within that area. This ensures that the performance parameters of all chips within the region consistently fall within the acceptable range, effectively improving wafer-level performance uniformity and preventing chip failures due to localized calibration mismatches, thereby reducing yield losses.

[0053] This invention uses historical data from target wafers of the same type as the core input, without being bound to specific wafer sizes, process nodes, or chip types, thus possessing broad adaptability. For wafers of the same type, such as the same Flash IP or chips for the same application scenario, even if there are slight differences in production batches or customer requirements, the region division and calibration codes can be quickly updated simply by incorporating the performance data under the new scenario into the historical data overlay process, without the need to redevelop the entire calibration logic. Regardless of wafer sizes or products of different process nodes, the core process of historical data modeling, regional calibration, and batch application can be reused, significantly reducing the adaptation cost for mass production in multiple scenarios and shortening the mass production introduction cycle for new types of products.

[0054] For example, see Figure 2 As shown, multiple historical performance test MAP maps are overlaid and iterated to obtain a performance parameter distribution map of the target wafer. This map includes three regions, denoted as Region I, Region II, and Region III, where Region I is the central high-stability region and Region III is the edge fluctuation region. Several target chips are selected within each region, and their parameters are calibrated to generate three sets of calibration codes corresponding to the three regions, denoted as D1, D2, and D3. Three sets of test programs, CP_program1, CP_program2, and CP_program3, are then provided for each of the three sets of calibration codes, fundamentally solving the problem of incomplete coverage by a single CP flow (wafer probe testing process).

[0055] Traditional single CP flow can only adapt to the performance parameters of a certain region of the wafer (such as the central region). When faced with the performance parameter differences in the edge region (region III) caused by process fluctuations, it is easy to cause calibration failure and test misjudgment. However, the chip in region III in the example can compensate for the edge performance deviation through a dedicated D3 calibration code, and then use CP_program3 to test according to the qualified threshold of the edge region, ensuring that the entire calibration-test process fits the characteristics of the region.

[0056] Furthermore, the three sets of calibration codes and three CP programs form a closed loop of region-calibration-test, covering all performance ranges of the wafer from the center to the edge, thus completely reducing the adverse effects of wafer in-plane uniformity differences on yield.

[0057] In the calibration phase, it's unnecessary to generate calibration codes for every single chip on the wafer. Only a small number of target chips in each of the three regions need to be selected to generate three sets of calibration codes (D1, D2, and D3) to cover the entire wafer. This reduces the amount of calibration operations from tens of thousands to individual units, significantly decreasing calibration time. In the testing phase, CP_program1~3 correspond to the performance parameter ranges of regions I~III, respectively. During testing, there's no need to adjust the test standards for each chip; simply calling the corresponding program for each region quickly completes the judgment. This avoids the redundant operations of repeatedly adjusting thresholds and performing multiple retests in general CP programs, further shortening the testing cycle and ultimately achieving cost reduction throughout the entire calibration and testing process.

[0058] At the same time, this method is applicable to various complex circuit designs of different customers, reduces the difficulty of Flash testing, unifies the standards of Flash testing, and makes the process more standardized and modular.

[0059] As a preferred embodiment of the present invention, see Figure 3 As shown, the generation of calibration codes includes:

[0060] Multiple chips are randomly selected on the wafer in the target area, and the performance parameters of the selected chips are tested to screen out several target chips with moderate performance.

[0061] The selected target chips are connected to a tester. The configuration pins of the selected target chips are contacted by probes, calibration parameters are written, and the parameters of the target chips are adjusted until the calibration target is reached, thus obtaining the initial calibration code.

[0062] Verify whether the initial calibration code is compatible with other chips in this area. If so, use the obtained initial calibration code as the calibration code for this area; otherwise, select a new chip, adjust the parameters, and regenerate the initial calibration code.

[0063] This preferred embodiment avoids the limitations of traditional single-chip representation by randomly selecting multiple chips and then selecting target chips with moderate performance. Randomly selecting chips that cover varying performance fluctuations within the region prevents calibration codes from only fitting individual chips due to the selection of extreme-performance chips (such as the best or worst performing chips). Chips with moderate performance accurately reflect the common performance characteristics of most chips within the region, such as the average parameter deviation and process variation level. Calibration codes generated based on this naturally adapt to the performance requirements of the vast majority of chips within the region, eliminating the need for fine-tuning for individual chips. This ensures the accuracy of regionalized batch calibration from the source and avoids the risk of failure due to mismatch between calibration codes and chip performance.

[0064] In a preferred embodiment of the present invention, verifying whether the initial calibration code is compatible with other chips in the region specifically includes: writing the initial calibration code into multiple randomly selected chips other than the target chip, and retesting the performance parameters of the chips; if the performance parameters are within a preset range, it is determined that the standard is met, otherwise it is determined that the standard is not met; calculating the compliance rate of the multiple randomly selected chips other than the target chip, and in response to the compliance rate being greater than a first preset value, it is determined that the initial calibration code verification is passed, otherwise it is determined that the verification is not passed.

[0065] This preferred implementation transforms the criterion for determining whether the initial calibration code is compatible into a quantitative indicator of compliance rate, rather than relying on subjective human evaluation. Compliance is determined by whether performance parameters are within a preset range, and the final judgment is based on whether the compliance rate exceeds a first preset value. This makes the verification results measurable and reproducible. This quantitative logic avoids judgment biases caused by differences in experience among different operators, ensures uniform calibration code verification standards within the same region, and improves the objectivity and standardization of the verification process.

[0066] During the verification process, multiple chips other than the target chip are randomly selected, covering chips with different locations and performance characteristics within the region, rather than verifying only a few samples with performance similar to the target chip. This sampling method ensures that the verification objects are representative of the region and can effectively detect whether the calibration code can adapt to the performance fluctuations of various chips in the region, thus guaranteeing the adaptability of the calibration code to a batch of chips in the region from the source.

[0067] The mechanism, which determines compliance only upon exceeding a preset threshold, sets a clear entry threshold for calibration codes. If a calibration code is compatible with only a few chips (compliance rate below the threshold), it is directly deemed a verification failure, preventing it from entering subsequent batch calibration stages. This early interception effectively avoids the risk of large-scale performance failures caused by unqualified calibration codes being applied to all chips, reducing yield losses and rework costs due to calibration failures. Furthermore, the preset threshold can be flexibly adjusted according to product performance requirements, allowing the verification standard to adapt to the quality needs of different scenarios.

[0068] The mechanism of determining verification failure and regenerating calibration codes when the compliance rate fails to meet the preset value provides a clear direction for calibration code optimization. By analyzing the performance characteristics of the non-compliant chips, such as which parameters are out of range and where they are concentrated, the defects of the initial calibration codes can be accurately located, allowing the regenerated calibration codes to specifically address these shortcomings. This closed loop of verification, feedback, and optimization drives the calibration codes to continuously evolve towards higher adaptability, improving the effectiveness of regional batch calibration in the long term.

[0069] In a preferred embodiment of the present invention, after the initial calibration code verification is passed, the method further includes:

[0070] Set the process fluctuation parameters and corresponding fluctuation range in the testing machine;

[0071] Under process fluctuations, the performance parameters of the selected target chips are retested. If the performance parameters are within the preset range, the obtained initial calibration code is used as the batch calibration code for that region. If the performance parameters are not within the preset range, the parameters of the selected target chips are readjusted to obtain an optimized initial calibration code.

[0072] In a preferred embodiment of the present invention, when the number of target chips is one, the parameters of the selected target chip are directly calibrated to generate a calibration code.

[0073] When there are two or more target chips, the parameters of the selected target chips are adjusted to generate two or more sets of basic calibration codes.

[0074] Regional coverage testing was conducted by writing the generated basic calibration codes into multiple randomly selected chips (excluding the target chip) and retesting the chip performance parameters. If the performance parameters were within the preset range, the chip was deemed to have met the standard; otherwise, it was deemed to have failed the standard. The pass rate corresponding to each set of basic calibration codes was calculated.

[0075] If the pass rate fluctuation value corresponding to two or more sets of basic calibration codes is greater than the second preset value, the basic calibration code with the highest pass rate will be used as the calibration code.

[0076] If the compliance rate fluctuation value corresponding to two or more sets of basic calibration codes is not greater than the second preset value, an environmental stability test is conducted, and one set of basic calibration codes is selected as the calibration code based on the environmental stability test results.

[0077] This preferred implementation clearly distinguishes the processing logic for scenarios with one target chip versus two or more: for a single chip, calibration codes are directly generated, simplifying the operation process and adapting to scenarios where the performance of the target area is highly uniform and a single chip can represent the whole; for two or more chips, multiple sets of calibration codes are compared and optimized, adapting to scenarios where the performance of the target area has slight differences and multiple samples are needed for coverage. This scenario-specific adaptation design avoids the rigidity of applying a single logic to all situations. It avoids overly complex operations for single-target-chip scenarios and insufficient calibration code adaptability due to a lack of optimization criteria for multiple-target-chip scenarios, significantly improving the versatility of the solution in different mass production scenarios.

[0078] When the target number of chips is two or more, this implementation first calculates the compliance rate of each set of basic calibration codes through regional coverage testing, and then determines the selection logic based on the fluctuation value of the compliance rate: if the fluctuation value is greater than a second preset value, the calibration code with the highest compliance rate is directly selected. This operation takes the actual adaptation effect of the chips in the region as the core standard, ensuring that the finally selected calibration code can cover more chips in the region (the higher the compliance rate, the more chips are adapted), avoiding the problem of insufficient coverage caused by subjective selection (such as randomly selecting a set of calibration codes), and fundamentally guaranteeing the effect of regional batch calibration.

[0079] When the compliance rates of multiple sets of basic calibration codes fluctuate only slightly, indicating minimal differences in coverage, this implementation further incorporates environmental stability testing for optimization. This design precisely addresses the core requirement that stability determines long-term performance when coverage is similar: for example, if two sets of calibration codes both have a compliance rate of 95% and similar coverage, but one set is stable under temperature fluctuations while the other is prone to deviation, the former is selected through stability testing, avoiding the shortcoming of neglecting long-term reliability while only considering coverage. This hierarchical optimization logic, prioritizing coverage before stability, achieves a balance between short-term mass production adaptation and long-term reliability.

[0080] In a preferred embodiment of the present invention, an environmental stability test is performed, and based on the environmental stability test results, one set of basic calibration codes is selected as the calibration code, including:

[0081] Retest the performance parameters of the target chip under process fluctuations;

[0082] If the performance parameters of the target chip are within the preset range, the basic calibration code is retained; if the performance parameters of the target chip are not within the preset range, the basic calibration code is removed.

[0083] Identify the performance parameter fluctuation range of the target chip corresponding to several sets of retained basic calibration codes, and select the set of basic calibration codes with the smallest fluctuation range as the calibration code.

[0084] The first step of this implementation method is to retest the target chip performance under fluctuating process conditions and eliminate substandard calibration codes. Essentially, this sets a double entry threshold for the calibration codes. Previous regional coverage testing ensured that the calibration codes were compatible with most chips within the region, while this step ensures that the calibration codes can adapt to process fluctuations during mass production. In actual mass production, fluctuations such as equipment parameter drift, changes in workshop temperature and humidity, and batch differences in raw materials are difficult to completely avoid. If the calibration codes only meet the standards under ideal conditions—for example, performance is acceptable when the voltage is stable but exceeds the standard when the voltage fluctuates—it will directly lead to the failure of a batch of chips. This step, through retesting under fluctuating conditions, can identify these environmentally sensitive calibration codes in advance and eliminate them directly, preventing them from flowing into subsequent batch calibration stages. This blocks the risk of a sudden drop in yield caused by fluctuations from the source, ensuring mass production stability.

[0085] After retaining the calibration codes that meet the standards under fluctuating conditions, this implementation further selects the calibration code with the smallest performance parameter fluctuation range. The smaller the performance fluctuation range, the more stable the performance of the calibration code under different fluctuation scenarios. This not only adapts to short-term fluctuations in mass production but also supports the long-term reliable operation of the chip in end applications. For example, both sets of calibration codes can meet the standards with voltage fluctuations of ±5%, but the performance parameter fluctuation range of group A is 0.1V and that of group B is 0.3V. After selecting the calibration code of group A, even if the largest voltage fluctuation occurs during mass production, the chip performance can remain within a narrower acceptable range, reducing performance degradation caused by long-term fluctuations and extending the reliability of the chip throughout its entire life cycle.

[0086] For regional batch calibration, the performance consistency of all chips within the same region under fluctuating conditions is crucial. If the calibration code fluctuates significantly, even if the chips within the region initially meet the calibration standards, performance deviations may occur in some chips under the influence of mass production fluctuations, leading to increased performance differences within the region. This implementation selects the calibration code with the smallest fluctuation range, ensuring that the performance deviation of all chips within the region is similar under fluctuating conditions, rather than some chips having small fluctuations and others having large fluctuations. This further reduces performance differences within the wafer plane, improves overall uniformity, avoids localized yield losses caused by performance differentiation under fluctuations, and ultimately achieves a positive cycle of batch calibration, fluctuation stabilization, and uniformity optimization.

[0087] In a preferred embodiment of the present invention, when there are two or more target chips, the parameters of the selected target chips are adjusted to generate two or more sets of basic calibration codes, and the average value of the two or more sets of basic calibration codes is used as the calibration code.

[0088] Although two or more target chips are all mid-range performance chips, slight fluctuations in chip manufacturing processes can still result in parameter differences in the generated basic calibration codes. For example, the bias voltage of calibration code group A is 0.8V, while group B is 0.82V. Directly selecting a single calibration code group might bias towards the performance characteristics of that target chip group, leading to insufficient compatibility with chips in the same region that have similar performance to the other target chip group. For instance, selecting group A might result in slightly lower parameters for chips in group B with corresponding performance after calibration. However, averaging the values ​​from multiple calibration codes combines the parameter characteristics of each group, avoiding bias towards any single target chip while covering the performance range represented by multiple target chips. This allows the final calibration code to adapt to a wider range of chip performance fluctuations within the region, avoiding local compatibility failures caused by the bias of a single calibration code, and fundamentally improving the overall calibration compatibility of the region.

[0089] In a preferred embodiment of the present invention, after calibrating the parameters of all chips in the wafer according to the batch calibration code set, the target wafer is retested, and the performance test MAP is included in the historical sample library as a new sample.

[0090] This preferred implementation incorporates the performance test map of the calibrated target wafer into a historical sample library. Essentially, this supplements subsequent region segmentation and calibration code generation with calibration effect data from real-world mass production scenarios. As the data volume in the sample library continues to accumulate, the performance parameter distribution map formed by overlaying multiple performance test maps will better reflect the actual characteristics of the current mass production process. For example, it can more accurately identify performance fluctuation patterns in different regions of the wafer, such as parameter shifts in a certain region due to minor equipment aging, avoiding region segmentation errors caused by insufficient historical sample volume or data lag. Calibration codes generated based on a more comprehensive sample library can also more accurately match the actual performance requirements of chips within a region, further reducing the risk of calibration failures and forming a positive cycle from data accumulation to accuracy improvement.

[0091] Furthermore, as MAP charts from different operating conditions and batches accumulate in the sample library, hidden performance patterns can be gradually uncovered. For example, wafers produced in different seasons and using different equipment exhibit specific correlations in regional performance differences, allowing for targeted optimization of the calibration process. This includes adjusting the selection criteria for target chips in a specific region, optimizing the adjustment range of calibration parameters, and refining the granularity of region division. This continuous iteration capability enables the calibration scheme to adapt to changes in mass production needs over the long term, continuously improving calibration efficiency and yield, ultimately forming a virtuous cycle at the technical level and providing more mature experience support for the calibration of subsequent similar wafer products.

[0092] In summary, the wafer parameter calibration method of this invention first classifies and iterates multiple historical performance test MAP maps to obtain a performance parameter distribution map of the target wafer, which includes several regions. Then, calibration is performed only on a small number of target chips within each region, significantly reducing the total number of calibration operations. The generated batch calibration code set can directly cover all chips on the entire wafer, eliminating the need to repeatedly generate calibration codes for individual chips, thus significantly shortening the overall calibration cycle. Simultaneously, the reduction in calibration operations also reduces the occupancy pressure and wear risk of test equipment, and reduces resource consumption for data storage and processing, thereby lowering production costs from multiple dimensions, including equipment usage and manual maintenance.

[0093] In one embodiment, the present invention discloses a wafer parameter calibration system, see [link to relevant documentation]. Figure 4 As shown, the parameter calibration system 10 includes:

[0094] Module 11 is used to acquire historical performance test MAPs of multiple target wafers of the same type;

[0095] Classification module 12 is used to overlay multiple historical performance test MAP maps, perform classification iteration, and obtain a performance parameter distribution map of the target wafer, wherein the performance parameter distribution map includes several regions;

[0096] The generation module 13 is used to select several target chips in each region, perform parameter calibration on the selected target chips, and generate calibration codes.

[0097] The calibration module 14 is used to summarize the calibration codes of each region to form a batch calibration code set covering the wafer, and to perform parameter calibration on all chips in the wafer based on the batch calibration code set.

[0098] In one embodiment, the present invention discloses a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the steps in the above-described wafer parameter calibration method.

[0099] The above embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention.

Claims

1. A method for calibrating the parameters of a wafer, characterized in that, include: Obtain historical performance test MAPs for multiple target wafers of the same type; Multiple historical performance test MAP maps are overlaid, categorized, and iterated to obtain a performance parameter distribution map of the target wafer, which includes several regions. In each region, select several target chips, calibrate the parameters of the selected target chips, and generate calibration codes; The generation of the calibration code includes: Multiple chips are randomly selected on the wafer in the target area, and the performance parameters of the selected chips are tested to screen out several target chips with moderate performance. The selected target chips are connected to a tester. The configuration pins of the selected target chips are contacted by probes, calibration parameters are written, and the parameters of the target chips are adjusted until the calibration target is reached, thus obtaining the initial calibration code. Verify whether the initial calibration code is compatible with other chips in this area. If so, use the obtained initial calibration code as the calibration code for this area; otherwise, select a new chip, adjust the parameters, and regenerate the initial calibration code. When the target chip is one, the parameters of the selected target chip are directly calibrated to generate a calibration code. When there are two or more target chips, the parameters of the selected target chips are adjusted to generate two or more sets of basic calibration codes. Regional coverage testing was conducted by writing the generated basic calibration codes into multiple randomly selected chips (excluding the target chip) and retesting the chip performance parameters. If the performance parameters were within the preset range, the chip was deemed to have met the standard; otherwise, it was deemed to have failed the standard. The pass rate corresponding to each set of basic calibration codes was calculated. If the pass rate fluctuation value corresponding to two or more sets of basic calibration codes is greater than the second preset value, the basic calibration code with the highest pass rate will be used as the calibration code. If the compliance rate fluctuation value corresponding to two or more sets of basic calibration codes is not greater than the second preset value, an environmental stability test is conducted, and one set of basic calibration codes is selected as the calibration code based on the environmental stability test results. The calibration codes of each region are aggregated to form a batch calibration code set covering the wafer, and the parameters of all chips in the wafer are calibrated based on the batch calibration code set.

2. The wafer parameter calibration method according to claim 1, characterized in that, Verifying whether the initial calibration code is compatible with other chips in the region specifically includes: writing the initial calibration code into multiple randomly selected chips other than the target chip, and retesting the chip's performance parameters; if the performance parameters are within the preset range, the chip is deemed to have met the standard; otherwise, it is deemed to have failed the standard. The pass rate of multiple randomly selected chips other than the target chip is calculated. If the pass rate is greater than the first preset value, the initial calibration code verification is deemed to have passed; otherwise, the verification is deemed to have failed.

3. The wafer parameter calibration method according to claim 1, characterized in that: After the initial calibration code verification is successful, the following is also included: Set the process fluctuation parameters and corresponding fluctuation range in the testing machine; Under process fluctuations, the performance parameters of the selected target chips are retested. If the performance parameters are within the preset range, the obtained initial calibration code is used as the batch calibration code for that region. If the performance parameters are not within the preset range, the parameters of the selected target chips are readjusted to obtain an optimized initial calibration code.

4. The wafer parameter calibration method according to claim 1, characterized in that, Environmental stability testing was conducted, and based on the test results, one set of basic calibration codes was selected as the calibration code, including: Retest the performance parameters of the target chip under process fluctuations; If the performance parameters of the target chip are within the preset range, the basic calibration code is retained; if the performance parameters of the target chip are not within the preset range, the basic calibration code is removed. Identify the performance parameter fluctuation range of the target chip corresponding to several sets of retained basic calibration codes, and select the set of basic calibration codes with the smallest fluctuation range as the calibration code.

5. The wafer parameter calibration method according to claim 1, characterized in that, When there are two or more target chips, the parameters of the selected target chips are adjusted to generate two or more sets of basic calibration codes, and the average value of the two or more sets of basic calibration codes is used as the calibration code.

6. The wafer parameter calibration method according to claim 1, characterized in that: After calibrating the parameters of all chips in the wafer according to the batch calibration code set, the target wafer is retested, and the performance test MAP is added to the historical sample library as a new sample.

7. A wafer parameter calibration system, characterized in that, include: The acquisition module is used to acquire historical performance test MAPs of multiple target wafers of the same type; The classification module is used to overlay multiple historical performance test MAP maps, perform classification iterations, and obtain a performance parameter distribution map of the target wafer, which includes several regions. The generation module is used to select several target chips in each region, perform parameter calibration on the selected target chips, and generate calibration codes. The generation of the calibration code includes: Multiple chips are randomly selected on the wafer in the target area, and the performance parameters of the selected chips are tested to screen out several target chips with moderate performance. The selected target chip is connected to a tester. The configuration pins of the selected target chip are contacted by probes to write calibration parameters. The parameters of the target chip are adjusted until the calibration target is reached, and the initial calibration code is obtained. Verify whether the initial calibration code is compatible with other chips in this area. If so, use the obtained initial calibration code as the calibration code for this area; otherwise, select a new chip, adjust the parameters, and regenerate the initial calibration code. When the target chip is one, the parameters of the selected target chip are directly calibrated to generate a calibration code. When there are two or more target chips, the parameters of the selected target chips are adjusted to generate two or more sets of basic calibration codes. Regional coverage testing is conducted by writing the generated basic calibration codes into multiple randomly selected chips (excluding the target chip) and retesting the chip performance parameters. If the performance parameters are within a preset range, the chip is deemed compliant; otherwise, it is deemed non-compliant. The compliance rate corresponding to each set of basic calibration codes is calculated. If the compliance rate fluctuation value corresponding to two or more sets of basic calibration codes is greater than a second preset value, the basic calibration code with the highest compliance rate is used as the calibration code. If the compliance rate fluctuation value corresponding to two or more sets of basic calibration codes is not greater than the second preset value, an environmental stability test is conducted, and one set of basic calibration codes is selected as the calibration code based on the environmental stability test results. The calibration module is used to aggregate the calibration codes of each region to form a batch calibration code set covering the wafer, and to perform parameter calibration on all chips in the wafer based on the batch calibration code set.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the steps of the wafer parameter calibration method as described in any one of claims 1 to 6.

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