Flexible DC power transmission system simulation acceleration method and related device thereof

Abstract

The invention discloses a flexible direct-current power transmission system simulation acceleration method and a related device thereof. The method comprises the following steps: decoupling a flexible direct-current power transmission system through a semi-implicit delay method; during simulation, the control system is simulated in the CPU, and a control signal is obtained and output to the sub-module through the interface; parallel simulation is carried out on the main circuit module in the CPU, and bridge arm current is obtained and output to the sub-module and the control system through an interface; threads are distributed for all the sub-modules in the GPU for parallel simulation, capacitance voltage values of all the sub-modules are obtained and transmitted to the main circuit, simulation of the main circuit and the sub-modules is repeated till the one-step simulation step length of the control system is reached, and next-step simulation of the control system is repeated till simulation is finished; and a simulation interface for data transmission directly calls the control system and the DLL of the sub-module through a C language to realize low-delay data transmission. According to the method, the flexible direct-current power transmission system is simulated through the CPU-GPU heterogeneous architecture, so that the simulation efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of power system technology, and in particular to a simulation acceleration method for flexible DC transmission systems and related devices. Background Technology

[0002] Modular multilevel converters (MMCs) have become a commonly used converter topology in flexible DC transmission systems due to their advantages such as low switching losses and low harmonic content in the output waveform. With the widespread application of large-scale flexible DC transmission in my country's power grid, the research on efficient electromagnetic transient simulation models for MMCs is urgently needed.

[0003] For electromagnetic transient simulation models of Multimode Cryogenics (MMC), existing technologies have proposed various MMC electromagnetic transient models using different modeling methods. These models are categorized by their level of accuracy: detailed models, average-value models, and switching function models. Detailed models, through precise construction of each submodule, possess high accuracy, but suffer from low simulation efficiency when the number of submodules is large, making them unsuitable for large-scale systems. Average-value models utilize controlled sources to decouple the AC and DC sides, preserving external characteristics and offering high simulation efficiency, but they cannot reflect the charging and discharging behavior of submodules, resulting in limited accuracy. Switching function models simplify bridge arms by unifying capacitance and functions, ignoring capacitance differences, and thus struggle to support voltage balancing algorithm analysis. In electromagnetic transient simulation algorithms, the Node Analysis Method (NAM) is widely used due to its applicability to component-based differential circuit models. This method constructs the node voltage equations of the network and solves for node voltages and branch currents; its computational complexity is primarily influenced by the system size. Therefore, in the refined simulation of large-scale renewable energy power systems, NAM faces the challenge of insufficient computational speed. Summary of the Invention

[0004] This application provides a simulation acceleration method and related apparatus for flexible DC transmission systems, which can improve the simulation efficiency of flexible DC transmission systems.

[0005] In view of this, the first aspect of this application provides a method for accelerating the simulation of a flexible DC transmission system, comprising:

[0006] S1. The flexible DC transmission system is decoupled by a semi-implicit delay decoupling method to obtain the decoupled control system, main circuit module and sub-module;

[0007] S2. During simulation, the control system is simulated and calculated in the CPU to obtain control signals, and the control signals are output to the sub-module.

[0008] S3. Simulate and calculate the main circuit module in the CPU, obtain the bridge arm current, and output the bridge arm current to the sub-module and the control system through the interface;

[0009] S4. Simulate and calculate each sub-module in parallel using multi-threading in the GPU, obtain the capacitor voltage value of each sub-module, and transmit the superimposed capacitor voltage values ​​to the main circuit module and the control system. Return to step S3. After reaching one simulation step size of the control system, return to step S2 until the simulation ends.

[0010] Optionally, the formula for calculating the number of threads allocated to the submodule is:

[0011]

[0012] In the formula, m is the number of submodules, p GPU The number of threads allocated to all submodules; To return greater than or equal to The smallest integer.

[0013] Optionally, the method further includes:

[0014] The required memory capacity of each submodule is calculated based on the number of submodules and the number of bytes occupied by a single piece of data in each submodule.

[0015] If the memory capacity required by the submodule is less than the register memory capacity in the GPU, then the data of the submodule is stored in the registers in the GPU;

[0016] If the memory capacity required by the submodule is greater than the register memory capacity in the GPU but less than the shared memory capacity in the GPU, then the data of the submodule will be stored in the shared memory in the GPU.

[0017] If the memory required by the submodule is greater than the shared memory capacity in the GPU, then the data of the submodule will be stored in the global memory of the GPU.

[0018] Optionally, the step of performing simulation calculations on the main circuit module in the CPU to obtain the bridge arm current includes:

[0019] The main circuit module is divided into blocks based on the threads allocated by the CPU during simulation calculations.

[0020] The CPU uses multi-threading to solve the block matrix in parallel to obtain the bridge arm current.

[0021] Optionally, the main circuit module is built using PSCAD simulation software. The simulation code of the sub-modules deployed in the GPU and the simulation code of the control system deployed in the CPU are packaged into a standard format dynamic link library file. During simulation, communication between the main circuit module and each sub-module and the control system is realized through the PCIe bus to call the dynamic link library file for joint simulation.

[0022] Optionally, the interface construction process between the simulation model and the control system and submodules in PSCAD simulation software includes:

[0023] In the PSCAD simulation software, create custom components and set the amount of interactive data between the main circuit module and each sub-module and control system;

[0024] Configure the execution script for the custom component, wherein the execution script is used to set the simulation duration and simulation step size;

[0025] Add the custom component to the simulation model built using PSCAD simulation software, connect the input and output variables, and realize the use of the custom component;

[0026] Add a first source code file and a second source code file. The first source code file is written in ifort language and is used to implement the transfer of the second source code file. The second source code file is written in C language and is used to implement the calling of the dynamic link library files of the control system and sub-modules.

[0027] The execution script calls the dynamic link library file to perform co-simulation.

[0028] Optionally, the dynamic link library file includes an initialization module and a time-step calculation module;

[0029] The step of calling the dynamic link library file through the execution script to perform co-simulation includes:

[0030] The execution script determines whether the current simulation time is the initial simulation time.

[0031] If so, the initialization module in the dynamic link library file is called to initialize the parameters of the submodule and the control system;

[0032] If not, then the time-step calculation module in the dynamic link library file is called for co-simulation.

[0033] A second aspect of this application provides a simulation acceleration device for a flexible DC transmission system, comprising:

[0034] The decoupling unit is used to decouple the flexible DC transmission system using a semi-implicit delayed decoupling method, resulting in a decoupled control system, main circuit module, and sub-modules.

[0035] The first simulation calculation unit is used to perform simulation calculations on the control system in the CPU during simulation, obtain control signals, and output the control signals to the sub-module.

[0036] The second simulation calculation unit is used to perform simulation calculations on the main circuit module in the CPU, obtain the bridge arm current, and output the bridge arm current to the sub-module and the control system through the interface.

[0037] The third simulation calculation unit is used to perform simulation calculations on each of the sub-modules in parallel using multi-threading in the GPU, obtain the capacitor voltage values ​​of each of the sub-modules, and transmit the superimposed capacitor voltage values ​​to the main circuit module and the control system, triggering the second simulation calculation unit, and triggering the first simulation calculation unit after reaching one simulation step size of the control system, until the simulation ends.

[0038] A third aspect of this application provides an electronic device, the device including a processor and a memory;

[0039] The memory is used to store program code and transmit the program code to the processor;

[0040] The processor is used to execute the simulation acceleration method for flexible DC transmission systems according to any one of the first aspects, based on the instructions in the program code.

[0041] A fourth aspect of this application provides a computer-readable storage medium for storing program code that, when executed by a processor, implements the simulation acceleration method for flexible DC transmission systems according to any one of the first aspects.

[0042] As can be seen from the above technical solutions, this application has the following advantages:

[0043] This application provides a simulation acceleration method for flexible DC transmission systems. The flexible DC transmission system is decoupled using a semi-implicit delay decoupling method. Based on the characteristics of each module after decoupling, a CPU-GPU architecture is proposed. The control system and main circuit modules with high logic requirements and many branch prediction structures are run by the CPU, while the sub-modules with simple control processes and large amounts of computational verification are computed in parallel by the GPU. This can greatly utilize the computing resources of the computer to improve simulation efficiency. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A flowchart illustrating a simulation acceleration method for a flexible DC transmission system provided in this application embodiment;

[0046] Figure 2 A schematic diagram of the topology of a modular multilevel converter provided in this application embodiment;

[0047] Figure 3 The topology and equivalent circuit diagram of the single-port submodule MMC;

[0048] Figure 4 An equivalent circuit diagram of decoupling of a modular multilevel converter bridge arm is provided for an embodiment of this application;

[0049] Figure 5 A schematic diagram of a double-ended flexible DC transmission system provided in an embodiment of this application, and the distribution of each module on the CPU and GPU;

[0050] Figure 6 A simulation flowchart of the electrical and control systems provided for embodiments of this application;

[0051] Figure 7 This is a flowchart illustrating the overall simulation process of a flexible DC transmission system provided in an embodiment of this application.

[0052] Figure 8 A schematic diagram of matrix segmentation provided in an embodiment of this application;

[0053] Figure 9 This is a flowchart illustrating the data transmission between the PSCAD simulation software and the CPU-GPU architecture provided in this application embodiment.

[0054] Figure 10 This is a flowchart illustrating the interface between the PSCAD simulation software and the CPU-GPU architecture provided in the embodiments of this application.

[0055] Figure 11 A parameter diagram of a flexible DC transmission system provided in an embodiment of this application;

[0056] Figure 12 A comparison chart of the time consumption of the method proposed in this application and PSCAD simulation is provided for the embodiments of this application;

[0057] Figure 13This is a flowchart illustrating a simulation acceleration device for a flexible DC transmission system provided in an embodiment of this application. Detailed Implementation

[0058] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0059] With the widespread application of large-scale flexible DC transmission systems, the complexity and computational load of electromagnetic transient simulation are increasing. Traditional CPU-based electromagnetic transient simulation algorithms can no longer meet current computational efficiency requirements. In recent years, graphics processing units (GPUs) have risen rapidly, gaining a foothold in the field of high-performance computing. Their high thread count gives them unparalleled advantages in large-scale parallel computing. CPUs are suitable for handling computational problems with low parallelism, high logic requirements, high operational complexity, and numerous branching structures; GPUs are suitable for handling problems with high computational intensity, high parallelism, and simple control flows. Therefore, to fully utilize computing resources on GPU-equipped computers, different tasks can be assigned to the CPU and GPU to improve the simulation efficiency of flexible DC transmission systems. The solution process and data transfer between different steps in electromagnetic transient simulation are serial computation processes, suitable for CPU processing; while the solution of the computationally intensive and highly repetitive MMC submodule is suitable for parallel computing on GPUs. PSCAD simulation software, as a widely used electromagnetic transient simulation software, possesses accurate transient simulation calculation capabilities and good openness, making it suitable for joint simulation tasks with CPU-GPU heterogeneous computing architectures.

[0060] For easier understanding, please refer to Figure 1 This application provides a method for accelerating the simulation of a flexible DC transmission system, including:

[0061] S1. The flexible DC transmission system is decoupled by a semi-implicit delay decoupling method to obtain the decoupled control system, main circuit module and sub-module;

[0062] Semi-implicit delay decoupling is a method that uses matrix splitting to group the state variables within a system. Different integral forms are then applied to each group to construct half-step delay expressions between the state variable groups, thus achieving semi-implicit decoupling between system variables. This application will introduce a general decoupling method obtained by applying semi-implicit delay decoupling to the single-port submodule MMC.

[0063] The topology of the MMC main circuit and its sub-modules is as follows: Figure 2 As shown. Figure 2 In the middle, L arm For each bridge arm reactor, N sub-modules are connected in series, C is the sub-module capacitor, and u rj The total output voltage of the bridge arm consisting of all sub-modules on the same bridge arm (where r=p,n, representing the upper and lower bridge arms respectively; j=a,b,c, representing the three phases a, b, and c), i pj and i nj U represents the upper and lower bridge arm currents, respectively. j U represents the output voltage at the three-phase AC output of the MMC. dc This is the DC side voltage.

[0064] The topology of the single-port submodule MMC is as follows: Figure 3 As shown in (a) of the figure, i arm For the bridge arm current, u sm Let C be the voltage at the port of the submodule. Assume that each submodule contains m capacitors C1, C2, ..., C m For ease of analysis, the bridge arm inductance is evenly distributed to each submodule port, then we can obtain: L sm =L arm / N. Simultaneously, the switching groups of each IGBT (Insulated Gate Bipolar Transistor) and VD (Diode) in the submodule are modeled using a resistor model, resulting in the equivalent circuit as follows: Figure 3 As shown in (b) of the diagram.

[0065] The state equations for the simplified equivalent circuit are as follows:

[0066] (1)

[0067] In the formula: It is an m×m dimensional diagonal matrix; A is an m×1 dimensional column vector; u A i These are coefficient matrices related to capacitor voltage and inductor current, respectively. Since Cdu C / dt reflects the KCL (Kirchhoff's Current Law) relationship regarding current, then G eq It can be viewed as admittance connected in parallel with the capacitor. Similarly, Ldi arm / dt reflects the KVL (Kirchhoff's Voltage Law) relationship with respect to voltage, R eq It can be regarded as a resistor connected in series with an inductor.

[0068] To simplify the analysis, we assume that the resistance of each IGBT switch group is approximately infinite in the off state, i.e. By applying the semi-implicit delay decoupling method to split the state variables into two sets, and then applying the implicit trapezoidal rule and the forward Euler method to the two sets of state variables respectively, a semi-implicit difference equation for the one-step time delay between the two sets of state variables can be obtained:

[0069] (2)

[0070] From formula (2), the recursive formulas for capacitor voltage and inductor current can be obtained:

[0071] (3)

[0072] (4)

[0073] In the formula, the equivalent voltage source U eq =A u u C Equivalent current source Q eq =A i i arm The decoupling variable set is the capacitor voltage u. C and inductor current i arm .

[0074] After obtaining the decoupling circuit of a single submodule, the equivalent circuit of the entire bridge arm can be obtained by connecting the decoupling circuits on the bridge arm side of each submodule in series. Figure 3 Taking any one phase arm as an example, the MMC arm decoupling circuit is as follows: Figure 4 As shown.

[0075] S2. During simulation, the control system is simulated and calculated in the CPU, control signals are obtained, and control signals are output to the sub-module.

[0076] S3. Simulate and calculate the main circuit module in the CPU, obtain the bridge arm current, and output the bridge arm current to the sub-module and control system through the interface.

[0077] S4. Simulate and calculate each sub-module in parallel using multi-threading in the GPU, obtain the capacitor voltage value of each sub-module, and transmit the superimposed capacitor voltage values ​​to the main circuit module and the control system. Return to step S3. After reaching one simulation step size of the control system, return to step S2 until the simulation ends.

[0078] In terms of architecture, both CPUs and GPUs have three basic units: control units, arithmetic units, and storage units. However, their proportions within the core differ. The difference lies in the structure of their cache systems and digital logic units: CPUs have larger cache and control units per core, enabling branch prediction, but smaller computing units and fewer threads, making large-scale parallel computing difficult. GPUs, on the other hand, have smaller storage and control units per core, resulting in weaker logic processing capabilities, but significantly larger arithmetic units and more threads, enabling large-scale parallel computing.

[0079] The flexible DC transmission system consists of three modules: a main circuit module, sub-modules, and a control system. Each module has its own computational characteristics. The main circuit module has relatively low computational load, making it most suitable for solving on a CPU. The sub-modules have higher computational load, and since decoupled sub-modules can be solved in parallel, they are suitable for parallel computing via GPU programming. The control system involves many logical decisions, and the CPU's strong logic processing capabilities make it most suitable for solving using CPU programming. Figure 5 As shown.

[0080] Simulation of flexible DC transmission systems within a semi-implicit decoupling framework can be transformed into a large-scale, repetitive solution process using nodes and branches as basic units. The simulation process for the entire electrical system can be divided into two main steps: first, solving the state variables of the main circuit module; and second, solving the state variables of the sub-modules, with a half-step difference between the two. The solutions for the main circuit module and sub-module state variables can be further divided into three sub-steps: forming the historical current source column vector, solving the node voltage equations, and solving the branch currents. Since the main circuit module has low computational parallelism, it is suitable for computation on a CPU. After semi-implicit delay decoupling, the solutions for each node in the sub-modules are independent, exhibiting fine-grained parallel solution characteristics. Therefore, the multi-threaded architecture of GPUs can be used for parallel solution, further improving simulation efficiency.

[0081] The entire flexible DC transmission system can be divided into a control system and an electrical system (corresponding to the main circuit and each sub-module, but the circuit topology is different when solving the main circuit and each sub-module). The control system has a large acceptable time scale. Therefore, to save computing resources and improve simulation efficiency, it is usually designed so that when the control system simulation takes one step, the electrical system simulation takes multiple steps. The simulation of the control system is divided into four steps. First, the rectifier side performs outer-loop DC voltage control and outer-loop reactive power control, and the inverter side performs active power control and outer-loop reactive power control. Second, the stator direct-axis voltage and stator quadrature-axis voltage are calculated as inputs for current decoupling control. At the same time, circulating current suppression is performed on both the rectifier side and the inverter side to improve system stability and control accuracy. Finally, the control signal for the IGBT switch is obtained through nearest-level approximation modulation (NLM) and the control signal is output to the electrical system. The calculation of the control system has high logic requirements, but the computational intensity is not high, so it is suitable to run on a CPU. The simulation flow of the control system and the electrical system is as follows: Figure 6 As shown.

[0082] PSCAD simulation software, as a widely used electromagnetic transient simulation software, can be co-simulated with CPU-GPU architecture to improve simulation efficiency. Therefore, based on the above electrical system and control system simulation process, the overall simulation process of the flexible DC transmission system using PSCAD simulation software is as follows: When the control system simulation begins on the CPU, the system calculation program starts running on the PSCAD simulation software, performing simulation calculations on the main circuit module to obtain the bridge arm current value. This bridge arm current is then transmitted to the dynamic link library (DLL) calculation program of the sub-module located on the GPU through the developed PSCAD interface to obtain the capacitor voltage value of the sub-module. The capacitor voltage values ​​of the sub-module are then superimposed and transmitted to the main circuit module and the control system. This data transmission step between the main circuit module and the sub-module is repeated multiple times until the current simulation step of the control system ends, then the next simulation step of the control system begins. The process is as follows: Figure 7 As shown.

[0083] Since both CPUs and GPUs are multi-threaded hardware, to fully utilize their computing resources and accelerate the flexible DC transmission system, threads should be allocated as needed. For sub-modules solved in the GPU, since each sub-module only needs to complete one solution for the one-dimensional historical current source column vector, one solution for the one-dimensional node voltage equation, and one calculation for the one-dimensional branch current, the required threads are relatively few. Therefore, one GPU thread is allocated to each sub-module, thereby enabling parallel solving of all sub-modules. Furthermore, considering that GPU threads are allocated in bundles of 32 threads, the number of threads allocated to all sub-modules can be expressed as:

[0084] (5)

[0085] In the formula, m is the number of submodules, p GPU The number of threads allocated to all submodules; To return greater than or equal to The smallest integer.

[0086] Considering that GPU memory can be divided into three levels—registers, shared memory, and global memory—the access latency of these three types of memory differs significantly and can be independently controlled through CUDA programs. Registers, as storage space allocated separately for each thread, have the fastest access speed. However, if all simulation results of a submodule are stored in registers, it may lead to register overflow. Overflowing data will be stored entirely in global memory, which has the highest access latency and largest capacity, impacting simulation efficiency. Shared memory, on the other hand, is a storage space with access latency and capacity between registers and global memory. However, shared memory overflow can lead to more serious compilation errors or kernel startup failures. To avoid the decrease in model simulation efficiency due to high access latency when all submodule data is stored in global memory during simulation calculations, the memory required by submodules is quantified. The required memory capacity M of a submodule is calculated based on the number of submodules m and the number of bytes B occupied by a single data item within the submodule. GPU :

[0087] (6)

[0088] If the memory required by a submodule is less than the register memory capacity in the GPU, the submodule's data is stored in the GPU's registers; if the memory required by a submodule is greater than the register memory capacity in the GPU but less than the shared memory capacity in the GPU, the submodule's data is stored in the shared memory in the GPU; if the memory required by a submodule is greater than the shared memory capacity in the GPU, the submodule's data is stored in the GPU's global memory.

[0089] For control systems solved in the CPU, which are difficult to parallelize on a large scale due to their high seriality, two threads are allocated for parallel simulation, one for solving the rectifier-side control system and the other for solving the inverter-side control system.

[0090] For the main circuit module, which is solved in the CPU, the solution process can be divided into three steps: forming the column vector of historical current sources, solving the node voltage equations, and solving the branch currents. The simulation calculation process of the main circuit module includes:

[0091] (7)

[0092] (8)

[0093] (9)

[0094] In the formula, I h This is the equivalent current source vector of the capacitor and inductor after discretization and parallel connection on the branch; U n Let be the voltage vector composed of the voltages of the submodules; ∫ is the historical current coefficient; t is the current time, ∆t is the simulation step size; ∫ is the historical voltage coefficient; G is the admittance matrix; G eq The matrix is ​​formed by the admittances of each branch; I n Inject a current vector into the node; I b U is the branch current vector; m This is the branch voltage difference matrix.

[0095] The solution to the above matrix can be achieved using the remaining CPU threads p CPU Parallel solution is performed. Based on the allocated threads, the matrix to be solved in (7)-(9) is divided into blocks, taking equation (8) as an example. Figure 8 As shown. The matrix is ​​divided into rows, and multiplication and addition operations are performed in multiple rows. The solution is then performed in parallel using multithreading in the CPU. The solutions for formulas (7) and (9) are similar.

[0096] To achieve communication between different wind farm models, the reliability of the data interaction module must be guaranteed. Simultaneously, considering large-scale wind farm simulation, the economic efficiency of the data interaction module cannot be ignored. Both User Datagram Protocol (UDP) and Transmission Control Protocol (TCP) can achieve data interaction within the simulation framework. UDP is a highly efficient connectionless communication protocol that sends data directly without establishing a connection, resulting in high transmission efficiency and extremely low latency. However, it does not guarantee timely and accurate data transmission. This uncertainty can lead to the inability to synchronize calculation results from different parts in a timely manner, thus hindering effective co-simulation between PSCAD simulation software and the self-developed GPU code and control system. Therefore, it cannot be used for co-simulation with PSCAD simulation software. TCP is a connection-oriented and reliable transmission protocol. Because it introduces data verification and retransmission mechanisms at the protocol layer, it ensures the correctness and orderliness of data interaction. However, the establishment of a connection and acknowledgment mechanism results in slower data transmission speeds, thus affecting simulation efficiency.

[0097] To address the shortcomings of the above communication methods, this application embodiment employs the more advantageous PCIe bus communication. The PCIe bus utilizes a high-efficiency protocol stack, reducing data packet processing time and transmission latency, and offers good bandwidth scalability, allowing for expansion as needed, while also ensuring high data transmission reliability. This application embodiment packages the simulation code of the sub-modules deployed on the GPU and the simulation code of the control system deployed on the CPU into standard-format dynamic link library files. During simulation, communication between the main circuit module, sub-modules, and control system is achieved via the PCIe bus, enabling joint simulation by calling the dynamic link library files.

[0098] PSCAD simulation software can call DLLs using either gFortran or ifort compilers. gFortran, belonging to MinGW, is the built-in compiler for PSCAD simulation software; code can be compiled directly without special configuration and only supports CPU programs. Furthermore, as it is not a native Windows compiler, its execution efficiency is low. ifort, deeply integrated with Visual Studio, supports both CPU and GPU programs, and as a native Windows compiler, its execution efficiency is high. This application's embodiment uses the CUDA architecture from NVIDIA for its CPU-GPU co-computing electromagnetic transient simulation platform. ifort supports the CUDA architecture and can communicate with the GPU, while gFortran does not. Therefore, this application uses ifort in the backend to implement the PSCAD simulation software's call to DLL programs in the CPU and GPU. The data transmission process between the PSCAD simulation software and the CPU-GPU architecture is as follows: Figure 9 As shown.

[0099] In this embodiment, data transmission between the main circuit and the control system, and sub-modules, is achieved by constructing an interface between the PSCAD simulation software and the CPU-GPU architecture. The interface construction process is as follows: Figure 10As shown. First, a custom module is created in the PSCAD simulation software, setting the amount of interactive data between the main circuit module, the decoupled sub-modules, and the control system. Then, the execution script `globalinterface` for the custom component is set. This script's input is used to set the model simulation duration and simulation step size, enabling synchronous long-term simulation of the main circuit module and sub-modules. Next, the custom component is referenced. This is achieved by adding the custom component to the simulation model built in the PSCAD simulation software and connecting the input and output variables. Finally, two source code files are added to implement the `globalinterfacef` function defined in the custom component. These two files are named `interfaceCtrlFileF` (the first source code file) and `interfaceCtrlFileC` (the second source code file). `interfaceCtrlFileF` mainly contains the definition of the `globalinterfacef` function. Since the PSCAD simulation software does not support direct calls to C language code, `globalinterfacef` is written in Ifort to implement the conversion to `interfaceCtrlFileC`, enabling the calling of the sub-module's simulation code. The `interfaceCtrlFileC` code is written in C. This code primarily contains the `globalinterface` function, which loads the DLL and calls the DLL's initialization module (`init`) and time-step calculation module (`step`). The `init` code initializes parameters such as capacitors and IGBT switches in the submodules; `step` calls the DLL during simulation. The `globalinterface` function determines whether to execute `init` or `step` based on the current time. When simulation time = 0 (i.e., the initial simulation time), `init` runs to initialize the parameters of the submodules and the control system. When time > 0, `step` runs for co-simulation.

[0100] The main circuit model used in the simulation was built using modules provided by the PSCAD simulation software. The interfaces between the main circuit, control system, and submodules were programmed in C / C++ within the PSCAD simulation software. The upper-level main function code was written in C++, calling the control system and submodule calculation code. The control system program was written in C, while the submodule calculation code was written in CUDA to accelerate the simulation of the submodules on the GPU, thus implementing the method proposed in this application. The program results were compared with the results of undecoupled serial simulation to verify the accuracy and efficiency of the proposed method. The example used a single-ended 21-level half-bridge submodule MMC, with module parameters as follows... Figure 11As shown. The system simulation step size was set to 5µs. The simulation efficiency of the PSCAD simulation software's undecoupled serial simulation model and the simulation acceleration method based on the CPU-GPU heterogeneous architecture proposed in this application were compared. The simulation time of the PSCAD simulation software and the simulation time of the method proposed in this application were compared under different numbers of MMC units, and the speedup ratio was calculated. Figure 12 As shown. From Figure 12 As can be seen, the simulation speedup using the method proposed in this application is at least 3 times. The method proposed in this application has a significant model acceleration effect, and the simulation acceleration effect is more obvious as the number of MMC units increases, which can effectively improve the simulation efficiency of MMC.

[0101] Please refer to Figure 13 This application also provides a simulation acceleration device for a flexible DC transmission system, comprising:

[0102] Decoupling unit 10 is used to decouple the flexible DC transmission system using a semi-implicit delayed decoupling method to obtain the decoupled control system, main circuit module and sub-module;

[0103] The first simulation calculation unit 20 is used to perform simulation calculations on the control system in the CPU during simulation, obtain control signals, and output the control signals to the sub-modules.

[0104] The second simulation calculation unit 30 is used to perform simulation calculations on the main circuit module in the CPU, obtain the bridge arm current, and output the bridge arm current to the sub-module and the control system through the interface.

[0105] The third simulation calculation unit 40 is used to perform simulation calculations on each sub-module in parallel using multi-threading in the GPU, obtain the capacitor voltage values ​​of each sub-module, and transmit the superimposed capacitor voltage values ​​to the main circuit module and the control system, triggering the second simulation calculation unit 30. After reaching one simulation step size of the control system, the first simulation calculation unit 20 is triggered until the simulation ends.

[0106] As a further improvement, the device also includes: a selection unit for:

[0107] The number of submodules and the number of bytes occupied by a single piece of data in a submodule are used to calculate the memory capacity required for the submodule;

[0108] If the memory required by the submodule is less than the register memory capacity in the GPU, then the data of the submodule will be stored in the registers in the GPU.

[0109] If the memory required by the submodule is greater than the register memory capacity in the GPU but less than the shared memory capacity in the GPU, then the data of the submodule will be stored in the shared memory in the GPU.

[0110] If the memory required by a submodule is greater than the shared memory capacity in the GPU, the submodule's data will be stored in the GPU's global memory.

[0111] This application also provides an electronic device, which includes a processor and a memory;

[0112] The memory is used to store program code and transfer the program code to the processor;

[0113] The processor is used to execute the simulation acceleration method for flexible DC transmission systems in the foregoing method embodiments according to the instructions in the program code.

[0114] This application also provides a computer-readable storage medium for storing program code, which, when executed by a processor, implements the flexible DC transmission system simulation acceleration method in the aforementioned method embodiments.

[0115] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or apparatus.

[0116] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0117] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0118] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0119] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0120] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for executing all or part of the steps of the methods described in the various embodiments of this application through a computer device (which may be a personal computer, server, or network device, etc.). The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0121] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A simulation acceleration method for a flexible DC transmission system, characterized in that, include: S1. The flexible DC transmission system is decoupled by a semi-implicit delay decoupling method to obtain the decoupled control system, main circuit module and sub-module; S2. During simulation, the control system is simulated and calculated in the CPU to obtain control signals, and the control signals are output to the sub-module. S3. Simulate and calculate the main circuit module in the CPU, obtain the bridge arm current, and output the bridge arm current to the sub-module and the control system through the interface; S4. Simulate and calculate each sub-module in parallel using multi-threading in the GPU, obtain the capacitor voltage value of each sub-module, and transmit the superimposed capacitor voltage values ​​to the main circuit module and the control system. Return to step S3. After reaching one simulation step size of the control system, return to step S2 until the simulation ends.

2. The simulation acceleration method for flexible DC transmission systems according to claim 1, characterized in that, The formula for calculating the number of threads allocated to the submodule is as follows: In the formula, m is the number of submodules, p GPU The number of threads allocated to all submodules; To return greater than or equal to The smallest integer.

3. The simulation acceleration method for flexible DC transmission systems according to claim 1, characterized in that, The method further includes: The required memory capacity of each submodule is calculated based on the number of submodules and the number of bytes occupied by a single piece of data in each submodule. If the memory capacity required by the submodule is less than the register memory capacity in the GPU, then the data of the submodule is stored in the registers in the GPU; If the memory capacity required by the submodule is greater than the register memory capacity in the GPU but less than the shared memory capacity in the GPU, then the data of the submodule will be stored in the shared memory in the GPU. If the memory required by the submodule is greater than the shared memory capacity in the GPU, then the data of the submodule will be stored in the global memory of the GPU.

4. The simulation acceleration method for flexible DC transmission systems according to claim 1, characterized in that, The step of performing simulation calculations on the main circuit module in the CPU to obtain the bridge arm current includes: The main circuit module is divided into blocks based on the threads allocated by the CPU during simulation calculations. The CPU uses multi-threading to solve the block matrix in parallel to obtain the bridge arm current.

5. The simulation acceleration method for flexible DC transmission systems according to claim 1, characterized in that, The main circuit module is built using PSCAD simulation software. The simulation code of the sub-modules deployed in the GPU and the simulation code of the control system deployed in the CPU are packaged into a standard format dynamic link library file. During simulation, communication between the main circuit module and each sub-module and the control system is realized through the PCIe bus to call the dynamic link library file for joint simulation.

6. The simulation acceleration method for flexible DC transmission systems according to claim 5, characterized in that, The interface construction process between the simulation model and the control system and sub-modules in PSCAD simulation software includes: In the PSCAD simulation software, create custom components and set the amount of interactive data between the main circuit module and each sub-module and control system; Configure the execution script for the custom component, wherein the execution script is used to set the simulation duration and simulation step size; Add the custom component to the simulation model built using PSCAD simulation software, connect the input and output variables, and realize the use of the custom component; Add a first source code file and a second source code file. The first source code file is written in ifort language and is used to implement the transfer of the second source code file. The second source code file is written in C language and is used to implement the calling of the dynamic link library files of the control system and sub-modules. The execution script calls the dynamic link library file to perform co-simulation.

7. The simulation acceleration method for flexible DC transmission systems according to claim 6, characterized in that, The dynamic link library file includes an initialization module and a time-step calculation module; The step of calling the dynamic link library file through the execution script to perform co-simulation includes: The execution script determines whether the current simulation time is the initial simulation time. If so, the initialization module in the dynamic link library file is called to initialize the parameters of the submodule and the control system; If not, then the time-step calculation module in the dynamic link library file is called for co-simulation.

8. A simulation acceleration device for a flexible DC transmission system, characterized in that, include: The decoupling unit is used to decouple the flexible DC transmission system using a semi-implicit delayed decoupling method, resulting in a decoupled control system, main circuit module, and sub-modules. The first simulation calculation unit is used to perform simulation calculations on the control system in the CPU during simulation, obtain control signals, and output the control signals to the sub-module. The second simulation calculation unit is used to perform simulation calculations on the main circuit module in the CPU, obtain the bridge arm current, and output the bridge arm current to the sub-module and the control system through the interface. The third simulation calculation unit is used to perform simulation calculations on each of the sub-modules in parallel using multi-threading in the GPU, obtain the capacitor voltage values ​​of each of the sub-modules, and transmit the superimposed capacitor voltage values ​​to the main circuit module and the control system, triggering the second simulation calculation unit, and triggering the first simulation calculation unit after reaching one simulation step size of the control system, until the simulation ends.

9. An electronic device, characterized in that, The device includes a processor and a memory; The memory is used to store program code and transmit the program code to the processor; The processor is used to execute the simulation acceleration method for flexible DC transmission systems according to any one of claims 1-7, based on the instructions in the program code.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store program code, which, when executed by a processor, implements the simulation acceleration method for flexible DC transmission systems according to any one of claims 1-7.

Images