Data read-write method and hybrid memory

Abstract

The embodiment of the invention provides a data read-write method and a hybrid memory, relates to the field of terminals, and can improve read-write performance and reduce power consumption. The hybrid memory includes a memory controller, a volatile storage medium, and a non-volatile storage medium. A physical address field of the volatile storage medium is different from a physical address field of the non-volatile storage medium. The storage controller can receive a read / write instruction from the processor, wherein the read / write instruction carries a first address (the first address can be a physical address or a logical address); if the first address corresponds to the storage space of the volatile storage medium, the storage controller can perform data read-write processing in the storage space of the volatile storage medium; if the first address corresponds to the storage space of the nonvolatile storage medium, the storage controller can perform data read-write processing in the storage space of the nonvolatile storage medium.

Description

[0001] This application is a divisional application. The original application has the application number 202110654001.8 and the original application date is June 11, 2021. The entire contents of the original application are incorporated herein by reference.

[0002] This application claims priority to Chinese Patent Application No. 202110182302.5, filed on February 9, 2021, entitled "A Device Implementation Method and Apparatus for Hybrid Volatile and Non-volatile Storage Media", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of terminals, and more particularly to a data read / write method and a hybrid memory. Background Technology

[0004] Currently, various electronic devices (such as smartphones and tablets) contain two types of storage media: volatile memory (VM) and non-volatile memory (NVM). Volatile memory can include random access memory (RAM). RAM can be, for example, double data rate (DDR) memory. The contents of volatile memory are lost when the system experiences a sudden power outage. Non-volatile memory can include, for example, hard drive disks (HDDs) and solid-state disks (SSDs). Data in non-volatile memory is not lost when the computer is shut down or when the computer is suddenly or unexpectedly shut down.

[0005] Volatile and non-volatile memory have the following problems: volatile memory consumes high power when reading and writing data, while non-volatile memory encounters long delays and waiting times when reading and writing data, resulting in low read and write performance. Summary of the Invention

[0006] This application provides a data read / write method and a hybrid memory that can improve read / write performance and reduce power consumption.

[0007] In a first aspect, embodiments of this application provide a hybrid memory, which includes a memory controller, a volatile memory medium, and a non-volatile memory medium. The physical address segment of the volatile memory medium (also referred to as a volatile storage medium) is different from the physical address segment of the non-volatile memory medium (also referred to as a non-volatile storage medium). The memory controller is used to receive read / write instructions from a processor, the read / write instructions carrying a first address. The first address corresponds to the storage space of the volatile memory medium or the storage space of the non-volatile memory medium. If the first address corresponds to the storage space of the volatile memory medium, the memory controller is used to write data to or read data from the storage space of the volatile memory medium. If the first address corresponds to the storage space of the non-volatile memory medium, the memory controller is used to write data to or read data from the storage space of the non-volatile memory medium.

[0008] The volatile storage medium group in the hybrid memory provided in this application embodiment can support high-speed data processing and achieve high read / write performance. The non-volatile storage medium group in the hybrid memory has high performance and low power consumption at lower frequencies. Therefore, using hybrid memory can improve the read / write performance of electronic devices and reduce power consumption. It can meet the basic requirements of low power consumption and high performance of electronic devices on the market. Furthermore, the hybrid memory is simple to implement in hardware, has a simple internal design, and is low in cost.

[0009] In one possible implementation, the hybrid memory further includes at least one of a bus, a substrate, a package housing, and a bus interface; wherein the memory controller, volatile memory medium, and non-volatile memory medium are integrated on the substrate, the volatile memory medium and non-volatile memory medium are connected via a bus, and the memory controller, volatile memory medium, non-volatile memory medium, bus, and substrate are packaged inside the package housing, which externally presents the bus interface for connection with the processor. The hybrid memory has simple hardware implementation, simple internal design, is easier to implement, and has lower cost.

[0010] In one possible implementation, the volatile storage medium includes at least one of Double Data Rate (DDR) memory, DDR2, DDR3, DDR4, high bandwidth memory (HBM), dynamic random access memory (DRAM), and 3D Super-DRAM; the non-volatile storage medium includes at least one of single-level cell (SLC) NAND flash memory, magnetic random access memory (MRAM), resistance random access memory (RRAM), phase change random access memory (PCRAM), 3D-Xpoint storage medium, or 3D-SLC NAND flash memory. This application does not limit the type of volatile or non-volatile storage medium.

[0011] In one possible implementation, hybrid memory is installed as main memory in the electronic device. Program data can be stored in the hybrid memory during runtime. Thus, when the electronic device uses hybrid memory as main memory, the volatile storage media within the hybrid memory can support high-speed data processing, achieving high read / write performance. The non-volatile storage media within the hybrid memory exhibits high performance and low power consumption at lower frequencies. Therefore, using hybrid memory can improve the read / write performance of electronic devices and reduce power consumption, meeting the basic demands of low power consumption and high performance in electronic devices on the market.

[0012] In one possible implementation, the hybrid memory is powered off when the electronic device is in a screen-off state. Traditional memory (e.g., RAM) cannot be completely powered off in a screen-off state, otherwise data loss would occur. The data in the non-volatile storage medium group of the hybrid memory provided in this application embodiment is not lost. Useful data can be stored in the non-volatile storage medium group, allowing the electronic device to be completely powered off in a screen-off state, significantly reducing power consumption. Furthermore, traditional memory loses data when powered off. Upon the next power-on, running programs need to be imported into memory for processing before the system can boot. When the hybrid memory is powered off, the data in the non-volatile storage medium group of the hybrid memory is not lost. Running programs can be stored in the non-volatile storage medium group, allowing for quick restoration of running programs upon the next power-on, further reducing standby power consumption and improving startup performance.

[0013] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, which includes at least one of real-time trained AI data, models, and training results. Compared to existing technologies, the need to recalculate the preset type of data after power-on leads to power consumption, or reading the preset type of data from slow storage results in inefficiency. In this embodiment, the SoC can directly read the preset type of data from a hybrid memory acting as main memory, which takes significantly less time than recalculation and reading from slow storage.

[0014] In one possible implementation, the first address is either a physical address or a logical address. If the first address is a logical address, the storage controller further converts the logical address to a physical address. If the first address is a physical address, the storage controller can directly address the volatile or non-volatile storage medium based on the physical address to determine the storage space corresponding to the physical address. When the first address is a logical address, the storage controller further converts the logical address to a physical address, and then addresses the volatile or non-volatile storage medium based on the physical address to determine the storage space corresponding to the physical address.

[0015] Secondly, embodiments of this application provide a hybrid memory, which includes a memory controller, a volatile memory medium, and a non-volatile memory medium. The physical address segment of the volatile memory medium is the same as that of the non-volatile memory medium. The memory controller receives read / write instructions from the processor, and the read / write instructions carry a first address. If the processor's clock frequency is greater than the highest read / write frequency of the non-volatile memory medium, the memory controller is used to write data to or read data from the storage space of the volatile memory medium. If the processor's clock frequency is less than or equal to the highest read / write frequency of the non-volatile memory medium, the memory controller is used to write data to or read data from the storage space of the non-volatile memory medium.

[0016] Thus, when the processor operates at a high clock speed (i.e., the processor's clock frequency is higher than the maximum read / write frequency of the non-volatile storage medium), data is written to the volatile storage medium to meet the requirements of fast operation because the non-volatile storage medium's maximum read / write frequency is lower than the processor's (i.e., the non-volatile storage medium processes data slower than the processor). When the processor's clock speed decreases, the non-volatile storage medium's maximum read / write frequency is greater than or equal to the processor's frequency, meaning the non-volatile storage medium can process data at the same speed as the processor. Therefore, data can be written to the non-volatile storage medium to achieve lower power consumption. At this point, the volatile storage medium can enter an extremely low-power state, achieving the effect of reducing power consumption.

[0017] In one possible implementation, if the processor's clock frequency is greater than the maximum read / write frequency of the non-volatile storage medium, the storage controller is also used to write data written to the storage space of the volatile storage medium to the storage space of the non-volatile storage medium; if the processor's clock frequency is less than or equal to the maximum read / write frequency of the non-volatile storage medium, the storage controller is also used to write data written to the storage space of the non-volatile storage medium to the storage space of the volatile storage medium.

[0018] In other words, when the processor is operating at a high clock speed, data is first written to volatile storage, and then the storage controller automatically transfers the data to a lower-speed non-volatile storage medium. When the system is operating at a low speed range that the non-volatile storage medium can handle, data is first written to the non-volatile storage medium, and then the storage controller automatically transfers the data to the volatile storage medium. This process can be completed by the hybrid memory's storage controller without processor intervention, reducing the processor's load and improving its processing performance.

[0019] In one possible implementation, the hybrid memory further includes at least one of a bus, a substrate, a package housing, and a bus interface; wherein the memory controller, volatile memory medium, and non-volatile memory medium are integrated on the substrate, the volatile memory medium and non-volatile memory medium are connected via a bus, the memory controller, volatile memory medium, non-volatile memory medium, bus, and substrate are packaged inside the package housing, and the package housing 006 presents a bus interface to the outside, the bus interface being used to connect to the processor.

[0020] In one possible implementation, the volatile storage medium includes at least one of Double Data Rate (DDR) memory, DDR2, DDR3, DDR4, High Bandwidth Memory (HBM), Dynamic Random Access Memory (DRAM), or 3D Super DRAM; the non-volatile storage medium includes at least one of Single-Level Storage Flash Memory (SLC-NAND), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PCRAM), 3D-Xpoint storage medium, or 3D-SLC NAND flash memory.

[0021] In one possible implementation, hybrid memory is installed as RAM in an electronic device.

[0022] In one possible implementation, the hybrid memory is powered off when the electronic device is off.

[0023] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, which includes at least one of real-time trained artificial intelligence (AI) data, models, and training results.

[0024] In one possible implementation, the first address is either a physical address or a logical address; if the first address is a logical address, the storage controller is also used to convert the logical address into a physical address.

[0025] Thirdly, embodiments of this application provide a hybrid memory, which includes a memory controller, a volatile memory medium, and a non-volatile memory medium. The physical address segment of the volatile memory medium is partially identical to that of the non-volatile memory medium. The memory controller receives read / write instructions from a processor, each instruction carrying a first address. When the first address corresponds to the storage space of both the non-volatile and volatile memory media, if the processor's clock frequency is greater than the highest read / write frequency of the non-volatile memory medium, the memory controller writes data to or reads data from the storage space of the volatile memory medium. If the processor's clock frequency is less than... This value may be equal to the highest read / write frequency of the non-volatile storage medium. The storage controller is used to write data to or read data from the storage space of the non-volatile storage medium. When the first address corresponds to the non-volatile storage medium or the storage space of the volatile storage medium, if the first address corresponds to the storage space of the volatile storage medium, the storage controller is used to write data to or read data from the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller is used to write data to or read data from the storage space of the non-volatile storage medium.

[0026] In this embodiment, after the hybrid memory receives the first address, and the first address simultaneously corresponds to the storage space of both non-volatile and volatile storage media, when the processor is at a high clock frequency (i.e., the processor's clock frequency is higher than the maximum read / write frequency of the non-volatile storage media), since the maximum read / write frequency of the non-volatile storage media is lower than the clock frequency (i.e., the data processing speed of the non-volatile storage media is lower than the data processing speed of the processor), data is written to the volatile storage media to meet the requirements of fast operation. When the processor's clock frequency decreases, the maximum read / write frequency of the non-volatile storage media is greater than or equal to the clock frequency, meaning the data processing speed of the non-volatile storage media can reach the data processing speed of the processor. Therefore, data can be written to the non-volatile storage media to achieve lower power consumption. At this time, the volatile storage media can enter an extremely low power consumption state, achieving the effect of reducing power consumption.

[0027] When the first address corresponds to a non-volatile storage medium or a storage space of a volatile storage medium, data can be directly read from or written to the non-volatile storage medium or the storage space of the volatile storage medium indicated by the first address. The volatile storage medium group can support high-speed data processing and achieve high read / write performance. The non-volatile storage medium group in the hybrid memory exhibits high performance and low power consumption at lower frequencies. Therefore, using hybrid memory can improve the read / write performance of electronic devices and reduce power consumption, thus meeting the basic demands of low power consumption and high performance in electronic devices on the market.

[0028] In one possible implementation, if the processor's clock frequency is greater than the maximum read / write frequency of the non-volatile storage medium, the storage controller is also used to write data written to the storage space of the volatile storage medium to the storage space of the non-volatile storage medium; if the processor's clock frequency is less than or equal to the maximum read / write frequency of the non-volatile storage medium, the storage controller is also used to write data written to the storage space of the non-volatile storage medium to the storage space of the volatile storage medium.

[0029] In one possible implementation, the hybrid memory further includes at least one of a bus, a substrate, a package housing, and a bus interface; wherein the memory controller, volatile memory medium, and non-volatile memory medium are integrated on the substrate, the volatile memory medium and non-volatile memory medium are connected via a bus, the memory controller, volatile memory medium, non-volatile memory medium, bus, and substrate are packaged inside the package housing, and the package housing 006 presents a bus interface to the outside, the bus interface being used to connect to the processor.

[0030] In one possible implementation, the volatile storage medium includes at least one of Double Data Rate (DDR) memory, DDR2, DDR3, DDR4, High Bandwidth Memory (HBM), Dynamic Random Access Memory (DRAM), or 3D Super DRAM; the non-volatile storage medium includes at least one of Single-Level Storage Flash Memory (SLC-NAND), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PCRAM), 3D-Xpoint storage medium, or 3D-SLC NAND flash memory.

[0031] In one possible implementation, hybrid memory is installed as RAM in an electronic device.

[0032] In one possible implementation, the hybrid memory is powered off when the electronic device is off.

[0033] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, which includes at least one of real-time trained artificial intelligence (AI) data, models, and training results.

[0034] In one possible implementation, the first address is either a physical address or a logical address; if the first address is a logical address, the storage controller is also used to convert the logical address into a physical address.

[0035] Fourthly, embodiments of this application provide a data read / write method applied to a hybrid memory, the hybrid memory including a memory controller, a volatile memory medium, and a non-volatile memory medium; the physical address segment of the volatile memory medium is different from the physical address segment of the non-volatile memory medium; the method includes: the memory controller receiving a read / write instruction from a processor, the read / write instruction carrying a first address; if the first address corresponds to the storage space of the volatile memory medium, the memory controller writes data to the storage space of the volatile memory medium or reads data from the storage space of the volatile memory medium; if the first address corresponds to the storage space of the non-volatile memory medium, the memory controller writes data to the storage space of the non-volatile memory medium or reads data from the storage space of the non-volatile memory medium.

[0036] In one possible implementation, the hybrid memory further includes at least one of a bus, a substrate, a package housing, and a bus interface; wherein the memory controller, volatile memory medium, and non-volatile memory medium are integrated on the substrate, the volatile memory medium and non-volatile memory medium are connected via a bus, the memory controller, volatile memory medium, non-volatile memory medium, bus, and substrate are packaged inside the package housing, and the package housing 006 presents a bus interface to the outside, the bus interface being used to connect to the processor.

[0037] In one possible implementation, the volatile storage medium includes at least one of Double Data Rate (DDR) memory, DDR2, DDR3, DDR4, High Bandwidth Memory (HBM), Dynamic Random Access Memory (DRAM), or 3D Super DRAM; the non-volatile storage medium includes at least one of Single-Level Storage Flash Memory (SLC-NAND), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PCRAM), 3D-Xpoint storage medium, or 3D-SLC NAND flash memory.

[0038] In one possible implementation, hybrid memory is installed as RAM in an electronic device.

[0039] In one possible implementation, the hybrid memory is powered off when the electronic device is off.

[0040] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, which includes at least one of real-time trained artificial intelligence (AI) data, models, and training results.

[0041] In one possible implementation, the first address is either a physical address or a logical address; if the first address is a logical address, the storage controller is also used to convert the logical address into a physical address.

[0042] Fifthly, embodiments of this application provide a data read / write method applied to a hybrid memory, the hybrid memory including a memory controller, a volatile memory medium, and a non-volatile memory medium; the physical address segment of the volatile memory medium is the same as the physical address segment of the non-volatile memory medium; the method includes: the memory controller receiving a read / write instruction from a processor, the read / write instruction carrying a first address; if the processor's clock frequency is greater than the highest read / write frequency of the non-volatile memory medium, the memory controller writes data to the storage space of the volatile memory medium or reads data from the storage space of the volatile memory medium; if the processor's clock frequency is less than or equal to the highest read / write frequency of the non-volatile memory medium, the memory controller writes data to the storage space of the non-volatile memory medium or reads data from the storage space of the non-volatile memory medium.

[0043] In one possible implementation, if the processor's clock frequency is greater than the maximum read / write frequency of the non-volatile storage medium, the storage controller is also used to write data written to the storage space of the volatile storage medium to the storage space of the non-volatile storage medium; if the processor's clock frequency is less than or equal to the maximum read / write frequency of the non-volatile storage medium, the storage controller is also used to write data written to the storage space of the non-volatile storage medium to the storage space of the volatile storage medium.

[0044] In one possible implementation, the hybrid memory further includes at least one of a bus, a substrate, a package housing, and a bus interface; wherein the memory controller, volatile memory medium, and non-volatile memory medium are integrated on the substrate, the volatile memory medium and non-volatile memory medium are connected via a bus, the memory controller, volatile memory medium, non-volatile memory medium, bus, and substrate are packaged inside the package housing, and the package housing 006 presents a bus interface to the outside, the bus interface being used to connect to the processor.

[0045] In one possible implementation, the volatile storage medium includes at least one of Double Data Rate (DDR) memory, DDR2, DDR3, DDR4, High Bandwidth Memory (HBM), Dynamic Random Access Memory (DRAM), or 3D Super DRAM; the non-volatile storage medium includes at least one of Single-Level Storage Flash Memory (SLC-NAND), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PCRAM), 3D-Xpoint storage medium, or 3D-SLC NAND flash memory.

[0046] In one possible implementation, hybrid memory is installed as RAM in an electronic device.

[0047] In one possible implementation, the hybrid memory is powered off when the electronic device is off.

[0048] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, which includes at least one of real-time trained artificial intelligence (AI) data, models, and training results.

[0049] In one possible implementation, the first address is either a physical address or a logical address; if the first address is a logical address, the storage controller is also used to convert the logical address into a physical address.

[0050] Sixthly, embodiments of this application provide a data read / write method applied to a hybrid memory, the hybrid memory including a memory controller, a volatile memory medium, and a non-volatile memory medium; the physical address segment of the volatile memory medium is partially the same as the physical address segment of the non-volatile memory medium; the method includes: the memory controller receiving a read / write instruction from a processor, the read / write instruction carrying a first address; when the first address corresponds to the storage space of both the non-volatile memory medium and the volatile memory medium, if the processor's clock frequency is greater than the highest read / write frequency of the non-volatile memory medium, the memory controller writes data to the storage space of the volatile memory medium or reads data from the storage space of the volatile memory medium. If the processor's clock frequency is less than or equal to the highest read / write frequency of the non-volatile storage medium, the storage controller writes data to or reads data from the storage space of the non-volatile storage medium. If the first address corresponds to either the non-volatile storage medium or the storage space of the volatile storage medium, and if the first address corresponds to the storage space of the volatile storage medium, the storage controller writes data to or reads data from the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller writes data to or reads data from the storage space of the non-volatile storage medium.

[0051] In one possible implementation, if the processor's clock frequency is greater than the maximum read / write frequency of the non-volatile storage medium, the storage controller is also used to write data written to the storage space of the volatile storage medium to the storage space of the non-volatile storage medium; if the processor's clock frequency is less than or equal to the maximum read / write frequency of the non-volatile storage medium, the storage controller is also used to write data written to the storage space of the non-volatile storage medium to the storage space of the volatile storage medium.

[0052] In one possible implementation, the hybrid memory further includes at least one of a bus, a substrate, a package housing, and a bus interface; wherein the memory controller, volatile memory medium, and non-volatile memory medium are integrated on the substrate, the volatile memory medium and non-volatile memory medium are connected via a bus, the memory controller, volatile memory medium, non-volatile memory medium, bus, and substrate are packaged inside the package housing, and the package housing 006 presents a bus interface to the outside, the bus interface being used to connect to the processor.

[0053] In one possible implementation, the volatile storage medium includes at least one of Double Data Rate (DDR) memory, DDR2, DDR3, DDR4, High Bandwidth Memory (HBM), Dynamic Random Access Memory (DRAM), or 3D Super DRAM; the non-volatile storage medium includes at least one of Single-Level Storage Flash Memory (SLC-NAND), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PCRAM), 3D-Xpoint storage medium, or 3D-SLC NAND flash memory.

[0054] In one possible implementation, hybrid memory is installed as RAM in an electronic device.

[0055] In one possible implementation, the hybrid memory is powered off when the electronic device is off.

[0056] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, which includes at least one of real-time trained artificial intelligence (AI) data, models, and training results.

[0057] In one possible implementation, the first address is either a physical address or a logical address; if the first address is a logical address, the storage controller is also used to convert the logical address into a physical address.

[0058] In a seventh aspect, embodiments of this application provide an electronic device, including a processor, a hybrid memory, and a bus, wherein the processor and the hybrid memory are interconnected via the bus, and the hybrid memory includes a memory controller, a volatile memory medium, and a non-volatile memory medium; wherein the hybrid memory is used to store computer program code, the computer program code including computer instructions; when the computer instructions are executed by the processor, the processor and the hybrid memory cause the processor and the hybrid memory to perform any of the methods provided in the third to fifth aspects above.

[0059] Eighthly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform any of the methods provided in the third to fifth aspects above.

[0060] Ninthly, embodiments of this application provide a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the methods provided in the third to fifth aspects above.

[0061] In a tenth aspect, embodiments of this application provide a chip system including a processor and potentially a memory, for implementing any of the methods provided in the third to fifth aspects above. The chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0062] Figure 1 This is a schematic diagram of the structure of a hybrid memory provided in an embodiment of this application;

[0063] Figure 2 A schematic diagram of signal interaction provided in an embodiment of this application;

[0064] Figure 3 A schematic diagram of signal interaction provided in an embodiment of this application;

[0065] Figure 4 A cross-sectional view and a three-dimensional structural view of a hybrid memory provided in this application embodiment;

[0066] Figure 5 A schematic diagram of the physical address segment of a hybrid memory provided in an embodiment of this application;

[0067] Figure 6 A schematic diagram of the physical address segment of another hybrid memory provided in an embodiment of this application;

[0068] Figure 7 A schematic diagram of the physical address segment of another hybrid memory provided in an embodiment of this application;

[0069] Figure 8 A schematic diagram of the physical address segment of another hybrid memory provided in an embodiment of this application;

[0070] Figure 9 A schematic diagram of the physical address segment of a hybrid memory provided in an embodiment of this application;

[0071] Figure 10 A schematic diagram of the physical address segment of a hybrid memory provided in an embodiment of this application;

[0072] Figure 11 A schematic diagram of the physical address segment of a hybrid memory provided in an embodiment of this application;

[0073] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0074] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. In the description of this application, unless otherwise stated, "at least one" refers to one or more, and "more than one" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0075] Currently, the RAM commonly used for fast data access is Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM). Due to semiconductor leakage, DDR-SDRAM needs to constantly refresh the stored data (i.e., periodically rewrite the data), resulting in high power consumption. When the system suddenly loses power, its stored content is lost. Storage, on the other hand, is slow at processing data. When the system needs to write data to Storage, it typically encounters long delays and waiting times. For example, a SyncWrite command for critical data can cause a sudden drop in Storage's input / output (I / O) performance.

[0076] This application provides a hybrid memory (also known as heterogeneous memory or hybrid heterogeneous memory, which is not limited herein) that can be used flexibly as a memory device. It can improve the read / write performance of the operating system (OS) and also enhance the performance of databases using the hybrid memory as the storage medium. Furthermore, it ensures that fast-accessed data is not lost when power is off, allowing power to be cut off immediately after writing, thus saving power.

[0077] like Figure 1As shown, this application embodiment provides a hybrid memory 100. The hybrid memory 100 may include a memory controller 001, a volatile memory medium 002, a non-volatile memory medium 003, a bus 004, a substrate 005, a package 006, and a bus interface 007. The volatile memory medium 002 and the non-volatile memory medium 003 can be connected to the memory controller 001. The memory controller 001, the volatile memory medium 002, and the non-volatile memory medium 003 can be integrated on the substrate 005. The volatile memory medium 002 and the non-volatile memory medium 003 can be connected via the bus 004. The memory controller 001, the volatile memory medium 002 and non-volatile memory medium 003, the bus 004, and the substrate 005 can be packaged inside the package 006, and the package 006 can expose the bus interface 007 externally.

[0078] Volatile storage media can include DDR memory (DDR), DDR2, DDR3, DDR4, high-bandwidth memory (HBM), dynamic random access memory (DRAM), and 3D super DRAM. For example, a volatile storage medium can be HBM with a width of 512 bits and a capacity of 1GB.

[0079] Non-volatile storage media can be, for example, single-layer storage flash memory / single-cell flash memory SLC-NAND, magnetic random access memory (MRAM), resistive random access memory (RRAM), phase-change random access memory (PCRAM), 3D-Xpoint storage media, or 3D-SLC NAND flash memory, etc.

[0080] The hybrid memory 100 can be packaged in various ways, such as flip package, ball grid array (BGA) package, or wafer level chip scale package (WLCSP).

[0081] The bus interface 007 exposed by the package housing 006 can be a single interface. For example, it can be a DDR4 interface conforming to the Joint Electron Device Engineering Council (JEDEC) specification. Alternatively, the bus interface 007 exposed by the package housing 006 can include multiple (two or more) interfaces. For example, it can include two DDR4 interfaces conforming to the JEDEC specification.

[0082] The aforementioned hybrid memory can be incorporated into electronic devices and used as the device's main memory, meaning program data can be stored in the hybrid memory during runtime. The electronic device also includes a processor (e.g., a system-on-chip (SoC)). The SoC can act as a host device, and the hybrid memory as a slave device. The SoC can write data to or read data from the hybrid memory.

[0083] The SoC and hybrid memory can be connected via one or more of the following interfaces: DDR5, HBM DDR, or PCIe Gen5x4. This means that the bus connection between the SoC and hybrid memory offers a wide range of options and combinations.

[0084] like Figure 2 As shown, when the SoC needs to read data from the hybrid memory, it can send a read command to the memory controller 001. The read command includes a first address. After receiving the read command, the memory controller 001 determines the memory space corresponding to the first address and reads data from that memory space. The first address can be a first physical address or a first logical address. If the first address is a first physical address, after receiving the read command, the memory controller 001 directly addresses the volatile or non-volatile memory medium based on the first physical address to determine the memory space corresponding to the first physical address and reads the first data from that memory space. If the first address is a first logical address, after receiving the read command, the memory controller 001 determines the first physical address based on the first logical address, then addresses the volatile or non-volatile memory medium based on the first physical address to determine the memory space corresponding to the first physical address and reads the first data from that memory space. Then, the memory controller 001 sends the first data to the SoC.

[0085] like Figure 3As shown, when the SoC needs to write data to the hybrid memory, the SoC can send a write command to the memory controller 001. The write command includes a second address and the data to be written. After receiving the write command, the memory controller 001 determines the memory space corresponding to the second address and writes the data to be written to that memory space. The second address can be a second physical address or a second logical address. If the second address is a second physical address, after receiving the write command, the memory controller 001 directly addresses the volatile or non-volatile memory medium based on the second physical address to determine the memory space corresponding to the second physical address and writes the data to be written to the memory space corresponding to the second physical address. If the second address is a second logical address, after receiving the read command, the memory controller 001 determines the second physical address based on the second logical address, then addresses the volatile or non-volatile memory medium based on the second physical address to determine the memory space corresponding to the second physical address and reads the second data from the memory space corresponding to the second physical address. Optionally, the memory controller 001 can send a response message to the SoC to indicate that the write operation has been completed.

[0086] Figure 4 (a) in the figure shows a cross-sectional view of the hybrid memory. Figure 4 (b) shows a three-dimensional structural diagram of the hybrid memory. Figure 4 In (a), there are a substrate 501, internal interconnects 502, a volatile memory media group 503 (a volatile memory media group may include multiple volatile memory media, which may be referred to as a volatile memory media group), a non-volatile memory media group 504 (a non-volatile memory media group may include multiple non-volatile memory media, which may be referred to as a non-volatile memory media group), a memory controller 505, a housing 506, BGA pads 507, and a bus interface 508. Figure 4 (b) includes a substrate 501, a volatile memory medium group 503, a non-volatile memory medium group 504, and a BGA pad 507.

[0087] The substrate 501 can be equipped with a volatile memory media assembly 503 and a non-volatile memory media assembly 504. The volatile memory media assembly 503 can be connected to the BGA pads 507 via internal interconnects 502. The non-volatile memory media assembly 504 can be connected to the BGA pads 507 via internal interconnects 502. The memory controller 505 can be connected to the substrate 501 via pads 507.

[0088] For example, the thickness of substrate 501 can be 0.15 mm. Volatile memory media group 503 can include four (4pcs) MicronDDR4 chips using a 1Alphanm process node. Each MicronDDR4 chip can have a memory size of 8Gb (i.e., 1GB). The bonding lines (i.e., internal interconnects 502) between the MicronDDR4 chips can be gold wires. Non-volatile memory media group 504 can include four (4pcs) GlobalFoundry MRAM chips using a 28nm process node, each GlobalFoundry MRAM chip having a memory size of 1Gb. The bonding lines (i.e., internal interconnects 502) between the non-volatile memory media can be gold wires. Memory controller 505 is responsible for communicating with the HOST device (e.g., SoC) and managing both volatile memory media group 503 and non-volatile memory media group 504. The storage space size of the hybrid memory can include the sum of the storage space size of the volatile storage media group 503 (32Gb, i.e., 4GB) and the storage space size of the non-volatile storage media group 504 (4Gb, i.e., 1GB). The storage controller 505 can be a custom controller developed based on an application-specific integrated chip (ASIC) at a 22nm process node. The housing 506 can be made of plastic and can be labeled with the device model. The BGA pads 507 can have a pitch of 0.45mm. The hybrid memory may also include a power module, glue, and filler, etc. Figure 4 Not shown in the diagram. After the hybrid memory is packaged, it can be tested for package level on an automated test equipment (ATE) machine to ensure package quality.

[0089] It should be noted that when electronic devices use hybrid memory as their main memory, the volatile storage media within the hybrid memory can support high-speed data processing, achieving high read and write performance. The non-volatile storage media within the hybrid memory exhibits high performance and low power consumption at lower frequencies. Therefore, using hybrid memory can improve the read and write performance of electronic devices while reducing power consumption, thus meeting the basic demands of low power consumption and high performance in the market for electronic devices.

[0090] Furthermore, traditional memory (e.g., RAM) cannot be completely powered off in the screen-off state, otherwise data in the memory will be lost. The data in the non-volatile storage medium group of the hybrid memory provided in this application embodiment is not lost. Useful data can be stored in the non-volatile storage medium group, allowing the electronic device to be completely powered off in the screen-off state, significantly reducing power consumption. The screen-off state can also be called the screen-off state, where the electronic device may not display any information or may display limited information (e.g., current time, date, etc.). Moreover, with traditional memory, data is lost when power is off. Upon the next power-on, running programs need to be imported into memory for processing before the system can boot. When the hybrid memory is powered off, the data in the non-volatile storage medium group of the hybrid memory is not lost. Running programs can be stored in the non-volatile storage medium group, allowing for quick restoration of running programs upon the next power-on, further reducing standby power consumption and improving startup performance.

[0091] The hybrid memory described above can employ different address allocation modes. These modes can include parallel mode, shadow mode, and hybrid mode. The parallel mode, shadow mode, and hybrid mode are explained below.

[0092] In parallel mode, the physical address segments corresponding to volatile and non-volatile memory media do not overlap (are different). When the SoC accesses hybrid memory, it can address both volatile and non-volatile memory media separately.

[0093] In parallel mode, the storage space size of volatile and non-volatile storage media can be equal or unequal. For example, the number of physical addresses corresponding to the volatile storage media can be equal to the number of physical addresses corresponding to the non-volatile storage media. Figure 5 As shown, volatile and non-volatile storage media can correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x4; physical address segment 2 includes 0x5-0x8. Alternatively, the number of physical addresses corresponding to volatile storage media can be greater than the number of physical addresses corresponding to non-volatile storage media. For example... Figure 7 As shown, volatile and non-volatile storage media can correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x5; physical address segment 2 includes 0x6-0x8. This application does not impose limitations. Alternatively, the number of physical addresses corresponding to the volatile storage medium can be less than the number of physical addresses corresponding to the non-volatile storage medium. Figure 6As shown, volatile and non-volatile storage media can correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x3; physical address segment 2 includes 0x4-0x8.

[0094] In parallel mode, data in the non-volatile storage medium is not lost after the hybrid memory is powered off and then powered on again. For some preset data types, such as real-time trained artificial intelligence (AI) data, models (patterns), and training results, the preset data can be written to the non-volatile storage medium of the hybrid memory (e.g., FastNVM). This data, stored in FastNVM, can be accessed at any time, and is not lost even if the system is powered off, eliminating the need for recalculation. Compared to existing technologies, which require recalculating preset data after power-on, leading to power consumption, or reading preset data from slow storage, resulting in inefficiency, the SoC can directly read preset data from the hybrid memory (which serves as main memory), taking significantly less time than recalculation or reading from slow storage.

[0095] Parallel-mode hybrid memory is simple to implement in hardware, has a simple internal design, is easier to implement, and has a lower cost.

[0096] In shadow mode, the physical address ranges of volatile and non-volatile storage media are the same (overlapping). That is, the same physical address can point to either volatile or non-volatile storage media. In shadow mode, the sizes of volatile and non-volatile storage media are equal. That is, the number of physical addresses corresponding to the volatile storage media is equal to the number of physical addresses corresponding to the non-volatile storage media. For example, ... Figure 8 As shown, volatile and non-volatile storage media can correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x4; physical address segment 2 also includes 0x1-0x4.

[0097] When the address allocation mode is shadow mode, the hybrid memory can implement multiple data storage modes through the memory controller, including power / performance auto balance mode and data shadow mode. As shown in Table 1, power / performance auto balance mode and data shadow mode can be configured through the mode register (MR).

[0098] Table 1

[0099] mode register Data storage mode Power-on default 1 Automatic power consumption performance balancing mode √ 0 Data Shadow Mode

[0100] After power-on initialization, hybrid memory can default to a certain mode. For example, it can be defined that hybrid memory defaults to data shadow mode after power-on. Alternatively, it can default to automatic power / performance balancing mode. Table 1 shows that hybrid memory defaults to automatic power / performance balancing mode after power-on.

[0101] In automatic power / performance balancing mode: When the SoC is at a high clock speed (i.e., the CPU clock speed is higher than the maximum read / write frequency of the non-volatile memory), data is written to the volatile memory to meet the requirements of fast operation because the maximum read / write frequency of the non-volatile memory is lower than the clock speed (i.e., the non-volatile memory processes data slower than the processor). When the SoC's clock speed decreases, the maximum read / write frequency of the non-volatile memory is greater than or equal to the clock speed, meaning the non-volatile memory can process data at the same speed as the processor. Therefore, data can be written to the non-volatile memory to achieve lower power consumption. At this time, the volatile memory can enter an ultra-low power state to reduce power consumption. The above process can be completed by the hybrid memory's memory controller, eliminating the need for the SoC to write data to two different types of memory sub-cells, reducing the load on the SoC and improving its processing performance.

[0102] In data shadow mode, when the SoC is operating at a high clock frequency, data is first written to volatile memory, and then the memory controller automatically transfers the data to a lower-speed non-volatile memory. When the system is operating at a low speed range that the non-volatile memory can handle, data is first written to non-volatile memory, and then the memory controller automatically transfers the data to volatile memory. This process can be completed by the hybrid memory's memory controller without requiring SoC processing, reducing the load on the SoC and improving its processing performance.

[0103] In data shadow mode, when the hybrid memory loses power and then is powered on again, the data on the volatile storage medium of the hybrid memory is lost, but the data on the non-volatile storage medium is retained. Since the data recorded in the volatile storage medium and the non-volatile storage medium is the same, the data is not actually lost, effectively avoiding data loss.

[0104] In hybrid mode, some physical address segments of the hybrid memory can point to both volatile and non-volatile storage media; while other physical address segments point to only one type of storage medium. As shown in Table 2, the physical addresses corresponding to volatile storage media and the physical addresses corresponding to non-volatile storage media can be combined in various ways. For example, combinations can include combination 1, combination 2, and combination 3.

[0105] Table 2

[0106]

[0107] It's important to note that independent addresses can be accessed directly. Overlapping addresses, however, require configuration via a mode register. In other words, the memory controller determines how to access overlapping addresses. For example, access can be performed in automatic power / performance balancing mode or data shadow mode. This ensures both data processing speed and prevents data loss.

[0108] The number of overlapping addresses can be flexibly set based on the amount of important data that the electronic device needs to process (such as user profile training data, key context information, and real-time AI training data). If the electronic device needs to process a large amount of important data, more overlapping addresses can be set to ensure the processing speed of important data and prevent the loss of important data. If the electronic device needs to process a small amount of important data, fewer overlapping addresses can be set to avoid wasting storage space.

[0109] For example, as shown in Table 3, when the combination method is Combination 1, both the volatile storage medium and the non-volatile storage medium have a portion of independent addresses, and there is also some overlap in addresses. The number of independent addresses included in the volatile storage medium and the number of independent addresses included in the non-volatile storage medium can be the same or different, and this application does not impose any limitation.

[0110] Table 3

[0111]

[0112]

[0113] For example, such as Figure 9As shown, volatile and non-volatile storage media can correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x4. Physical address segment 1 includes independent addresses and overlapping addresses; independent addresses include 0x1-0x2; overlapping addresses include 0x3-0x4. Physical address segment 2 includes 0x3-0x6. Physical address segment 2 includes independent addresses and overlapping addresses; independent addresses include 0x5-0x6; overlapping addresses include 0x3-0x4. Of course, the number of independent addresses included in physical address segment 1 and physical address segment 2 can be different, and this application does not limit this.

[0114] Combination 1 is suitable for complex multi-core electronic devices such as mobile phones and tablets. When the CPU of an electronic device operates at a high clock frequency, it can read and write data in storage space (e.g., 4–8 GB) indicated by independent addresses on volatile storage media to meet the needs of rapid data processing. Important data (such as user profile training data, key context information, and real-time AI training data) can be stored in storage space indicated by overlapping addresses (e.g., 128 MB) to achieve the effects of not losing data after power failure, not requiring retraining, and rapid recovery. Boot code for the boot phase can be stored in storage space (e.g., 128 MB) indicated by independent addresses on non-volatile storage media to achieve rapid startup.

[0115] For example, as shown in Table 4, when the combination method is combination 2, only the volatile storage medium has a portion of independent addresses, while the non-volatile storage medium and a portion of the volatile storage medium have completely overlapping addresses.

[0116] Table 4

[0117]

[0118] For example, such as Figure 10 As shown, volatile and non-volatile storage media can correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x6. Physical address segment 1 includes independent addresses and overlapping addresses. Independent addresses include 0x1-0x2 and 0x5-0x6; overlapping addresses include 0x3-0x4. Physical address segment 2 includes 0x3-0x4. Physical address segment 2 only includes overlapping addresses, i.e., 0x3-0x4.

[0119] Combination 2 is also suitable for complex multi-core electronic devices such as mobile phones and tablets. Furthermore, the manufacturing cost of using Combination 2 with hybrid memory is lower than that of using Combination 1. Because non-volatile memory media does not have independent addresses, the boot code during the boot phase needs to be stored in memory space indicated by overlapping addresses. This means that the volatile memory media needs to be in a ready state when booting the electronic device, increasing its current consumption. However, compared to the operating state that electronic devices spend most of their daily use in, this additional power consumption is negligible, while the benefit of reduced chip cost outweighs the cost.

[0120] For example, as shown in Table 5, when the combination method is combination 3, the non-volatile storage medium has a portion of independent addresses, and a portion of the addresses of the non-volatile storage medium and the volatile storage medium completely overlap.

[0121] Table 5

[0122]

[0123] For example, such as Figure 11 As shown, volatile and non-volatile storage media can correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x2. Physical address segment 1 only includes overlapping addresses, i.e., 0x1-0x2. Physical address segment 2 includes independent addresses and overlapping addresses. Independent addresses include 0x3-0x4 and 0x5-0x6; overlapping addresses include 0x1-0x2.

[0124] Combination 3 is suitable for wearable devices, IoT devices, etc. The processors in wearable devices and IoT devices typically have a lower clock speed than the maximum read / write frequency of non-volatile storage media. Therefore, most data can be read and written in the storage space indicated by a separate address on the non-volatile storage medium (e.g., 256MB). Data requiring high-speed processing (e.g., real-time training data for speech recognition) can be processed in the storage space indicated by an overlapping address (e.g., 128MB), that is, within the storage space of volatile storage media, to achieve the effects of not losing data when power is off, not needing to repeat training, and fast recovery. The processed results can be stored in non-volatile memory to avoid loss.

[0125] In hybrid mode, when the hybrid memory loses power and then gains power again, the data in the physical address segments of the non-volatile storage medium is retained. If a separate volatile storage address segment exists, the data from before power-on is lost.

[0126] Hybrid mode allows volatile and non-volatile storage media to reuse physical addresses according to actual needs, making it more flexible and convenient.

[0127] In addition, the SoC can use software to use the parallel mode hybrid memory as shadow mode or hybrid mode according to actual needs, which is not limited in this application.

[0128] This application also provides an electronic device that can be equipped with the above-mentioned hybrid memory. The electronic device can be, for example, a mobile phone, tablet computer, desktop computer, laptop computer, ultra-mobile personal computer (UMPC), handheld computer, netbook, personal digital assistant (PDA), etc.

[0129] For example, such as Figure 12 The following is an example illustration of the structure of an electronic device (e.g., a mobile phone) provided in the embodiments of this application. The electronic device 200 may include: a processor 210, an external memory interface 220, a hybrid memory (i.e., a hybrid type memory) 221, a universal serial bus (USB) interface 230, a charging management module 240, a power management module 241, a battery 242, antenna 1, antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headphone jack 270D, a sensor module 280, buttons 290, a motor 291, an indicator 292, a camera 293, a display screen 294, and a subscriber identification module (SIM) card interface 295, etc.

[0130] The aforementioned sensor module 280 may include sensors such as pressure sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, distance sensors, proximity sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, and bone conduction sensors.

[0131] It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device 200. In other embodiments, the electronic device 200 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0132] Processor 210 may include one or more processing units, such as application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, memory, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0133] The controller can be the nerve center and command center of the electronic device 200. The controller can generate operation control signals according to the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0134] The processor 210 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 210 is a cache memory. This memory can store instructions or data that the processor 210 has just used or that are used repeatedly. If the processor 210 needs to use the instruction or data again, it can directly retrieve it from the memory. This avoids repeated accesses, reduces the waiting time of the processor 210, and thus improves the efficiency of the system.

[0135] In some embodiments, the processor 210 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0136] It is understood that the interface connection relationships between the modules illustrated in this embodiment are merely illustrative and do not constitute a structural limitation on the electronic device 200. In other embodiments, the electronic device 200 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0137] The charging management module 240 receives charging input from a charger, which can be a wireless charger or a wired charger. While charging the battery 242, the charging management module 240 can also supply power to the electronic device via the power management module 241.

[0138] The power management module 241 connects the battery 242, the charging management module 240, and the processor 210. The power management module 241 receives input from the battery 242 and / or the charging management module 240, and supplies power to the processor 210, hybrid memory 221, external memory, display 294, camera 293, and wireless communication module 260, etc. In some embodiments, the power management module 241 and the charging management module 240 may also be housed in the same device.

[0139] The wireless communication function of electronic device 200 can be implemented through antenna 1, antenna 2, mobile communication module 250, wireless communication module 260, modem processor, and baseband processor. In some embodiments, antenna 1 of electronic device 200 is coupled to mobile communication module 250, and antenna 2 is coupled to wireless communication module 260, enabling electronic device 200 to communicate with networks and other devices through wireless communication technology.

[0140] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 200 can be used to cover one or more communication frequency bands. Different antennas can also be multiplexed to improve antenna utilization. For example, antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with a tuning switch.

[0141] The mobile communication module 250 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the electronic device 200. The mobile communication module 250 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 250 can receive electromagnetic waves via antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation.

[0142] The mobile communication module 250 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via the antenna 1. In some embodiments, at least some functional modules of the mobile communication module 250 can be housed in the processor 210. In some embodiments, at least some functional modules of the mobile communication module 250 and at least some modules of the processor 210 can be housed in the same device.

[0143] The wireless communication module 260 can provide solutions for wireless communication applications on electronic devices 200, including WLAN (such as wireless fidelity, Wi-Fi) networks, Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) technology, etc.

[0144] The wireless communication module 260 can be one or more devices integrating at least one communication processing module. The wireless communication module 260 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signal, and sends the processed signal to processor 210. The wireless communication module 260 can also receive signals to be transmitted from processor 210, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.

[0145] Electronic device 200 implements display functions through a GPU, a display screen 294, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 210 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0146] The display screen 294 is used to display images, videos, etc. The display screen 294 includes a display panel.

[0147] The electronic device 200 can implement its shooting function through an ISP, a camera 293, a video codec, a GPU, a display 294, and an application processor. The ISP is used to process the data fed back by the camera 293. The camera 293 is used to capture still images or videos. In some embodiments, the electronic device 200 may include one or N cameras 293, where N is a positive integer greater than 1.

[0148] The external storage interface 220 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 200. The external memory card communicates with the processor 210 through the external storage interface 220 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0149] The hybrid memory 221 can be used to store computer executable program code, which includes instructions. The processor 210 executes various functional applications and data processing of the electronic device 200 by running the instructions stored in the hybrid memory 221. For example, in this embodiment, the processor 210 can execute instructions stored in the hybrid memory 221, which may include a program storage area and a data storage area.

[0150] The program storage area can store the operating system, at least one application program required for a function (such as sound playback, image playback, etc.). The data storage area can store data created during the use of the electronic device 200 (such as audio data, phonebook, etc.). Furthermore, the hybrid memory 221 can include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0151] Electronic device 200 can implement audio functions such as music playback and recording through audio module 270, speaker 270A, receiver 270B, microphone 270C, headphone jack 270D, and application processor.

[0152] Buttons 290 include a power button, volume buttons, etc. Buttons 290 can be mechanical buttons or touch-sensitive buttons. Motor 291 can generate vibration alerts. Motor 291 can be used for incoming call vibration alerts or for touch vibration feedback. Indicator 292 can be an indicator light, used to indicate charging status, battery level changes, messages, missed calls, notifications, etc. SIM card interface 295 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 295 to achieve contact and separation with the electronic device 200. The electronic device 200 can support one or N SIM card interfaces, where N is a positive integer greater than 1. SIM card interface 295 can support Nano SIM cards, Micro SIM cards, SIM cards, etc.

[0153] It is understandable that the aforementioned mobile phone 100 may have more than Figure 12 The more or fewer components shown can be combined into two or more components, or they can have different component configurations. Figure 12 The various components shown can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing or application-specific integrated circuits.

[0154] This embodiment also provides a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device performs the aforementioned method steps to implement the methods described in the above embodiments.

[0155] This embodiment also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the methods described in the above embodiments.

[0156] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component, or module. The apparatus may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the apparatus is running, the processor may execute the computer execution instructions stored in the memory to cause the chip to execute the methods in the above-described method embodiments.

[0157] In this embodiment, the electronic device, computer storage medium, computer program product or chip are all used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding method provided above, and will not be repeated here.

[0158] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0159] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0160] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0161] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0162] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), RAM, magnetic disks, or optical disks.

[0163] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A hybrid memory, used in electronic devices, characterized in that, The hybrid memory includes a memory controller, a volatile memory medium, and a non-volatile memory medium; The physical address segment of the volatile storage medium is different from the physical address segment of the non-volatile storage medium; The storage controller is configured to receive read / write instructions from the processor, the read / write instructions carrying a first address; If the first address corresponds to the storage space of the volatile storage medium, the storage controller is used to write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; If the first address corresponds to the storage space of the non-volatile storage medium, the storage controller is used to write data to the storage space of the non-volatile storage medium or read data from the storage space of the non-volatile storage medium.

2. A hybrid memory, used in electronic devices, characterized in that, The hybrid memory includes a memory controller, a volatile memory medium, and a non-volatile memory medium; The physical address segment of the volatile storage medium is the same as the physical address segment of the non-volatile storage medium; The storage controller receives read / write instructions from the processor, the read / write instructions carrying a first address; If the processor's clock frequency is greater than the highest read / write frequency of the non-volatile storage medium, the storage controller is used to write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium. If the processor's clock frequency is less than or equal to the highest read / write frequency of the non-volatile storage medium, the storage controller is used to write data to or read data from the storage space of the non-volatile storage medium.

3. A hybrid memory, used in electronic devices, characterized in that, The hybrid memory includes a memory controller, a volatile memory medium, and a non-volatile memory medium; the physical address segment of the volatile memory medium is the same as the physical address segment of the non-volatile memory medium. The storage controller receives read / write instructions from the processor, the read / write instructions carrying a first address; When the first address corresponds to both the non-volatile storage medium and the storage space of the volatile storage medium, if the processor's clock frequency is greater than the highest read / write frequency of the non-volatile storage medium, the storage controller is used to write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium. If the processor's clock frequency is less than or equal to the highest read / write frequency of the non-volatile storage medium, the storage controller is used to write data into the storage space of the non-volatile storage medium or read data from the storage space of the non-volatile storage medium. When the first address corresponds to the non-volatile storage medium or the storage space of the volatile storage medium, if the first address corresponds to the storage space of the volatile storage medium, the storage controller is used to write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium. If the first address corresponds to the storage space of the non-volatile storage medium, the storage controller is used to write data to the storage space of the non-volatile storage medium or read data from the storage space of the non-volatile storage medium.

4. The hybrid memory according to claim 2 or 3, characterized in that, If the processor's clock frequency is greater than the highest read / write frequency of the non-volatile storage medium, the storage controller is further configured to write the data written to the storage space of the volatile storage medium into the storage space of the non-volatile storage medium. If the processor's clock frequency is less than or equal to the highest read / write frequency of the non-volatile storage medium, the storage controller is further configured to write data written to the storage space of the non-volatile storage medium into the storage space of the volatile storage medium.

5. The hybrid memory according to any one of claims 1-4, characterized in that, The hybrid memory further includes at least one of a bus, a substrate, a package housing, and a bus interface; The memory controller, the volatile memory medium, and the non-volatile memory medium are integrated on the substrate. The volatile memory medium and the non-volatile memory medium are connected via the bus. The memory controller, the volatile memory medium, the non-volatile memory medium, the bus, and the substrate are encapsulated inside the package housing. The package housing exposes the bus interface to the outside, and the bus interface is used to connect to the processor.

6. The hybrid memory according to any one of claims 1-5, characterized in that, The volatile storage medium includes dynamic random access memory (DRAM), and the DRAM includes at least one of double data rate (DDR) memory, DDR2, DDR3, DDR4, high bandwidth memory (HBM), or 3D super DRAM. The non-volatile storage medium includes at least one of single-layer storage flash memory (SLC-NAND), magnetic random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), 3D-Xpoint storage medium, or 3D-SLC NAND flash memory.

7. The hybrid memory according to any one of claims 1-6, characterized in that, The hybrid memory is installed as memory in the electronic device.

8. The hybrid memory according to claim 7, characterized in that, When the electronic device is turned off, the hybrid memory is powered down.

9. The hybrid memory according to any one of claims 1-8, characterized in that, The non-volatile storage medium is used to store data of a preset type, which includes at least one of real-time trained artificial intelligence (AI) data, models, and training results.

10. The hybrid memory according to any one of claims 1-9, characterized in that, The first address is a physical address or a logical address; If the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.

11. A data read / write method, characterized in that, It is applied to hybrid memory, which includes a memory controller, a volatile memory medium, and a non-volatile memory medium; The physical address segment of the volatile storage medium is different from the physical address segment of the non-volatile storage medium; the method includes: The storage controller receives read / write instructions from the processor, the read / write instructions carrying a first address; If the first address corresponds to the storage space of the volatile storage medium, the storage controller writes data to the storage space of the volatile storage medium or reads data from the storage space of the volatile storage medium; If the first address corresponds to the storage space of the non-volatile storage medium, the storage controller writes data to the storage space of the non-volatile storage medium or reads data from the storage space of the non-volatile storage medium.

12. A data read / write method, characterized in that, It is applied to hybrid memory, which includes a memory controller, a volatile memory medium, and a non-volatile memory medium; The physical address segment of the volatile storage medium is the same as the physical address segment of the non-volatile storage medium; the method includes: The storage controller receives read / write instructions from the processor, the read / write instructions carrying a first address; If the processor's clock frequency is greater than the maximum read / write frequency of the non-volatile storage medium, the storage controller will write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium. If the processor's clock frequency is less than or equal to the highest read / write frequency of the non-volatile storage medium, the storage controller will write data to or read data from the storage space of the non-volatile storage medium.

13. A data read / write method, characterized in that, It is applied to hybrid memory, which includes a memory controller, a volatile memory medium, and a non-volatile memory medium; The physical address segment of the volatile storage medium is the same as the physical address segment portion of the non-volatile storage medium; the method includes: The storage controller receives read / write instructions from the processor, the read / write instructions carrying a first address; When the first address corresponds to both the non-volatile storage medium and the storage space of the volatile storage medium, if the processor's clock frequency is greater than the maximum read / write frequency of the non-volatile storage medium, the storage controller writes data to or reads data from the storage space of the volatile storage medium; if the processor's clock frequency is less than or equal to the maximum read / write frequency of the non-volatile storage medium, the storage controller writes data to or reads data from the storage space of the non-volatile storage medium. When the first address corresponds to the non-volatile storage medium or the storage space of the volatile storage medium, if the first address corresponds to the storage space of the volatile storage medium, the storage controller writes data to the storage space of the volatile storage medium or reads data from the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller writes data to the storage space of the non-volatile storage medium or reads data from the storage space of the non-volatile storage medium.

14. The method according to claim 12 or 13, characterized in that, If the processor's clock speed is greater than the highest read / write frequency of the non-volatile storage medium, the method further includes: The storage controller writes the data written to the storage space of the volatile storage medium to the storage space of the non-volatile storage medium; If the processor's clock speed is less than or equal to the highest read / write frequency of the non-volatile storage medium, the method further includes: The storage controller writes the data to be written to the storage space of the non-volatile storage medium into the storage space of the volatile storage medium.

15. The method according to any one of claims 11-14, characterized in that, The hybrid memory further includes at least one of a bus, a substrate, a package housing, and a bus interface; The memory controller, the volatile memory medium, and the non-volatile memory medium are integrated on the substrate. The volatile memory medium and the non-volatile memory medium are connected via the bus. The memory controller, the volatile memory medium, the non-volatile memory medium, the bus, and the substrate are encapsulated inside the package housing. The package housing exposes the bus interface to the outside, and the bus interface is used to connect to the processor.

16. The method according to any one of claims 11-15, characterized in that, The volatile storage medium includes dynamic random access memory (DRAM), and the DRAM includes at least one of double data rate (DDR) memory, DDR2, DDR3, DDR4, high bandwidth memory (HBM), or 3D super DRAM. The non-volatile storage medium includes at least one of single-layer storage flash memory (SLC-NAND), magnetic random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), 3D-Xpoint storage medium, or 3D-SLC NAND flash memory.

17. The method according to any one of claims 11-16, characterized in that, The hybrid memory is installed as memory in the electronic device.

18. The method according to claim 17, characterized in that, When the electronic device is turned off, the hybrid memory is powered down.

19. The method according to any one of claims 11-18, characterized in that, The non-volatile storage medium is used to store data of a preset type, which includes at least one of real-time trained artificial intelligence (AI) data, models, and training results.

20. The method according to any one of claims 11-19, characterized in that, The first address is a physical address or a logical address; If the first address is a logical address, the method further includes: The storage controller also translates the logical address into a physical address.

21. An electronic device, characterized in that, It includes a processor, a hybrid memory, and a bus, wherein the processor and the hybrid memory are interconnected via the bus, and the hybrid memory includes a memory controller, a volatile memory medium, and a non-volatile memory medium; The hybrid memory is used to store computer program code, which includes computer instructions; when the computer instructions are executed by the processor, the processor and the hybrid memory perform the method as described in any one of claims 11-20.

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