Storage controller, storage system, and chip
By introducing write channel read/write controller, read channel read/write controller, and memory read/write arbitrator into the storage controller and system, the shortcomings of traditional FIFO memory in terms of uncertain write order and temporary data processing are solved, achieving efficient storage resource utilization and hardware simplification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUZHOU ROCKCHIP SEMICON
- Filing Date
- 2024-11-27
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional FIFO memory cannot meet the data storage needs of uncertain write order in some application scenarios, cannot support the operation of temporarily writing data and then reading and writing it back, and requires multiple memory, resulting in resource waste.
A storage controller, storage system, and chip are provided. Through a write channel read/write controller, a read channel read/write controller, and a memory read/write arbitrator, independent control and arbitration of the write channel and read channel are achieved, supporting data write, read, and release operations and optimizing storage space utilization.
It improves storage efficiency, reduces memory capacity overhead, simplifies hardware architecture design, and enhances memory flexibility and resource utilization.
Smart Images
Figure CN122111903A_ABST
Abstract
Description
Technical Field
[0001] This disclosure pertains to the field of memory technology, and in particular relates to memory controllers, memory systems, and chips. Background Technology
[0002] In a FIFO (First In First Out) memory, input and output are operated through a set of ports. The write channel is used to write data into the FIFO, and the read channel is used to read data from the FIFO. Whenever data enters the FIFO through the write channel, the write pointer is automatically updated to mark the next writable position. This update process is transmitted to the read channel through a synchronization mechanism, ensuring that the reading end can know the current data status in the FIFO. This synchronization mechanism ensures that the data structure within the FIFO always remains ordered, and that the reading end will not read data that has not yet been written. Furthermore, the read pointer is also automatically updated after data is successfully read, marking the next readable data position, thus maintaining the smooth operation of the entire data flow. Summary of the Invention
[0003] This disclosure provides a storage controller, a storage system, and a chip for storing data from different channels on the same storage medium.
[0004] In a first aspect, embodiments of this disclosure provide a storage controller. The storage controller includes: a write channel read / write controller configured to control read access, write access, and release operations on at least one write channel of the memory; a read channel read / write controller configured to control read access, write access, and release operations on at least one read channel of the memory; and a memory read / write arbitrator configured to arbitrate read accesses and write accesses on the write channels and the read channels.
[0005] In one implementation of the first aspect, the write channel read / write controller is configured to: determine whether read access, write access, and release operations on the write channel are allowed; if read access or write access on the write channel is allowed, send the allowed read access or write access to the memory read / write arbitrator; and if release operation on the write channel is allowed, synchronize the length of the releasable storage space corresponding to the write channel to the read channel read / write controller.
[0006] In one implementation of the first aspect, the write channel read / write controller is configured to: allow access to the write channel if the amount of storage space required to access the write channel is less than or equal to the amount of remaining writable space of the write channel; otherwise, prohibit access to the write channel.
[0007] In one implementation of the first aspect, each of the write channels supports both data write operations and data read operations.
[0008] In one implementation of the first aspect, the write channel read / write controller is configured to: maintain a write base address pointer and determine the storage location of data in the memory based on the write base address pointer and an offset.
[0009] In one implementation of the first aspect, the write channel read / write controller is configured to: record the total length of data that has been processed by each write channel, and determine the length of the releasable storage space corresponding to each write channel based on the total length of data that has been processed by each write channel.
[0010] In one implementation of the first aspect, the read channel read / write controller is configured to: determine whether read access, write access, and release operations on the read channel are allowed; if read access or write access on the read channel is allowed, send the allowed read access or write access to the memory read / write arbitrator; and if release operation on the read channel is allowed, synchronize the length of the releasable storage space corresponding to the read channel to the write channel read / write controller.
[0011] In one implementation of the first aspect, the read channel read / write controller is configured to: allow access to the read channel if the amount of storage space required to access the read channel is less than or equal to the amount of remaining readable space of the read channel; otherwise, prohibit access to the read channel.
[0012] In one implementation of the first aspect, each of the read channels supports data read operations and data write-back operations.
[0013] In one implementation of the first aspect, the read channel read / write controller is configured to: maintain a read base address pointer and determine the storage location of data in the memory based on the read base address pointer and an offset.
[0014] In one implementation of the first aspect, the read channel read / write controller is configured to: record the total length of data that has been processed by each read channel, and determine the length of the releasable storage space corresponding to each read channel based on the total length of data that has been processed by each read channel.
[0015] In one implementation of the first aspect, the memory read / write arbitrator is configured to: arbitrate read and write accesses to entropy decoding information of a video bitstream; arbitrate read and write accesses to coding tree units of a video image; or arbitrate read and write accesses to command information required for data computation in a pipeline.
[0016] In one implementation of the first aspect, the memory includes a single-port memory, a dual-port memory, or a register.
[0017] Secondly, embodiments of this disclosure provide a storage system. The storage system includes a write channel read / write controller, a read channel read / write controller, a memory read / write arbitrator, and a memory, wherein: the memory includes at least one write channel and at least one read channel; the write channel read / write controller is configured to control read access, write access, and release operations on the write channel; the read channel read / write controller is configured to control read access, write access, and release operations on the read channel; and the memory read / write arbitrator is configured to arbitrate read access and write access to the write channel and the read channel.
[0018] Thirdly, this disclosure provides a chip. The chip includes a memory controller and a memory system provided in this disclosure.
[0019] The storage controller provided in this embodiment can store data from different channels in the same memory, which is beneficial for improving storage efficiency, reducing memory capacity overhead, and simplifying hardware structure design.
[0020] In the embodiments of this disclosure, the channels of the memory are independent of each other, and there are no restrictions on the writing order and sequence, which provides high flexibility. Attached Figure Description
[0021] Figure 1 The diagram shown is a schematic representation of the structure of a storage system provided in an embodiment of this disclosure.
[0022] Figure 2 and Figure 3 The diagram shown is a schematic representation of the storage space of the memory in an embodiment of this disclosure.
[0023] Figure 4 The diagram shown illustrates an implementation environment of the storage system provided in this disclosure.
[0024] Figure 5 This is a schematic diagram of a traditional assembly line design.
[0025] Figure 6 The diagram shown illustrates an implementation environment of the storage system provided in this disclosure.
[0026] Figure 7 The diagram shown illustrates an implementation environment of the storage system provided in this disclosure. Detailed Implementation
[0027] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0028] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. Therefore, the illustrations only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0029] In this disclosure, the terms "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0030] In this disclosure, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.
[0031] Traditional FIFO memory designs struggle to meet the demands of certain application scenarios. For instance, in some scenarios, it's necessary to write n sets of data, but the order of these n sets is uncertain. In this case, a traditional FIFO memory cannot store all n sets of data. Here, n is a positive integer. Another example is the need to temporarily write data to memory before reading and processing it, and then write the processed data back to memory. Since the write channel of a traditional FIFO memory does not support read operations, it cannot meet the data storage requirements in these scenarios. Furthermore, for the same data that needs to be sent to m functional modules, a traditional FIFO implementation would require m memory modules, leading to a waste of storage resources. Here, m is an integer greater than 1.
[0032] To address at least the aforementioned problems, this disclosure provides a storage controller, a storage system, and a chip. The technical solutions in this disclosure will now be described in detail with reference to the accompanying drawings.
[0033] Figure 1 This is a schematic diagram illustrating the structure of a storage controller provided according to an embodiment of the present disclosure. For example... Figure 1 As shown, memory 2 includes write channels WCH0 to WCHN and read channels RCH0 to RCHM, where N and M are both integers. Each write channel can support data write operations and data read operations. Each read channel can support data read operations and data write-back operations. Memory controller 1 is used to store the data content of write channels WCH0 to WCHN of memory 2, and to read the data content of read channels RCH0 to RCHM of memory 2.
[0034] The memory controller 1 includes a write channel read / write controller 11, a read channel read / write controller 12, and a memory read / write arbitrator 13. The write channel read / write controller 11 is configured to control read access, write access, and release operations on write channels WCH0 to WCHN of the memory 2. The read channel read / write controller 12 is configured to control read access, write access, and release operations on read channels RCH0 to RCHM of the memory 2. The memory read / write arbitrator 13 is configured to arbitrate read and write accesses on the write and read channels.
[0035] In some implementations, the write channel read / write controller 11 is configured to determine whether read access, write access, and release operations on each write channel are permitted. If a read or write access to a write channel is permitted, the write channel read / write controller 11 sends the permitted read or write access to the memory read / write arbitrator 13 for read / write arbitration. If a release operation on a write channel is permitted, the write channel read / write controller 11 synchronizes the length of the releasable memory space corresponding to the write channel to the read channel read / write controller 12.
[0036] In some implementations, the write channel read / write controller 11 is configured to: if the amount of storage space required for accessing the write channel is less than or equal to the remaining writable space of the write channel, allow access to the write channel; otherwise, prohibit access to the write channel.
[0037] In some implementations, the write channel read / write controller 11 is configured to maintain a write base address pointer and confirm the storage location of data in the memory according to the write base address pointer and the offset.
[0038] In some implementations, the write channel read / write controller 11 is configured to record the total length of data that has been processed by each write channel and determine the length of the storage space that can be released corresponding to the write channel according to the total length of data that has been processed by each write channel.
[0039] Specifically, for a segment of storage space, the read channel can access the storage space only after all write channels have released the space of this storage space. For example, when the number of write channels is 2, one write channel has released a total of 10 storage spaces, and the other write channel has released a total of 15 storage spaces. At this time, the read channel can only read the content of 10 storage spaces. Based on this, in the embodiments of the present disclosure, after a write channel has processed a certain amount of data, it will inform the write channel read / write controller 11 of the length of the data that has been processed currently. After all write channels have completed the processing of a certain amount of data, the write channel read / write controller 11 can synchronize the length of the storage space corresponding to this part of the data amount as the length of the storage space that can be released corresponding to the write channel to the read channel read / write controller 12, and the read channel can perform a read operation on this storage space.
[0040] Figure 2 FIG. is an example diagram showing the storage space of the memory 2 in the write channel access scenario, where total_depth represents the storage space depth of the memory 2, w_space2full represents the remaining writable space of the write channel, wptr_base represents the write base address pointer, and wch_wr_offset represents the offset.
[0041] Exemplarily, for the i-th write channel WCHi, when w_space2full[i] < wch_wr_offset[i], access to the storage space by this write channel WCHi is prohibited, and at this time, the response signal of the write channel access request is 0. When w_space2full[i] ≥ wch_wr_offset[i], access to the storage space by this write channel WCHi is allowed, and at this time, the response signal of the write channel access request is 1. Where w_space2full[i] and wch_wr_offset[i] respectively represent the remaining writable space of the write channel WCHi and the amount of storage space required for accessing the write channel WCHi.
[0042] For example, upon reset, w_space2full[i] can be configured as the total_depth of the storage space in memory 2. After a write channel release operation, w_space2full[i] can be configured as the difference between w_space2full[i] and wch_release_len[i], where wch_release_len[i] represents the length of data that WCHi has processed. After read channel synchronization is complete, w_space2full[i] can be configured as the sum of w_space2full[i] and r_sync_release_len, where r_sync_release_len represents the length of the releasable storage space corresponding to the read channel synchronized by the read channel read / write controller 12 to the write channel read / write controller 11.
[0043] For example, the update method for the write base address pointer wptr_base[i] includes: incrementing wch_release_len[i] after data is written to the write channel WCHi. If wptr_base[i] is greater than the storage space depth total_depth of memory 2, then the write base address pointer wptr_base[i] is subtracted from the storage space depth total_depth and a new round of pointer loop is entered, as specifically implemented as follows:
[0044] wptr_base_tmp[i]=wptr_base[i]+wch_release_len[i];
[0045] wptr_base[i]=wptr_base_tmp[i]≥total_depth? wptr_base_tmp[i]-total_depth:wptr_base_tmp[i].
[0046] For example, the write channel read / write controller 11 can synchronize the minimum total length of the data that has been processed by each write channel as the length of the releaseable storage space w_sync_release_len corresponding to the write channel to the read channel read / write controller 12.
[0047] For example, upon reset, the total length of processed data in the write channel WCHi is w_release_total_len[i] = 0. After releasing the write channel, w_release_total_len[i] can be configured as the sum of w_release_total_len[i] and wch_release_len[i]. After the write channel synchronization is complete, w_release_total_len[i] can be configured as the difference between w_release_total_len[i] and w_sync_release_len. w_sync_release_len represents the length of the releasable storage space corresponding to the write channel synchronized by the write channel read / write controller 11 to the read channel read / write controller 12. Based on this, w_sync_release_len = min{w_release_total_len[i]} can be calculated, where i = 0, 1, ..., N, and min is the function for finding the minimum value.
[0048] For example, if there are two channels, denoted as channel 0 and channel 1, channel 0 and channel 1 release 20 and 5 storage spaces respectively, then w_release_total_len[0] = 20 and w_release_total_len[1] = 5. w_sync_release_len = min{w_release_total_len[0], w_release_total_len[1]} = 5, indicating that 5 storage spaces can be released for read operations. After these 5 storage spaces are released, w_release_total_len[0] is updated to w_release_total_len[0] - w_sync_release_len = 15, and w_release_total_len[1] is updated to w_release_total_len[1] - w_sync_release_len = 0. At this point, it is necessary to wait for channel 1 to finish processing the data before further storage space can be released.
[0049] In some implementations, the read channel read / write controller 12 is configured to determine whether read access, write access, and release operations on each read channel are permitted. If a read access or write access to a read channel is permitted, the read channel read / write controller 12 sends the permitted read access or write access to the memory read / write arbitrator 13. If a release operation on a read channel is permitted, the read channel read / write controller 12 synchronizes the length of the releasable memory space corresponding to the read channel to the write channel read / write controller 11.
[0050] In some implementations, the read channel read / write controller 12 is configured to: if the amount of storage space required for accessing the read channel is less than or equal to the remaining readable space of the read channel, allow access to the read channel; otherwise, prohibit access to the read channel.
[0051] In some implementations, the read channel read / write controller 12 is configured to maintain a read base address pointer, and the read channel read / write controller 12 determines the storage location of data in the memory according to the read base address pointer and the offset.
[0052] In some implementations, the read channel read / write controller 12 is configured to record the total length of data that has been processed by each read channel, and determine the length of the storage space that can be released corresponding to the read channel according to the total length of data that has been processed by each read channel.
[0053] Specifically, for a segment of storage space, after all read channels have released the space of this storage space, the write channel can access this storage space. For example, when the number of read channels is 2, one read channel has released a total of 10 storage spaces, and the other read channel has released a total of 15 storage spaces. At this time, the write channel can only write to 10 storage spaces. Based on this, in the embodiments of the present disclosure, after the read channel has processed a certain amount of data, it will inform the read channel read / write controller 12 of the length of the data that has been processed currently. After all read channels have completed the processing of a certain amount of data, the read channel read / write controller 12 can synchronize the length of the storage space corresponding to this part of the data volume to the write channel read / write controller 11 as the length of the storage space that can be released corresponding to the read channel, and the write channel can perform a write operation on this storage space.
[0054] Figure 3 FIG. is an example diagram showing the storage space of the memory 2 in the read channel access scenario, where r_space2empty represents the remaining readable space of the read channel, rptr_base represents the read base address pointer, and rch_wr_offset represents the offset.
[0055] Exemplarily, for the i-th read channel RCHIi, when r_space2empty[i] < rch_wr_offset[i], access to the storage space by this read channel RCHi is prohibited, and at this time, the response signal of the read channel access request is 0. When r_space2empty[i] ≥ rch_rd_offset[i], this read channel RCHi is allowed to access the storage space, and at this time, the response signal of the read channel request is 1. Where r_space2empty[i] and rch_wr_offset[i] respectively represent the remaining readable space of the read channel RCHi and the amount of storage space required for accessing the read channel RCHi.
[0056] For example, r_space2empty[i] can be configured to 0 upon reset. After a read channel release operation, r_space2empty[i] can be configured as the difference between r_space2empty[i] and rch_release_len[i], where rch_release_len[i] represents the length of data that RCHi has processed. After write channel synchronization is complete, r_space2empty[i] can be configured as the sum of r_space2empty[i] and w_sync_release_len, where w_sync_release_len represents the length of the releaseable storage space corresponding to the write channel synchronized by the write channel read / write controller 11 to the read channel read / write controller 12.
[0057] For example, the update method for the read base address pointer rptr_base[i] includes: incrementing rch_release_len[i] after reading data from the read channel RCHi. If rptr_base[i] is greater than the storage space depth total_depth of memory 2, then rptr_base[i] is subtracted from the storage space depth total_depth and a new round of pointer loop is entered, as specifically implemented as follows:
[0058] rptr_base_tmp[i]=rptr_base[i]+rch_release_len[i];
[0059] rptr_base[i]=rptr_base_tmp[i]>=total_depth? rptr_base_tmp[i]-total_depth:rptr_base_tmp[i].
[0060] For example, the read channel read / write controller 12 can synchronize the minimum total length of the data that has been processed by each read channel as the length of the releaseable storage space r_sync_release_len corresponding to the read channel to the write channel read / write controller 11.
[0061] For example, upon reset, the total length of data already processed in the read channel RCHi is r_release_total_len[i] = 0. After releasing the read channel, r_release_total_len[i] can be configured as the sum of r_release_total_len[i] and rch_release_len[i]. After the read channel synchronization is complete, r_release_total_len[i] can be configured as the difference between r_release_total_len[i] and r_sync_release_len. r_sync_release_len represents the length of the releasable storage space corresponding to the read channel synchronized by the read channel read / write controller 12 to the write channel read / write controller 11. Based on this, r_sync_release_len = min{r_release_total_len[i]} can be calculated, where i = 0, 1, ..., M, and min is the function for finding the minimum value.
[0062] In some implementations, the read and write accesses of the write channel and read channel of memory 2 are arbitrated by the memory read / write arbitrator 2 and then accessed in a time-division multiplexing manner.
[0063] In some implementations, memory 2 includes storage media such as single-port memory, dual-port memory, or registers.
[0064] This disclosure also provides a storage system. The storage system includes a write channel read / write controller, a read channel read / write controller, a memory read / write arbitrator, and a memory. The memory includes at least one write channel and at least one read channel. The write channel read / write controller is configured to control read access, write access, and release operations on the write channel. The read channel read / write controller is configured to control read access, write access, and release operations on the read channel. The memory read / write arbitrator is configured to arbitrate read and write accesses to the write and read channels.
[0065] In some implementations, the memory read / write arbitrator is configured to arbitrate read and write accesses to entropy decoding information of the video bitstream, or read and write accesses to coding tree units of the video image, or read and write accesses to command information required for data computation in the pipeline.
[0066] Figure 4 This is a schematic diagram illustrating an implementation environment of a storage system according to an embodiment of the present disclosure. For example, as shown... Figure 4As shown, the storage system provided in this embodiment can be applied to the video decoding process. During video decoding, the entropy decoding (CADAC) module performs syntax parsing on the received video bitstream and sends the parsed syntax information to the inter-frame prediction module, the intra-frame prediction module, and the inverse quantization and inverse transform (IQIT) module. In this application scenario, the memory may include one write channel and three read channels. Only after the inter-frame prediction module, the intra-frame prediction module, and the inverse quantization and inverse transform module have read and consumed all the syntax information from the storage system can the storage space occupied by this syntax information be returned to the entropy decoding module for continued use.
[0067] For example, based on the storage system provided in this disclosure, the syntax information sent by the entropy decoding module to the intra-frame prediction module, inter-frame prediction module, and inverse quantization and inverse transform module only needs to be stored once. All three modules can read this single copy of syntax information. If a standard FIFO memory is used, three identical copies of the syntax information need to be stored, one for each module. In comparison, the storage system provided in this disclosure reduces the demand for storage resources, which is beneficial for reducing chip area.
[0068] For example, the storage system provided in this disclosure can be applied to command (cmd) synchronization processing in pipeline design. In pipeline design, if only some pipeline stages need to use cmd information, or some pipeline stages use the same cmd information. Figure 5 This is a schematic diagram illustrating a traditional assembly line design. (Example) Figure 5 As shown, if a traditional design is used, the cmd and data need to be synchronized and stamped, which requires allocating storage resources for each pipeline stage.
[0069] Figure 6 This is a schematic diagram illustrating an implementation environment of a storage system according to an embodiment of the present disclosure. For example... Figure 6 As shown, based on the storage system provided in this embodiment, only one read channel needs to be configured at the location where cmd is required to obtain cmd information, without the need to allocate storage resources for each pipeline stage.
[0070] For example, in a 20-stage pipeline scenario, if only some stages require CMD information, or if some stages use the same CMD information, a traditional design would require 20 CMD storage resources. Based on the storage system provided in this disclosure, only one read channel needs to be configured at the location where CMD is required to obtain the CMD information, and the memory depth in the storage system can be configured to 2. In comparison, the storage system provided in this disclosure reduces the demand for storage resources, which is beneficial for reducing chip area.
[0071] Figure 7 This is a schematic diagram illustrating an implementation environment of a storage system according to an embodiment of the present disclosure. For example, please refer to... Figure 7 The storage system provided in this embodiment can be applied to H.265 video decoding, reconstruction, and filtering design. Assuming a ctu = 64x64 image block size, the storage space can store a maximum of 4 ctus, with each storage space storing one 4x4 data block, requiring a storage space depth of 1024. For ease of understanding, it can be assumed that residual data is written first, and the space is released only after an entire 64x64 ctu is written.
[0072] The memory in the storage system can include predictive data write channels and residual data write channels. After residual data is written to a CTU block, the residual data write channel can free up 64 write spaces. The predictive data write channel reads the 64x64 residual data from this CTU, reconstructs it with the predictive data, and then writes it back to this 64x64 space area, freeing up another 64 write spaces. Since both write channels have freed up a CTU space area, this portion of the CTU data can be accessed by the read channels.
[0073] The memory in the storage system can contain three read channels. The de-blocking filtering module uses read channel 0 to read the CTU, performs de-blocking filtering, and writes the filtering result back to the CTU's storage space. The SAO filtering module uses read channel 1 to read the CTU, performs SAO filtering, and writes the filtering result back to the CTU's storage space. Then, the storage space of this CTU is released. The DDR write control module reads the CTU data that has undergone all filtering, writes it to the DDR, and releases the storage space of this CTU. At this point, all three read channels have completed the data processing for the first CTU and released the space, which can then be released to the write channels to continue writing new CTUs.
[0074] This disclosure also provides a chip that includes a memory controller or memory system provided in this disclosure.
[0075] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).
[0076] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.
[0077] In the embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0078] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0079] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0080] In the above embodiments, the functions of each functional unit can be implemented, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this disclosure is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.
[0081] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.
[0082] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.
Claims
1. A storage controller, characterized in that, include: A write channel read / write controller is configured to control read access, write access, and release operations on at least one write channel of the memory; A read channel read / write controller is configured to control read access, write access, and release operations on at least one read channel of the memory; as well as A memory read / write arbitrator is configured to arbitrate read and write accesses to the write channel and the read channel.
2. The storage controller according to claim 1, characterized in that, The write channel read / write controller is configured as follows: Determine whether read access, write access, and release operations on the write channel are allowed; If a read or write access to the write channel is permitted, the permitted read or write access is sent to the memory read / write arbitrator. as well as If the release operation of the write channel is allowed, the length of the releasable storage space corresponding to the write channel is synchronized to the read channel read / write controller.
3. The storage controller according to claim 2, characterized in that, The write channel read / write controller is configured as follows: If the amount of storage space required to access the write channel is less than or equal to the amount of remaining writable space in the write channel, then access to the write channel is allowed; otherwise, access to the write channel is prohibited.
4. The storage controller according to claim 2, characterized in that, Each of the write channels supports both data writing and data reading operations.
5. The storage controller according to claim 2, characterized in that, The write channel read / write controller is configured as follows: Maintain a write base address pointer and determine the storage location of data in the memory based on the write base address pointer and the offset.
6. The storage controller according to claim 2, characterized in that, The write channel read / write controller is configured as follows: Record the total length of data that has been processed by each write channel, and determine the length of the releasable storage space corresponding to each write channel based on the total length of data that has been processed by each write channel.
7. The storage controller according to claim 1, characterized in that, The read channel read / write controller is configured as follows: Determine whether read access, write access, and release operations on the read channel are allowed; If a read or write access to the read channel is permitted, the permitted read or write access is sent to the memory read / write arbitrator. as well as If the release operation of the read channel is allowed, the length of the releasable storage space corresponding to the read channel is synchronized to the write channel read / write controller.
8. The storage controller according to claim 7, characterized in that, The read channel read / write controller is configured as follows: If the amount of storage space required to access the read channel is less than or equal to the amount of remaining readable space in the read channel, then access to the read channel is allowed; otherwise, access to the read channel is prohibited.
9. The storage controller according to claim 7, characterized in that, Each of the aforementioned read channels supports data read operations and data write-back operations.
10. The storage controller according to claim 7, characterized in that, The read channel read / write controller is configured as follows: Maintain the read base address pointer and determine the storage location of the data in the memory based on the read base address pointer and the offset.
11. The storage controller according to claim 7, characterized in that, The read channel read / write controller is configured as follows: Record the total length of data that has been processed by each read channel, and determine the length of the releasable storage space corresponding to each read channel based on the total length of data that has been processed by each read channel.
12. The storage controller according to claim 1, characterized in that, The memory read / write arbitrator is configured as follows: Arbitrate read and write accesses to the entropy decoding information of the video bitstream; Arbitrate read and write accesses to coding tree units of video images; or Arbitrate read and write accesses to command information required for data computation in the pipeline.
13. The storage controller according to claim 1, characterized in that, The memory includes a single-port memory, a dual-port memory, or a register.
14. A storage system, characterized in that, The storage system includes a write channel read / write controller, a read channel read / write controller, a memory read / write arbitrator, and a memory, wherein: The memory includes at least one write channel and at least one read channel; The write channel read / write controller is configured to control read access, write access, and release operations on the write channel; The read channel read / write controller is configured to control read access, write access, and release operations on the read channel; and The memory read / write arbitrator is configured to arbitrate read and write accesses to the write channel and the read channel.
15. A chip, characterized in that, Includes the storage controller according to any one of claims 1 to 13 or the storage system according to claim 14.