Instruction processing method and device, computer equipment and storage medium

Abstract

Embodiments of the invention provide an instruction processing method and apparatus, a computer device and a storage medium. The method comprises the steps of obtaining a setting instruction and a vector calculation instruction from a preset instruction local memory or an instruction buffer; updating a preset shadow register according to the setting instruction to obtain a first update value; performing data recovery on the first update value by using a preset real register to obtain a second update value; and executing the vector calculation instruction according to the second update value. According to the method, the preset shadow register is used for speculative execution according to the instruction of the assembly line, an update value is obtained in advance, and when the instruction needing to be scoured is executed, the wrong update value is backed up and recovered by using the preset real register, so that the register values of the shadow register and the real register are kept consistent; therefore, the performance and the efficiency when the vector calculation instruction is executed are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to an instruction processing method and device, a computer device and a storage medium. BACKGROUND

[0002] The calculation of vectors has always been an important part of operations in various fields, and RISC-V also has a corresponding basic vector extension V extension. Before using V instructions, it is usually necessary to use VSET (set) instructions to set the vstart / vl / vtype register to configure the total length of the vector, as well as the length of the vector calculation and the vector data type, and then perform the corresponding vector instructions such as vector multiplication, vector addition, etc.

[0003] In the prior art, the related calculation of vectors is usually used in a way of flushing the pipeline, that is, the VSET instruction is first read in the instruction fetching stage, and after the instruction execution unit reads the VSET instruction, the flushing operation of the pipeline is performed to make the instruction fetching unit fetch instructions again and read the subsequent vector calculation instructions. However, this method will cause a large number of clock cycles to be wasted on resetting the pipeline instead of actually executing useful instructions. Especially in the case where VSET instructions and vector processing unit (VPU) instructions need to be frequently executed, this architecture causes the processor to spend most of the time on flushing operations of the processing pipeline instead of effectively executing instructions. This significantly reduces the overall performance of the processor when performing vector operations. SUMMARY

[0004] The present application provides an instruction processing method, device, equipment and storage medium, which aims to solve the technical problem of how to improve the performance and efficiency when executing vector calculation instructions.

[0005] In a first aspect of the present application, an instruction processing method is provided, which comprises: obtaining a setting instruction and a vector calculation instruction from a preset instruction local memory or instruction cache; updating a preset shadow register according to the setting instruction to obtain a first update value; recovering data of the first update value by using a preset real register to obtain a second update value; executing the vector calculation instruction according to the second update value.

[0006] In an optional embodiment of the present application, the step of updating the preset shadow register according to the setting instruction to obtain a first register value comprises: identifying and decoding the setting instruction through a preset pipeline stage to extract the address or identifier of the preset shadow register; Locate a target shadow register according to an address or an identifier of the shadow register; Calculate a current value of the setting instruction and write the current value of the setting instruction into the target shadow register to obtain the first update value.

[0007] In an optional embodiment of the present application, the step of recovering data of the first update value by using the preset real register to obtain a second update value comprises: recovering data of the preset shadow register by using the correct value in the preset real register to replace the first update value, obtaining a recovery value of the preset shadow register, and determining the recovery value of the shadow register as the second update value.

[0008] In an optional embodiment of the present application, the step of recovering data of the first update value by using the correct value in the real register to replace the first update value, obtaining a recovery value of the shadow register, and determining the recovery value of the shadow register as the second update value comprises: reading the correct value of the preset real register; recovering an error value in the preset shadow register according to the correct value of the preset real register to obtain a data-recovered preset shadow register; reading the recovery value from the preset shadow register and determining the recovery value as the second update value.

[0009] In an optional embodiment of the present application, before the step of recovering an error value in the preset shadow register according to the correct value of the preset real register to obtain a data-recovered preset shadow register, comprising: monitoring an execution state of a preset pipeline stage, and if it is detected that the execution state of the preset pipeline stage is an abnormal state, determining whether the setting instruction is an instruction that needs to be revoked due to the abnormal state; if the setting instruction is an instruction that needs to be revoked due to the abnormal state, determining that the current value of the preset shadow register is an error value.

[0010] In an optional embodiment of the present application, the step of executing the vector calculation instruction according to the second update value comprises: inputting the second update value into a preset vector decoder, combining the vector calculation instruction to perform a decoding operation, and obtaining decoding information of the vector calculation instruction; transmitting the decoding information to a preset vector processing unit through a preset pipeline stage transmission mechanism, and performing an operation of the vector calculation instruction by using the second update value.

[0011] In an optional embodiment of the present application, before the step of inputting the second update value into the preset vector decoder, combining the vector calculation instruction, and performing a decoding operation to obtain decoding information of the vector calculation instruction, the method comprises the following steps of: verifying whether the second update value is consistent with the correct value of the real register; if consistent, sending a state update signal to the preset pipeline stage; based on the state update signal, removing the pause state of the preset pipeline stage and obtaining an instruction address; based on the instruction address, inputting the second update value into the preset vector decoder to execute the vector calculation instruction.

[0012] A second aspect of an embodiment of the present application provides an instruction processing device, which comprises: an acquisition module, configured to acquire a setting instruction and a vector calculation instruction from a preset instruction local memory or an instruction cache; an update module, configured to update a preset shadow register according to the setting instruction to obtain a first update value; a recovery module, configured to perform data recovery on the first update value by using a preset real register to obtain a second update value; an execution module, configured to execute the vector calculation instruction according to the second update value.

[0013] A third aspect of an embodiment of the present application provides a computer device, which comprises a memory and a processor, the memory stores a computer program, and the processor implements the steps of the instruction processing method of any one of the above aspects when executing the computer program.

[0014] A fourth aspect of an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is characterized in that, when executed by a processor, the computer program implements the steps of the instruction processing method of any one of the above aspects. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the present application, constitute a part of the present application and illustrate the illustrative embodiments of the present application and their descriptions serve to explain the present application and do not constitute improper limitations on the present application. In the drawings: Figure 1 a flushing pipeline flowchart based on a multi-stage pipeline processor provided by an embodiment of the present application; Figure 2 a flowchart of the instruction processing method provided by the first embodiment of the present application; Figure 3 a flowchart of the instruction processing method provided by the second embodiment of the present application; Figure 4 A flow chart of an instruction processing method provided for a third embodiment of the present application; Figure 5 A brief flow chart provided for the instruction processing method of the present application; Figure 6 A flow chart of recovering the value of a real register from a shadow register provided for the instruction processing method of the present application; Figure 7 A structure diagram of an instruction processing method device provided for an embodiment of the present application; Figure 8 A structure diagram of a computer device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0016] In the process of implementing the present application, the inventors found that in the prior art, a multi-stage pipeline processor is usually used to perform a vector-related calculation in a flush pipeline manner, i.e., a setup instruction is first read in the instruction fetch stage, and after the instruction execution unit reads the setup instruction, a flush pipeline operation is performed to let the instruction fetch unit fetch instructions again and read subsequent vector calculation instructions.

[0017] In the architecture of a multi-stage pipeline processor, using a flush pipeline manner to use a setup instruction usually wastes a large number of clock cycles, as shown in Figure 1 Figure 1 A flush pipeline flow chart based on a multi-stage pipeline processor.

[0018] As can be seen from Figure 1 , the last-but-one stage of the multi-stage pipeline processor is where the registers exist, and after the setup instruction updates the registers, the vector calculation instruction is also in the execution part of the execution unit. However, the vector calculation unit needs to obtain the setup data from the decoding part of the execution unit and then send it to the vector processing unit to perform an execution operation, so the registers need to be flushed. However, all vector operation instructions need to use a setup instruction to set the vector-related registers before performing the operation. Taking a 5-stage pipeline processor in Figure 1 as an example, the flush pipeline cost is 4 cycles, and if a large number of setup instructions and vector calculation instructions are executed, a large number of processor clock cycles are spent on processing the flush pipeline, and very few instructions are actually executed, which greatly affects the vector operation performance of the processor.

[0019] ​To solve the above problems, the embodiment of the present application provides an instruction processing method, device, computer equipment and storage medium. The method comprises the following steps: obtaining a setting instruction and a vector calculation instruction from a preset instruction local memory or an instruction cache; updating a preset shadow register according to the setting instruction to obtain a first update value; performing data recovery on the first update value by using a preset real register to obtain a second update value; and executing the vector calculation instruction according to the second update value. The method uses the preset shadow register to obtain the update value in advance according to the instruction speculation execution of the pipeline. When the instruction that needs to be flushed is executed, the incorrect update value is backed up and recovered by using the preset real register, so that the values stored in the shadow register and the real register are consistent, thereby improving the performance and efficiency when the vector calculation instruction is executed.

[0020] The scheme in the embodiment of the present application can be implemented in various computer languages, such as object-oriented programming languages Java and interpreted scripting languages JavaScript.

[0021] In order to make the technical solutions and advantages in the embodiments of the present application clearer, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0022] The application environment of the instruction processing method provided by the embodiment of the present application is briefly described below: Please refer to Figure 2 In the first embodiment provided by the embodiment of the present application, the instruction processing method comprises steps S10-S40. Step S10, obtaining a setting instruction and a vector calculation instruction from a preset instruction local memory or an instruction cache; It should be noted that the setting (VSET) instruction is a special instruction used to configure the vector processing environment. It is usually used to initialize or adjust the key parameters of the vector register, so that the subsequent vector operation can be executed correctly.

[0023] The vector calculation instruction refers to the instruction set for directly operating the vector data, which depends on the vector environment configured in advance by the VSET instruction. The vector calculation instruction includes but is not limited to vector addition, vector subtraction, vector multiplication and vector division, etc.

[0024] Specifically, in the process of the preset multi-stage pipeline level in the instruction fetching stage, the instruction local memory or the instruction cache is sent a request for fetching instructions, and the instructions are fetched from the instruction local memory or the instruction cache based on the request for fetching instructions and are sent to the instruction decoder. Then, the type of each instruction is parsed by the instruction decoder, the setting instruction and the vector calculation instruction are determined, and the setting instruction and the vector calculation instruction are transmitted to the execution unit of the preset multi-stage pipeline level so as to participate in subsequent configuration of the vector register parameters.

[0025] In step S20, the preset shadow register is updated according to the setting instruction to obtain a first updated value. It should be noted that the shadow register is a special register designed in the embodiment and is usually used for temporarily storing or buffering the data of the real register.

[0026] The first updated value is a new value stored in the shadow register after the setting instruction (such as a VSET instruction) is executed. The value represents the latest change made to the configuration of the vector register according to the current setting instruction. Since there may be pipeline abnormal conditions (for example, a jump prediction failure), the value may be incorrect, and therefore the correct value in the real register needs to be used for recovery subsequently.

[0027] It can be understood that since the shadow register can be quickly updated without affecting the real register, the execution of step S20 can effectively reduce the possibility of pipeline flushing and improve the efficiency of the system.

[0028] In an available embodiment, step S20 can include steps S21-S23. In step S21, the preset shadow register address or identifier is extracted by identifying and decoding the setting instruction through the preset pipeline level. It should be noted that the preset pipeline level usually refers to a specific stage (for example, a decoding stage or an execution stage) in the processor pipeline responsible for instruction decoding or execution, which ensures that the processing of the setting instruction (such as a VSET) is synchronized with the execution of other instructions.

[0029] Specifically, first, in the instruction acquisition or decoding stage of the preset pipeline level, whether the instruction acquired in step S10 is a setting instruction is identified through the instruction opcode. For example, the instruction opcode of the setting instruction can be defined as 0x1A, which is distinguished from the instruction opcodes of other instructions (such as VADD and VMUL).

[0030] Then, the fields in the setting instruction are decoded to obtain the address or identifier of the shadow register that needs to be updated, and the new configuration value (such as vector length, data type) provided in the setting instruction. According to the decoding result, the identifier of the target shadow register is obtained. For example, if the shadow register group has 8 registers, the address range is 0x00 to 0x07, and the identifier SHADOW_REG_0 corresponds to the address 0x00.

[0031] Through the above steps, the setting instruction is processed at a specific stage of the pipeline to ensure that the update of the shadow register is seamlessly connected with the decoding and execution of the vector calculation instruction.

[0032] In step S22, the target shadow register is located according to the address or identifier of the shadow register. It should be noted that the shadow register is usually implemented in the form of a register file, which includes a plurality of register units, and each unit has a unique address or identifier. The target register is directly accessed through an address bus or a control signal.

[0033] Specifically, the address or identifier extracted in step S21 is used as a gating signal generated by an address decoder. For example, if the target address is 0x03, the fourth register in the shadow register group is gated. In addition, it is checked whether the target shadow register is occupied by other instructions or is in a protection state. If there is a conflict, the current operation is suspended or the priority problem is solved through an arbitration mechanism.

[0034] In step S23, the current value of the setting instruction is calculated, and the current value of the setting instruction is written into the target shadow register to obtain the first update value.

[0035] Specifically, if the setting instruction directly provides an immediate value, the value is directly used as the new configuration value. If the setting value needs to be based on the value of other registers, the data in the specified general-purpose register is read as the new value.

[0036] Then, the calculated new value is written to the target shadow register located in step S22 through a data bus. For example, if the target register address is 0x03, the new value is written to the register unit corresponding to the address. For example, if the target register address is 0x03, the new value is written to the register unit corresponding to the address, and the new value is used as the first update value.

[0037] Through the above steps, by introducing the shadow register, the update of the setting instruction can be directly written to the shadow register in the early stage of the pipeline, without waiting for the instruction to be submitted to the real register. This enables the vector calculation instruction to immediately use the latest configuration value for decoding and execution, avoiding performance loss due to pipeline flushing (such as jump prediction failure).

[0038] Step S30, data recovery of the first update value by using the preset real register to obtain a second update value; It should be noted that the real register is the authority value of the vector configuration stored in the processor, and its content is only updated after the instruction is successfully submitted. It serves as a backup of the shadow register to restore the error value of the shadow register to the correct value when a pipeline anomaly (such as jump prediction failure, pipeline flush) is detected.

[0039] The second update value is a new value obtained by restoring the error value of the shadow register by the correct value of the real register. This value ensures the correctness of the vector configuration, so that the subsequent instructions can be executed based on the reliable configuration.

[0040] It can be understood that since the shadow register is updated before the instruction is submitted, and the instruction for updating the shadow register may not be submitted at all due to the occurrence of pipeline flush, the updated value of the shadow register is incorrect. Therefore, step S30 is performed to recover the error value in the shadow register by the real register of the later stage pipeline.

[0041] In a possible implementation mode, step S30 can include step S31: Step S31, data recovery of the preset shadow register by using the correct value in the preset real register to replace the first update value, to obtain a recovery value of the preset shadow register, and to determine the recovery value of the shadow register as the second update value.

[0042] When the set instruction is not submitted due to pipeline anomaly (such as jump prediction failure, interruption, pipeline flush), the updated shadow register value (first update value) will become an error value, which may cause the subsequent vector instruction to be executed based on the error configuration.

[0043] Therefore, in the present embodiment, the correct value of the real register is used to cover the error value of the shadow register, to ensure the system state consistency, and to generate the second update value for the subsequent instruction.

[0044] In another possible implementation mode, step S31 can further include steps S311-S313: Step S311, reading the correct value of the preset real register; Specifically, the current stored vector configuration value (such as vector length, data type) in the real register is read. It should be noted that since the value of the real register is only updated after the instruction is successfully submitted, it is not affected by the unsubmitted instruction, and is always a valid value.

[0045] Step S312: Recover the erroneous value in the preset shadow register according to the correct value of the preset real register to obtain the preset shadow register after data recovery; The erroneous value in the shadow register is restored based on the correct value of the real register. That is, the correct value of the real register is used to overwrite the current erroneous value (first update value) of the shadow register, resulting in the shadow register after data recovery.

[0046] Step S313: Read the recovered value from the preset shadow register after data recovery, and determine the recovered value as the second update value. The correct recovered value is output through the shadow register after data recovery, and this recovered value is confirmed as the second updated value.

[0047] Through the above steps, the processor can efficiently utilize the collaborative working mechanism of shadow registers and real registers to quickly recover from misconfigurations caused by pipeline anomalies and ensure the continuity and correctness of vector operation instructions.

[0048] Step S40: Execute the vector calculation instruction based on the second updated value.

[0049] Understandably, since the restored value of the shadow register (i.e. the second updated value) has been verified and corrected by the correct value of the real register, ensuring the consistency and reliability of the vector configuration, executing step S40 can ensure that the system can seamlessly continue the vector operation task after the abnormal recovery.

[0050] In one feasible embodiment, step S40 may include steps S41 to S42: Step S41: Input the second updated value into the preset vector decoder, and perform a decoding operation in conjunction with the vector calculation instruction to obtain the decoding information of the vector calculation instruction; Specifically, after obtaining the second updated value (recovered value) output by the shadow register after data recovery in step S30, this second updated value is immediately transmitted to the vector decoder to participate in the decoding operation of the vector instruction, generating accurate decoding information. That is, the second updated value is used to parse information such as the operand range and data type of the vector calculation instruction. For example, if the second updated value indicates that the vector length is 256, the decoder will parse that the vector calculation instruction needs to process 256 elements. If the second updated value indicates that the data type is floating-point, the decoder will select the floating-point unit (FPU) for subsequent execution.

[0051] Step S42: The decoded information is transmitted to a preset vector processing unit through a preset pipeline-level transmission mechanism, and the vector calculation instruction is performed using the second update value.

[0052] It should be noted that pipelined transfer mechanisms refer to the hardware pathways and protocols for transferring data and control information between different stages of the processor pipeline. They typically include latches, buffers, bypass networks, and control signals.

[0053] Specifically, the decoded information (including the second update value) is sent to the vector processing unit without interruption through the pipeline execution stage via a preset pipeline-level transmission mechanism.

[0054] After receiving the decoded information, the vector processing unit determines the specific operation range and method based on the second update value (such as vector length and data type) in the decoded information. During vector computation, the number of iterations or the segmented processing range is determined based on the vector length. An appropriate computation unit is selected based on the data type. Data is loaded from the shadow register file based on the operand address.

[0055] By utilizing the collaborative working mechanism of shadow registers and real registers through the above embodiments, no pipeline flushing action can be generated. Vector instructions and set instructions are executed without interruption, and there is no pipeline flushing, thus avoiding the cost of pipeline flushing.

[0056] Please see Figure 3 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the second embodiment of this application to an instruction processing method. The instruction processing method provided in this application embodiment further includes the following steps A1-A2 before step S312: Step A1: Monitor the execution status of the preset pipeline level. If the execution status of the preset pipeline level is detected to be abnormal, determine whether the setting instruction is an abnormal instruction. Step A2: If the setting instruction is an abnormal instruction, then the current value of the preset shadow register is determined to be an error value.

[0057] Compared to the first embodiment, in this embodiment, by explicitly monitoring the pipeline status and determining the undo requirement of the set instruction, the affected shadow register can be identified more accurately, thereby reducing unnecessary recovery operations and improving the efficiency and flexibility of the system.

[0058] Specifically, firstly, the status of each stage of the pipeline is monitored in real time through hardware monitoring modules (such as pipeline state machines or anomaly detection units). Key states to be monitored include, but are not limited to, jump prediction failures, interrupt requests, and pipeline flushing requests. Furthermore, status registers are used to record the current operational status of multiple pipeline stages.

[0059] If a pipeline-level abnormal state is detected, query the instruction queue at the time of the abnormality to confirm whether there are any uncommitted configuration instructions, and determine whether the configuration instructions need to be revoked due to the abnormality.

[0060] If it is confirmed that the setting instruction needs to be revoked due to an error, the value updated by the instruction in the shadow register is marked as an "error value". Specifically, a flag (such as Error_Flag) is set in the shadow register file to indicate whether the current value is an error.

[0061] By using the methods described in the above embodiments, and by explicitly monitoring the pipeline status and determining the cancellation requirements of the setting instructions, the affected shadow registers can be identified more accurately, avoiding unnecessary recovery operations.

[0062] Please see Figure 4 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the third embodiment of this application to an instruction processing method. The instruction processing method provided in this application embodiment further includes the following steps B1-B4 before step S41: Step B1: Verify whether the second updated value is consistent with the correct value of the real register; Step B2: If they match, send a status update signal to the preset pipeline level. Step B3: Based on the status update signal, release the pause state of the preset pipeline level and obtain the instruction address; Step B4: Based on the instruction address, input the second update value into the preset vector decoder to execute the vector calculation instruction.

[0063] Compared to the first and second embodiments, in this embodiment, by adding a verification mechanism and a state update signal design, the reliability of the system and the continuity of the pipeline can be significantly improved.

[0064] Specifically, after the operation to restore the erroneous value of the shadow register is completed, a hardware comparator is used to verify whether the second updated value is consistent with the correct value of the real register, ensuring the accuracy of the restoration result.

[0065] If verification fails, the system logs an error or triggers a reset to prevent the spread of incorrect configurations.

[0066] If verification is successful, an explicit status update signal is sent to lift the pipeline-level pause, ensuring the system can quickly resume normal operation. After lifting the pause, the instruction address is quickly obtained to ensure seamless follow-up instructions and avoid performance loss due to waiting.

[0067] Finally, based on the obtained instruction address, the second update value is input into the vector decoder to generate decoding information.

[0068] By introducing a verification mechanism and a state update signal, the accuracy of the recovery operation is ensured and the pipeline pause state is quickly lifted through the above-described embodiments, thereby significantly improving the overall performance and fault tolerance of the processor.

[0069] For example, to help understand the implementation flow of the instruction processing method obtained by combining this embodiment with the above embodiment one, please refer to... Figure 5 , Figure 5 A simplified flowchart of an instruction processing method is provided, specifically: Based on the existing design, this embodiment designs a shadow register. The shadow register predicts the execution of pipeline instructions and obtains the latest value in advance. When an instruction that needs to be flushed is executed, the erroneous update value is backed up and restored using the real register to keep it consistent with the value of the real register.

[0070] like Figure 5 As shown, a shadow register is designed in the next stage of the decoder pipeline. When the set instruction arrives at the pipeline containing the shadow register, it updates the register. At this time, the vector computation instruction is being decoded in the decoder pipeline of the execution unit. The updated register value can be immediately sent to the decoder to participate in the decoding operation of the vector instruction. The decoded information of the vector computation instruction can be sent to the vector processing unit for vector operation without interruption. No pipeline flushing occurs. The vector computation instruction and the set instruction are executed without interruption, and there is no pipeline flushing, thus avoiding the pipeline flushing cost.

[0071] However, since the shadow register is updated before the instruction is committed, and the instruction that updates this shadow register may not be committed at all due to pipeline flushing, the update of the shadow register is incorrect. In this case, the value of the shadow register needs to be restored using the real register of the subsequent pipeline. Figure 5 As shown, Figure 6 A flowchart illustrating the process of restoring the value of the shadow register to the real register.

[0072] Depend on Figure 6As we can see, the shadow register has been modified by a set instruction, and the vector operation instruction is retrieving data from the shadow register. However, a pipeline flush occurs at this point. For example, if the set instruction was preceded by a jump instruction, and the jump prediction fails during execution, the pipeline needs to be flushed to redirect the instruction address. However, the next set instruction has already modified the shadow register. Therefore, the value of the shadow register used by subsequent vector instructions will be incorrect. The real register, on the other hand, is only updated by committed instructions and is always correct. When this happens, overwriting the shadow register with the real register restores the incorrectly updated shadow register to its correct value, allowing subsequent vector instructions to continue using the shadow register's value without error.

[0073] The above-described method not only improves performance by providing data for the arithmetic instructions in advance using the prediction mechanism of the preset shadow register, but also solves the problem of subsequent instruction execution errors caused by speculative execution errors that may occur due to the shadow register.

[0074] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0075] Please see Figure 7 One embodiment of this application provides an instruction processing apparatus, including: The acquisition module 10 is used to acquire setting instructions and vector calculation instructions from a preset instruction local memory or instruction cache; Update module 20 is used to update the preset shadow register according to the setting instruction to obtain the first update value; Recovery module 30 is used to recover data from the first updated value using a preset real register and obtain the second updated value; The execution module 40 is used to execute the vector calculation instruction according to the second updated value.

[0076] For specific limitations regarding the aforementioned instruction processing device, please refer to the limitations on the instruction processing method above, which will not be repeated here. Each module in the aforementioned instruction processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0077] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 8 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements one of the instruction processing methods described above. It includes: memory and a processor; the memory stores a computer program; and the processor executes the computer program to implement any step of the instruction processing method described above.

[0078] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, can perform any of the steps in the instruction processing method described above.

[0079] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0080] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0081] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0082] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0083] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0084] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An instruction processing method, characterized in that, The method includes: Retrieve setup instructions and vector calculation instructions from the preset instruction local memory or instruction cache; The preset shadow register is updated according to the setting instruction to obtain the first update value; The first updated value is recovered using a preset real register to obtain the second updated value; The vector calculation instruction is executed based on the second updated value.

2. The method as described in claim 1, characterized in that, The step of updating the preset shadow register according to the setting instruction to obtain the first register value includes: The preset pipeline level identifies and decodes the setting instructions, and extracts the address or identifier of the preset shadow register; Locate the target shadow register based on its address or identifier; Calculate the current value of the setting instruction and write the current value of the setting instruction into the target shadow register to obtain the first updated value.

3. The method as described in claim 1, characterized in that, The step of restoring the first updated value using a preset real register to obtain the second updated value includes: The preset shadow register is restored by using the correct value in the preset real register to replace the first update value, the restored value of the preset shadow register is obtained, and the restored value of the shadow register is determined as the second update value.

4. The method as described in claim 3, characterized in that, The step of restoring data to the shadow register using the correct value in the real register to replace the first update value, obtaining the restored value of the shadow register, and determining the restored value of the shadow register as the second update value includes: Read the correct value of the preset real register; The incorrect value in the preset shadow register is recovered based on the correct value of the preset real register to obtain the preset shadow register after data recovery; The recovered value is read from the preset shadow register after the data is recovered, and the recovered value is determined as the second update value.

5. The method as described in claim 4, characterized in that, Before the step of restoring the erroneous value in the preset shadow register based on the correct value of the preset real register to obtain the preset shadow register after data recovery, the following steps are included: Monitor the execution status of the preset pipeline level. If the execution status of the preset pipeline level is detected to be abnormal, determine whether the setting instruction is an abnormal instruction. If the setting instruction is an abnormal instruction, then the current value of the preset shadow register is determined to be an error value.

6. The method as described in claim 1, characterized in that, The step of executing the vector calculation instruction based on the second updated value includes: The second updated value is input into the preset vector decoder, and the vector calculation instruction is combined with it to perform a decoding operation to obtain the decoding information of the vector calculation instruction. The decoded information is transmitted to a preset vector processing unit through a preset pipeline-level transmission mechanism, and the vector calculation instruction is performed using the second update value.

7. The method as described in claim 6, characterized in that, Before the step of inputting the second updated value into the preset vector decoder and performing a decoding operation in conjunction with the vector calculation instruction to obtain the decoding information of the vector calculation instruction, the following steps are included: Verify whether the second updated value is consistent with the correct value of the actual register; If they match, a status update signal is sent to the preset pipeline level; Based on the status update signal, the pause state of the preset pipeline level is released and the instruction address is obtained; Based on the instruction address, the second update value is input into the preset vector decoder to execute the vector calculation instruction.

8. An instruction processing apparatus, characterized in that, The instruction processing device includes: The acquisition module is used to acquire setting instructions and vector calculation instructions from a preset instruction local memory or instruction cache; The update module is used to update the preset shadow register according to the setting instruction to obtain the first update value; The recovery module is used to recover the data of the first updated value using a preset real register and obtain the second updated value; An execution module is used to execute the vector calculation instruction based on the second updated value.

9. An instruction processing device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the instruction processing method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the instruction processing method as described in any one of claims 1 to 7.

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