A texture memory bank read access optimization system and optimization method

Abstract

The application provides a texture memory bank read access optimization system and optimization method, conflict detection is performed on generated 16-way texture addresses, texture addresses accessing the same texture block are composed into address groups, a plurality of address groups are obtained, a conflict flag of each address group and an effective texel mark bit in the group are generated, and an access request and the conflict flag are sent to a corresponding storage unit Bank in parallel according to each address group; when each storage unit Bank receives the access request, corresponding texture block data is returned, and a data assembly module reads corresponding texel data from the corresponding texture block data in parallel according to the effective texel mark bit in each address group. The application performs feature comparison conflict detection on texture addresses in parallel, groups the texture storage unit Bank, and then outputs in parallel, without preprocessing, and is not coupled with other parts in the texture unit, and is easy to implement; and the design mode of the pipeline is adopted, and the execution efficiency is high.

Description

Technical Field

[0001] This invention relates to the field of graphics processor technology, and more specifically, to a texture storage read access optimization system and optimization method. Background Technology

[0002] In real-time graphics rendering using GPUs (Graphics Processing Units), the texture cache is a key component for improving GPU texture data access performance. With the increasing demand for high-resolution, ultra-large-scale textures in graphics applications, the access to texture image data has become one of the main performance bottlenecks in GPU graphics rendering.

[0003] Traditional caching strategies are mostly based on the principle of spatiotemporal locality, dividing the texture storage into multiple banks according to the storage method of texture tiles, in order to improve the parallel reading of texture sampling. However, a texture tile may often contain multiple pixels, and simultaneous access to a texture tile by multiple channels will inevitably lead to storage read conflicts.

[0004] Currently, most GPUs use parallel sampling for texture sampling, distributing sampling addresses to multiple texture banks and achieving high-speed texture sampling through parallel access to these banks. However, due to the spatiotemporal locality of texture data, the potential address conflicts during parallel sampling have not been adequately addressed. This leads to memory access queue accumulation when texture address conflicts occur, causing latency. Traditional strategies increase the number of banks in the texture bank to improve the parallelism of the sampling process and increase the overall texture sampling rate, but this increases chip area and power consumption and does not fundamentally solve the texture memory address conflict problem.

[0005] Therefore, there is an urgent need for an efficient method to read texture storage that can resolve this conflict, in order to improve access locality, reduce latency, and thus improve overall rendering performance and energy efficiency. Summary of the Invention

[0006] This invention addresses the technical problems existing in the prior art by providing a texture storage read access optimization system and method, aiming to solve the conflicting access generated when reading the texture storage during texture parallel sampling, improve texture sampling efficiency, reduce circuit switching frequency, and reduce data read latency.

[0007] According to a first aspect of the present invention, a texture storage read access optimization system is provided, comprising a 4-way texture address generation unit, a 4-way video memory address generation unit, a conflict detection and Bank grouping unit, a storage unit Bank, and a data assembly module;

[0008] Each of the texture address generation units is used to generate four texture sampling relative addresses based on a texture sampling request task;

[0009] Each of the memory address generation units is used to generate four absolute texture sampling addresses based on the four relative texture sampling addresses generated by each texture address generation unit, and to record the absolute texture sampling addresses as texture addresses.

[0010] The conflict detection and Bank grouping unit is used to perform conflict detection on 16 texture addresses, group at least one texture address accessing the same texture block into multiple address groups, generate a conflict flag bit and a valid texel flag bit within each address group, the conflict flag bit carrying the texture address that has conflicted; it is also used to send an access request and a conflict flag bit in parallel to the corresponding storage unit Bank according to each address group.

[0011] Each storage unit (Bank) is used to return the corresponding texture block data when an access request is received, and to transfer the texture block data to the data assembly module;

[0012] The data assembly module is used to read the corresponding texel data in parallel from the corresponding texture block data according to the effective texel marker bits within each address group.

[0013] Based on the above technical solution, the present invention can also be improved as follows.

[0014] Optionally, each of the texture address generation units is configured to generate four texture sampling relative addresses based on one of the four texture sampling request tasks, including:

[0015] When a texture sampling request task is received, four texture sampling relative addresses are generated based on the sampling coordinates in the texture sampling request task;

[0016] Among them, a grid coordinate system is established based on the texel size. The size of the grid is one texel, the horizontal direction of the grid is the x-axis, and the vertical direction of the grid is the y-axis.

[0017] If the sampling coordinates are located at the intersection of the x-axis and y-axis, then one texture sampling relative address is generated, and a texel width and height consistency flag is output. The texel width and height consistency flag indicates that the four texture sampling relative addresses are the same.

[0018] If the sampling coordinates are located on the x-axis or y-axis, two texture sampling relative addresses are generated, and a texel width or height consistency flag is output, indicating that two of the four texture sampling relative addresses are the same, and the other two texture sampling relative addresses are the same.

[0019] If the sampling coordinates are neither on the x-axis nor on the y-axis, then four texture sampling relative addresses are generated.

[0020] Optionally, the texture sampling relative address is the relative address of the fingerprint based on the texture image. Each of the memory address generation units is used to generate four texture sampling absolute addresses based on the four texture sampling relative addresses generated by each texture address generation unit, and the texture sampling absolute addresses are recorded as texture addresses, including:

[0021] Each of the aforementioned memory address generation units is used to output the absolute address of four texels in the memory based on the four texture sampling relative addresses generated by each of the aforementioned texture address generation units and the offset address of the texture image stored in the memory.

[0022] Optionally, the conflict detection and bank grouping unit is used to perform conflict detection on the 16-way texture addresses, grouping at least one texture address accessing the same texture block into multiple address groups, including:

[0023] Obtain the texture block to be accessed for each texture address. If the texture blocks to be accessed for all 16 texture addresses are different, it means that there is no conflict among the 16 texture addresses.

[0024] If more than one texture address requests access to the same texture block, it indicates a texture address conflict.

[0025] When a texture address conflict occurs, multiple texture addresses accessing the same texture block are grouped together to obtain multiple address groups;

[0026] Generate a conflict flag and a valid texel flag for each address group. The conflict flag carries the texture address where the conflict occurred, and the valid texel flag indicates the texel data that needs to be accessed within the address group.

[0027] Optionally, each storage unit (Bank) is configured to return a corresponding texture block upon receiving an access request and transmit the texture block to the data assembly module, including:

[0028] Each of the storage units Bank is used to receive the address group carried in the access request, and compare the texture address with 64 Tag address features cached in the storage unit Bank according to each texture address in the address group. The Tag address features refer to the address features of the texture blocks cached in the storage unit Bank. There are 64 texture blocks cached in one storage unit Bank.

[0029] If a match is found, the texture block data corresponding to the matched Tag address feature will be directly output to the data assembly module.

[0030] If a miss occurs, an access request is sent to the video memory. After the video memory returns a texture block, the returned texture block data is output to the data assembly module, and the cache of the storage unit Bank is updated based on the returned texture block data.

[0031] Optionally, each texture block stores 16 texels. The data assembly module is used to read the corresponding texel data from the corresponding texture block data according to the valid texel flag bit within each address group, including:

[0032] Based on the texture sampling address in each address group, the number of the texture block in the storage unit Bank is located, and then the valid texel data output in the texture block is determined according to the valid texel flag bit in the group.

[0033] Optionally, determining the effective texels output in the texture block based on the effective texel marker bits within the group includes:

[0034] Store the 16 texels of each texture block into a 16-way texel selector;

[0035] Based on the valid texel flag bits within the group, determine the activation state of the 16-channel texel selector and output the texel data corresponding to the texel selector in the active state.

[0036] Based on the group end flag of each address group, the output of texels is stopped, and finally all texel data is output in parallel.

[0037] Optionally, the system further includes a 4-channel texture filtering unit, and the data assembly module outputs all the read texel data in parallel to multiple texture filtering units;

[0038] Multiple texture filtering units are used to perform texture filtering on the output texel data in parallel.

[0039] According to a second aspect of the present invention, a texture storage read access optimization method is provided, applied to a texture storage read access optimization system, the method comprising:

[0040] Based on a texture sampling request task, each texture address generation unit generates 4 texture sampling relative addresses;

[0041] Based on the four texture sampling relative addresses generated by each texture address generation unit, each memory address generation unit generates four texture sampling absolute addresses, and the texture sampling absolute addresses are recorded as texture addresses.

[0042] The conflict detection and Bank grouping unit performs conflict detection on the 16 texture addresses, groups at least one texture address accessing the same texture block into multiple address groups, generates a conflict flag bit and a valid texel flag bit within each address group, the conflict flag bit carries the texture address that has conflicted; and according to each address group, sends an access request and a conflict flag bit to the corresponding storage unit Bank in parallel.

[0043] When each storage unit Bank receives an access request, it returns the corresponding texture block data and transmits the texture block data to the data assembly module.

[0044] The data assembly module reads the corresponding texel data in parallel from the corresponding texture block data based on the valid texel flag bits within each address group.

[0045] This invention provides a texture storage read access optimization system and method that performs feature comparison and conflict detection on texture addresses in parallel, groups texture storage units according to Bank, and then outputs them in parallel. It requires no preprocessing, is not coupled with other parts within the texture unit, and is easy to implement. It adopts a pipelined design approach, resulting in high execution efficiency. Attached Figure Description

[0046] Figure 1 This is a schematic diagram illustrating the GPU texture sampling stage.

[0047] Figure 2 This is a diagram illustrating whether a conflict occurs during the access of multipath pixel addresses;

[0048] Figure 3 This is a schematic diagram of a texture storage read access optimization system according to an embodiment of the present invention;

[0049] Figure 4 A schematic diagram illustrating the generation of texture addresses for the texture address generation unit;

[0050] Figure 5 Workflow diagram for conflict detection and Bank grouping unit;

[0051] Figure 6 A schematic diagram illustrating the operation of accessing the storage unit Bank;

[0052] Figure 7 This is a schematic diagram of the internal structure of a storage unit (Bank).

[0053] Figure 8 A schematic diagram of the internal structure of the data assembly module;

[0054] Figure 9 A flowchart of a texture storage read access optimization method provided in an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0056] During the texture sampling stage, the GPU, such as Figure 1 As shown, multiple texture address generation units generate the addresses of multipath texels in the texture memory in parallel. The multipath address selects which memory bank to access based on the memory bank number. Multipath address conflicts may occur, causing congestion in the texture memory queue, resulting in reduced sampling efficiency and increased latency.

[0057] The existing technical solution proposes to use 2x2 grid parallel sampling. The sampling process generates 16 texel addresses, which are then sent to 4 texture blocks in parallel. The 16 texel addresses sent in parallel will inevitably have the possibility of address conflicts. Figure 2 Taking four texel samples as an example, the left side is conflict-free (where texel addresses 15, 3, 0, and 12 correspond to different texture blocks, so there is no conflict). On the right side, addresses 7 and 11 conflict (both correspond to texture block T0), and addresses 4 and 8 conflict (both correspond to texture block T1). Extending this to 16 access requests to the texture storage, there may be more severe conflict situations, which seriously increases the queue pressure of the texture storage, invalid power consumption, and texture sampling latency.

[0058] Based on this, the present invention designs a method to solve the problem of texture storage volume read conflict, thereby solving the problem of texture storage volume read conflict in the texture parallel sampling process, reducing texture sampling latency and improving sampling efficiency.

[0059] See Figure 3 This invention illustrates a texture storage read access optimization system according to an embodiment of the present invention. The system includes a 4-way texture address generation unit, a 4-way video memory address generation unit, a conflict detection and Bank grouping unit, a storage unit Bank, and a data assembly module.

[0060] Each of the texture address generation units is used to generate four texture sampling relative addresses based on a texture sampling request task;

[0061] Each of the memory address generation units is used to generate four absolute texture sampling addresses based on the four relative texture sampling addresses generated by each texture address generation unit, and to record the absolute texture sampling addresses as texture addresses.

[0062] The conflict detection and Bank grouping unit is used to perform conflict detection on 16 texture addresses, group at least one texture address accessing the same texture block into multiple address groups, generate a conflict flag bit and a valid texel flag bit within each address group, the conflict flag bit carrying the texture address that has conflicted; it is also used to send an access request and a conflict flag bit in parallel to the corresponding storage unit Bank according to each address group.

[0063] Each storage unit (Bank) is used to return the corresponding texture block data when an access request is received, and to transfer the texture block data to the data assembly module;

[0064] The data assembly module is used to read the corresponding texel data in parallel from the corresponding texture block data according to the effective texel marker bits within each address group.

[0065] Among them, see Figure 4 , Figure 4 The diagram illustrates the working principle of each texture address generation unit. The four texture address generation units each execute one of the 2×2 texture sampling request tasks. The 2×2 texture sampling mode is currently the common method in the industry.

[0066] Specifically, when the texture address generation unit receives a texture sampling request task, it generates four texture sampling relative addresses based on the sampling coordinates in the texture sampling request task.

[0067] Specifically, a grid coordinate system is established based on the texel size. The grid size is one texel, with the horizontal direction of the grid as the x-axis and the vertical direction as the y-axis. The established xy coordinate system is as follows: Figure 4 As shown.

[0068] If the sampling coordinates are located at the intersection of the x-axis and y-axis, then one texture sampling relative address is generated, and a texel width and height consistency flag is output. The texel width and height consistency flag indicates that the four texture sampling relative addresses are the same.

[0069] If the sampling coordinates are located on the x-axis or y-axis, two texture sampling relative addresses are generated, and a texel width or height consistency flag is output, indicating that two of the four texture sampling relative addresses are the same, and the other two texture sampling relative addresses are the same.

[0070] If the sampling coordinates are neither on the x-axis nor on the y-axis, then four texture sampling relative addresses are generated.

[0071] Therefore, one texture address generation unit can generate four texture sample relative coordinates based on one sampling coordinate, and four texture address generation units can generate 16 texture sample relative addresses.

[0072] Each texture address generation unit generates four texture sampling relative addresses, which are then transmitted to the corresponding video memory address generation unit. The texture sampling relative address is the relative address of the fingerprint based on the texture image. Each video memory address generation unit outputs the absolute address of four texels in video memory based on the four texture sampling relative addresses generated by each texture address generation unit and the offset address of the texture image stored in video memory.

[0073] The 4-channel memory address generation unit transmits the generated 16-channel texture sampling absolute addresses (hereinafter referred to as texture addresses) to the conflict detection and Bank grouping unit.

[0074] The conflict detection and Bank grouping unit performs conflict detection on the 16-way texture addresses. A conflict refers to different texture addresses pointing to the same texture tile. The principle behind the conflict detection and Bank grouping unit's conflict detection on the 16-way texture addresses can be found in [link to relevant documentation]. Figure 5 :

[0075] Obtain the texture block to be accessed for each texture address. If the texture blocks to be accessed for all 16 texture addresses are different, it means that there is no conflict among the 16 texture addresses.

[0076] If more than one texture address requests access to the same texture block, it indicates a texture address conflict.

[0077] When a texture address conflict occurs, multiple texture addresses accessing the same texture block are grouped together to obtain multiple address groups;

[0078] Generate a conflict flag and a valid texel flag for each address group. The conflict flag carries the texture address where the conflict occurred, and the valid texel flag indicates the texel data that needs to be accessed within the address group.

[0079] Understandably, the specific process of 16-way texture address conflict detection and bank grouping is as follows: First, the texture block (Tile) corresponding to each texture address is determined based on the 16 texture addresses. If more than one texture address points to the same texture block, it indicates that these multiple texture addresses have conflicted. Therefore, the multiple texture addresses pointing to the same texture block are divided into an address group, and the address group includes the multiple texture addresses that have conflicted. In this way, the 16 texture addresses are divided into multiple address groups. A conflict flag bit and a valid texel flag bit are generated for each address group. The conflict flag bit carries the texture address that has conflicted, and the valid texel flag bit indicates the specific texel data address that needs to be accessed within the address group.

[0080] It should be noted that a storage unit (Bank) typically stores 64 texture tiles. Therefore, the required storage unit (Bank) can be located based on the texture tiles corresponding to each address group. Consequently, the conflict detection and Bank grouping unit sends an access request and a conflict flag to the corresponding storage unit (Bank) in parallel, based on the Bank corresponding to each address group, to access the data in the corresponding storage unit (Bank). The access process can be found in [link to relevant documentation]. Figure 6 .

[0081] Each storage unit (Bank) receives the address group carried in the access request. Based on each texture address in the address group, it compares the texture address with the 64 Tag address features cached in the storage unit (Bank). The Tag address features refer to the address features of the texture blocks cached in the storage unit (Bank). There are 64 texture blocks cached in one storage unit (Bank).

[0082] If a match is found, the texture block data corresponding to the matched tag address is directly output to the data assembly module. If a match is not found, an access request is sent to the video memory. After the video memory returns the texture block, the returned texture block data is output to the data assembly module, and the cache of the storage unit Bank is updated based on the returned texture block data.

[0083] Understandably, each storage unit (Bank) caches 64 texture tiles. The storage structure of the storage unit (Bank) can be found in [link to relevant documentation]. Figure 7 In this context, B0, B1, B2, and B3 are all texture blocks, and a storage unit Bank contains 64 texture tiles.

[0084] When each storage unit (Bank) receives an access request, it compares the texture address in the address group with the 64 Tag address features (texture block address features) cached in the storage unit (Bank). If a match is found, the corresponding texture block data is output. If a match is not found, an access request is sent to the video memory, the corresponding texture block data is retrieved from the video memory, and the storage unit (Bank) is updated.

[0085] Each storage unit (Bank) outputs texture block data corresponding to an address group, which is then transmitted to the data assembly module. The data assembly module assembles multiple texture block data sets. It's important to note that during conflict detection and address grouping within the Bank, the number of texture addresses included in different address groups can vary. Therefore, the access time for outputting texture block data differs depending on the address group being accessed within the storage unit (Bank). Consequently, the data assembly module must wait until all storage units (Banks) have been accessed before assembling the texture block data.

[0086] The data assembly module accesses the specific texel data from the corresponding texture block data based on each texture address. Each texture block stores 16 texels. Therefore, the data assembly module reads the corresponding texel data from the corresponding texture block data based on the valid texel flag bit within each address group. Specifically, this includes: locating the texture block number in the storage unit Bank based on the texture address in each address group, and then determining the valid texel data output from the texture block based on the valid texel flag bit within the group.

[0087] The data assembly module assembles the texture block data output from the storage bank, such as... Figure 8 As shown, the 16 texel data of each texture block are simultaneously stored in a 16-channel texel selector. The 16-channel texel selector determines the active state of texel selectors 0 through F based on the valid texel flag bits within the address group. Active texel selectors output the texel data. Specifically, the lower two bits of the address group determine the texture block number in the storage bank of the texel selector, and finally, the texel address within the texture block tile is determined based on the pixel index number (determined by the valid texel flag bits within the group). Finally, based on the group end flag bit of the address group, the corresponding 16 channels of texel data are output in parallel.

[0088] The texture storage read access optimization system provided in this embodiment of the invention also includes a 4-way texture filtering unit. The data assembly module outputs all the read texel data in parallel to multiple texture filtering units. Multiple texture filtering units are used to perform texture filtering on the output texel data in parallel according to the filtering mode, and the entire texture sampling state ends.

[0089] See Figure 9This paper illustrates a texture storage read access optimization method according to an embodiment of the present invention, applied to a texture storage read access optimization system. The method includes the following steps:

[0090] Step 1: Based on a texture sampling request task, each texture address generation unit generates 4 texture sampling relative addresses;

[0091] Step 2: Based on the four texture sampling relative addresses generated by each texture address generation unit, each memory address generation unit generates four texture sampling absolute addresses, and the texture sampling absolute addresses are recorded as texture addresses;

[0092] Step 3: The conflict detection and Bank grouping unit performs conflict detection on the 16 texture addresses, groups at least one texture address accessing the same texture block into multiple address groups, generates a conflict flag bit and a valid texel flag bit within each address group, the conflict flag bit carries the texture address that has conflicted; and according to each address group, sends an access request and a conflict flag bit to the corresponding storage unit Bank in parallel.

[0093] Step 4: When each storage unit Bank receives an access request, it returns the corresponding texture block data and transmits the texture block data to the data assembly module.

[0094] Step 5: The data assembly module reads the corresponding texel data in parallel from the corresponding texture block data according to the valid texel flag bit in each address group.

[0095] Understandably, corresponding to the above Figure 3 The provided texture memory read access optimization system also includes a texture memory read access optimization method. When the shader issues a texture sampling task, the texture address generation unit and the memory address generation unit output 2×2 sampling coordinates as up to 16 memory read addresses. Conflict detection and conflict grouping are performed based on the characteristics of each address. Based on the lower two bits of the address group, the grouped texel address groups are divided into corresponding memory banks, and finally, a read request is sent to the memory banks. Simultaneously, the valid flag bits within the address groups are sent to the array assembly module. After receiving the texture block data returned from the memory banks, the data assembly module determines which texel selectors are activated in this return data based on the valid flag bits within the groups. Upon detecting the group end flag, the data assembly module completes the data assembly task and outputs 16 texels in parallel to the texture filtering unit, ending the operation.

[0096] This invention provides a texture storage read access optimization system and method that, without adding extra storage units, avoids texture storage address conflicts by adding tag comparison and conflict address grouping between the texture storage and texture address generation. This prevents queue accumulation in texture storage access and significantly reduces texture sampling latency. Furthermore, it achieves conflict resolution without software intervention or additional configuration; the pipelined design effectively improves conflict resolution efficiency and offers strong scalability.

[0097] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0098] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0100] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0101] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0102] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0103] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A texture storage volume read access optimization system, characterized in that, It includes a 4-way texture address generation unit, a 4-way video memory address generation unit, a conflict detection and Bank grouping unit, a storage Bank unit, and a data assembly module; Each of the texture address generation units is used to generate four texture sampling relative addresses based on a texture sampling request task; Each of the memory address generation units is used to generate four absolute texture sampling addresses based on the four relative texture sampling addresses generated by each texture address generation unit, and to record the absolute texture sampling addresses as texture addresses. The conflict detection and Bank grouping unit is used to perform conflict detection on 16 texture addresses, group at least one texture address accessing the same texture block into an address group, obtain multiple address groups, generate a conflict flag bit and a valid texel flag bit within each address group, and the conflict flag bit carries the texture address that has conflicted. It is also used to send an access request and a conflict flag to the corresponding storage unit Bank in parallel for each address group; Each storage unit (Bank) is used to return the corresponding texture block data when an access request is received, and to transfer the texture block data to the data assembly module; The data assembly module is used to read the corresponding texel data in parallel from the corresponding texture block data according to the effective texel marker bits within each address group.

2. The texture storage read access optimization system according to claim 1, characterized in that, Each of the texture address generation units is used to generate four texture sampling relative addresses based on one of the four texture sampling request tasks, including: When a texture sampling request task is received, four texture sampling relative addresses are generated based on the sampling coordinates in the texture sampling request task; Among them, a grid coordinate system is established based on the texel size. The size of the grid is one texel, the horizontal direction of the grid is the x-axis, and the vertical direction of the grid is the y-axis. If the sampling coordinates are located at the intersection of the x-axis and y-axis, then one texture sampling relative address is generated, and a texel width and height consistency flag is output. The texel width and height consistency flag indicates that the four texture sampling relative addresses are the same. If the sampling coordinates are located on the x-axis or y-axis, two texture sampling relative addresses are generated, and a texel width or height consistency flag is output, indicating that two of the four texture sampling relative addresses are the same, and the other two texture sampling relative addresses are the same. If the sampling coordinates are neither on the x-axis nor on the y-axis, then four texture sampling relative addresses are generated.

3. The texture storage read access optimization system according to claim 1, characterized in that, The texture sampling relative address is the relative address of the fingerprint based on the texture image. Each of the memory address generation units is used to generate four texture sampling absolute addresses based on the four texture sampling relative addresses generated by each texture address generation unit. The texture sampling absolute addresses are recorded as texture addresses, including: Each of the aforementioned memory address generation units is used to output the absolute address of four texels in the memory based on the four texture sampling relative addresses generated by each of the aforementioned texture address generation units and the offset address of the texture image stored in the memory.

4. The texture storage read access optimization system according to claim 1, characterized in that, The conflict detection and bank grouping unit is used to perform conflict detection on the 16-way texture addresses, grouping at least one texture address accessing the same texture block into multiple address groups, including: Obtain the texture block to be accessed for each texture address. If the texture blocks to be accessed for all 16 texture addresses are different, it means that there is no conflict among the 16 texture addresses. If more than one texture address requests access to the same texture block, it indicates a texture address conflict. When a texture address conflict occurs, multiple texture addresses accessing the same texture block are grouped together to obtain multiple address groups; Generate a conflict flag and a valid texel flag for each address group. The conflict flag carries the texture address where the conflict occurred, and the valid texel flag indicates the texel data that needs to be accessed within the address group.

5. The texture storage read access optimization system according to claim 1, characterized in that, Each storage unit (Bank) is used to return a corresponding texture block upon receiving an access request, and to transmit the texture block to the data assembly module, including: Each of the storage units Bank is used to receive the address group carried in the access request, and compare the texture address with 64 Tag address features cached in the storage unit Bank according to each texture address in the address group. The Tag address features refer to the address features of the texture blocks cached in the storage unit Bank. There are 64 texture blocks cached in one storage unit Bank. If a match is found, the texture block data corresponding to the matched Tag address feature will be directly output to the data assembly module. If a miss occurs, an access request is sent to the video memory. After the video memory returns a texture block, the returned texture block data is output to the data assembly module, and the cache of the storage unit Bank is updated based on the returned texture block data.

6. The texture storage read access optimization system according to claim 5, characterized in that, Each texture block stores 16 texels. The data assembly module is used to read the corresponding texel data from the corresponding texture block data according to the valid texel flag bit within each address group, including: Based on the texture sampling address in each address group, the number of the texture block in the storage unit Bank is located, and then the valid texel data output in the texture block is determined according to the valid texel flag bit in the group.

7. The texture storage read access optimization system according to claim 6, characterized in that, The step of determining the effective texels output in the texture block based on the effective texel marker bits within the group includes: Store the 16 texels of each texture block into a 16-way texel selector; Based on the valid texel flag bits within the group, determine the activation state of the 16-channel texel selector and output the texel data corresponding to the texel selector in the active state. Based on the group end flag of each address group, the output of texels is stopped, and finally all texel data is output in parallel.

8. The texture storage read access optimization system according to claim 1, characterized in that, The system also includes a 4-channel texture filtering unit, and the data assembly module outputs all the read texel data in parallel to multiple texture filtering units. Multiple texture filtering units are used to perform texture filtering on the output texel data in parallel.

9. A method for optimizing read access to texture storage, applied to the texture storage read access optimization system of claim 1, characterized in that, The method includes; Based on a texture sampling request task, each texture address generation unit generates 4 texture sampling relative addresses; Based on the four texture sampling relative addresses generated by each texture address generation unit, each memory address generation unit generates four texture sampling absolute addresses, and the texture sampling absolute addresses are recorded as texture addresses. The conflict detection and Bank grouping unit performs conflict detection on the 16-way texture addresses, groups at least one texture address that accesses the same texture block into an address group, and generates a conflict flag bit and a valid texel flag bit within each address group. The conflict flag bit carries the texture address that has caused the conflict. And based on each address group, send an access request and a conflict flag to the corresponding storage unit Bank in parallel; When each storage unit Bank receives an access request, it returns the corresponding texture block data and transmits the texture block data to the data assembly module. The data assembly module reads the corresponding texel data in parallel from the corresponding texture block data based on the valid texel flag bits within each address group.

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