Input / output circuit supporting multiple protocols and artificial intelligence chip

Abstract

This invention provides an input / output circuit supporting multiple protocols and an artificial intelligence chip. The input / output circuit includes a first input / output terminal, a second input / output terminal, a transmitting circuit, and a receiving circuit. The transmitting circuit includes a programmable high-speed driver, a low-dropout linear regulator, a first switching circuit, a second switching circuit, and a switcher. The low-dropout linear regulator is electrically connected to the programmable high-speed driver. The first switching circuit is electrically connected to the programmable high-speed driver and the first input / output terminal. The second switching circuit is electrically connected to the programmable high-speed driver and the second input / output terminal. The switcher is electrically connected to the first switching circuit and the second switching circuit. The receiving circuit is electrically connected to the first input / output terminal and the second input / output terminal. The input / output circuit of this invention can realize the function of supporting multiple protocols.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and more particularly to an input / output circuit that supports multiple protocols and an artificial intelligence chip. Background Technology

[0002] With the development of semiconductor technology, general-purpose chips have received widespread attention and application due to their high adaptability. To enable chips to switch freely between different application scenarios and product forms while maintaining a limited number of bumps and supporting multiple communication protocols, the research on compatible IP physical layer circuits (combo PHYs) has become increasingly important. However, existing compatible PHY designs only achieve compatibility with protocols with similar input / output (I / O) voltages or adjust the number of bumps, leading to wasted circuit layout area. Summary of the Invention

[0003] This invention relates to an input / output circuit that supports multiple protocols and an artificial intelligence chip, which is applicable to data transmission of various communication protocols.

[0004] According to an embodiment of the present invention, the multi-protocol input / output circuit of the present invention includes a first input / output terminal, a second input / output terminal, a transmitting circuit, and a receiving circuit. The transmitting circuit includes a programmable high-speed driver, a low-dropout linear regulator, a first switching circuit, a second switching circuit, and a switcher. The low-dropout linear regulator is electrically connected to the programmable high-speed driver. The first switching circuit is electrically connected to the programmable high-speed driver and the first input / output terminal. The second switching circuit is electrically connected to the programmable high-speed driver and the second input / output terminal. The switcher is electrically connected to the first switching circuit and the second switching circuit. The receiving circuit is electrically connected to the first input / output terminal and the second input / output terminal.

[0005] In the input / output circuit according to an embodiment of the present invention, the input / output circuit further includes a first resistor and a second resistor. A first terminal of the first resistor is electrically connected to a first input / output terminal and a receiving terminal circuit, and a second terminal of the first resistor is electrically connected to a first switching circuit. A first terminal of the second resistor is electrically connected to a second input / output terminal and a receiving terminal circuit, and a second terminal of the second resistor is electrically connected to a second switching circuit.

[0006] In the input / output circuit according to an embodiment of the present invention, the input / output circuit further includes a first general-purpose input / output buffer and a second general-purpose input / output buffer. The first general-purpose input / output buffer is electrically connected to the second terminal of a first resistor and a first switching circuit. The second general-purpose input / output buffer is electrically connected to the second terminal of a second resistor and a second switching circuit.

[0007] In the input / output circuit according to an embodiment of the present invention, a low-dropout linear regulator is used to receive a mode selection signal, and a programmable high-speed driver is used to receive a first data signal and a second data signal. The low-dropout linear regulator is used to control the programmable high-speed driver to perform impedance matching according to the mode selection signal, and the programmable high-speed driver is used to generate a first transmit signal to a first switching circuit according to the first data signal, and to generate a second transmit signal to a second switching circuit according to the second data signal.

[0008] In an input / output circuit according to an embodiment of the present invention, a programmable high-speed driver includes a plurality of driving units. The plurality of driving units are connected in parallel and electrically connected to a first switching circuit and a second switching circuit. Each of the plurality of driving units includes a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor is electrically connected to a low-dropout linear regulator, and a second terminal of the first transistor is electrically connected to the first switching circuit. A control terminal of the first transistor receives a second data signal. A first terminal of the second transistor is electrically connected to the first terminal of the first transistor and the low-dropout linear regulator. A second terminal of the second transistor is electrically connected to the second switching circuit. A control terminal of the second transistor receives the first data signal. A first terminal of the third transistor is electrically connected to the second terminal of the first transistor and the first switching circuit. A second terminal of the third transistor is grounded. A control terminal of the third transistor is electrically connected to the control terminal of the second transistor and receives the first data signal. A first terminal of the fourth transistor is electrically connected to the second terminal of the second transistor and the second switching circuit. A second terminal of the fourth transistor is grounded. A control terminal of the fourth transistor is electrically connected to the control terminal of the first transistor and receives the second data signal.

[0009] In the input / output circuit according to an embodiment of the present invention, the first transistor, the second transistor, the third transistor, and the fourth transistor are N-type transistors.

[0010] In the input / output circuit according to an embodiment of the present invention, the low-dropout linear regulator includes a first operational amplifier, a fifth transistor, a multiplexer, a third resistor, a first variable resistor, and a fourth resistor. The first terminal of the first operational amplifier receives a reference voltage. The first terminal of the fifth transistor receives an operating voltage. The control terminal of the fifth transistor is electrically connected to the output terminal of the first operational amplifier. The first input terminal of the multiplexer is electrically connected to the second terminal of the fifth transistor. The control terminal of the multiplexer receives a mode selection signal. The first terminal of the third resistor is electrically connected to the second terminal of the fifth transistor and the first input terminal of the multiplexer. The second terminal of the third resistor is electrically connected to the second input terminal of the first operational amplifier. The first terminal of the first variable resistor is electrically connected to the second terminal of the third resistor and the second input terminal of the first operational amplifier. The second terminal of the first variable resistor is electrically connected to the second input terminal of the multiplexer. The first terminal of the fourth resistor is electrically connected to the second terminal of the first variable resistor and the second input terminal of the multiplexer. The second terminal of the fourth resistor is grounded.

[0011] In the input / output circuit according to an embodiment of the present invention, the fifth transistor is an N-type transistor.

[0012] In an input / output circuit according to an embodiment of the present invention, a first switching circuit includes a sixth transistor, a first terminal of which is electrically connected to a first resistor, a second terminal of which is electrically connected to a programmable high-speed driver, and a control terminal of which is electrically connected to a switch. A second switching circuit includes a seventh transistor, a first terminal of which is electrically connected to a second resistor, a second terminal of which is electrically connected to a programmable high-speed driver, and a control terminal of which is electrically connected to a switch.

[0013] In the input / output circuit according to an embodiment of the present invention, the sixth transistor and the seventh transistor are N-type transistors.

[0014] In the input / output circuit according to an embodiment of the present invention, the switch is used to receive an enable signal to control the sixth transistor to output a first transmit signal to the first input / output terminal according to the enable signal, and to control the seventh transistor to output a second transmit signal to the second input / output terminal according to the enable signal.

[0015] In the input / output circuit according to an embodiment of the present invention, the switch is used to convert the enable signal from the low voltage domain to the high voltage domain and output it to the control terminal of the sixth transistor and the control terminal of the seventh transistor.

[0016] In the input / output circuit according to an embodiment of the present invention, the receiving end circuit includes a differential input amplifier circuit. The differential input amplifier circuit is electrically connected to a first input / output terminal and a second input / output terminal.

[0017] In the input / output circuit according to an embodiment of the present invention, the receiving end circuit further includes a common-mode voltage control circuit. The common-mode voltage control circuit is electrically connected to the first input / output terminal and the second input / output terminal.

[0018] In the input / output circuit according to an embodiment of the present invention, the differential input amplifier circuit includes a differential input amplifier, a second variable resistor, and a third variable resistor. The first input terminal of the differential input amplifier is electrically connected to a first input / output terminal. The second input terminal of the differential input amplifier is electrically connected to a second input / output terminal. The first terminal of the second variable resistor is electrically connected to the first input terminal of the differential input amplifier. The first terminal of the third variable resistor is electrically connected to the second input terminal of the differential input amplifier. The second terminal of the third variable resistor is electrically connected to the second terminal of the second variable resistor.

[0019] In the input / output circuit according to an embodiment of the present invention, the common-mode voltage control circuit includes a second operational amplifier, a first current source, and a second current source. The first input terminal of the second operational amplifier receives a common-mode control voltage. The second input terminal of the second operational amplifier is electrically connected to the second terminal of a second variable resistor and the second terminal of a third variable resistor. The first current source is electrically connected to the output terminal of the second operational amplifier and the second input terminal of a differential input amplifier. The second current source is electrically connected to the output terminal of the second operational amplifier and the first input terminal of the differential input amplifier.

[0020] According to an embodiment of the present invention, the artificial intelligence chip of the present invention includes a core circuit, an input / output circuit, a first input / output pad, and a second input / output pad. The input / output circuit is electrically connected to the core circuit. The first input / output pad is electrically connected to a first input / output terminal of the input / output circuit. The second input / output pad is electrically connected to a second input / output terminal of the input / output circuit. The input / output circuit includes a transmitting circuit and a receiving circuit. The transmitting circuit includes a programmable high-speed driver, a low-dropout linear regulator, a first switching circuit, a second switching circuit, and a switcher. The low-dropout linear regulator is electrically connected to the programmable high-speed driver. The first switching circuit is electrically connected to the programmable high-speed driver and the first input / output terminal. The second switching circuit is electrically connected to the programmable high-speed driver and the second input / output terminal. The switcher is electrically connected to the first switching circuit and the second switching circuit. The receiving circuit is electrically connected to the first input / output terminal and the second input / output terminal.

[0021] Based on the above, the multi-protocol input / output circuit and artificial intelligence chip of the present invention can transmit and receive data from multiple communication protocols in different voltage domains through the transmitting end circuit and the receiving end circuit.

[0022] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the input / output circuit of an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the input / output circuit of another embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the input / output circuit of another embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention.

[0027] Explanation of icon numbers

[0028] 100: Input / output circuit;

[0029] 101: First input / output terminal;

[0030] 102: Second input / output terminal;

[0031] 110: Transmitter circuit;

[0032] 111: Programmable high-speed driver;

[0033] 112: Low dropout linear regulator;

[0034] 113: First switching circuit;

[0035] 114: Second switching circuit;

[0036] 115: Switcher;

[0037] 216: First general-purpose input / output buffer;

[0038] 217: Second general purpose input / output buffer;

[0039] 120: Receiver circuit;

[0040] 221: Differential input amplifier circuit;

[0041] 222: Common-mode voltage control circuit;

[0042] 231: First resistor;

[0043] 232: Second resistor;

[0044] 311_1: First drive unit;

[0045] 311_M: The Mth driving unit;

[0046] 3111: First transistor;

[0047] 3112: Second transistor;

[0048] 3113: Third transistor;

[0049] 3114: Fourth transistor;

[0050] 3121: First operational amplifier;

[0051] 3122: The fifth transistor;

[0052] 3123: Multiplexer;

[0053] 3124: Third resistor;

[0054] 3125: First variable resistor;

[0055] 3126: Fourth resistor;

[0056] 3131: The sixth transistor;

[0057] 3141: The seventh transistor;

[0058] 3211: Differential input amplifier;

[0059] 3212: Second variable resistor;

[0060] 3213: Third variable resistor;

[0061] 3221: Second operational amplifier;

[0062] 3222: First current source;

[0063] 3223: Second current source;

[0064] 400: Artificial intelligence chip;

[0065] 420: Core circuit;

[0066] 431: First input / output pad;

[0067] 432: Second input / output pad;

[0068] Din1: First data signal;

[0069] Din2: Second data signal;

[0070] Dout: Data signal;

[0071] Drv_trm: Digital control signal;

[0072] EN: Enable signal;

[0073] SEL: Mode selection signal;

[0074] Vref: First reference voltage;

[0075] V1: Second reference voltage;

[0076] VCM: Common-mode control voltage;

[0077] outn: The first output terminal;

[0078] outp: Second output terminal. Detailed Implementation

[0079] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0080] Figure 1 This is a schematic diagram of the input / output circuit of an embodiment of the present invention. (See reference) Figure 1 The input / output circuit 100 includes a first input / output terminal 101, a second input / output terminal 102, a transmitting circuit 110, and a receiving circuit 120. The transmitting circuit 110 includes a programmable high-speed driver 111, a low-dropout regulator (LDO) 112, a first switching circuit 113, a second switching circuit 114, and a switch 115. The low-dropout regulator 112 is electrically connected to the programmable high-speed driver 111. The first switching circuit 113 is electrically connected to the programmable high-speed driver 111 and the first input / output terminal 101. The second switching circuit 114 is electrically connected to the programmable high-speed driver 111 and the second input / output terminal 102. The switch 115 is electrically connected to the first switching circuit 113 and the second switching circuit 114. The receiving circuit 120 is electrically connected to the first input / output terminal 101 and the second input / output terminal 102.

[0081] In this embodiment, the low-dropout linear regulator 112 is used to receive the mode selection signal SEL. The programmable high-speed driver 111 is used to receive the first data signal Din1 and the second data signal Din2. The low-dropout linear regulator 112 is used to control the programmable high-speed driver 111 to perform impedance matching according to the mode selection signal SEL, and the programmable high-speed driver 111 is used to generate a first transmit signal to the first switching circuit 113 according to the first data signal Din1 and a second transmit signal to the second switching circuit 114 according to the second data signal Din2.

[0082] In this embodiment, the switch 115 receives an enable signal EN to control the first switch circuit 113 and the second switch circuit 114 according to the enable signal EN. When the input / output circuit 100 performs data transmission, the switch 115 can switch the first switch circuit 113 and the second switch circuit 114 to the ON state to send data to the first input / output terminal 101 and the second input / output terminal 102 (i.e., send a first transmit signal to the first input / output terminal 101 and send a second transmit signal to the second input / output terminal 102). When the input / output circuit 100 performs data reception, the switch 115 can switch the first switch circuit 113 and the second switch circuit 114 to the OFF state and receive data from the first input / output terminal 101 and the second input / output terminal 102 through the receiving terminal circuit 120.

[0083] In this embodiment, the low-dropout linear regulator 112 can control the programmable high-speed driver 111 according to the mode selection signal SEL, enabling it to perform on-die termination (ODT) impedance matching to achieve the impedance required for data transmission of the current communication protocol. The programmable high-speed driver 111 can convert the first data signal and the second data signal corresponding to the communication protocol into a first transmit signal and a second transmit signal, respectively, according to the setting result, and send them to the first switching circuit 113 and the second switching circuit 114, so that the first transmit signal and the second transmit signal can be sent to the first input / output terminal 101 and the second input / output terminal 102, respectively, via the turned-on first switching circuit 113 and second switching circuit 114.

[0084] In this embodiment, the communication protocol may include, for example, a serializer / deserializer (SerDes) communication protocol (which may include a Mobile Industry Processor Interface (MIPI) protocol using SerDes transmission technology), a Double Data Rate (DDR) communication protocol, and a Low Voltage Differential Signaling (LVDS) communication protocol. In this embodiment, the input / output circuit 100 can control a programmable high-speed driver 111 through a low-dropout linear regulator 112 to realize the data transmission function of differential signal form of different communication protocols.

[0085] Figure 2 This is a schematic diagram of an input / output circuit according to another embodiment of the present invention. (See reference) Figure 2The input / output circuit 100 includes a first input / output terminal 101, a second input / output terminal 102, a transmitting circuit 110, a receiving circuit 120, a first resistor 231, and a second resistor 232. The transmitting circuit 110 includes a programmable high-speed driver 111, a low-dropout linear regulator 112, a first switching circuit 113, a second switching circuit 114, a switcher 115, a first general-purpose input / output buffer 216, and a second general-purpose input / output buffer 217. The receiving circuit 120 includes a differential input amplifier circuit 221 and a common-mode voltage control circuit 222.

[0086] In this embodiment, the low-dropout linear regulator 112 is electrically connected to the programmable high-speed driver 111. The first terminal of the first resistor 231 is electrically connected to the first input / output terminal 101 and the receiving circuit 120. The first switching circuit 113 is electrically connected to the programmable high-speed driver 111 and the second terminal of the first resistor 231. The first terminal of the second resistor 232 is electrically connected to the second input / output terminal 102 and the receiving circuit 120. The second switching circuit 114 is electrically connected to the programmable high-speed driver 111 and the second terminal of the second resistor 232. The switch 115 is electrically connected to the first switching circuit 113 and the second switching circuit 114. The first general-purpose input / output buffer 216 is electrically connected to the second terminal of the first resistor 231 and the first switching circuit 113. The second general-purpose input / output buffer 217 is electrically connected to the second terminal of the second resistor 232 and the second switching circuit 114.

[0087] In this embodiment, the differential input amplifier circuit 221 is electrically connected to the first input / output terminal 101 and the second input / output terminal 102. The common-mode voltage control circuit 222 is electrically connected to the differential input amplifier circuit 221, the first input / output terminal 101, and the second input / output terminal 102.

[0088] In this embodiment, when the input / output circuit 100 operates to transmit data using the SerDes communication protocol, DDR communication protocol, or Low Voltage Differential Signaling (LVDS) communication protocol, the switch 115 can switch the first switching circuit 113 and the second switching circuit 114 to the on state according to the enable signal EN. Furthermore, the low dropout linear regulator 112 can receive the mode selection signal SEL to control the programmable high-speed driver 111 to perform impedance matching according to the mode selection signal SEL. The programmable high-speed driver 111 can implement ODT impedance matching corresponding to the current communication protocol, and generate a first transmit signal to the first switching circuit 113 according to the first data signal Din1, and a second transmit signal to the second switching circuit 114 according to the second data signal Din2. Furthermore, the switch 115 receives the enable signal EN and controls the first switch circuit 113 and the second switch circuit 114 to be in the on state according to the enable signal EN, so as to send data to the first input / output terminal 101 and the second input / output terminal 102 (that is, the first transmission signal and the second transmission signal are respectively transmitted to the first input / output terminal 101 and the second input / output terminal 102 via the first resistor 231 and the second resistor 232).

[0089] In this embodiment, when the input / output circuit 100 operates to transmit data in single-ended transmission mode using the General-Purpose Input / Output (GPIO) communication protocol, the switch 115 can switch the first switch circuit 113 and the second switch circuit 114 to the off state according to the enable signal EN. Furthermore, at least one of the first GPIO buffer 216 and the second GPIO buffer 217 can send data to at least one of the first input / output terminal 101 and the second input / output terminal 102.

[0090] It is worth noting that since the data transmission of the GPIO communication protocol is applied to the high-voltage domain, while the data transmission of the SerDes communication protocol, DDR communication protocol, or Low Voltage Differential Signaling (LVDS) communication protocol is applied to the lower-voltage domain, the first switching circuit 113 and the second switching circuit 114 can be high-voltage resistant switching circuits. Furthermore, the switcher 115 can be used to switch the enable signal EN from the low-voltage domain to the high-voltage domain to control the first switching circuit 113 and the second switching circuit 114. In this way, when the input / output circuit 100 operates for GPIO communication protocol data transmission, the first switching circuit 113 and the second switching circuit 114 can be switched to the off state to effectively protect the downstream programmable high-speed driver 111, the low-dropout linear regulator 112, and other related core circuit components operating in the low-voltage domain.

[0091] Furthermore, the high-voltage domain and low-voltage domain described in this embodiment are relative. The high-voltage domain described in this embodiment is used to represent the operating voltage of electronic components at a higher voltage than the low-voltage domain. The specific values ​​of the high-voltage domain and low-voltage domain may vary depending on the application of different circuit nodes, and may also be selected, for example, based on the device operating voltage of the Process Design Kit (PDK).

[0092] In this embodiment, the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217 can also be used to receive GPIO communication protocol data from the first input / output terminal 101 and the second input / output terminal 102, respectively. In this embodiment, the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217 can respectively receive or transmit GPIO communication protocol data. To this end, the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217 can respectively receive a transmit enable signal and a receive enable signal to determine whether the operation is in a transmit or receive state. Furthermore, the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217 can also be configured with a drive strength register to achieve the required drive current.

[0093] In this embodiment, when the input / output circuit 100 is used to receive data from the SerDes communication protocol or the DDR communication protocol, the differential input amplifier circuit 221 can receive differential signals from the first input / output terminal 101 and the second input / output terminal 102, convert them into corresponding data signals Dout, and then output them to the core circuit elements at the back end.

[0094] In this embodiment, when the input / output circuit 100 is used to receive data from the LVDS communication protocol, the common-mode voltage control circuit 222 can control the common-mode voltage at the input terminal of the differential input amplifier circuit 221 to match the data transmission of the LVDS communication protocol.

[0095] In this embodiment, the input / output circuit 100 can control the programmable high-speed driver 111 via the low-dropout linear regulator 112 to select the data transmission function in differential signal form of the SerDes communication protocol, DDR communication protocol, or Low Voltage Differential Signaling (LVDS) communication protocol. It can also select the data transmission function of the GPIO communication protocol via at least one of the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217. Furthermore, the input / output circuit 100 can also select the data reception function of the SerDes communication protocol, DDR communication protocol, LVDS communication protocol, or GPIO communication protocol via the receiving circuit 120. In addition, the input / output circuit 100 of this embodiment can effectively protect the back-end circuit components operating in the low-voltage domain via the high-voltage-resistant first switching circuit 113 and second switching circuit 114.

[0096] Figure 3 This is a schematic diagram of an input / output circuit according to another embodiment of the present invention. (See reference) Figure 3 The input / output circuit 100 includes a first input / output terminal 101, a second input / output terminal 102, a transmitting circuit 110, a receiving circuit 120, a first resistor 231, and a second resistor 232. The transmitting circuit 110 includes a programmable high-speed driver 111, a low-dropout linear regulator 112, a first switching circuit 113, a second switching circuit 114, a switcher 115, a first general-purpose input / output buffer 216, and a second general-purpose input / output buffer 217. The receiving circuit 120 includes a differential input amplifier circuit 221 and a common-mode voltage control circuit 222.

[0097] In this embodiment, the programmable high-speed driver 111 includes multiple driving units (e.g., first driving units 311_1 to Mth driving units 311_M, where M is a positive integer). The multiple driving units (e.g., first driving units 311_1 to Mth driving units 311_M) are connected in parallel and electrically connected to a first switching circuit 113 and a second switching circuit 114. In this embodiment, each of the multiple driving units (e.g., first driving units 311_1 to Mth driving units 311_M) includes a first transistor 3111, a second transistor 3112, a third transistor 3113, and a fourth transistor 3114. The first terminal of the first transistor 3111 is electrically connected to the output terminal of the multiplexer 3123 of the low-dropout linear regulator 112. The second terminal of the first transistor 3111 is electrically connected to the first switching circuit 113 (e.g., electrically connected to the first switching circuit 113 via its first output terminal outn). The control terminal of the first transistor 3111 receives a second data signal Din2. The first terminal of the second transistor 3112 is electrically connected to the first terminal of the first transistor 3111 and the output terminal of the multiplexer 3123 of the low-dropout linear regulator 112. The second terminal of the second transistor 3112 is electrically connected to the second switching circuit 114 (e.g., electrically connected to the second switching circuit 114 via the second output terminal outp). The control terminal of the second transistor 3112 receives the first data signal Din1. The first terminal of the third transistor 3113 is electrically connected to the second terminal of the first transistor 3111 and is also electrically connected to the first switching circuit 113 (e.g., electrically connected to the first switching circuit 113 via the first output terminal outn). The second terminal of the third transistor 3113 is grounded. The control terminal of the third transistor 3113 is electrically connected to the control terminal of the second transistor 3112 and receives the first data signal Din1. The first terminal of the fourth transistor 3114 is electrically connected to the second terminal of the second transistor 3112 and is also electrically connected to the second switching circuit 114 (e.g., electrically connected to the second switching circuit 114 via the second output terminal outp). The second terminal of the fourth transistor 3114 is grounded. The control terminal of the fourth transistor 3114 is electrically connected to the control terminal of the first transistor 3111 and receives the second data signal Din2.

[0098] In this embodiment, the low-dropout linear regulator 112 includes a first operational amplifier 3121, a fifth transistor 3122, a multiplexer 3123, a third resistor 3124, a first variable resistor 3125, and a fourth resistor 3126. The fifth transistor 3122 may be an N-type transistor. The first terminal (e.g., the non-inverting input terminal) of the first operational amplifier 3121 receives a first reference voltage Vref. The first terminal of the fifth transistor 3122 receives an operating voltage VDDH. The control terminal of the fifth transistor 3122 is electrically connected to the output terminal of the first operational amplifier 3121. The first input terminal of the multiplexer 3123 is electrically connected to the second terminal of the fifth transistor 3122. The control terminal of the multiplexer 3123 receives a mode selection signal SEL. The first terminal of the third resistor 3124 is electrically connected to the second terminal of the fifth transistor 3122 and the first input terminal of the multiplexer 3123. The second terminal of the third resistor 3124 is electrically connected to the second input terminal (e.g., the inverting input terminal) of the first operational amplifier 3121. The first terminal of the first variable resistor 3125 is electrically connected to the second terminal of the third resistor 3124 and the second input terminal of the first operational amplifier 3121. The second terminal of the first variable resistor 3125 is electrically connected to the second input terminal of the multiplexer 3123. The first terminal of the fourth resistor 3126 is electrically connected to the second terminal of the first variable resistor 3125 and the second input terminal of the multiplexer 3123. The second terminal of the fourth resistor 3126 is grounded.

[0099] In this embodiment, the first switching circuit 113 includes a sixth transistor 3131. The first terminal of the sixth transistor 3131 is electrically connected to a first resistor 231. The second terminal of the sixth transistor 3131 is electrically connected to the first output terminal (i.e., the aforementioned first output terminal outn) of each of the plurality of driving units (e.g., the first driving unit 311_1 to the Mth driving unit 311_M) of the programmable high-speed driver 111. The control terminal of the sixth transistor 3131 is electrically connected to a switch 115. The second switching circuit 114 includes a seventh transistor 3141. The first terminal of the seventh transistor 3141 is electrically connected to a second resistor 232. The second terminal of the seventh transistor 3141 is electrically connected to the second output terminal (i.e., the aforementioned second output terminal outp) of each of the plurality of driving units (e.g., the first driving unit 311_1 to the Mth driving unit 311_M) of the programmable high-speed driver 111. The control terminal of the seventh transistor 3141 is electrically connected to the switch 115. The sixth transistor 3131 and the seventh transistor 3141 can be N-type transistors.

[0100] In this embodiment, the first general-purpose input / output buffer 216 is electrically connected to the second terminal of the first resistor 231 and the second terminal of the sixth transistor 3131. The second general-purpose input / output buffer 217 is electrically connected to the second terminal of the second resistor 232 and the second terminal of the seventh transistor 3141.

[0101] In this embodiment, the differential input amplifier circuit 221 includes a differential input amplifier 3211, a second variable resistor 3212, and a third variable resistor 3213. The first input terminal (e.g., a non-inverting input terminal) of the differential input amplifier 3211 is electrically connected to the first input / output terminal 101 and the first terminal of the first resistor 231. The second input terminal (e.g., an inverting input terminal) of the differential input amplifier 3211 is electrically connected to the second input / output terminal 102 and the first terminal of the second resistor 232. The first terminal of the second variable resistor 3212 is electrically connected to the first input terminal of the differential input amplifier 3211. The first terminal of the third variable resistor 3213 is electrically connected to the second input terminal of the differential input amplifier 3211. The second terminal of the third variable resistor 3213 is electrically connected to the second terminal of the second variable resistor 3212.

[0102] In this embodiment, the common-mode voltage control circuit 222 includes a second operational amplifier 3221, a first current source 3222, and a second current source 3223. The first input terminal (e.g., a non-inverting input terminal) of the second operational amplifier 3221 receives the common-mode control voltage VCM. The second input terminal (e.g., an inverting input terminal) of the second operational amplifier 3221 is electrically connected to the second terminal of a second variable resistor 3212 and the second terminal of a third variable resistor 3213. The first current source 3222 is electrically connected to the output terminal of the second operational amplifier 3221. The first current source 3222 receives or is clamped to a second reference voltage V1 and is electrically connected between the second input terminal (e.g., an inverting input terminal) of the differential input amplifier 3211. The second current source 3223 is electrically connected between the first input terminal (e.g., a non-inverting input terminal) of the differential input amplifier 3211 and the ground terminal.

[0103] In this embodiment, when the input / output circuit 100 operates to transmit data using the SerDes communication protocol, DDR communication protocol, or Low Voltage Differential Signaling (LVDS) communication protocol, the switch 115 can switch at least one of the sixth transistor 3131 and the seventh transistor 3141 to the on state according to the enable signal EN. The multiplexer 3123 of the low dropout linear regulator 112 can receive the mode selection signal SEL to output the corresponding voltage signal according to the mode selection signal SEL. The multiplexer 3123 selectively outputs the voltage signal of circuit node N1 or circuit node N2 to multiple drive units (e.g., the first drive unit 311_1 to the Mth drive unit 311_M) according to the mode selection signal SEL. Next, the programmable high-speed driver 111 can determine, according to the digital control signal Drv_trm, to drive at least one of the multiple driving units (e.g., the first driving unit 311_1 to the Mth driving unit 311_M), to adjust the current output from the programmable high-speed driver 111 to the sixth transistor 3131 and the seventh transistor 3141, thereby achieving ODT impedance matching corresponding to the first data signal Din1 and the second data signal Din2, to effectively reduce or eliminate signal reflection. The programmable high-speed driver 111 can generate a first transmit signal to the sixth transistor 3131 and a second transmit signal to the seventh transistor 3141 according to the first data signal Din1 and the second data signal Din2, to further transmit data to the first input / output terminal 101 and the second input / output terminal 102 (i.e., the first transmit signal and the second transmit signal are transmitted to the first input / output terminal 101 and the second input / output terminal 102 via the first resistor 231 and the second resistor 232, respectively).

[0104] In this embodiment, when the input / output circuit 100 operates to transmit data in a single-ended transmission format using the GPIO communication protocol, the switch 115 can switch the sixth transistor 3131 and the seventh transistor 3141 to the off state according to the enable signal EN. Furthermore, at least one of the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217 can send data to at least one of the first input / output terminal 101 and the second input / output terminal 102.

[0105] It is worth noting that the sixth transistor 3131 and the seventh transistor 3141 can be designed as high-voltage resistant transistors, and the switch 115 can be used to switch the enable signal EN from the low-voltage domain to the high-voltage domain (e.g., from the core voltage VDDC to the operating voltage VDDH, where the operating voltage VDDH is higher than the core voltage VDDC) to control the sixth transistor 3131 and the seventh transistor 3141. In this way, when the input / output circuit 100 operates for data transmission using the GPIO communication protocol, the sixth transistor 3131 and the seventh transistor 3141 can be switched off to effectively protect the back-end programmable high-speed driver 111, the low-dropout linear regulator 112, and other related core circuit elements operating in the low-voltage domain.

[0106] In this embodiment, the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217 can also be used to receive GPIO communication protocol data from the first input / output terminal 101 and the second input / output terminal 102. In this embodiment, the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217 can respectively receive or transmit GPIO communication protocol data. To this end, the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217 can respectively receive a transmit enable signal and a receive enable signal to determine whether the operation is in a transmit or receive state. Furthermore, the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217 can also be configured with a drive strength register to achieve the required drive current.

[0107] In this embodiment, when the input / output circuit 100 operates to receive data using the SerDes communication protocol or the DDR communication protocol, the second operational amplifier 3221 may not receive the common-mode control voltage VCM, or the common-mode control voltage VCM may be 0 volts or disabled, and the resistances of the second variable resistor 3212 and the third variable resistor 3213 may be adjusted accordingly. Then, the differential input amplifier circuit 221 may receive differential signals from the first input / output terminal 101 and the second input / output terminal 102, convert them into the corresponding data signal Dout, and output them to the core circuit elements at the back end.

[0108] In this embodiment, when the input / output circuit 100 is used to receive data from the LVDS communication protocol, the second operational amplifier 3221 receives the common-mode control voltage VCM and determines to output a corresponding control signal to control the first current source 3222 and the second current source 3223 based on the voltage magnitude of the circuit node between the second variable resistor 3212 and the third variable resistor 3213, so as to adjust the input common-mode voltage of the differential input amplifier 3211, thereby operating to receive data from the LVDS communication protocol, and converting it into the corresponding data signal Dout before outputting it to the core circuit elements at the back end.

[0109] In this embodiment, the input / output circuit 100 can control the programmable high-speed driver 111 via the low-dropout linear regulator 112 to select the data transmission function in differential signal form of the SerDes communication protocol, DDR communication protocol, or Low Voltage Differential Signaling (LVDS) communication protocol. It can also select the data transmission function of the GPIO communication protocol via at least one of the first general-purpose input / output buffer 216 and the second general-purpose input / output buffer 217. Furthermore, the input / output circuit 100 can also select the data reception function of the SerDes communication protocol, DDR communication protocol, LVDS communication protocol, or GPIO communication protocol via the receiving circuit 120. In addition, the input / output circuit 100 of this embodiment can effectively protect the back-end circuit components operating in the low-voltage domain via the high-voltage-resistant first switching circuit 113 and second switching circuit 114.

[0110] In addition, the above Figure 1 and Figure 2 The internal circuitry of the input / output circuit 100 in this embodiment can be referred to... Figure 3 The specific circuit structure of the corresponding circuit is used to implement this.

[0111] Figure 4 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention. (Reference) Figure 4 The artificial intelligence chip 400 includes an input / output circuit 100, a core circuit 420, a first input / output pad 431, and a second input / output pad 432. The input / output circuit 100 is electrically connected to the core circuit 420. The first input / output pad 431 is electrically connected to the first input / output terminal of the input / output circuit 100. The second input / output pad 432 is electrically connected to the second input / output terminal of the input / output circuit 100.

[0112] In this embodiment, the input / output circuit 100 may have the features described above. Figure 1 , Figure 2 or Figure 3 The circuit architecture of the input / output circuit in the embodiment. For relevant implementation methods and technical details of the input / output circuit 100, please refer to the description of the general input / output circuits in the above embodiments, where sufficient teaching, suggestions, and implementation instructions can be obtained.

[0113] In this embodiment, the core circuit 420 can provide input data to the input / output circuit 100, and the input / output circuit 100 outputs corresponding data signals to the first input / output pad 431 and the second input / output pad 432 according to the corresponding communication protocol, so as to output corresponding data signals to external devices via the first input / output pad 431 and the second input / output pad 432. The input / output circuit 100 can receive data signals from external devices through the first input / output pad 431 and the second input / output pad 432, and provide corresponding data signals to the core circuit 420 according to the corresponding communication protocol.

[0114] The AI ​​chip 400 can be any one of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Tensor Processing Unit (TPU), Neural Network Processing Unit (NPU), Deep Learning Processing Unit (DPU), Accelerated Processing Unit (APU), and General-Purpose Graphics Processing Unit (GPGPU).

[0115] In summary, the input / output circuit and artificial intelligence chip of this invention are compatible with data transmission of different communication protocols in multiple scenarios. The input / output circuit of this invention can achieve data transmission functionality supporting multiple communication protocols through the two input / output pads (i.e., the two bumps after packaging) of the artificial intelligence chip, without changing the number of pads on the chip. Therefore, the input / output circuit and artificial intelligence chip of this invention have wide applicability and good robustness, and can be effectively applied to different products and various application scenarios.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An input / output circuit supporting multiple protocols, characterized in that, include: First input / output terminal; Second input / output terminal; The receiving circuit is electrically connected to the first input / output terminal and the second input / output terminal; as well as The transmitting circuit includes: Programmable high-speed driver; A low-dropout linear regulator is electrically connected to the programmable high-speed driver; A first switching circuit is electrically connected to the programmable high-speed driver and the first input / output terminal; A second switching circuit is electrically connected to the programmable high-speed driver and the second input / output terminal; and The switcher is electrically connected to the first switching circuit and the second switching circuit; The programmable high-speed driver includes multiple drive units connected in parallel and electrically connected to the first switching circuit and the second switching circuit. The programmable high-speed driver is used to determine, based on a digital control signal, to drive at least one of the multiple drive units.

2. The input / output circuit supporting multiple protocols according to claim 1, characterized in that, Also includes: A first resistor, the first end of which is electrically connected to the first input / output terminal and the receiving terminal circuit, and the second end of which is electrically connected to the first switching circuit. as well as The second resistor has its first end electrically connected to the second input / output terminal and the receiving terminal circuit, and its second end electrically connected to the second switching circuit.

3. The input / output circuit supporting multiple protocols according to claim 2, characterized in that, Also includes: A first general-purpose input / output buffer is electrically connected to the second terminal of the first resistor and the first switching circuit; as well as The second general-purpose input / output buffer is electrically connected to the second terminal of the second resistor and the second switching circuit.

4. The input / output circuit supporting multiple protocols according to claim 2, characterized in that, The low-dropout linear regulator is used to receive the mode selection signal, and the programmable high-speed driver is used to receive the first data signal and the second data signal. The low-dropout linear regulator is used to control the programmable high-speed driver to perform impedance matching according to the mode selection signal, and the programmable high-speed driver is used to generate a first transmit signal to the first switching circuit according to the first data signal and to generate a second transmit signal to the second switching circuit according to the second data signal.

5. The multi-protocol input / output circuit according to claim 4, characterized in that, Each of the plurality of drive units includes: A first transistor, the first terminal of which is electrically connected to the low dropout linear regulator, the second terminal of which is electrically connected to the first switching circuit, and the control terminal of the first transistor receiving the second data signal; The second transistor has its first terminal electrically connected to the first terminal of the first transistor and the low-dropout linear regulator, its second terminal electrically connected to the second switching circuit, and its control terminal receiving the first data signal. A third transistor, wherein a first terminal of the third transistor is electrically connected to a second terminal of the first transistor and the first switching circuit, the second terminal of the third transistor is grounded, and the control terminal of the third transistor electrically receives the first data signal; and A fourth transistor, the first terminal of which is electrically connected to the second terminal of the second transistor and the second switching circuit, the second terminal of which is grounded, and the control terminal of which receives the second data signal.

6. The input / output circuit supporting multiple protocols according to claim 5, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are N-type transistors.

7. The input / output circuit supporting multiple protocols according to claim 4, characterized in that, The low-dropout linear regulator includes: A first operational amplifier, wherein a first terminal of the first operational amplifier receives a reference voltage; A fifth transistor, wherein the first terminal of the fifth transistor receives an operating voltage, and the control terminal of the fifth transistor is electrically connected to the output terminal of the first operational amplifier; A multiplexer, wherein the first input terminal of the multiplexer is electrically connected to the second terminal of the fifth transistor, and the control terminal of the multiplexer receives the mode selection signal; The third resistor has its first end electrically connected to the second end of the fifth transistor and the first input end of the multiplexer, and its second end electrically connected to the second input end of the first operational amplifier. A first variable resistor, the first terminal of which is electrically connected to the second terminal of the third resistor and the second input terminal of the first operational amplifier, and the second terminal of the first variable resistor is electrically connected to the second input terminal of the multiplexer; and A fourth resistor, the first end of which is electrically connected to the second end of the first variable resistor and the second input terminal of the multiplexer, and the second end of the fourth resistor is grounded.

8. The input / output circuit supporting multiple protocols according to claim 7, characterized in that, The fifth transistor is an N-type transistor.

9. The multi-protocol input / output circuit according to claim 4, characterized in that, The first switching circuit includes a sixth transistor, the first terminal of which is electrically connected to the first resistor, the second terminal of which is electrically connected to the programmable high-speed driver, and the control terminal of which is electrically connected to the switch. The second switching circuit includes a seventh transistor, the first terminal of which is electrically connected to the second resistor, the second terminal of which is electrically connected to the programmable high-speed driver, and the control terminal of which is electrically connected to the switch.

10. The multi-protocol input / output circuit according to claim 9, characterized in that, The sixth transistor and the seventh transistor are N-type transistors.

11. The input / output circuit supporting multiple protocols according to claim 9, characterized in that, The switch is used to receive an enable signal to control the sixth transistor to output the first transmit signal to the first input / output terminal according to the enable signal, and to control the seventh transistor to output the second transmit signal to the second input / output terminal according to the enable signal.

12. The input / output circuit supporting multiple protocols according to claim 11, characterized in that, The switch is used to convert the enable signal from the low voltage domain to the high voltage domain and output it to the control terminal of the sixth transistor and the control terminal of the seventh transistor.

13. The input / output circuit supporting multiple protocols according to claim 1, characterized in that, The receiving circuit includes: The differential input amplifier circuit is electrically connected to the first input / output terminal and the second input / output terminal.

14. The multi-protocol input / output circuit according to claim 13, characterized in that, The receiving circuit also includes: A common-mode voltage control circuit is electrically connected to the first input / output terminal and the second input / output terminal.

15. The multi-protocol input / output circuit according to claim 14, characterized in that, The differential input amplifier circuit includes: A differential input amplifier, wherein the first input terminal of the differential input amplifier is electrically connected to the first input output terminal, and the second input terminal of the differential input amplifier is electrically connected to the second input output terminal; A second variable resistor, the first terminal of which is electrically connected to the first input terminal of the differential input amplifier; and A third variable resistor, the first end of which is electrically connected to the second input terminal of the differential input amplifier, and the second end of which is electrically connected to the second end of the second variable resistor.

16. The multi-protocol input / output circuit according to claim 15, characterized in that, The common-mode voltage control circuit includes: A second operational amplifier, wherein the first input terminal of the second operational amplifier receives a common-mode control voltage, and the second input terminal of the second operational amplifier is electrically connected to the second terminal of the second variable resistor and the second terminal of the third variable resistor; A first current source is electrically connected to the output terminal of the second operational amplifier and the second input terminal of the differential input amplifier; and The second current source is electrically connected to the output terminal of the second operational amplifier and the first input terminal of the differential input amplifier.

17. An artificial intelligence chip, characterized in that, include: Core circuit; Input / output circuits are electrically connected to the core circuit. The first input / output pad is electrically connected to the first input / output terminal of the input / output circuit; as well as The second input / output pad is electrically connected to the second input / output terminal of the input / output circuit. The input / output circuit includes: The transmitting circuit includes: Programmable high-speed driver; A low-dropout linear regulator is electrically connected to the programmable high-speed driver; A first switching circuit is electrically connected to the programmable high-speed driver and the first input / output terminal; A second switching circuit is electrically connected to the programmable high-speed driver and the second input / output terminal; and The switcher is electrically connected to the first switching circuit and the second switching circuit; and The receiving circuit is electrically connected to the first input / output terminal and the second input / output terminal; The programmable high-speed driver includes multiple drive units connected in parallel and electrically connected to the first switching circuit and the second switching circuit. The programmable high-speed driver is used to determine, based on a digital control signal, to drive at least one of the multiple drive units.

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