Serial communication method and electronic device

Abstract

The application discloses a serial communication method and an electronic device, relates to the technical field of I2C communication, and comprises the following steps: generating a plurality of operation data packets based on a serial communication task message; reading each operation data packet according to the execution time sequence of each operation step corresponding to the plurality of operation data packets; configuring a hardware register according to operation information corresponding to the read operation data packet; enabling an external device to read the operation information from the hardware register through a serial communication bus and execute corresponding operation; enabling a processor to exit the current operation after completing the configuration of the hardware register; enabling the processor to continue to read a next operation data packet after detecting that the external device has completed the execution of the corresponding operation based on the operation information; and enabling the processor to complete the processing of the plurality of operation data packets until the serial communication process is completed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Inter-Integrated Circuit (I2C) communication, and particularly relates to a serial communication method and an electronic device. BACKGROUND

[0002] In a running process of an enterprise-level solid state disk, multiple sensors need to be called to ensure a stable running environment. For example, if the current device temperature runs to a high temperature, part of the functions of the device need to be limited, such as reducing the read-write processing speed and the like, in this scenario, the processor and the temperature sensor need to communicate.

[0003] Generally, the processor depends on an I2C communication bus to read the data collected by the sensor, and the bus is a synchronous communication bus, in the process of communication, the processor cannot jump to other task execution, which will cause the system resources to be occupied in the data transmission process, and further affect the read-write performance of the enterprise-level solid state disk, and finally may interfere with the continuity and efficiency of the customer business. SUMMARY

[0004] The present application provides a serial communication method and an electronic device, to at least solve the problem of poor read-write performance of the enterprise-level solid state disk caused by the synchronous communication transmission process occupying system resources when the processor depends on the I2C communication bus to read the data collected by the sensor in the related technology.

[0005] The present application provides a serial communication method, comprising:

[0006] Based on a serial communication task message, a plurality of operation data packets are generated, and the operation steps corresponding to the plurality of operation data packets constitute a serial communication process;

[0007] According to the execution time sequence of each operation step corresponding to the plurality of operation data packets, the plurality of operation data packets are read in turn;

[0008] Operation information corresponding to the current operation data packet read is obtained, and a hardware register is configured based on the operation information, so that an external device reads the operation information from the hardware register through a serial communication bus and performs a corresponding operation;

[0009] Wherein, the processor jumps out of the current operation after the configuration of the hardware register is completed, and continues to read the next operation data packet after detecting that the external device performs the corresponding operation based on the operation information, and configures the hardware register based on the operation information of the next operation data packet, until the plurality of operation data packets are all processed.

[0010] The present application also provides a serial communication device, comprising:

[0011] The task decomposition module is used to generate multiple operation data packets based on serial communication task messages. The operation steps corresponding to the multiple operation data packets constitute a serial communication process.

[0012] The data packet reading module is used to read the multiple operation data packets sequentially according to the execution sequence of each operation step corresponding to the multiple operation data packets;

[0013] The configuration module is used to obtain the operation information corresponding to the current operation data packet being read, and to configure the hardware register based on the operation information, so that the external device can read the operation information from the hardware register through the serial communication bus and execute the corresponding operation;

[0014] After configuring the hardware registers, the processor exits the current operation and continues to read the next operation data packet after detecting that the external device has completed the corresponding operation based on the operation information. The processor then configures the hardware registers based on the operation information of the next operation data packet until all the operation data packets have been processed.

[0015] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described serial communication methods when executing the computer program.

[0016] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described serial communication methods.

[0017] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described serial communication methods.

[0018] This application achieves the decomposition of a single serial communication process into multiple operation data packets by generating multiple operation data packets based on serial communication task messages. Then, each operation data packet is read according to its execution sequence, and hardware registers are configured based on the operation information corresponding to the read operation data packets. This allows external devices to read operation information from the hardware registers via the serial communication bus and execute corresponding operations. After configuring the hardware registers, the processor exits the current operation. It continues reading the next operation data packet and configuring the hardware registers based on the operation information of the next operation data packet after detecting that the external device has completed its corresponding operation. This process continues until all operation data packets have been processed, completing one serial communication process. Thus, a single serial communication process is decomposed into multiple operation data packets. The operation steps are executed, and the current operation is exited after the hardware registers are configured. This allows the processor to perform other tasks during serial communication. Once the current operation is completed, it returns to the serial communication process to continue reading the next data packet without waiting for the entire serial communication process to finish. This fully utilizes the waiting time wasted by the processor waiting for external devices to complete their operations, thereby reducing the overall communication time. This effectively alleviates the constraint of serial communication on hard drive read / write performance and reduces the impact of synchronous communication on I / O, thus helping to improve the overall performance of the hard drive. Therefore, it can solve the technical problem of poor read / write performance of enterprise-level solid-state drives caused by the synchronous communication transmission process occupying system resources when the processor relies on the I2C communication bus to read data collected by sensors. This achieves the technical effect of improving the overall performance of the hard drive and improving the quality of product services. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the communication process of I2C communication in related technologies is shown;

[0021] Figure 2 A simplified diagram illustrating each step in I2C communication is shown.

[0022] Figure 3 A flowchart illustrating a serial communication method provided in an exemplary embodiment of this application;

[0023] Figure 4 A flowchart illustrating a serial communication method provided as another exemplary embodiment of this application;

[0024] Figure 5A schematic diagram of the data structure of multiple operation data packets according to an exemplary embodiment of this application is shown;

[0025] Figure 6 A flowchart illustrating a serial communication method provided in yet another exemplary embodiment of this application;

[0026] Figure 7 This illustration shows a flowchart of an I2C hardware peripheral processing module processing operation data packets according to an exemplary embodiment of this application.

[0027] Figure 8 This diagram illustrates how the complete operation steps of I2C synchronous communication are broken down into multiple minimum communication steps in this application.

[0028] Figure 9 This is a schematic diagram of the structure of a serial communication device provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0030] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0031] Enterprise-grade SSDs require a stable operating environment. For example, if the device temperature reaches a high level, some functions need to be limited, such as reducing read and write speeds. Furthermore, according to the NVMe (Non-Volatile Memory Express) protocol, users can limit the device's maximum power consumption by issuing management commands. In both of these scenarios, communication is required between the processor and temperature / power sensors, respectively. Generally, this communication is based on the I2C communication bus, a synchronous communication bus that requires the processor to prevent it from switching to other tasks during communication. A critical performance metric for enterprise-grade SSDs is Quality of Service (QoS). This metric indicates the quality of the hard drive server; frequent processor lock-ins can lead to excessively high QoS scores, impacting customer business processing efficiency. Therefore, optimizing I2C communication between sensors is crucial.

[0032] Figure 1 This diagram illustrates the communication process of I2C communication in related technologies, such as... Figure 1 As shown, the current I2C communication process includes the following steps: (1) Send the start bit through the I2C bus; (2) Send the slave address and mark the subsequent operation as a write operation; (3) Wait for the slave to reply with an acknowledgment signal (ACK). There is usually a timeout during this stage; (4) If there is no timeout, send the slave register address, which indicates which data the master wants to read from the slave; (5) Wait for the slave to reply with an ACK; (6) Send the restart bit through the I2C bus; (7) Send the slave address and mark the subsequent operation as a read operation, and wait for an ACK; (8) Read the slave data; (9) Process the data after reading and perform data conversion; (10) Send the end bit through the I2C bus.

[0033] In the aforementioned communication process, operations such as writing, reading, starting, ending, and restarting are all performed by the processor hardware unit. For the processor, this only requires configuring the corresponding registers of the hardware unit. Therefore, each step can be simply written as follows: Figure 2 The process shown includes the following steps: (1) configuring a hardware register of the I2C hardware peripheral; (2) polling a status register of the I2C hardware peripheral and waiting for the hardware register operation to complete. In actual applications, most of the time is spent waiting for the hardware register operation to complete, resulting in a long processor occupation time and affecting the read and write performance of enterprise-level solid-state drives.

[0034] To address the aforementioned issues, this application provides a serial communication scheme applicable to the I2C communication process of solid-state drives. By splitting the I2C communication operation into multiple step-by-step operations, step-by-step communication of I2C peripherals is achieved. This breaks down the originally concentrated communication time into minimized operation time slices, reducing the impact of synchronous communication on input / output (I / O). It effectively alleviates the constraints of sensor communication on hard drive read / write performance and improves the product's QoS performance indicators. This solution helps to significantly improve the overall performance and market competitiveness of the product.

[0035] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] This application provides a serial communication method, which can be executed by a serial communication device provided in this application. This device can be implemented in software and / or hardware and can be integrated into an electronic device, such as a device containing a solid-state drive (SSD), an enterprise-grade SSD, etc., and can specifically be applied to the processor of an electronic device. The method is described in detail below with reference to its execution flow.

[0037] Figure 3 A flowchart illustrating a serial communication method provided in an exemplary embodiment of this application is shown below. Figure 3 As shown, the serial communication method may include the following steps:

[0038] Step 101: Based on the serial communication task message, generate multiple operation data packets. The operation steps corresponding to the multiple operation data packets constitute a serial communication process.

[0039] A serial communication task message represents a serial communication task, such as reading data from a sensor or writing data to an external device. A serial communication task can be a task based on an I2C communication bus. The message structure of a serial communication task message includes the following data: target device address, target register address, target operation identifier, data length, and data address. The target device address represents the device address of the external device to be read / written; the target register address represents the address of the external device where data is being read or written; the target operation identifier indicates whether a read or write operation is performed; the data length is the length of the data to be read or written; and the data address is the data storage address on the processor side.

[0040] In this embodiment, the serial communication task message contains relevant information about the serial communication task, such as the target device address and target operation identifier. This information can be obtained by parsing the serial communication task message, and multiple operation data packets can be generated based on the obtained information. Each operation data packet corresponds to a minimum operation step in the serial communication task, such as Start, End, Restart, Read, or Write. All the operation steps corresponding to the generated multiple operation data packets constitute one serial communication process. The operation step corresponding to each operation data packet can be determined by the operation identifier contained in the operation data packet. By generating multiple operation data packets, a complete I2C synchronous communication process is broken down into multiple minimum communication steps, allowing a single communication operation to be completed in multiple steps.

[0041] Step 102: Read multiple operation data packets sequentially according to the execution sequence of each operation step corresponding to the multiple operation data packets.

[0042] In this embodiment, for the generated multiple operation data packets, the multiple operation data packets can be read sequentially according to the execution sequence of each operation step corresponding to the multiple operation data packets. For example, if the operation steps corresponding to the multiple operation data packets are Start, End, and Read, and the execution sequence of these operation steps is Start→Read→End, then the reading order of the multiple data packets is as follows: operation data packet containing the Start operation identifier, operation data packet containing the Read operation identifier, and operation data packet containing the End operation identifier. Then, the operation data packets are read sequentially according to the reading order of each operation data packet, and only one operation data packet is read at a time.

[0043] Step 103: Obtain the operation information corresponding to the current operation data packet, and configure the hardware register based on the operation information so that the external device can read the operation information from the hardware register and execute the corresponding operation through the serial communication bus; wherein, after the processor completes the configuration of the hardware register, it exits the current operation, and continues to read the next operation data packet and configure the hardware register based on the operation information of the next operation data packet after detecting that the external device has completed the corresponding operation based on the operation information, until multiple operation data packets have been processed.

[0044] In this embodiment, for the currently read operation data packet (referred to as the current operation data packet), operation information can be obtained from the current operation data packet. The operation information includes an operation identifier, which indicates whether the corresponding operation is Start, End, Restart, read, or write. For write operations, the operation information may also include the data to be written. Next, hardware registers (control registers) can be configured based on the operation information so that external devices can read the operation information from the hardware registers and execute the corresponding operation via the serial communication bus.

[0045] In I2C communication, each I2C slave device (i.e., an external device, such as a sensor, electrically erasable programmable read-only memory (EEPROM), real-time clock (RTC), etc.) has a unique device address (usually a 7-bit or 10-bit address) used for identification and addressing by the master device (i.e., the processor) on the bus. In this embodiment, the processor can obtain the device address of the external device to be accessed from the serial communication task message, and then determine the hardware register of the external device corresponding to that device address. After obtaining the operation information, the processor can configure the corresponding hardware register based on the obtained operation information, configuring the operation identifier, the data to be written, and / or the register address in the hardware register. The external device can obtain the operation information from the hardware register through the serial communication bus (I2C bus) and execute the corresponding operation according to the operation information.

[0046] In this embodiment, after configuring the hardware registers, the processor exits the current operation and can perform other tasks while waiting for the external device to execute its operation, thus ensuring the performance of the electronic device. The processor can periodically or intermittently detect whether the external device has completed its current operation. Once it detects that the external device has completed the corresponding operation based on the operation information, it continues to read the next operation data packet and configure the hardware registers based on the operation information of the next operation data packet. This process is repeated until multiple operation data packets have been processed, at which point the current serial communication process ends, and the serial communication task represented by the serial communication task message is completed. Afterward, the processor can continue to acquire and process the next serial communication task message until no more serial communication task messages are received.

[0047] The serial communication method in this application, by generating multiple operation data packets based on serial communication task messages, decomposes a serial communication process into operation steps corresponding to multiple operation data packets. Then, it reads each operation data packet according to the execution sequence of each operation step corresponding to the multiple operation data packets, configures hardware registers based on the operation information corresponding to the read operation data packets, enabling external devices to read operation information from the hardware registers via the serial communication bus and execute corresponding operations. After the processor completes the hardware register configuration, it exits the current operation. It continues to read the next operation data packet and configure hardware registers based on the operation information of the next operation data packet after detecting that the external device has completed the corresponding operation, until all multiple operation data packets have been processed, completing one serial communication process. Thus, a serial communication process is decomposed into... The solution involves executing multiple operation steps and exiting the current operation immediately after configuring the hardware registers. This allows the processor to perform other tasks during serial communication. Once the current operation is complete, it returns to the serial communication process to continue reading the next data packet, without waiting for the entire serial communication process to finish. This fully utilizes the waiting time wasted by the processor waiting for external devices to complete their operations, thereby reducing the overall communication time. This effectively alleviates the constraint of serial communication on hard drive read / write performance and reduces the impact of synchronous communication on I / O, contributing to improved overall hard drive performance. Therefore, it can solve the technical problem of poor read / write performance of enterprise-level solid-state drives caused by the synchronous communication transmission process occupying system resources when the processor relies on the I2C communication bus to read data collected by sensors, achieving the technical effect of improving overall hard drive performance and enhancing product service quality.

[0048] In one alternative embodiment of this application, such as Figure 4 As shown, based on the foregoing embodiments, step 101 may include the following sub-steps:

[0049] Step 201: Parse the serial communication task message to obtain the target operation identifier and operation object information carried in the serial communication task message.

[0050] The target operation identifier is used to indicate a read or write operation, and the operation object information may include the data to be written.

[0051] In this embodiment, the acquired serial communication task message is parsed, and the target operation identifier and operation object information can be obtained based on the information carried by each message structure of the serial communication task message.

[0052] Step 202: Obtain the preset control operation identifier.

[0053] Among them, the control operation identifier is used to indicate the control operation. One control operation identifier corresponds to a unique control operation. The control operations include Start, End and Restart.

[0054] Step 203: According to the preset data structure, generate multiple operation data packets based on the target operation identifier, control operation identifier, and operation object information. Each operation data packet includes a target operation identifier or a control operation identifier.

[0055] The data structure includes a control operation field, a read / write operation field, a data field, and an acknowledgment signal configuration field. The control operation field indicates whether the operation corresponding to the operation data packet is a control operation. This status bit can only be set for the three bus control operations: Start, End, and Restart. For example, the control operation field is set to 1 for a control operation and 0 for a read / write operation. The read / write operation field indicates whether the operation corresponding to the operation data packet is a read or write operation. The data field indicates the type of control operation (i.e., which of the three operations: Start, End, or Restart) or the data to be written (i.e., the data to be sent to the bus) for a write operation. The data field is invalid for read operations. The acknowledgment signal configuration field configures the acknowledgment signal information for read or write operations. For write operations, the acknowledgment signal configuration information indicates whether to wait for an ACK; for read operations, it indicates whether to send an ACK. By setting the data structure of the operation data packet, conditions are provided for generating operation data packets in a unified format, and this unified format facilitates the processor's reading of data from the operation data packets.

[0056] In this embodiment, after obtaining the target operation identifier, operation object information, and control operation identifier, multiple operation data packets can be generated based on this information according to a preset data structure. Each operation data packet includes either a target operation identifier or a control operation identifier; that is, one operation data packet corresponds to one operation step. When generating an operation data packet, a control operation identifier can be filled into a data field, and the value of the control identifier field can be set to indicate that the operation is a control operation (e.g., 1), thus generating one operation data packet. A target operation identifier can be filled into a read / write field, and when the target operation identifier indicates that the operation is a write operation, the data to be written can be filled into the data field. The value of the control identifier field can be set to indicate that the operation is not a control operation (e.g., 0). Furthermore, the acknowledgment signal configuration information in the acknowledgment signal configuration field can be set according to whether ACK waiting is required. For example, the generated multiple operation data packets are as follows: Figure 5 As shown.

[0057] The serial communication method of this application embodiment obtains the target operation identifier and operation object information carried in the serial communication task message by parsing the serial communication task message, and obtains the preset control operation identifier. Then, according to the preset data structure, multiple operation data packets are generated based on the target operation identifier, control operation identifier, and operation object information. Thus, multiple operation data packets can be obtained by parsing a serial communication task message, realizing the splitting of a serial communication process into multiple operation steps, laying the foundation for completing a communication work in multiple steps.

[0058] Furthermore, in one optional embodiment of this application, in such... Figure 4 Based on the illustrated embodiment, when acquiring the operation information corresponding to the currently read operation data packet and configuring the hardware register based on the operation information, the operation information corresponding to the currently read operation data packet can be acquired. This operation information includes an operation identifier, and for write operation steps, it also includes the data to be written. Then, if the operation identifier in the operation information is a control operation identifier, the operation identifier is configured in the hardware register. That is, if the operation identifier in the operation information acquired from the currently read operation data packet is a control operation identifier, then the operation step corresponding to the currently read operation data packet is a control operation, i.e., one of Start, End, or Restart. In this case, configuring the operation identifier in the operation information in the hardware register is sufficient to inform the external device that the operation step is Start, End, or Restart.

[0059] Optionally, if the operation identifier in the operation information is a read operation identifier, then the read operation identifier is configured in a hardware register.

[0060] As mentioned above, if an operation data packet includes a target operation identifier as a write operation identifier, meaning the operation step corresponding to the operation data packet is a write operation, then the operation data packet also includes operation object information, which is the data to be written. Therefore, in an optional embodiment of this application, after obtaining the operation information corresponding to the current operation data packet, the method further includes: if the operation identifier in the operation information is a write operation identifier, configuring the operation information in a hardware register, wherein the operation information includes a write operation identifier and operation object information. That is, for an operation data packet whose corresponding operation step is a write operation, the obtained operation information includes a write operation identifier and operation object information. In this case, the write operation identifier and operation object information are configured in the hardware integrator to inform the external device that a write operation needs to be performed and the data to be written.

[0061] In this embodiment, by obtaining the operation information corresponding to the current operation data packet, if the operation identifier in the operation information is a control operation identifier, the operation identifier is configured in the hardware register; if the operation identifier in the operation information is a write operation identifier, the operation information (including the write operation identifier and operation object information) is configured in the hardware register. Thus, the hardware register configuration corresponding to each operation step is realized, so that the external device can know the operation steps to be executed and execute them by accessing the hardware register, thereby realizing the step-by-step execution of a serial communication process.

[0062] In one alternative embodiment of this application, such as Figure 6 As shown, based on the foregoing embodiments, the serial communication method may further include the following steps:

[0063] Step 301: Access the status register of the external device according to a preset time period to check whether the target flag bit of the corresponding operation in the status register is set. If the target flag bit is set, it means that the corresponding operation has been completed.

[0064] The preset time period can be set according to actual needs, and the specific time period depends on the product application. This application does not restrict the specific value of the time period. Generally, the length of the time period is less than the time required for the external device to perform the operation.

[0065] Each external device has its own status register to reflect its current working status or operating result. When the external device finishes its operation, it automatically updates the status register for the processor to query. In this embodiment, after configuring the hardware registers and exiting the current operation, the processor can access the external device's status register at a preset time interval to check whether the target flag bit of the corresponding operation in the status register is set. A set target flag bit indicates that the corresponding operation has been completed. In this embodiment, for different operations in I2C communication, corresponding flag bits can be set in the status register, with one flag bit for each operation to reflect whether the operation has been completed. When a flag bit is set (e.g., set to 1, the default is 0), it indicates that the corresponding operation has ended.

[0066] Step 302: If the target flag is detected to be set, determine that the external device has completed the corresponding operation based on the operation information.

[0067] In this embodiment, the target flag bit of the corresponding operation in the status register is periodically checked to see if it is set. If the target flag bit is detected as set, it is determined that the external device has completed the corresponding operation based on the operation information, and the next operation data packet is read. If the target flag bit is detected as not set, it means that the external device has not completed the operation. The processor then continues to execute other tasks and accesses the external device's status register again when the next time period arrives, until it is determined that the external device has completed the corresponding operation based on the operation information.

[0068] In one optional embodiment of this application, if the corresponding operation performed by the external device based on the operation information is a write operation, before determining that the external device has completed the corresponding operation based on the operation information, acknowledgment signal configuration information can be obtained from the current operation data packet. If the acknowledgment signal configuration information indicates that an acknowledgment signal from the external device needs to be waited for, it is further determined whether an acknowledgment signal from the external device has been received. In response to receiving an acknowledgment signal from the external device, it is determined that the external device has completed the write operation based on the operation information. That is, when the operation performed by the external device is a write operation, if the target flag corresponding to the write operation is set in the external device's status register, and an acknowledgment signal from the external device is received while waiting for it, it is determined that the external device has completed the write operation based on the operation information. Further, if the acknowledgment signal configuration information indicates that an acknowledgment signal from the external device needs to be waited for, and the processor does not receive an ACK from the external device, then in response to not receiving an acknowledgment signal from the external device, the current serial communication process ends, and the next serial communication task message is obtained for processing. Thus, in write operations, when an external device returns an ACK, the system only confirms the successful completion of the communication and continues reading the next data packet upon receiving the ACK from the external device. This ensures successful data writing and allows the serial communication process to end promptly if an ACK is not received from the external device, avoiding wasted communication time due to prolonged waiting for the ACK signal.

[0069] The serial communication method of this application accesses the status register of an external device according to a preset time period to query whether the target flag bit of the corresponding operation in the status register is set. The target flag bit being set indicates that the corresponding operation has been completed. When the target flag bit is detected to be set, it is determined that the external device has completed the corresponding operation based on the operation information. Therefore, by querying whether the target flag bit of the corresponding operation in the status register is set, the execution status of the operation can be known in a timely manner, so that the next operation data packet can be obtained and processed in a timely manner after the execution is completed, which helps to shorten the communication time and improve the communication efficiency.

[0070] In practical applications, an independent I2C communication unit can be designed, which will handle all operations requiring I2C interaction. This unit can specifically include the following modules: IPC interaction module, IPC message processing module, and I2C hardware peripheral processing module.

[0071] The IPC interaction module is responsible for message interaction with other modules. Specifically, it establishes a request queue and a completion queue based on a First-In-First-Out (FIFO) mechanism. The request queue stores pending serial communication task messages, while the completion queue stores the execution results of the corresponding serial communication tasks. When there are pending messages in the request queue, a serial communication task message is retrieved, parsed, and the parsed data is handed over to the IPC message processing module for processing. Additionally, the IPC interaction module returns the results processed by the I2C hardware peripheral processing module to the task module that initiated the corresponding serial communication task message via Inter-Process Communication (IPC). This stage implements two specific message structures: the request message must contain at least the following data: target device address, target register address, target operation (read / write), data length, and data address; the return message must contain at least the following data: target device address, target register address, target operation (read / write), data length, data address, and operation completion status.

[0072] The IPC message processing module is responsible for the conversion between IPC messages and I2C messages. This includes retrieving valid messages from the parsed data sent by the IPC interaction module, generating multiple operation data packets, and handing these operation data packets over to the I2C hardware peripheral processing module for processing. This module ensures that only one valid communication is in progress at a time; that is, the IPC message processing module sends one operation data packet to the I2C hardware peripheral processing module at a time. The module then packages the processing result from the I2C hardware peripheral processing module into an IPC completion message and returns it to the IPC interaction module. The IPC interaction module stores the completion message in a completion queue for the task module to read.

[0073] The I2C hardware peripheral processing module is responsible for sending access sequences to the I2C bus according to a specific timing sequence, enabling inter-hardware communication. Specifically, the I2C hardware peripheral processing module sends the corresponding operation to the I2C bus through the hardware peripheral according to a certain clock cycle (i.e., time period, the specific clock cycle depends on the product application). Through the module structure in this example, the task module can send task requests to access external devices via IPC messages. Each module, through the above process, can convert IPC messages into operation data packets containing the minimum operation steps of I2C communication and process them one by one. This achieves step-by-step communication of I2C peripherals, reduces the impact of synchronous communication on I / O, improves the product's QoS performance indicators, and enhances product competitiveness.

[0074] The specific processing flow of an operation data packet by the I2C hardware peripheral processing module is as follows: Figure 7 As shown, the main steps include:

[0075] 1. Retrieve a control data (i.e., an operation data packet);

[0076] 2. Determine whether the control operation field of the current data is a control bit. If it is a control bit, the operation corresponding to the currently read operation data packet is a control operation, and then continue to the next step (step 3); otherwise, proceed to step 4.

[0077] 3. Determine which of the three operations (Start, End, Restart) it is based on the data field of the current data, then send the corresponding operation to the I2C bus, exit and wait for the next cycle;

[0078] 4. Determine whether it is a read operation or a write operation. If it is a read operation, proceed to step 5; otherwise, proceed to step 6.

[0079] 5. Read peripheral hardware registers. If the reading needs to continue, send an ACK operation; otherwise, exit the current communication.

[0080] 6. Write operation: Configure peripheral hardware registers, exit the current operation, wait for the next tick, determine whether a hardware ACK is needed, if an ACK is needed, proceed to the next operation (i.e., step 7), otherwise retrieve the next control data;

[0081] 7. If an ACK is received, retrieve the next control data and continue communication;

[0082] 8. If no ACK is received, the current communication will be reported as an error (failure), the current communication will be terminated, the message will be returned to the IPC message processing module for processing, and the next IPC message will begin to be processed.

[0083] Optionally, in a Real-Time Operating System (RTOS) scenario, the communication mechanism between the modules of the aforementioned I2C communication unit can be modified from IPC to a mailbox communication mechanism to avoid redesign.

[0084] In summary, the serial communication scheme of this application breaks down the complete operation steps of I2C synchronous communication into multiple minimal communication steps, such as... Figure 8 As shown, the configuration of I2C hardware peripherals is broken down into: after configuring the hardware registers, the waiting operation hardware operation is completed, and then the next step is started and executed. In this way, a communication operation is completed in multiple steps, and the operation time of I2C hardware peripherals and the processor waiting time are concurrently combined. This makes full use of the processor time wasted due to the I2C bus waiting time, reduces the overall communication time, solves the impact of sensor access on hard disk performance, and improves the overall performance of the product.

[0085] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0086] Embodiments of this application also provide a serial communication device, which can be implemented in software and / or hardware and can be integrated into an electronic device.

[0087] Figure 9 This is a schematic diagram of the structure of a serial communication device provided in an embodiment of this application, as shown below. Figure 9 As shown, the serial communication device 50 includes: a task decomposition module 510, a data packet reading module 520, and a configuration module 530.

[0088] Among them, the task decomposition module 510 is used to generate multiple operation data packets based on serial communication task messages, and the operation steps corresponding to the multiple operation data packets constitute a serial communication process.

[0089] The data packet reading module 520 is used to read multiple operation data packets sequentially according to the execution sequence of each operation step corresponding to multiple operation data packets;

[0090] The configuration module 530 is used to obtain the operation information corresponding to the current operation data packet being read, and to configure the hardware register based on the operation information, so that the external device can read the operation information from the hardware register through the serial communication bus and execute the corresponding operation.

[0091] After configuring the hardware registers, the processor exits the current operation and continues to read the next operation data packet after detecting that the external device has completed the corresponding operation based on the operation information. It then configures the hardware registers based on the operation information of the next operation data packet until all operation data packets have been processed.

[0092] Optionally, the task breakdown module 510 is also used for:

[0093] Parse the serial communication task message to obtain the target operation identifier and operation object information carried in the serial communication task message;

[0094] Obtain the preset control operation identifier;

[0095] According to the preset data structure, multiple operation data packets are generated based on the target operation identifier, control operation identifier, and operation object information. Each operation data packet includes a target operation identifier or a control operation identifier.

[0096] Optionally, the configuration module 530 is also used for:

[0097] Get the operation information corresponding to the current operation data packet;

[0098] If the operation identifier in the operation information is a control operation identifier, the operation identifier is configured in the hardware register.

[0099] Optionally, if the target operation identifier included in the operation data packet is a write operation identifier, the operation data packet also includes operation object information; the configuration module 530 is further configured to: configure the operation information in a hardware register when the operation identifier in the operation information is a write operation identifier; wherein the operation information includes a write operation identifier and operation object information.

[0100] Optionally, the data structure includes a control operation field, a read / write operation field, a data field, and an acknowledgment signal configuration field; wherein, the control operation field is used to indicate whether the operation corresponding to the operation data packet is a control operation; the read / write operation field is used to indicate whether the operation corresponding to the operation data packet is a read operation or a write operation; the data field is used to indicate the type of control operation or the data to be written corresponding to the write operation; and the acknowledgment signal configuration field is used to configure the acknowledgment signal configuration information for the read operation or the write operation.

[0101] Optionally, the serial communication device 50 further includes:

[0102] The status query module is used to access the status register of the external device according to a preset time period to query whether the target flag bit of the corresponding operation in the status register is set. The target flag bit being set indicates that the corresponding operation has been completed.

[0103] The status determination module is used to determine whether an external device has completed the corresponding operation based on the operation information when the target flag bit is detected to be set.

[0104] Optionally, the corresponding operation performed by the external device based on the operation information is a write operation; the serial communication device 50 further includes:

[0105] The configuration information acquisition module is used to acquire response signal configuration information from the current operation data packet;

[0106] The judgment module is used to determine whether a response signal has been received from an external device when the response signal configuration information indicates that a response signal needs to be waited for from an external device.

[0107] The state determination module is specifically used to: in response to receiving a response signal returned by an external device, determine that the external device has completed the write operation based on the operation information.

[0108] Optionally, the serial communication device 50 further includes:

[0109] The message acquisition module is used to terminate the current serial communication process and acquire the next serial communication task message for processing if no response signal is received from the external device.

[0110] Optionally, the serial communication task message includes the following data: target device address, target register address, target operation identifier, data length, and data address.

[0111] For a description of the features in the embodiments corresponding to the serial communication device, please refer to the relevant descriptions in the embodiments corresponding to the serial communication method, which will not be repeated here.

[0112] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described serial communication method embodiments.

[0113] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described serial communication method embodiments when it is run.

[0114] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0115] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described serial communication method embodiments.

[0116] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described serial communication method embodiments.

[0117] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0118] The serial communication method and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A serial communication method, characterized in that, include: Based on a serial communication task message, multiple operation data packets are generated. The operation steps corresponding to these multiple operation data packets constitute a serial communication process. The multiple operation data packets are generated based on a preset data structure, a preset control operation identifier, a target operation identifier obtained by parsing the serial communication task message, and operation object information. Each operation data packet includes either a target operation identifier or a control operation identifier. The data structure includes a control operation field, a read / write operation field, a data field, and an acknowledgment signal configuration field. The control operation field indicates whether the operation corresponding to the operation data packet is a control operation. The read / write operation field indicates whether the operation corresponding to the operation data packet is a read or write operation. The data field indicates the type of control operation or the data to be written for a write operation. The acknowledgment signal configuration field configures the acknowledgment signal information for the read or write operation. According to the execution sequence of each operation step corresponding to the multiple operation data packets, the multiple operation data packets are read sequentially; Obtain the operation information corresponding to the current operation data packet being read, and configure the hardware register based on the operation information so that the external device can read the operation information from the hardware register through the serial communication bus and execute the corresponding operation; After configuring the hardware registers, the processor exits the current operation and continues to read the next operation data packet after detecting that the external device has completed the corresponding operation based on the operation information. The processor then configures the hardware registers based on the operation information of the next operation data packet until all the operation data packets have been processed.

2. The serial communication method according to claim 1, characterized in that, The generation of multiple operation data packets based on serial communication task messages includes: Parse the serial communication task message to obtain the target operation identifier and operation object information carried in the serial communication task message; Obtain the preset control operation identifier; According to a preset data structure, the multiple operation data packets are generated based on the target operation identifier, the control operation identifier, and the operation object information.

3. The serial communication method according to claim 2, characterized in that, The step of acquiring the operation information corresponding to the currently read operation data packet and configuring the hardware registers based on the operation information includes: Obtain the operation information corresponding to the current operation data packet; If the operation identifier in the operation information is the control operation identifier, the operation identifier is configured in the hardware register.

4. The serial communication method according to claim 3, characterized in that, If the target operation identifier included in the operation data packet is a write operation identifier, the operation data packet also includes the operation object information; The method further includes: If the operation identifier in the operation information is the write operation identifier, the operation information is configured in the hardware register; The operation information includes the write operation identifier and the operation object information.

5. The serial communication method according to claim 1, characterized in that, Before continuing to read the next operation data packet after detecting that the external device has completed the corresponding operation based on the operation information, the method further includes: Access the status register of the external device according to a preset time period to check whether the target flag bit of the corresponding operation in the status register is set. The target flag bit being set indicates that the corresponding operation has been completed. If the target flag is detected to be set, it is determined that the external device has completed the corresponding operation based on the operation information.

6. The serial communication method according to claim 5, characterized in that, The corresponding operation performed by the external device based on the operation information is a write operation; Before determining that the external device has completed the corresponding operation based on the operation information, the method further includes: Obtain the response signal configuration information from the current operation data packet; If the response signal configuration information indicates that it is necessary to wait for a response signal from the external device, determine whether a response signal from the external device has been received; In response to receiving a response signal from the external device, it is determined that the external device has completed the write operation based on the operation information.

7. The serial communication method according to claim 6, characterized in that, The method further includes: If no response signal is received from the external device, the current serial communication process ends, and the next serial communication task message is obtained and processed.

8. The serial communication method according to any one of claims 1-7, characterized in that, The serial communication task message includes the following data: target device address, target register address, target operation identifier, data length, and data address.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the serial communication method as described in any one of claims 1 to 8.

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