Method, device and equipment for preventing physical verification violation in chip design and medium

Abstract

The invention provides a method, a device, equipment and a storage medium for preventing physical verification violation in chip design, which are characterized in that a target area capable of triggering PM.M1. X1. C.1 violation in a design drawing is found in advance, then, an FILLSGCAP Cell unit is transformed by referring to the structure of an M1E1 pattern in the FILLXCCAP Cell unit, so that the M1E1 pattern is also arranged in the FILLSGCAP Cell unit, the transformed FILLSGCAP Cell unit is filled in the target area, and the M1E1 pattern is formed in the FILLXCCAP Cell unit. The M1E1 pattern density of the target area is increased, so that PM.M1. X1. C.1 physical verification violations are prevented from occurring in a pattern matching check before back-end design is delivered to a factory on the basis of not losing energy consumption and not generating other violations.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design technology, and particularly relates to a method, apparatus, device and medium for preventing physical verification violations in chip design. Background Technology

[0002] The M1 layer wiring of LN04LPP (Samsung 4nm Low Power Plus, Samsung 4nm LPP process) uses SAUPEUV process. Simply put, SAUP uses self-alignment technology to generate alternating M1 double patterns (M1_E1 and M1_E2) from the originally dense M1 pattern in photolithography. EUV is to directly expose the M1 double pattern with high precision.

[0003] The above process requires that M1 winding be performed in only one direction and special windings such as jog, L shape, and off-grid are not allowed. (Jog: small bends or bumps in the metal wire during the wiring process, usually to bypass obstacles or meet design rules; L shape: the metal wire is a "L" shaped structure with a right angle bend; off-grid: the metal wire or contact hole is not aligned with the design grid.)

[0004] To better support EUV processes, the X1-cut pattern has been introduced into the LN04LPP design. When the tip-to-tip spacing (T2T spacing) of M1_E1 or M1_E2 is 24μm, the tool will automatically add an X1-cut pattern at the specified spacing position according to the technical file. If the spacing is greater than 60μm, the X1-cut pattern will not be inserted. See [link to technical documentation]. Figure 5 .

[0005] In advanced processes, EUV lithography is extremely sensitive to the metal density in the design. Therefore, to improve yield, a pattern matching check (PM) using LN04LPP is required before the back-end design is delivered to the factory. This check imposes the following requirements on the M1_E1 pattern and the X1-cut pattern: When the minimum width of M1 in the design is ≤0.014μm, the density of M1_E1 pattern and X1-cut pattern is detected with a grid cell of 3μm*3μm and a step size of 1.5μm. When the density of M1_E1 pattern is ≤3% and 0 < X1-cut pattern density is ≤0.65%, a PM.M1.X1.C.1 violation will be triggered. Summary of the Invention

[0006] Based on this, and in response to the aforementioned technical problems, a method, apparatus, device, and medium for preventing physical verification violations in chip design are provided.

[0007] The technical solution adopted in this invention is as follows: As a first aspect of the present invention, a method for preventing physical verification violations in chip design is provided, characterized in that the method is based on chip design tools and includes: S101. Using a square detection grid of preset size and a preset step size, perform DFM detection on the chip design diagram to find all regions that satisfy M1_E1 pattern density ≤ N% and 0 < X1-cut pattern density ≤ M%. Take each found region as a target region, where N and M are the thresholds for M1_E1 pattern density and X1-cut pattern density that trigger PM.M1.X1.C.1 violation, respectively. S102. Select the target size of the Dcap Cell unit, wherein the target size satisfies that the Dcap Cell unit with the target size can be filled into the target area; S103. Referring to the routing track position of the M1_E1 pattern inside the FILLXCCAP Cell cell with the target size, modify the FILLXCCAP Cell cell: add the M1_E1 pattern on the corresponding routing track inside the FILLXCCAP Cell cell with the target size, and set the added M1_E1 pattern to be blocked by routing. S104. Fill all target areas with the modified FILLSGCAP Cell units, and the number of units n filled in each target area satisfies: x*x*N%≤n*m*s, where x represents the length and width of the square detection grid, m represents the M1_E1 pattern density of the modified FILLSGCAP Cell unit, and s represents the area of ​​the FILLSGCAP Cell unit.

[0008] As a second aspect of the present invention, a device for preventing physical verification violations in chip design is provided, characterized in that the device is based on a chip design tool and includes: The first module is used by S101 to perform DFM detection on the chip design pattern with a square detection grid of preset size and a preset step size, to find all regions that satisfy M1_E1 pattern density ≤ N% and 0 < X1-cut pattern density ≤ M%, and to take each found region as a target region, where N and M are the thresholds for M1_E1 pattern density and X1-cut pattern density that trigger PM.M1.X1.C.1 violation, respectively. The second module is used in S102 to select the target size of the Dcap Cell unit, wherein the target size satisfies that the Dcap Cell unit with the target size can be filled into the target area. The third module is used for S103. Referring to the routing track position of the M1_E1 pattern inside the FILLXCCAP Cell cell with the target size, the module modifies the FILLSGCAP Cell cell by adding the M1_E1 pattern to the corresponding routing track inside the FILLSGCAP Cell cell with the target size and setting the added M1_E1 pattern to be blocked by routing. The fourth module is used in S104 to fill all target areas with the modified FILLSGCAP Cell units. The number of units n filled in each target area satisfies: x*x*N%≤n*m*s, where x represents the length and width of the square detection grid, m represents the M1_E1 pattern density of the modified FILLSGCAP Cell unit, and s represents the area of ​​the FILLSGCAP Cell unit.

[0009] As a third aspect of the present invention, an electronic device is provided, characterized in that it includes a storage module, the storage module including instructions loaded and executed by a processor, the instructions, when executed, causing the processor to perform a method for preventing physical verification violations in a chip design according to the first aspect described above.

[0010] As a fourth aspect of the present invention, a computer-readable storage medium is provided that stores one or more programs, characterized in that, when the one or more programs are executed by a processor, they implement the physical verification violation prevention method in chip design described in the first aspect above.

[0011] This invention pre-identifies the target area in the design drawing that will trigger a PM.M1.X1.C.1 violation. Then, referring to the structure of the M1_E1 pattern inside the FILLXCCAP Cell, the FILLXCCAP Cell is modified to also have an M1_E1 pattern inside. The modified FILLXCCAP Cell is then filled into the target area to increase the M1_E1 pattern density in the target area. This avoids PM.M1.X1.C.1 physical verification violations during the graphic matching check before the back-end design is delivered to the factory, without sacrificing energy consumption or causing other violations. Attached Figure Description

[0012] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments: Figure 1 A flowchart of a method for preventing physical verification violations in chip design, provided as an embodiment of the present invention; Figure 2 A schematic diagram of a device for preventing physical verification violations in chip design, provided by an embodiment of the present invention; Figure 3A schematic diagram of an electronic device provided in an embodiment of the present invention; Figure 4 (a) is a schematic diagram of the internal structure of the FILLSGCAP Cell unit before modification. Figure 4 (b) is a schematic diagram of the internal structure of the FILLXCCAPCell cell. Figure 4 (c) is a schematic diagram of the internal structure of the FILLSGCAP Cell unit after modification according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the X1-cut pattern. Detailed Implementation

[0013] The embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that the embodiments described in this specification are not exhaustive and do not represent the only embodiments of the present invention. The corresponding embodiments below are only for clearly illustrating the inventive content of this patent and are not intended to limit its implementation. For those skilled in the art, different variations and modifications can be made based on the embodiments described. Any variations or modifications that fall within the technical concept and inventive content of this invention and are obvious are also within the protection scope of this invention.

[0014] like Figure 1 As shown, this application provides a method for preventing physical verification violations in chip design, which is based on chip design tools (such as IC Compiler II, Cadence Innovus, etc.).

[0015] Taking the IC Compiler II tool as an example, the specific flow of the method in this application embodiment is as follows: S101. Using a square detection grid of preset size and a preset step size, perform DFM (Design for Manufacturability) detection on the chip design diagram to find all regions that satisfy M1_E1 pattern density ≤ N% and 0 < X1-cut pattern density ≤ M%. Take each found region as a target region, where N and M are the thresholds for M1_E1 pattern density and X1-cut pattern density that trigger PM.M1.X1.C.1 violation, respectively.

[0016] In the LN04LPP (Samsung 4nm Low Power Plus) process, a 3μm*3μm square detection grid with a step size of 1.5μm is typically used to detect the density of the M1_E1 pattern and the X1-cut pattern. When the density of the M1_E1 pattern is ≤3% and 0 < X1-cut pattern density is ≤0.65% (i.e., N=3, M=0.65), a PM.M1.X1.C.1 violation is triggered, and each region that triggers a PM.M1.X1.C.1 violation is considered as a target region.

[0017] The target area essentially represents a region in the chip design diagram with fewer logic cells, where the M1_E1 pattern is insufficient, such as the channel region between mem cells. In this case, only a few logic cells are often placed. On the other hand, the non-target area represents a region with more logic cells, where the M1_E1 pattern is sufficient.

[0018] S102. Select the target size of the Dcap Cell unit, such that the Dcap Cell unit with the target size can be filled into the target area.

[0019] Cells are the smallest units in a chip. There are many types of cells. During chip design, dcap cells (Decoupling Capacitance Cells) need to be added to improve power integrity and reduce power noise, which is especially critical in advanced process nodes (such as 7nm, 5nm and below).

[0020] The larger the drive value of a cell (representing the size of its internal transistor), the larger its physical size. Therefore, the drive value can be used to represent the size of a cell. There are many types of drive values ​​for cell cells, such as 128, 64, 32, 16, 8, 4, etc. Among them, the size of the Dcap cell needs to match the area of ​​the target region. The size that can be placed in the target region is selected as the target size.

[0021] S103. Referring to the location of the M1_E1 pattern inside the FILLXCCAP Cell cell with the target size, modify the FILLXCCAP Cell cell by adding the M1_E1 pattern to the corresponding trace track inside the FILLXCCAP Cell cell with the target size, and setting the added M1_E1 pattern to be blocked by a winding.

[0022] The standard cell library of Samsung LN04LPP provides two types of dcap cell units: FILLSGCAP Cell Unit and FILLXCCAP Cell Unit.

[0023] FILLSGCAP is used to add decoupling capacitors between power supply (VDD) and ground (VSS) to suppress ground bounce in the power network.

[0024] FILLXCCAP is used to cross-connect the gates of two MOSFETs to form a positive feedback loop (similar to the structure of an inverter pair). It is usually composed of two NMOS or PMOS transistors. A decoupling capacitor is added between the power supply (VDD) and ground (VSS) to suppress ground bounce in the power network.

[0025] According to the GDSII layout results, the FILLXCCAP Cell contains an M1_E1 pattern. Taking a 32-drive FILLXCCAP Cell as an example, its internal M1_E1 pattern density is 16%, and the area of ​​the 32-drive FILLXCCAP Cell is 0.3456. However, the FILLSGCAP Cell does not contain an M1_E1 pattern. Therefore, it can be seen that if the target area is filled with FILLXCCAP Cells, the PM.M1.X1.C.1 violation can be avoided: 3*3*3%≤n*16%*0.3456. When n≥5, this violation will not be triggered. However, the presence of an M2 pattern within the FILLXCCAP cell can lead to physical verification violations with existing M2 power supply traces in the target area (such as the channel area). Furthermore, the timing library for the Samsung LN04LPP shows that the leakage of the FILLXCCAP cell is approximately 7.6 times that of the FILLSGCAP cell with the same drive value, representing a significant energy loss. Therefore, this application modifies the FILLSGCAPCell cell based on the FILLXCCAP Cell.

[0026] Specifically, in this embodiment, a 32-drive value is selected as the target size. First, referring to the routing track position of the M1_E1 pattern inside the FILLSGCAP Cell cell with a 32-drive value, the M1_E1 pattern is added to the corresponding routing track on the GDSII layout of the FILLSGCAP Cell cell using the calibre tool. Then, in the ndm process library of the FILLSGCAP Cell cell, the create_routing_blockage command in the IC Compiler II Library Manager tool is used to set up routing blockage for the added M1_E1 pattern, ensuring that the physical information in the ndm is consistent with the GDSII layout. Figure 1 To avoid introducing new M1 windings during the winding stage and causing physical verification violations, the mask constraint attribute of the M1_E1 pattern is changed to mask one. Mask one means that we mark the winding blockage of the added M1_E1 pattern as E1 to correspond to M1_E1.

[0027] In order to increase the density of M1_E1 patterns in the FILLSGCAP Cell, after adding M1_E1 patterns to the corresponding trace tracks inside the FILLSGCAP Cell with the target size, the M1_E1 patterns located on the same trace track are first extended and connected end to end, and then the added M1_E1 patterns are set to be blocked by winding.

[0028] In the field of digital back-end design, ndm (New Data Model) is a unified data model introduced by Synopsys. It includes logical information (such as timing and functionality) and physical information (such as layout and routing) in the design, integrating these into a comprehensive model to improve the efficiency of the design process and data consistency.

[0029] Figure 4 (a) shows the internal structure of the FILLSGCAP Cell unit before modification, such as Figure 4 As shown in (b), the 32-drive FILLXCCAP Cell has six M1_E1 patterns inside, occupying three tracks from top to bottom. Accordingly, six M1_E1 patterns are added to the corresponding three tracks of the FILLXCCAP Cell. See [reference needed]. Figure 4 (c).

[0030] S104. Fill all target areas with the modified FILLSGCAP Cell units. The number of units n filled in each target area satisfies: x*x*N%≤n*m*s, where x represents the length and width of the square detection grid, m represents the M1_E1 pattern density of the modified FILLSGCAP Cell unit, and s represents the area of ​​the FILLSGCAP Cell unit.

[0031] Specifically, in this embodiment, the read_ref_libs instruction in the IC Compiler II Library Manager tool is first used to relink the ndm process library of the FILLSGCAP Cell to the corresponding database of the chip design. The modified FILLSGCAP Cell is then included in the Dcap Cell list and set as the only Dcap Cell type used. Finally, the modified FILLSGCAP Cell is filled into the target area using the create_stdcell_filler instruction.

[0032] In this embodiment, the M1_E1 pattern density m of the modified 32-drive FILLSGCAP Cell unit is 16%, and the area s of the 32-drive FILLSGCAP Cell unit is 0.3456. If the M1_E1 patterns on the same trace are extended end to end, the M1_E1 pattern density m is 18.5%, and the area s remains unchanged.

[0033] The Database is a collection of dedicated binary files created and managed by Electronic Design Automation (EDA) tools to store all relevant data for the current chip design. It can be understood as a highly integrated chip project file where "everything is an object." It doesn't just contain one type of data; it integrates and correlates information such as netlists, layouts, timings, constraints, and physical libraries into a unified, binary format environment. Before inserting a dcap cell, ICC2 (the tool for digital back-end physical implementation) must pre-load the physical information of these cells for easy access. This information resides in the dcap cell's NDM (Non-Dedicated Modeling Module), so the modified FILLSGCAP Cell's NDM process library needs to be relinked to the corresponding database in the chip design.

[0034] As can be seen from the above, the method for preventing physical verification violations in chip design provided by this application embodiment first identifies the target area in the design drawing that will trigger a PM.M1.X1.C.1 violation. Then, referring to the structure of the M1_E1 pattern inside the FILLXCCAP Cell, the FILLXCCAP Cell is modified so that it also has an M1_E1 pattern. The modified FILLXCCAP Cell is then filled into the target area to increase the M1_E1 pattern density in the target area. Thus, without sacrificing energy consumption or causing other violations, the PM.M1.X1.C.1 physical verification violation is avoided during the pattern matching check before the back-end design is delivered to the factory.

[0035] The following describes in detail one or more embodiments of the present invention a device for preventing physical verification violations in chip design. Those skilled in the art will understand that these devices can be configured using commercially available hardware components through the steps taught in this solution. Figure 4 This invention illustrates a device for preventing physical verification violations in chip design, based on chip design tools (such as IC Compiler II, Cadence Innovus, etc.). Taking IC Compiler II as an example... Figure 2 As shown, the device includes a first module 11, a second module 12, a third module 13, and a fourth module 14.

[0036] The first module 11 is used in S101 to perform DFM detection on the chip design pattern with a square detection grid of preset size and a preset step size, to find all regions that satisfy M1_E1 pattern density ≤ N% and 0 < X1-cut pattern density ≤ M%, and to take each found region as a target region, where N and M are the thresholds for M1_E1 pattern density and X1-cut pattern density that trigger PM.M1.X1.C.1 violation, respectively.

[0037] In the LN04LPP (Samsung 4nm Low Power Plus) process, a 3μm*3μm square detection grid with a step size of 1.5μm is typically used to detect the density of the M1_E1 pattern and the X1-cut pattern. When the density of the M1_E1 pattern is ≤3% and 0 < X1-cut pattern density is ≤0.65% (i.e., N=3, M=0.65), a PM.M1.X1.C.1 violation is triggered, and each region that triggers a PM.M1.X1.C.1 violation is considered as a target region.

[0038] The target area essentially represents a region in the chip design diagram with fewer logic cells, where the M1_E1 pattern is insufficient, such as the channel region between mem cells. In this case, only a few logic cells are often placed. On the other hand, the non-target area represents a region with more logic cells, where the M1_E1 pattern is sufficient.

[0039] The second module 12 is used in S102 to select the target size of the Dcap Cell unit, wherein the target size is such that the Dcap Cell unit with the target size can be filled into the target area.

[0040] Cells are the smallest units in a chip. There are many types of cells. During chip design, dcap cells (Decoupling Capacitance Cells) need to be added to improve power integrity and reduce power noise, which is especially critical in advanced process nodes (such as 7nm, 5nm and below).

[0041] The larger the drive value of a cell (representing the size of its internal transistor), the larger its physical size. Therefore, the drive value can be used to represent the size of a cell. There are many types of drive values ​​for cell cells, such as 128, 64, 32, 16, 8, 4, etc. Among them, the size of the Dcap cell needs to match the area of ​​the target region. The size that can be placed in the target region is selected as the target size.

[0042] The third module 13 is used in S103 to modify the FILLSGCAP Cell by referring to the location of the M1_E1 pattern inside the FILLSGCAP Cell with the target size: adding the M1_E1 pattern on the corresponding trace track inside the FILLSGCAP Cell with the target size, extending and connecting the M1_E1 patterns located on the same trace track, and setting the added M1_E1 pattern to be blocked by a winding.

[0043] The standard cell library of Samsung LN04LPP provides two types of dcap cell units: FILLSGCAP Cell Unit and FILLXCCAP Cell Unit.

[0044] FILLSGCAP is used to add decoupling capacitors between power supply (VDD) and ground (VSS) to suppress ground bounce in the power network.

[0045] FILLXCCAP is used to cross-connect the gates of two MOSFETs to form a positive feedback loop (similar to the structure of an inverter pair). It is usually composed of two NMOS or PMOS transistors. A decoupling capacitor is added between the power supply (VDD) and ground (VSS) to suppress ground bounce in the power network.

[0046] According to the GDSII layout results, the FILLXCCAP Cell contains an M1_E1 pattern. Taking a 32-drive FILLXCCAP Cell as an example, its internal M1_E1 pattern density is 16%, and the area of ​​the 32-drive FILLXCCAP Cell is 0.3456. However, the FILLSGCAP Cell does not contain an M1_E1 pattern. Therefore, it can be seen that if the target area is filled with FILLXCCAP Cells, the PM.M1.X1.C.1 violation can be avoided: 3*3*3%≤n*16%*0.3456. When n≥5, this violation will not be triggered. However, the presence of an M2 pattern within the FILLXCCAP cell can lead to physical verification violations with existing M2 power supply traces in the target area (such as the channel area). Furthermore, the timing library for the Samsung LN04LPP shows that the leakage of the FILLXCCAP cell is approximately 7.6 times that of the FILLSGCAP cell with the same drive value, representing a significant energy loss. Therefore, this application modifies the FILLSGCAPCell cell based on the FILLXCCAP Cell.

[0047] Specifically, in this embodiment, a 32-drive value is selected as the target size. First, referring to the routing track position of the M1_E1 pattern inside the FILLSGCAP Cell cell with a 32-drive value, the M1_E1 pattern is added to the corresponding routing track on the GDSII layout of the FILLSGCAP Cell cell using the calibre tool. Then, in the ndm process library of the FILLSGCAP Cell cell, the create_routing_blockage command in the IC Compiler II Library Manager tool is used to set up routing blockage for the added M1_E1 pattern, ensuring that the physical information in the ndm is consistent with the GDSII layout. Figure 1 To avoid introducing new M1 windings during the winding stage and causing physical verification violations, the mask constraint attribute of the M1_E1 pattern is changed to mask one. Mask one means that we mark the winding blockage of the added M1_E1 pattern as E1 to correspond to M1_E1.

[0048] In order to increase the density of M1_E1 patterns in the FILLSGCAP Cell, after adding M1_E1 patterns to the corresponding trace tracks inside the FILLSGCAP Cell with the target size, the M1_E1 patterns located on the same trace track are first extended and connected end to end, and then the added M1_E1 patterns are set to be blocked by winding.

[0049] In the field of digital back-end design, ndm (New Data Model) is a unified data model introduced by Synopsys. It includes logical information (such as timing and functionality) and physical information (such as layout and routing) in the design, integrating these into a comprehensive model to improve the efficiency of the design process and data consistency.

[0050] Figure 4 (a) shows the internal structure of the FILLSGCAP Cell unit before modification, such as Figure 4 As shown in (b), the 32-drive FILLXCCAP Cell has six M1_E1 patterns inside, occupying three tracks from top to bottom. Accordingly, six M1_E1 patterns are added to the corresponding three tracks of the FILLXCCAP Cell. See [reference needed]. Figure 4 (c).

[0051] The fourth module 14 is used for S104 to fill all target areas with the modified FILLSGCAP Cell units. The number of units n filled in each target area satisfies: x*x*N%≤n*m*s, where x represents the length and width of the square detection grid, m represents the M1_E1 pattern density of the modified FILLSGCAP Cell unit, and s represents the area of ​​the FILLSGCAP Cell unit.

[0052] Specifically, in this embodiment, the read_ref_libs instruction in the IC Compiler II Library Manager tool is first used to relink the ndm process library of the FILLSGCAP Cell to the corresponding database of the chip design. The modified FILLSGCAP Cell is then included in the Dcap Cell list and set as the only Dcap Cell type used. Finally, the modified FILLSGCAP Cell is filled into the target area using the create_stdcell_filler instruction.

[0053] In this embodiment, the M1_E1 pattern density m of the modified 32-drive FILLSGCAP Cell unit is 16%, and the area s of the M1_E1 pattern of the modified 32-drive FILLSGCAP Cell unit is 0.3456. If the M1_E1 patterns on the same routing track are extended end to end, the M1_E1 pattern density m is 18.5%, and the area s remains unchanged.

[0054] The Database is a collection of dedicated binary files created and managed by Electronic Design Automation (EDA) tools to store all relevant data for the current chip design. It can be understood as a highly integrated chip project file where "everything is an object." It doesn't just contain one type of data; it integrates and correlates information such as netlists, layouts, timings, constraints, and physical libraries into a unified, binary format environment. Before inserting a dcap cell, ICC2 (the tool for digital back-end physical implementation) must pre-load the physical information of these cells for easy access. This information resides in the dcap cell's NDM (Non-Dedicated Modeling Module), so the modified FILLSGCAP Cell's NDM process library needs to be relinked to the corresponding database in the chip design.

[0055] In summary, the physical verification violation prevention device in the chip design provided in the above embodiments can execute the physical verification violation prevention method in the chip design provided in the foregoing embodiments.

[0056] Similar to the above concept, the above Figure 2 The structure of the anti-violation winding device shown can be implemented as an electronic device. Figure 3 A schematic block diagram of the structure of an electronic device provided by an embodiment of the present invention is shown.

[0057] For example, the electronic device includes a storage module 21 and a processor 22. The storage module 21 includes instructions loaded and executed by the processor 22. When executed, the instructions cause the processor 22 to perform the steps described in the section on a method for preventing physical verification violations in a chip design described above in this specification, according to various exemplary embodiments of the present invention.

[0058] It should be understood that processor 22 can be a Central Processing Unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, the general-purpose processor can be a microprocessor or any conventional processor.

[0059] This invention also provides a computer-readable storage medium that stores one or more programs, which, when executed by a processor, implement the steps described in the section on the method for preventing physical verification violations in a chip design according to various exemplary embodiments of the invention.

[0060] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer-readable storage media (or non-transitory media) and communication media (or transient media).

[0061] As is known to those skilled in the art, the term computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0062] For example, the computer-readable storage medium may be an internal storage unit of the electronic device described in the foregoing embodiments, such as a hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc., provided on the electronic device.

[0063] The electronic devices and computer-readable storage media provided in the foregoing embodiments pre-identify the target area in the design drawing that will trigger a PM.M1.X1.C.1 violation. Then, referring to the structure of the M1_E1 pattern inside the FILLXCCAP Cell unit, the FILLXCCAP Cell unit is modified to also have an M1_E1 pattern inside. The modified FILLXCCAP Cell unit is then filled into the target area to increase the M1_E1 pattern density in the target area. This avoids PM.M1.X1.C.1 physical verification violations during the graphic matching check before the back-end design is delivered to the factory, without sacrificing energy consumption or causing other violations.

[0064] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for preventing physical verification violations in chip design, characterized in that, This method is based on chip design tools, which include: S101. Using a square detection grid of preset size and a preset step size, perform DFM detection on the chip design diagram to find all regions that satisfy M1_E1 pattern density ≤ N% and 0 < X1-cut pattern density ≤ M%. Take each found region as a target region, where N and M are the thresholds for M1_E1 pattern density and X1-cut pattern density that trigger PM.M1.X1.C.1 violation, respectively. S102. Select the target size of the Dcap Cell unit, wherein the target size satisfies that the Dcap Cell unit with the target size can be filled into the target area; S103. Referring to the routing track position of the M1_E1 pattern inside the FILLXCCAP Cell cell with the target size, modify the FILLXCCAP Cell cell: add the M1_E1 pattern on the corresponding routing track inside the FILLXCCAP Cell cell with the target size, and set the added M1_E1 pattern to be blocked by routing. S104. Fill all target areas with the modified FILLSGCAP Cell units, and the number of units n filled in each target area satisfies: x*x*N%≤n*m*s, where x represents the length and width of the square detection grid, m represents the M1_E1 pattern density of the modified FILLSGCAP Cell unit, and s represents the area of ​​the FILLSGCAP Cell unit.

2. The method for preventing physical verification violations in chip design according to claim 1, characterized in that, S103 further includes: Referring to the location of the M1_E1 pattern inside the FILLXCCAP Cell cell with the target size, use the calibre tool to add the M1_E1 pattern on the corresponding trace track of the GDSII layout of the FILLXCCAP Cell cell.

3. The method for preventing physical verification violations in chip design according to claim 1, characterized in that, S103 further includes: After adding the M1_E1 pattern to the corresponding routing track inside the FILLSGCAP Cell unit with the target size, first extend and connect the M1_E1 patterns located on the same routing track, and then set the added M1_E1 pattern to be blocked by a winding.

4. The method for preventing physical verification violations in chip design according to claim 2, characterized in that, S103 further includes: In the ndm process library of the FILLSGCAP Cell, the create_routing_blockage command in the IC Compiler II Library Manager tool is used to set up the routing blockage for the added M1_E1 pattern, and the mask constraint attribute of the M1_E1 pattern is changed to mask one.

5. The method for preventing physical verification violations in chip design according to claim 4, characterized in that, S104 further includes: The ndm process library of the FILLSGCAP Cell is relinked to the corresponding database of the chip design using the read_ref_libs instruction in the IC Compiler II Library Manager tool. The modified FILLSGCAP Cell is then included in the Dcap Cell list and set as the only Dcap Cell type used. Finally, the modified FILLSGCAP Cell is filled into the target area using the create_stdcell_filler instruction.

6. A device for preventing physical verification violations in chip design, characterized in that, The device is based on chip design tools and includes: The first module is used by S101 to perform DFM detection on the chip design pattern with a square detection grid of preset size and a preset step size, to find all regions that satisfy M1_E1 pattern density ≤ N% and 0 < X1-cut pattern density ≤ M%, and to take each found region as a target region, where N and M are the thresholds for M1_E1 pattern density and X1-cut pattern density that trigger PM.M1.X1.C.1 violation, respectively. The second module is used in S102 to select the target size of the Dcap Cell unit, wherein the target size satisfies that the Dcap Cell unit with the target size can be filled into the target area. The third module is used for S103. Referring to the routing track position of the M1_E1 pattern inside the FILLXCCAP Cell cell with the target size, the module modifies the FILLXCCAP Cell cell by adding the M1_E1 pattern to the corresponding routing track inside the FILLXCCAP Cell cell with the target size and setting the added M1_E1 pattern to be blocked by routing. The fourth module is used to fill all target areas with the modified FILLSGCAP Cell units. The number of units n filled in each target area satisfies: x*x*N%≤n*m*s, where x represents the length and width of the square detection grid, m represents the M1_E1 pattern density of the modified FILLSGCAP Cell unit, and s represents the area of ​​the FILLSGCAP Cell unit.

7. An electronic device, characterized in that, The device includes a storage module comprising instructions loaded and executed by a processor, which, when executed, cause the processor to perform a method for preventing physical verification violations in a chip design according to any one of claims 1-5.

8. A computer-readable storage medium storing one or more programs, characterized in that, When the one or more programs are executed by the processor, they implement the method for preventing physical verification violations in chip design as described in any one of claims 1-5.

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