SRAM read-write assisting circuit and SRAM memory system

Abstract

The application provides an SRAM read-write auxiliary circuit and an SRAM storage system, and relates to the technical field of registers.The SRAM read-write auxiliary circuit comprises a write auxiliary circuit, a read auxiliary circuit and a control module.When in a data reading stage, the control module is used for sending a first control signal to the write auxiliary circuit and the read auxiliary circuit, closing the write auxiliary circuit, driving the read auxiliary circuit to raise the power supply voltage of an SRAM array module, and pulling down the power supply ground voltage of the SRAM array module.When in a data writing stage, the control module is used for sending a second control signal to the write auxiliary circuit and the read auxiliary circuit, closing the read auxiliary circuit, driving the write auxiliary circuit to pull down the power supply voltage of the SRAM array module, and raising the power supply ground voltage of the SRAM array module.Based on this, the application constructs a peripheral auxiliary circuit to improve the anti-interference ability and the read-write stability of the SRAM.

Description

Technical Field

[0001] This application relates to the field of memory technology, and more specifically, to an SRAM read / write auxiliary circuit and an SRAM storage system. Background Technology

[0002] Static Random Access Memory (SRAM) is used for writing, reading, and storing digital information. Therefore, accurate writing, reading, and retention are fundamental requirements in SRAM design. However, with advancements in manufacturing processes, the power supply voltage of field-effect transistors has gradually decreased, and process variations have exacerbated the fluctuations in the turn-on voltage (Vth). Consequently, the SRAM's noise immunity and stability are correspondingly negatively affected by the turn-on voltage (Vth).

[0003] To improve the anti-interference capability and stability of SRAM, technicians typically employ the following methods: The first is to change the structure of the SRAM, such as optimizing 6T SRAM to 7T, 8T, 9T, 10T, etc. However, due to the large number of SRAMs in the memory array, the internal structure of the SRAM increases, which in turn significantly increases the area and power consumption of the memory. The second method is to design through improved processes, but using improved processes will increase costs and is not conducive to commercial development.

[0004] Therefore, there is an urgent need for a technical solution that can improve the anti-interference capability and stability of SRAM while maintaining low cost and low power consumption. Summary of the Invention

[0005] The purpose of this application is to provide an SRAM read / write auxiliary circuit and an SRAM storage system that can improve the anti-interference capability and stability of SRAM while maintaining low cost and low power consumption.

[0006] In a first aspect, the present invention provides an SRAM read / write auxiliary circuit, applied to an SRAM storage system. The SRAM storage system includes an SRAM array module. The SRAM read / write auxiliary circuit includes a write auxiliary circuit, a read auxiliary circuit, and a control module. The output terminals of the write auxiliary circuit and the read auxiliary circuit are both connected to the power supply terminals of the SRAM array module. The control module is also connected to the control terminals of the write auxiliary circuit and the read auxiliary circuit.

[0007] When in the data reading stage, the control module sends the first control signal to the write auxiliary circuit and the read auxiliary circuit to shut down the write auxiliary circuit, drive the read auxiliary circuit to raise the power supply voltage of the SRAM array module based on the capacitor characteristics, and pull down the power supply ground voltage of the SRAM array module to improve the read noise margin.

[0008] When in the data writing stage, the control module sends a second control signal to the write auxiliary circuit and the read auxiliary circuit to shut down the read auxiliary circuit, drive the write auxiliary circuit to pull down the power supply voltage of the SRAM array module, and raise the power supply ground voltage of the SRAM array module to improve the write noise margin.

[0009] In one possible implementation, the power supply terminals of the SRAM array module include a positive power supply terminal and a ground power supply terminal; the read auxiliary circuit includes a first power input module, a first capacitor assembly, and a first power output module; the first power input module, the first capacitor assembly, and the first power output module are connected in sequence to form a first power supply branch and a second power supply branch, the output terminal of the first power supply branch is connected to the positive power supply terminal; the output terminal of the second power supply branch is connected to the ground power supply terminal.

[0010] The control module is used to send a first control signal to the read auxiliary circuit, drive the first power supply branch to raise the power supply voltage of the SRAM array module based on the capacitive effect, and drive the second power supply branch to lower the power supply ground voltage based on the capacitive effect.

[0011] In one possible implementation, the first power input module includes a PMOS transistor pair and an NMOS transistor pair, wherein the source of each PMOS transistor in the PMOS transistor pair is connected to the positive power rail of the SRAM memory system; the source of each NMOS transistor in the NMOS transistor pair is connected to the ground power rail of the SRAM memory system; and the gate of each PMOS transistor and the gate of each NMOS transistor are connected to the control module.

[0012] When in the data reading stage, the control module is used to send a first enable signal to the target PMOS transistor and a second enable signal to the other PMOS transistors besides the target PMOS transistor.

[0013] The control module is also used to send a first enable signal to the target NMOS transistor and a second enable signal to the other NMOS transistors besides the target NMOS transistor.

[0014] The first enable signal and the second enable signal are complementary signals;

[0015] The target PMOS transistor is used to characterize the PMOS transistor used to construct the first power supply branch in the PMOS transistor pair; the target NMOS transistor is used to characterize the NMOS transistor used to construct the second power supply branch in the NMOS transistor pair.

[0016] In one possible implementation, the first capacitor assembly includes two capacitor units and two MOSFETs, each capacitor unit including a capacitor element formed by connecting the MOSFETs; the control terminal of each MOSFET is connected to a control module.

[0017] When in the data reading stage, the control module sends a first enable signal to the target MOS transistor and a second enable signal to the MOS transistors other than the target MOS transistor, so that the node voltage of the target capacitor cell is greater than the voltage of the positive power rail and the node voltage of the capacitor cells other than the target capacitor cell is less than the voltage of the ground power rail.

[0018] The target capacitor unit is used to characterize the capacitor unit used to construct the first power supply branch under the first capacitor assembly; the target MOS transistor is used to characterize the MOS transistor corresponding to the target capacitor unit;

[0019] Specifically, for any power supply branch, the channel type of the MOSFET corresponding to the current power supply branch is opposite to the MOSFET type in the corresponding power input module.

[0020] In one possible implementation, the power input module includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor, and the first capacitor assembly includes a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, and a fourth NMOS transistor;

[0021] The sources of the first PMOS transistor and the second PMOS transistor are connected to the positive power rail of the SRAM memory system; the sources of the first NMOS transistor and the second NMOS transistor are connected to the ground power rail of the SRAM memory system; the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor and the gate of the fourth PMOS transistor to receive the first enable signal; the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor and the gate of the third NMOS transistor to receive the second enable signal; the drain of the first PMOS transistor is connected to the gate of the third PMOS transistor. The third PMOS transistor is connected to the drain of the second PMOS transistor and the drain of the third NMOS transistor. The source of the third PMOS transistor is also connected to its own drain. The drain of the second NMOS transistor is connected to the drain of the third NMOS transistor, the drain of the fourth NMOS transistor, and the second input terminal of the first power output module. The source of the fourth PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the fourth NMOS transistor. The source of the fourth NMOS transistor is connected to its own drain.

[0022] In one possible implementation, the first power output module includes a fifth PMOS transistor and a fifth NMOS transistor. The source of the fifth PMOS transistor serves as the first terminal of the first power output module and is connected to the drain of the first PMOS transistor. The gates of both the fifth PMOS transistor and the fifth NMOS transistor are connected to the control module. The source of the fifth NMOS transistor serves as the second terminal of the first power output module and is connected to the drain of the second NMOS transistor. The drain of the fifth PMOS transistor is connected to the positive power supply terminal of the SRAM array module, and the drain of the fifth NMOS transistor is connected to the ground power supply terminal of the SRAM array module.

[0023] When in the data reading stage, the control module is also used to send a third enable signal to the fifth NMOS transistor and a fourth enable signal to the fifth PMOS transistor, so that the first power supply branch provides power to the SRAM array module through the fifth PMOS transistor to raise the power supply voltage; and so that the second power supply branch provides power ground to the SRAM array through the fifth NMOS transistor.

[0024] Among them, the third enable signal and the fourth enable signal are complementary signals.

[0025] In one possible implementation, when in the data reading stage, the control module is also used to drive the first PMOS transistor to turn off, the third NMOS transistor to turn off, the second PMOS transistor to turn on, and the fifth PMOS transistor to turn on, so as to obtain the first power supply branch to power the SRAM array module.

[0026] The control module is also used to drive the second NMOS transistor to turn off, the first NMOS transistor to turn on, the fourth PMOS transistor to turn off, and the fifth NMOS transistor to turn on, so as to obtain the second power supply branch and provide power ground for the SRAM array module;

[0027] During the data writing phase, the control module is also used to drive the fifth PMOS transistor to turn off and the fifth NMOS transistor to turn off.

[0028] In one possible implementation, the write auxiliary circuit includes a second power input module and a second power output module; both the second power input module and the second power output module include a pair of MOS transistors, each pair of MOS transistors including a PMOS transistor and an NMOS transistor; the gate of each PMOS transistor and the gate of each NMOS transistor are connected to the control module.

[0029] When in the data writing stage, the control module sends second control signals to each PMOS transistor and NMOS transistor under the second power input module and the second power output module respectively, cuts off the power supply path of the second power input module, and connects the positive power supply terminal and the ground power supply terminal of the SRAM array module through the second power output module to pull down the power supply voltage of the SRAM array module and raise the power supply ground voltage of the SRAM array module.

[0030] In one possible implementation, the second power output module includes a sixth PMOS transistor, a sixth NMOS transistor, and an eighth PMOS transistor; the second power input module includes a seventh PMOS transistor and a seventh NMOS transistor.

[0031] The source of the seventh PMOS transistor is connected to the positive power rail of the SRAM memory system; the source of the seventh NMOS transistor is connected to the ground power rail of the SRAM memory system; the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor and the source of the sixth PMOS transistor; the drain of the seventh NMOS transistor is connected to the drain of the eighth PMOS transistor and the source of the sixth NMOS transistor; the drain of the sixth NMOS transistor is connected to the power ground of the SRAM array module; the drain of the sixth PMOS transistor is connected to the positive power terminal of the SRAM array module; the gates of the sixth PMOS transistor, the sixth NMOS transistor, the seventh PMOS transistor, the seventh NMOS transistor, and the eighth PMOS transistor are all connected to the control module.

[0032] When in the data reading stage, the control module is also used to drive the sixth PMOS transistor to turn off and the sixth NMOS transistor to turn off.

[0033] When in the data writing phase, the control module is also used to drive the sixth PMOS transistor to turn on, the sixth NMOS transistor to turn on, the eighth PMOS transistor to turn on, the seventh PMOS transistor to turn off, and the seventh NMOS transistor to turn off.

[0034] In a second aspect, the present invention also provides an SRAM storage system, including an SRAM array module and an SRAM read / write auxiliary circuit according to any one of the first aspects above.

[0035] The SRAM read / write auxiliary circuit and SRAM storage system provided in this application have the following advantages:

[0036] The SRAM read / write auxiliary circuit includes a write auxiliary circuit, a read auxiliary circuit, and a control module. The outputs of both the write and read auxiliary circuits are connected to the power supply of the SRAM array module. The control module includes at least a read data stage and a write data stage. During the read data stage, the control module sends a first control signal to both the write and read auxiliary circuits to disable the write auxiliary circuit, drive the read auxiliary circuit to raise the power supply voltage of the SRAM array module, and lower the power supply ground voltage of the SRAM array module. During the write data stage, the control module sends a second control signal to both the write and read auxiliary circuits to disable the read auxiliary circuit, drive the write auxiliary circuit to lower the power supply voltage of the SRAM array module, and raise the power supply ground voltage of the SRAM array module. Based on this, this application constructs an external auxiliary circuit, which includes a read auxiliary circuit and a write auxiliary circuit. The read auxiliary circuit is based on the characteristic that the voltage difference across the capacitor cannot change abruptly, and the write auxiliary circuit is based on the on / off state to redistribute the charge to adjust the output node voltage, thereby improving the read noise margin or write noise margin of the SRAM array module, and improving the anti-interference capability and read / write stability of SRAM on the basis of low cost and low power consumption. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of an SRAM storage system provided in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of the SRAM read / write auxiliary circuit provided in an embodiment of this application;

[0040] Figure 3 This is one of the schematic diagrams of the read auxiliary circuit provided in the embodiments of this application;

[0041] Figure 4 This is a second schematic diagram of the structure of the reading auxiliary circuit provided in the embodiments of this application;

[0042] Figure 5 This is the third schematic diagram of the read auxiliary circuit provided in the embodiments of this application;

[0043] Figure 6 One of the circuit schematics of the SRAM read / write auxiliary circuit provided in the embodiments of this application;

[0044] Figure 7 The second circuit schematic diagram of the SRAM read / write auxiliary circuit provided in the embodiments of this application;

[0045] Figure 8 A simplified circuit diagram of the read auxiliary circuit provided in the embodiments of this application during the data reading stage;

[0046] Figure 9 Timing diagram of the data reading stage provided in the embodiments of this application;

[0047] Figure 10 This is one of the schematic diagrams of the write auxiliary circuit provided in the embodiments of this application;

[0048] Figure 11 The third circuit schematic diagram of the SRAM read / write auxiliary circuit provided in the embodiments of this application;

[0049] Figure 12 A simplified circuit diagram of the write auxiliary circuit provided in the embodiments of this application during the data reading stage;

[0050] Figure 13 This is a timing diagram of the write data stage provided in an embodiment of this application.

[0051] Icons: 10 - SRAM storage system; 100 - SRAM read / write auxiliary circuit; 200 - SRAM array module; 101 - Write auxiliary circuit; 102 - Read auxiliary circuit; 103 - Control module; 201 - First power input module; 202 - First capacitor assembly; 203 - First power output module; 204 - Second power input module; 205 - Second power output module; 301 - Capacitor unit;

[0052] PM1 - First PMOS transistor; NM1 - First NMOS transistor; PM2 - Second PMOS transistor; NM2 - Second NMOS transistor; PM3 - Third PMOS transistor; NM3 - Third NMOS transistor; PM4 - Fourth PMOS transistor; NM4 - Fourth NMOS transistor; PM5 - Fifth PMOS transistor; NM5 - Fifth NMOS transistor; PM6 - Sixth PMOS transistor; NM6 - Sixth NMOS transistor; PM7 - Seventh PMOS transistor; NM7 - Seventh NMOS transistor; PM8 - Eighth PMOS transistor; RCLKB - First enable signal; RCLK - Second enable signal; WCLKB - Third enable signal; WCLK - Fourth enable signal. Detailed Implementation

[0053] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0054] Please refer to Figure 1 , Figure 1This is a schematic diagram of the SRAM storage system provided in an embodiment of this application. The SRAM storage system 10 includes an SRAM array module 200 and an SRAM read / write auxiliary circuit 100. The output terminal of the SRAM read / write auxiliary circuit 100 is connected to the power supply terminal of the SRAM array module 200. In this embodiment, the SRAM array module 200 includes at least a data read stage, a data write stage, and a data retention stage.

[0055] In this embodiment, the write auxiliary circuit of the SRAM read / write auxiliary circuit is essentially based on the charge in the static holding stage, which is redistributed in the write data stage to realize the corresponding transformation of the power supply voltage and ground voltage of the SRAM array module, so as to improve the write noise margin (WM); while the read auxiliary circuit is based on the principle that the voltage difference across the capacitor cannot change abruptly to change the capacitor voltage value, so as to improve the read static noise margin (RSNM).

[0056] In summary, the SRAM read / write auxiliary circuit in this embodiment can improve the anti-interference capability and read / write stability of the entire SRAM storage system based on the above-mentioned technical principles.

[0057] Please Figure 1 Based on, refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the SRAM read / write auxiliary circuit provided in the embodiment of this application. The SRAM read / write auxiliary circuit 100 includes a write auxiliary circuit 101, a read auxiliary circuit 102, and a control module 103. The output terminals of the write auxiliary circuit 101 and the read auxiliary circuit 102 are both connected to the power supply terminal of the SRAM array module 200. The control module 103 is also connected to the control terminal of the write auxiliary circuit 101 and the control terminal of the read auxiliary circuit 102.

[0058] When in the data reading stage, the control module 103 sends a first control signal to the write auxiliary circuit 101 and the read auxiliary circuit 102 to turn off the write auxiliary circuit 101, drive the read auxiliary circuit 102 to raise the power supply voltage of the SRAM array module 200, and pull down the power supply ground voltage of the SRAM array module 200 to improve the read noise margin.

[0059] When in the data writing stage, the control module 103 sends a second control signal to the write auxiliary circuit 101 and the read auxiliary circuit 102 to turn off the read auxiliary circuit 102, drive the write auxiliary circuit 101 to pull down the power supply voltage of the SRAM array module 200, and raise the power supply ground voltage of the SRAM array module 200 to improve the write noise margin.

[0060] Based on this, the SRAM read / write auxiliary circuit in this embodiment can be adapted to different stages of the SRAM array module, such as the read data stage and the write data stage. In different stages, the control module sends corresponding control signals. For example, in the read data stage, the write auxiliary circuit can be turned off, while the read auxiliary circuit is driven to raise the power supply voltage of the SRAM array module and lower the power supply ground voltage of the SRAM array module to improve the read noise margin. As another example, in the write data stage, the read auxiliary circuit can be turned off, while the write auxiliary circuit is driven to lower the power supply voltage of the SRAM array module and raise the power supply ground voltage of the SRAM array module to improve the write noise margin. Thus, by improving the read noise margin and / or the write noise margin, the anti-interference capability and read / write stability of the SRAM storage system are improved.

[0061] It should be noted that, to avoid interference from the write auxiliary circuit to the read auxiliary circuit during the data reading stage, this embodiment requires the control module to shut down the write auxiliary circuit. Similarly, to avoid interference from the read auxiliary circuit to the write auxiliary circuit during the data writing stage, this embodiment requires the control module to shut down the read auxiliary circuit.

[0062] In this embodiment, the read auxiliary circuit includes multiple PMOS transistors and multiple NMOS transistors. Based on this, this application can adjust the on / off state of each PMOS transistor and each NMOS transistor through the control module, thereby using the capacitor characteristics to raise the power supply voltage of the SRAM array module and lower the power supply ground voltage of the SRAM array module.

[0063] It should be noted that in this embodiment, the channel type of the MOSFET under the first capacitor component corresponding to the first power supply branch is opposite to the MOSFET type under the corresponding first power input module.

[0064] And / or the channel type of the MOSFET under the first capacitor component corresponding to the second power supply branch is opposite to the MOSFET type under the first power input module corresponding to it.

[0065] In one possible implementation, the total number of PMOS transistors in this embodiment is the same as the total number of NMOS transistors.

[0066] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the read auxiliary circuit provided in an embodiment of this application. When the power supply terminal of the SRAM array module 200 includes a positive power supply terminal VC and a ground power supply terminal VSC; the read auxiliary circuit 102 includes a first power input module 201, a first capacitor assembly 202, and a first power output module 203; the first power input module 201, the first capacitor assembly 202, and the first power output module 203 are connected in sequence to form a first power supply branch and a second power supply branch. The output terminal of the first power supply branch is connected to the positive power supply terminal VC; the output terminal of the second power supply branch is connected to the ground power supply terminal VSC.

[0067] The control module 103 is used to send a first control signal to the read auxiliary circuit 102 to drive the first power supply branch to raise the power supply voltage of the SRAM array module based on the capacitive effect; and to drive the second power supply branch to lower the power supply ground voltage of the SRAM array module based on the capacitive effect.

[0068] It should be noted that this embodiment does not limit the arrangement structure of the SRAM array module. The SRAM array module can be a traditional matrix array. Based on this, in this embodiment, the positive power supply terminal of the matrix array can be the positive power supply terminal of the SRAM array module, and the ground of the matrix array can be the ground power supply terminal of the SRAM array module.

[0069] Please refer to Figure 4 , Figure 4 This is another schematic diagram of the read auxiliary circuit provided in the embodiment of this application. The first power input module 201 includes a PMOS transistor pair and an NMOS transistor pair. The source of each PMOS transistor in the PMOS transistor pair is connected to the positive power rail of the SRAM memory system to receive the VDD voltage. The source of each NMOS transistor in the NMOS transistor pair is connected to the ground power rail of the SRAM memory system 10 to receive the VSS voltage. The gate of each PMOS transistor and the gate of each NMOS transistor are connected to the control module 103.

[0070] It should be noted that the PMOS or NMOS transistor pairs described in this embodiment are only used to simply describe the number of PMOS and / or NMOS transistors, and are not intended to limit their matching relationship.

[0071] When in the data reading stage, the control module 103 is used to send a first enable signal RCLKB to the target PMOS transistor and a second enable signal RCLK to the other PMOS transistors.

[0072] In this embodiment, the target PMOS transistor is used to characterize the PMOS transistor used to construct the first power supply branch in the PMOS transistor pair.

[0073] Meanwhile, the control module 103 is also used to send a first enable signal RCLKB to the target NMOS transistor in the NMOS transistor pairing, and to send a second enable signal RCLK to the other NMOS transistors besides the target NMOS transistor; in this embodiment, the target NMOS transistor is used to characterize the NMOS transistor used to construct the second power supply branch in the NMOS transistor pairing.

[0074] It should be noted that in this embodiment, the first enable signal RCLKB and the second enable signal RCLK are complementary signals.

[0075] Please Figure 4 Based on, refer to Figure 5 , Figure 5 This is another schematic diagram of the read auxiliary circuit provided in the embodiments of this application. The first capacitor assembly 202 includes two capacitor units 301 and two MOSFETs. Each capacitor unit 301 corresponds to one MOSFET; the control terminal of each MOSFET is connected to the control module 103.

[0076] In this embodiment, the MOS transistor corresponding to the capacitor unit is used to provide the initial voltage to the capacitor unit.

[0077] When in the data reading stage, the control module 103 sends a first enable signal RCLKB to the target MOS transistor and a second enable signal RCLK to the other MOS transistors, so that the node voltage of the target capacitor cell is greater than the VDD voltage of the positive power rail, and the node voltage of the capacitor cell 301 other than the target capacitor cell is less than the VSS voltage.

[0078] In this embodiment, the target capacitor unit is used to characterize the capacitor unit used to construct the first power supply branch under the first capacitor assembly. The target MOSFET is used to characterize the MOSFET corresponding to the target capacitor unit.

[0079] For any power supply branch, the channel type of the MOSFET under the capacitor unit corresponding to the current power supply branch is opposite to the MOSFET type under the corresponding power input module.

[0080] For example, if the switching transistor of the power input module under the first power supply branch is a PMOS transistor, then the corresponding MOS transistor under the target capacitor unit should be an NMOS transistor. As another example, if the switching transistor of the power input module under the second power supply branch is an NMOS transistor, then the corresponding MOS transistor under the capacitor unit 301 that constructs the second power supply branch should be a PMOS transistor.

[0081] Based on this, when in the data reading stage, the control module 103 in this embodiment will adjust the on / off state of each PMOS transistor under the first power supply branch, for example, one on and one off, thereby improving the node voltage of the capacitor unit under that branch.

[0082] Similarly, in this embodiment, the control module 103 will adjust the on / off state of each NMOS transistor in the second power supply branch, for example, one on and one off, thereby improving the node voltage of the capacitor unit in this branch.

[0083] To reduce the device size of the SRAM read / write auxiliary circuit 100, in one possible implementation, the capacitor unit in this embodiment may include a capacitor device connected by MOS transistors.

[0084] Please Figure 5 Based on, refer to Figure 6 , Figure 6The circuit diagram of the read auxiliary circuit provided in the embodiment of this application shows that the first power input module 201 includes a first PMOS transistor PM1, a first NMOS transistor NM1, a second PMOS transistor PM2, and a second NMOS transistor NM2, and the first capacitor assembly 202 includes a third PMOS transistor PM3, a third NMOS transistor NM3, a fourth PMOS transistor PM4, and a fourth NMOS transistor NM4.

[0085] In this embodiment, the second PMOS transistor PM2 is the target PMOS transistor in the first power input module 201, and the second NMOS transistor NM2 is the target NMOS transistor in the first power input module 201. The third PMOS transistor PM3 is the target capacitor unit for constructing the first power supply branch; the fourth NMOS transistor NM4 is the capacitor unit for constructing the second power supply branch; wherein, the third NMOS transistor NM3 is the MOS transistor corresponding to the target capacitor unit.

[0086] The sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are connected to the positive power rail of the SRAM memory system 10 to receive the VDD voltage; the sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected to the ground power rail of the SRAM memory system 10; the gate of the first PMOS transistor PM1 is connected to the gate of the first NMOS transistor NM1 and the gate of the fourth PMOS transistor PM4 to receive the first enable signal RCLKB; the gate of the second PMOS transistor PM2 is connected to the gate of the second NMOS transistor NM2 and the gate of the third NMOS transistor NM3 to receive the second enable signal RCLK; the drain of the first PMOS transistor PM1 is connected to the gate of the third NMOS transistor NM3. The gate of PMOS transistor PM3, the drain of the fourth PMOS transistor PM4, and the first input terminal of the first power output module 203 are connected. The source of the third PMOS transistor PM3 is connected to the drain of the second PMOS transistor PM2 and the source of the third NMOS transistor NM3. The source of the third PMOS transistor is also connected to its own drain. The drain of the second NMOS transistor NM2 is connected to the drain of the third NMOS transistor NM3, the drain of the fourth NMOS transistor NM4, and the second input terminal of the first power output module 203. The source of the fourth PMOS transistor PM4 is connected to the drain of the first NMOS transistor NM1 and the gate of the fourth NMOS transistor NM4. The source of the fourth NMOS transistor NM4 is connected to its own drain.

[0087] Please Figure 6 Based on, refer to Figure 7 , Figure 7This is another circuit diagram of the read auxiliary circuit provided in the embodiments of this application. In this embodiment, the first power output module 203 includes a fifth PMOS transistor PM5 and a fifth NMOS transistor NM5. The source of the fifth PMOS transistor PM5 serves as the first terminal of the first power output module 203 and is connected to the drain of the first PMOS transistor PM1. The gates of the fifth PMOS transistor PM5 and the fifth NMOS transistor NM5 are both connected to the control module 103. The source of the fifth NMOS transistor NM5 serves as the second terminal of the first power output module 203 and is connected to the drain of the second NMOS transistor NM2. The drain of the fifth PMOS transistor PM5 is connected to the positive terminal of the power supply, and the drain of the fifth NMOS transistor NM5 is connected to the ground terminal of the power supply.

[0088] When in the data reading stage, the control module 103 is also used to send a third enable signal WCLKB to the fifth NMOS transistor NM5 and a fourth enable signal WCLK to the fifth PMOS transistor PM5, so that the first power supply branch provides power to the SRAM array module 200 through the fifth PMOS transistor PM5 to raise the power supply voltage; and so that the second power supply branch provides power ground to the SRAM array module through the fifth NMOS transistor NM5 to lower the power ground voltage.

[0089] In this embodiment, the third enable signal WCLKB and the fourth enable signal WCLK are complementary signals.

[0090] Please continue to refer to this. Figure 7 When in the data reading stage, the second enable signal RCLK and the third enable signal WCLKB are at a high level, while the first enable signal RCLKB and the fourth enable signal WCLK are at a low level.

[0091] Based on this, the working principle of the read auxiliary module in this embodiment is as follows: the first PMOS transistor PM1 is turned off, the third NMOS transistor NM3 is turned off, the second PMOS transistor PM2 is turned on, and the fifth PMOS transistor PM5 is turned on, thus obtaining the first power supply branch to power the SRAM array module 200. At the same time, the control module 103 will also drive the second NMOS transistor NM2 to turn off, the first NMOS transistor NM1 to turn on, the fourth PMOS transistor PM4 to turn off, and the fifth NMOS transistor NM5 to turn on, thus obtaining the second power supply branch to provide power ground for the SRAM array module, thereby pulling down the power ground voltage.

[0092] Specifically, please Figure 7 Based on, refer to Figure 8 , Figure 8This is a simplified circuit diagram of the data reading stage in an embodiment of this application. The second enable signal RCLK and the third enable signal WCLKB are at high level, and the first enable signal RCLKB and the fourth enable signal WCLK are at low level. When the SRAM array module 200 is composed of 6TSRAM, the first PMOS transistor PM1 in the read auxiliary circuit 102 is turned off, the v1 node of the third PMOS transistor PM3 is disconnected from the positive power rail, the third NMOS transistor NM3 is turned off, and the second PMOS transistor PM2 is turned on. At this time, the voltage at the v2 node of the third PMOS transistor PM3 changes from VSS voltage to VDD voltage. According to the capacitor characteristic that the voltage difference across the capacitor cannot jump, when the voltage at the v2 node changes from VSS voltage to VDD voltage, the voltage at the v1 node will be greater than the initial VDD voltage value. Since the fifth PMOS transistor PM5 is turned on, the current generated at the v1 node flows through the positive power supply terminal of the SRAM array module 200 to supply power to the SRAM array module 200.

[0093] Please Figure 7 Based on, refer to Figure 9 , Figure 9 The timing diagram for the data reading stage in this embodiment shows that the voltage VC at the positive terminal of the SRAM array is raised to 973mV during this stage.

[0094] Please continue to refer to Figure 8 In this embodiment, the second NMOS transistor NM2 is off, the v4 node of the fourth NMOS transistor NM4 is disconnected from the ground power rail, the first NMOS transistor NM1 is on, and the fourth PMOS transistor PM4 is off. When the voltage at the v3 node of the fourth NMOS transistor NM4 jumps from VDD to VSS, due to the capacitance effect of the fourth NMOS transistor NM4, the voltage at the v4 node will be less than the VSS voltage, and the fifth NMOS transistor NM5 will be on. At this time, a current is generated at the v4 node and flows through the power ground terminal VSC of the SRAM array module 200. Please continue to refer to Figure 8 At this point, the voltage at the VSC terminal is pulled down to -70mV.

[0095] Based on this, in this embodiment, the read assist circuit 102 raises the power supply voltage of the SRAM array module 200 and lowers the power supply ground voltage of the SRAM array module 200, thereby improving the read noise margin.

[0096] In addition, to avoid interference from the read auxiliary circuit 102 during the data writing stage, in this embodiment, the control module 103 will drive the fifth PMOS transistor PM5 to turn off and the fifth NMOS transistor NM5 to turn off, so as to avoid the influence of the VDD voltage provided by the positive power rail and the VSS voltage provided by the ground power rail in the read auxiliary circuit 102 on the data writing stage.

[0097] Please refer to Figure 10 , Figure 10 This is a schematic diagram of the write auxiliary circuit provided in an embodiment of this application. The write auxiliary circuit 101 includes a second power input module 204 and a second power output module 205. Both the second power input module 204 and the second power output module 205 include a pair of MOS transistors, each pair including a PMOS transistor and an NMOS transistor; the gate of each PMOS transistor and the gate of each NMOS transistor are connected to the control module 103.

[0098] When in the data writing stage, the control module 103 sends second control signals to each PMOS transistor and NMOS transistor under the second power input module 204 and the second power output module 205 respectively, cuts off the power supply path of the second power input module 204, and connects the positive power supply terminal and the ground power supply terminal of the SRAM array module 200 through the second power output module 205 to pull down the power supply voltage of the SRAM array module 200 and raise the power supply ground voltage of the SRAM array module 200.

[0099] Please Figure 7 Based on, refer to Figure 11 , Figure 11 The circuit schematic diagram of the write auxiliary circuit provided in the embodiment of this application shows that the second power output module 205 includes a sixth PMOS transistor PM6, a sixth NMOS transistor NM6, and an eighth PMOS transistor PM8; the second power input module 204 includes a seventh PMOS transistor PM7 and a seventh NMOS transistor NM7.

[0100] The source of the seventh PMOS transistor PM7 is connected to the positive power rail of the SRAM memory system 10; the source of the seventh NMOS transistor NM7 is connected to the ground power rail of the SRAM memory system 10 to receive the VSS voltage; the drain of the seventh PMOS transistor PM7 is connected to the source of the eighth PMOS transistor PM8 and the source of the sixth PMOS transistor PM6; the drain of the seventh NMOS transistor NM7 is connected to the drain of the eighth PMOS transistor PM8 and the source of the sixth NMOS transistor NM6; the drain of the sixth NMOS transistor NM6 is connected to the power ground terminal VSC of the SRAM array module; the drain of the sixth PMOS transistor PM6 is connected to the positive power terminal VC of the SRAM array module; the gates of the sixth PMOS transistor PM6, the sixth NMOS transistor NM6, the seventh PMOS transistor PM7, the seventh NMOS transistor NM7, and the eighth PMOS transistor PM8 are all connected to the control module 103.

[0101] When in the data reading stage, in this embodiment, the control module 103 is used to send a second enable signal RCLK to the sixth PMOS transistor PM6, a first enable signal RCLKB to the sixth NMOS transistor NM6, a fourth enable signal WCLK to the seventh PMOS transistor PM7, and a third enable signal WCLKB to the seventh NMOS transistor NM7 and the eighth PMOS transistor PM8.

[0102] At this time, the fourth enable signal WCLK and the first enable signal RCLKB are at a high level, while the third enable signal WCLKB and the second enable signal RCLK are at a low level. This causes the sixth PMOS transistor PM6, the sixth NMOS transistor NM6, and the eighth PMOS transistor PM8 to be turned on, while the seventh PMOS transistor PM7 and the seventh NMOS transistor NM7 are turned off. Correspondingly, the fifth PMOS transistor PM5 and the fifth NMOS transistor NM5 in the read auxiliary circuit 102 are both turned off to prevent the read auxiliary circuit 102 from affecting the data writing stage.

[0103] Please Figure 11 Based on, refer to Figure 12 , Figure 13 , Figure 12 This is a simplified circuit diagram of the data writing stage in an embodiment of this application. Figure 13 This is a timing diagram of the write data stage in this embodiment. The working principle of the write data stage in this embodiment is as follows:

[0104] When the seventh PMOS transistor PM7 and the seventh NMOS transistor NM7 are turned off, and the sixth PMOS transistor PM6 and the sixth NMOS transistor NM6 are turned on, the positive power supply terminal of the SRAM array module 200 is disconnected from the positive power rail, and the ground power supply terminal is also disconnected from the ground power rail. That is, there is no external power supply during the write data stage, which can further reduce the energy consumption during the write stage.

[0105] Simultaneously, the eighth PMOS transistor PM8 is turned on, connecting the positive power supply terminal to the ground terminal in the SRAM array module 200, thereby transferring the charge stored in the SRAM array module 200. Figure 13 As shown, the VC voltage at the lower positive terminal of the SRAM array module 200 drops to 330mV, and correspondingly, the VSC voltage at the power ground terminal rises to 261mV. This achieves the reduction of the power supply voltage and the increase of the ground voltage in the SRAM array module 200, thereby improving the write noise margin WM of the SRAM array module 200.

[0106] Meanwhile, during this stage, the SRAM array module 200 is not powered by an external power source, which allows the voltage of the internal SRAM nodes to be maintained at VC. Therefore, after the write window closes, the fourth enable signal WCLK will go low. When the SRAM array module 200 is reconnected to the power supply, the internal SRAM nodes will also be pulled to the VDD value.

[0107] Similar to the previous embodiment, when in the data holding phase, the control module 103 is also used to send a third control signal to the write auxiliary circuit 101 and the read auxiliary circuit 102, driving the read auxiliary circuit 102 to provide power supply voltage to the SRAM array module 200, and driving the write auxiliary circuit 101 to provide power ground voltage to the SRAM array module 200. That is, in this embodiment, the voltage value VC at the positive power terminal of the SRAM array module 200 is equal to the voltage value VDD of the positive power rail of the SRAM storage system 10, making the power ground voltage value VSC of the SRAM array module 200 equal to the voltage value VSS of the lower ground power rail of the SRAM storage system 10.

[0108] Specifically, during the data holding phase, the second enable signal RCLK and the third enable signal WCLKB are low, while the first enable signal RCLKB and the fourth enable signal WCLK are high. Please refer to the following: Figure 11 In this embodiment, since the second enable signal RCLK and the third enable signal WCLKB are at a low level, the first PMOS transistor PM1 and the fifth PMOS transistor PM5 are turned on, connecting the positive power rail to the positive power terminal of the SRAM array module 200 to supply power to the SRAM array module 200. Since the first enable signal RCLKB and the fourth enable signal WCLK are at a high level, the second NMOS transistor NM2 and the fifth NMOS transistor NM5 are turned on, connecting the ground power rail in the read auxiliary circuit 102 to the ground terminal of the SRAM array module 200 to provide a ground terminal for the SRAM array module 200.

[0109] Simultaneously, because the sixth NMOS transistor NM6 and the seventh PMOS transistor PM7 in the write auxiliary circuit 101 are turned on, the positive power rail in the write auxiliary circuit 101 is connected to the positive power terminal of the SRAM array module 200, thus supplying power to the SRAM array module 200. The turn-on of the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7, and the turn-off of the eighth PMOS transistor PM8, connect the ground power rail in the write auxiliary circuit 101 to the ground terminal of the SRAM array module 200, thus providing ground to the SRAM array module 200.

[0110] Based on this, in the data retention phase of this embodiment, the power supply voltage in the SRAM array module 200 is equal to the voltage value VDD of the positive power rail, and the power ground voltage VSC of the power ground terminal is equal to the voltage value VSS of the ground power rail.

[0111] In summary, this embodiment constructs an external auxiliary circuit. During the read phase, the external auxiliary circuit adjusts the node voltage of the read auxiliary circuit based on the characteristic that the voltage difference across the capacitor cannot change abruptly. During the write phase, the control module adjusts the on / off state of each MOS transistor to redistribute the charge, thereby adjusting the output node voltage of the write auxiliary circuit and overcoming the mutual influence between the read and write auxiliary circuits. This can improve the read noise margin or write noise margin of the SRAM array module, and improve the anti-interference capability and read / write stability of SRAM while maintaining low cost and low power consumption.

[0112] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0113] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0114] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0115] It should be noted that if the function is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0116] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0117] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An SRAM read / write auxiliary circuit, applied to an SRAM storage system, the SRAM storage system comprising an SRAM array module, characterized in that, The SRAM read / write auxiliary circuit includes a write auxiliary circuit, a read auxiliary circuit, and a control module. The output terminals of the write auxiliary circuit and the read auxiliary circuit are both connected to the power supply terminal of the SRAM array module. The control module is also connected to the control terminals of the write auxiliary circuit and the read auxiliary circuit. When in the data reading stage, the control module is used to send a first control signal to the write auxiliary circuit and the read auxiliary circuit, turn off the write auxiliary circuit, drive the read auxiliary circuit to raise the power supply voltage of the SRAM array module based on the capacitor characteristics, and pull down the power supply ground voltage of the SRAM array module to improve the read noise margin. When in the data writing stage, the control module sends a second control signal to the write auxiliary circuit and the read auxiliary circuit to shut down the read auxiliary circuit, drive the write auxiliary circuit to pull down the power supply voltage of the SRAM array module, and raise the power supply ground voltage of the SRAM array module to improve the write noise margin.

2. The SRAM read / write auxiliary circuit according to claim 1, characterized in that, The power supply terminal of the SRAM array module includes a positive power supply terminal and a ground power supply terminal; the read auxiliary circuit includes a first power input module, a first capacitor assembly, and a first power output module; the first power input module, the first capacitor assembly, and the first power output module are connected in sequence to form a first power supply branch and a second power supply branch, and the output terminal of the first power supply branch is connected to the positive power supply terminal. The output terminal of the second power supply branch is connected to the power supply ground terminal; The control module is used to send a first control signal to the read auxiliary circuit to drive the first power supply branch to raise the power supply voltage of the SRAM array module based on the capacitive effect; and to drive the second power supply branch to lower the power supply ground voltage based on the capacitive effect.

3. The SRAM read / write auxiliary circuit according to claim 2, characterized in that, The first power input module includes a PMOS transistor pair and an NMOS transistor pair. The source of each PMOS transistor in the PMOS transistor pair is connected to the positive power rail of the SRAM memory system. The source of each NMOS transistor in the NMOS transistor pair is connected to the ground power rail of the SRAM memory system. The gate of each PMOS transistor and the gate of each NMOS transistor are connected to the control module. When in the data reading stage, the control module is used to send a first enable signal to the target PMOS transistor and a second enable signal to the other PMOS transistors besides the target PMOS transistor. The control module is also configured to send a first enable signal to the target NMOS transistor and a second enable signal to the other NMOS transistors besides the target NMOS transistor. The first enable signal and the second enable signal are complementary signals; The target PMOS transistor is used to characterize the PMOS transistor in the PMOS transistor pair used to construct the first power supply branch; the target NMOS transistor is used to characterize the NMOS transistor in the NMOS transistor pair used to construct the second power supply branch.

4. The SRAM read / write auxiliary circuit according to claim 3, characterized in that, The first capacitor assembly includes two capacitor units and two MOSFETs. Each capacitor unit includes a capacitor device formed by connecting MOSFETs. The control terminal of each MOSFET is connected to the control module. When in the data reading stage, the control module is used to send a first enable signal to the target MOS transistor and a second enable signal to the MOS transistors other than the target MOS transistor, so that the node voltage of the target capacitor unit is greater than the voltage of the positive power rail, and the node voltage of the capacitor units other than the target capacitor unit is less than the voltage of the ground power rail. The target capacitor unit is used to characterize the capacitor unit used to construct the first power supply branch under the first capacitor assembly; the target MOS transistor is used to characterize the MOS transistor corresponding to the target capacitor unit; Specifically, for any power supply branch, the channel type of the MOSFET corresponding to the current power supply branch is opposite to the MOSFET type in the corresponding power input module.

5. The SRAM read / write auxiliary circuit according to claim 4, characterized in that, The power input module includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor, and the first capacitor assembly includes a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, and a fourth NMOS transistor; The sources of the first PMOS transistor and the second PMOS transistor are connected to the positive power rail of the SRAM memory system; the sources of the first NMOS transistor and the second NMOS transistor are connected to the ground power rail of the SRAM memory system; the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor and the gate of the fourth PMOS transistor to receive the first enable signal; the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor and the gate of the third NMOS transistor to receive the second enable signal; the drain of the first PMOS transistor is connected to the gate of the third PMOS transistor. The gate of the first NMOS transistor, the drain of the fourth NMOS transistor, and the first input terminal of the first power output module are connected. The source of the third NMOS transistor is connected to the drain of the second NMOS transistor and the source of the third NMOS transistor. The source of the third NMOS transistor is also connected to its own drain. The drain of the second NMOS transistor is connected to the drain of the third NMOS transistor, the drain of the fourth NMOS transistor, and the second input terminal of the first power output module. The source of the fourth NMOS transistor is connected to the drain of the first NMOS transistor and the gate of the fourth NMOS transistor. The source of the fourth NMOS transistor is connected to its own drain.

6. The SRAM read / write auxiliary circuit according to claim 5, characterized in that, The first power output module includes a fifth PMOS transistor and a fifth NMOS transistor. The source of the fifth PMOS transistor serves as the first input terminal of the first power output module and is connected to the drain of the first PMOS transistor. The gates of the fifth PMOS transistor and the fifth NMOS transistor are both connected to the control module. The source of the fifth NMOS transistor serves as the second input terminal of the first power output module and is connected to the drain of the second NMOS transistor. The drain of the fifth PMOS transistor is connected to the positive power supply terminal of the SRAM array module, and the drain of the fifth NMOS transistor is connected to the ground power supply terminal of the SRAM array module. When in the data reading stage, the control module is also used to send a third enable signal to the fifth NMOS transistor and a fourth enable signal to the fifth PMOS transistor, so that the first power supply branch provides power to the SRAM array module through the fifth PMOS transistor to raise the power supply voltage; and so that the second power supply branch provides power ground to the SRAM array module through the fifth NMOS transistor. The third enable signal and the fourth enable signal are complementary signals.

7. The SRAM read / write auxiliary circuit according to claim 6, characterized in that, When in the data reading stage, the control module is also used to drive the first PMOS transistor to turn off, the third NMOS transistor to turn off, the second PMOS transistor to turn on, and the fifth PMOS transistor to turn on, so as to obtain the first power supply branch and supply power to the SRAM array module. The control module is also used to drive the second NMOS transistor to turn off, the first NMOS transistor to turn on, the fourth PMOS transistor to turn off, and the fifth NMOS transistor to turn on, so as to obtain the second power supply branch and provide power ground for the SRAM array module; When in the data writing phase, the control module is also used to drive the fifth PMOS transistor to turn off and the fifth NMOS transistor to turn off.

8. The SRAM read / write auxiliary circuit according to any one of claims 1 to 7, characterized in that, The write auxiliary circuit includes a second power input module and a second power output module; both the second power input module and the second power output module include a pair of MOS transistors, each pair of MOS transistors including a PMOS transistor and an NMOS transistor; the gate of each PMOS transistor and the gate of each NMOS transistor are connected to the control module. When in the data writing stage, the control module is used to send second control signals to each PMOS transistor and NMOS transistor in the second power input module and the second power output module respectively, cut off the power supply path of the second power input module, and connect the positive power terminal and the ground power terminal of the SRAM array module through the second power output module to pull down the power supply voltage of the SRAM array module and raise the power supply ground voltage of the SRAM array module.

9. The SRAM read / write auxiliary circuit according to claim 8, characterized in that, The second power output module includes a sixth PMOS transistor, a sixth NMOS transistor, and an eighth PMOS transistor; the second power input module includes a seventh PMOS transistor and a seventh NMOS transistor. The source of the seventh PMOS transistor is connected to the positive power rail of the SRAM memory system; the source of the seventh NMOS transistor is connected to the ground power rail of the SRAM memory system; the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor and the source of the sixth PMOS transistor; the drain of the seventh NMOS transistor is connected to the drain of the eighth PMOS transistor and the source of the sixth NMOS transistor; the drain of the sixth NMOS transistor is connected to the power ground terminal of the SRAM array module; the drain of the sixth PMOS transistor is connected to the positive power terminal of the SRAM array module; and the gates of the sixth PMOS transistor, the sixth NMOS transistor, the seventh PMOS transistor, the seventh NMOS transistor, and the eighth PMOS transistor are all connected to the control module. When in the data reading stage, the control module is also used to drive the sixth PMOS transistor to turn off and the sixth NMOS transistor to turn off; When in the data writing phase, the control module is also used to drive the sixth PMOS transistor to turn on, the sixth NMOS transistor to turn on, the eighth PMOS transistor to turn on, the seventh PMOS transistor to turn off, and the seventh NMOS transistor to turn off.

10. An SRAM storage system, characterized in that, It includes an SRAM array module and the SRAM read / write auxiliary circuit as described in any one of claims 1 to 9.

Images