A high-precision ptp time engine synchronization system and method across clock domains

Abstract

The application relates to the technical field of network time synchronization, in particular to a cross-clock-domain high-precision PTP time engine synchronization system and method, which comprises a master clock domain, a master time engine module is established in the master clock domain, the master time engine module comprises a master time engine counter, the master clock domain is used for driving the master time engine counter, the bit width of the master time engine counter is 80 bits, the master time engine counter is used for generating master time information and a second pulse signal 1PPS_OUT_M, a port Rx clock domain is further included, a port Rx time engine module is independently arranged in the port Rx clock domain, the port Rx time engine module comprises a port Rx time engine counter, the port Rx clock domain is used for driving the port Rx time engine counter, the bit width of the port Rx time engine counter is 80+N bits, wherein the high 48 bits Counter_Rx[79+N:32+N] represent the second bit, the low 32+N bits Counter_Rx[31+N:0] represent the part within the second, and one LSB represents 2^‑N nanoseconds, so that the precision of the device is improved.

Description

Technical Field

[0001] This application relates to the field of network time synchronization technology, and in particular to a high-precision PTP time engine synchronization system and method across clock domains. Background Technology

[0002] In a typical PTP device architecture, multiple clock domains typically exist. 1. Master Clock Domain: Driven by the device's local clock, it maintains a master time engine as a reference. 2. Port Clock Domain: Each physical network port (e.g., 1G / 10G Ethernet) has its own independent transmit and receive data paths. The transmit path is driven by the Tx clock, which can be clocked simultaneously with the master clock; while the receive path's clock is extracted from the line data by the Clock Data Recovery (CDR) module. This CDR clock typically belongs to a different clock domain than the master clock.

[0003] In existing technologies, when timestamping PTP event messages in the receiving path, since the Rx clock and the main time engine are in different clock domains, traditional designs must insert an asynchronous FIFO between them for cross-clock domain processing. While this ensures the stability of signal sampling, it inevitably introduces a fixed error of at least one PTP time engine clock cycle, which has become a bottleneck restricting further improvements in PTP synchronization accuracy.

[0004] Therefore, a high-precision PTP time engine synchronization system and method across clock domains is proposed. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a high-precision PTP time engine synchronization system and method across clock domains. This solves the problem that traditional designs must insert an asynchronous FIFO between the two for cross-clock domain processing, introducing at least one fixed error in the PTP time engine clock cycle, resulting in low device accuracy.

[0006] The above-mentioned objective of this application is achieved through the following technical solution: a cross-clock domain high-precision PTP time engine synchronization system, including a master clock domain, a master time engine module established in the master clock domain, a master time engine counter in the master time engine module, the master clock domain being used to drive the master time engine counter, the master time engine counter having a bit width of 80 bits, used to generate master time information and second pulse signal 1PPS_OUT_M, and also including a port Rx clock domain, a port Rx time engine module independently deployed in the port Rx clock domain, the port Rx time engine module including a port Rx time engine counter, the port Rx clock domain being used to drive the port Rx time engine counter, the port Rx time engine counter having a bit width of 80+N bits, where the high 48 bits Counter_Rx[79+N: 32+N] represent the second digit, the low 32+N bits Counter_Rx[31+N:0] represent the portion within the second, and one LSB represents 2^-N nanoseconds.

[0007] Furthermore, it also includes a time-to-digital converter (TDC), which measures the phase deviation ΔT between 1PPS_OUT_M and the second pulse signal 1PPS_OUT_Rx of the port Rx time engine module, and calculates the residual based on the count value of the port Rx time engine counter at the second flip-off moment.

[0008] Furthermore, a cross-clock domain high-precision PTP time engine synchronization method, applied to any of the above-mentioned technical solutions in a cross-clock domain high-precision PTP time engine synchronization system, includes the following steps:

[0009] S1. The master clock domain establishes the master time engine module, using the master clock to drive the master time engine counter. The master time engine counter has a bit width of 80 bits and is used to generate master time information and second pulse signal 1PPS_OUT_M.

[0010] S2. Deploy the port Rx time engine module independently in the port Rx clock domain, and use the port Rx clock to drive the port Rx time engine counter. The port Rx time engine counter has a bit width of 80+N bits, of which the high 48 bits represent seconds and the low 32+N bits represent the part within seconds. One LSB represents 2^-N nanoseconds, where N is a positive integer.

[0011] S3. Perform coarse synchronization on the port Rx time engine module to align the port Rx time engine module with the main time engine module at the nanosecond level.

[0012] S4. High-precision phase deviation detection: The phase deviation ΔT between 1PPS_OUT_M and the second pulse signal 1PPS_OUT_Rx of the port Rx time engine module is measured using a time-to-digital converter (TDC). The residual is calculated based on the count value of the port Rx time engine counter at the second flip time. The residual is used to correct ΔT to obtain the true phase deviation ΔT_actual.

[0013] S5. Generate a step correction value based on the actual phase deviation ΔT_actual, which is used to adjust the step value of the port Rx time engine counter;

[0014] S6. Synchronize the port Rx time engine module with the main time engine module through closed-loop control.

[0015] Furthermore, the specific detection steps in the high-precision phase deviation detection process include:

[0016] S41. Use TDC to measure the phase deviation ΔT between 1PPS_OUT_M and 1PPS_OUT_Rx;

[0017] S42, the first count value of the latch port Rx time engine counter after the second toggle;

[0018] S43. Calculate the difference between the count value and the theoretical second value to obtain the residual.

[0019] S44. Add the residual to the phase deviation ΔT measured by TDC to obtain the actual phase deviation ΔT_actual = ΔT + residual.

[0020] In summary, this application includes at least one of the following beneficial technical effects:

[0021] In this invention, the bit width of the Counter_Rx time engine counter is expanded to 80+N bits, where the high 48 bits of Counter_Rx[79+N: 32+N] represent the seconds, and the low 32+N bits of Counter_Rx[31+N: 0] represent the portion within the seconds. One LSB represents 2^-N nanoseconds. This method improves the step value correction accuracy from 1 nanosecond to 2^-N nanoseconds, an improvement of 2^N times. Within a 1-second period, the quantization error is only (2^-N) * f_rx (where f_rx is the CLK_Rx clock frequency), greatly reducing the quantization error. Since Counter_Rx is in the same clock domain as the received data path, it can be directly used to timestamp received PTP messages without going through an asynchronous FIFO, eliminating the inherent one-clock-cycle error and improving the device's accuracy.

[0022] The flip time of 1PPS_OUT_Rx may not be at an integer second. In this case, it is necessary to latch the first count value of Counter_Rx after each flip and calculate its residual with the theoretical second value. This residual is used as a correction amount to compensate for the original measurement result ΔT of TDC, thereby obtaining the true phase deviation and further improving the accuracy of the device. Attached Figure Description

[0023] Figure 1 This is a block diagram of the overall architecture of this embodiment;

[0024] Figure 2 This is the timing diagram for phase deviation testing and correction in this embodiment. Detailed Implementation

[0025] The present application will be further described in detail below with reference to the accompanying drawings.

[0026] Example, refer to Figure 1 A cross-clock domain high-precision PTP time engine synchronization system includes a master clock domain, in which a master time engine module is established, and the master time engine module includes a master time engine counter. The master clock domain is used to drive the master time engine counter. The master time engine counter has a bit width of 80 bits and is used to generate master time information and second pulse signal 1PPS_OUT_M. It also includes a port Rx clock domain, in which a port Rx time engine module is independently deployed. The port Rx time engine module includes a port Rx time engine counter. The port Rx clock domain is used to drive the port Rx time engine counter. The port Rx time engine counter has a bit width of 80+N bits, where the high 48 bits Counter_Rx[79+N: 32+N] represent the second digits, and the low 32+N bits Counter_Rx[31+N: 0] represent the portion within the second. One LSB represents 2^-N nanoseconds. When using the device, a local high-stability oscillator (such as an OCXO) can be used to drive the main time engine module via a clock CLK_M generated by a PLL. The main time engine module can receive an external high-precision time reference source (such as 1PPS+ToD) for calibration, ensuring its long-term accuracy is traceable to UTC. The main time engine module generates a second pulse signal 1PPS_OUT_M, whose rising edge precisely corresponds to the second flip-off moment of the main time engine. In this invention, the bit width of the Counter_Rx time engine counter is extended to 80+N bits, where the high 48 bits Counter_Rx[79+N: 32+N] represent the second digit, and the low 32+N bits Counter_Rx[31+N: 0] represent the portion within the second. One LSB represents 2^-N nanoseconds. This method improves the step value correction accuracy from 1 nanosecond to 2^-N nanoseconds, an improvement of 2^N times.

[0027] For example, within a 1-second period, the quantization error is only (2^-N) * f_rx (where f_rx is the CLK_Rx clock frequency), greatly reducing the quantization error. Since Counter_Rx is in the same clock domain as the received data path, it can be directly used to timestamp received PTP messages without going through an asynchronous FIFO, eliminating the inherent one-clock-cycle error. The local master time engine CLK_M has a clock frequency of 250MHz and drives an 80-bit master time engine counter Counter_M[79:0], where Counter_M[79:32] represents the seconds, Counter_M[31:0] represents the nanoseconds, 1 LSB represents 1 nanosecond, and the counter increments by 4 nanoseconds every 250MHz clock cycle; the line recovery clock CLK_RX has a nominal clock frequency of 156.25MHz and drives a 112-bit Rx time engine counter Counter_Rx[111:0], where Counter_Rx[111:64] represents the seconds, Counter_Rx[63:0] represents the portion below the seconds, 1 LSB represents 2^-32 nanoseconds, and the counter increments by 6.4 nanoseconds every 156.25MHz clock cycle;

[0028] The initial step value for the Rx time engine counter Counter_Rx is:

[0029] Step_Base = Round( (1 / f_rx) * 1e9 * 2^32) = Round(27,487,790,694.4) = 27,487,790,694. In the above embodiment, the line recovery clock CLK_RX actually has a frequency offset of +1ppm, that is, the true frequency is 156.25MHz*(1+1e6). Furthermore, the independent port time engine module design allows each port to adapt to its own line clock, making it particularly suitable for multi-port applications.

[0030] It also includes a Time-to-Digital Converter (TDC), which measures the phase deviation ΔT between 1PPS_OUT_M and the second pulse signal 1PPS_OUT_Rx from the port Rx time engine module, and calculates the residual based on the count value of the port Rx time engine counter at the second flip point. The flip point of 1PPS_OUT_Rx may not be at an integer second. In this case, the first count value of Counter_Rx after each second flip needs to be latched, and its residual with the theoretical second value needs to be calculated. This residual is used as a correction amount to compensate for the original measurement result ΔT of the TDC, thereby obtaining the true phase deviation and further improving the accuracy of the device.

[0031] A cross-clock-domain high-precision PTP time engine synchronization method, applied to a cross-clock-domain high-precision PTP time engine synchronization system according to any one of the above-mentioned technical solutions, includes the following steps:

[0032] S1. Establish the master time engine module in the master clock domain. Use the master clock to drive the master time engine counter. The master time engine counter has a bit width of 80 bits and is used to generate master time information and the second pulse signal 1PPS_OUT_M. This step is the establishment and traceability of the master time engine: use the clock CLK_M generated by the local high-stability oscillator (such as OCXO) via PLL to drive an 80-bit master time engine counter Counter_M[79:0]. The high 48 bits Counter_M[79:32] represent seconds, and the low 32 bits Counter_M[31:0] represent nanoseconds. One LSB represents 1 nanosecond. The master time engine can receive an external high-precision time reference source (such as 1PPS+ToD) for calibration, so that its long-term accuracy traceability is to UTC. The master time engine generates a second pulse signal 1PPS_OUT_M, the rising edge of which precisely corresponds to the second flip time of the master time engine.

[0033] S2. Deploy the port Rx time engine module independently in the port Rx clock domain. Use the port Rx clock to drive the port Rx time engine counter. The port Rx time engine counter has a bit width of 80+N bits, where the high 48 bits represent seconds and the low 32+N bits represent the portion within seconds. One LSB represents 2^-N nanoseconds, where N is a positive integer. This step is the independent deployment of the port time engine: in the Rx direction of each network port, use the clock CLK_Rx recovered by the port CDR module to independently drive a port Rx time engine counter Counter_Rx. In traditional designs, the PTP time engine counter bit width is generally designed to be 80 bits (48 bits for seconds + 32 bits for nanoseconds). When the counter step value needs to be adjusted, the minimum adjustment step size is 1 LSB (1 nanosecond), resulting in large quantization errors and making it impossible to achieve sub-nanosecond level fine compensation. In this invention, the bit width of the Counter_Rx time engine counter is expanded to 80+N bits, where the high 48 bits of Counter_Rx[79+N: 32+N] represent the seconds, and the low 32+N bits of Counter_Rx[31+N: 0] represent the portion within the seconds. One LSB represents 2^-N nanoseconds. This method improves the step value correction accuracy from 1 nanosecond to 2^-N nanoseconds, an improvement of 2^N times. Within a 1-second period, the quantization error is only (2^-N) * f_rx (where f_rx is the CLK_Rx clock frequency), greatly reducing the quantization error. Since Counter_Rx is in the same clock domain as the received data path, it can be directly used to timestamp received PTP messages without going through an asynchronous FIFO, eliminating the inherent one-clock-cycle error.

[0034] S3. Perform coarse synchronization on the port Rx time engine module to align it with the main time engine module at the nanosecond level. This step is the coarse synchronization of the port time engine: After port initialization, on the rising edge of the 1PPS_OUT_M signal, latch the current time value of the main time engine (i.e., ToD: year, month, day, hour, minute, second); on the next rising edge of the 1PPS_OUT_M signal, increment this ToD value by 1 second and write it to the high 80 bits of the port Rx time engine counter, Counter_Rx[79+N: N], and set the low N bits of Counter_Rx[N-1:0] to 0, thus achieving coarse synchronization between the port Rx time engine and the main time engine; the port Rx time engine then outputs its own second pulse signal 1PPS_OUT_Rx, the rising edge of which corresponds to the second flip time of the Rx time engine.

[0035] S4. High-precision phase deviation detection: The phase deviation ΔT between 1PPS_OUT_M and the second pulse signal 1PPS_OUT_Rx from the port Rx time engine module is measured using a time-to-digital converter (TDC). The residual is calculated based on the count value of the port Rx time engine counter at the second flip point, and the residual is used to correct ΔT to obtain the true phase deviation ΔT_actual. This step constitutes high-precision phase deviation detection: The phase deviation ΔT between 1PPS_OUT_M and 1PPS_OUT_Rx is continuously measured using a TDC; ΔT = 1PPS_OUT_Rx - 1PPS_OUT_M. A positive ΔT indicates that 1PPS_OUT_Rx leads 1PPS_OUT_M, and a negative ΔT indicates that 1PPS_OUT_Rx lags 1PPS_OUT_M.

[0036] Key correction mechanism: The flip time of 1PPS_OUT_Rx may not fall on an integer second. In this case, the first count value of Counter_Rx after each flip needs to be latched, and its residual with the theoretical second value is calculated. This residual is used as a correction amount to compensate for the original measurement result ΔT of TDC, thereby obtaining the true phase deviation. ΔT_actual = ΔT + residual, where residual represents the residual between the first count value after Counter_Rx flip and the theoretical second value, and ΔT_actual is the true phase deviation between 1PPS_OUT_M and 1PPS_OUT_Rx after correcting the residual, with units in nanoseconds. This step further improves the accuracy of the device.

[0037] S5. Generate a step correction value based on the actual phase deviation ΔT_actual to adjust the step value of the port Rx time engine counter. This step involves generating the step correction value: the frequency of the port Rx clock CLK_Rx is determined by the clock data recovery module CDR. When adjusting the port Rx time engine, this invention does not adjust the CLK_Rx frequency, but indirectly compensates for the frequency offset and phase difference of CLK_Rx relative to CLK_M by dynamically correcting the step value of the port Rx time engine counter. The advantage of this is that it ensures the port Rx time engine is in the same clock domain as the received data path, thus allowing it to be directly used to timestamp received PTP messages.

[0038] The method for generating step correction values ​​can be selected as needed (such as PID control or master clock driving algorithm, etc.). Taking PID control as an example:

[0039] 1. Control Model:

[0040] Controlled object: Port time engine counter Counter_Rx;

[0041] Control objective: To make the actual phase deviation ΔT_actual between 1PPS_OUT_Rx and 1PPS_OUT_M approach zero;

[0042] Control value: Step_Correction, the step correction value of the counter.

[0043] 2. PID controller design:

[0044] Assuming the nominal frequency of CLK_Rx is f_rx, then the initial step value of the Rx time engine counter Counter_Rx[79+N:0] is...

[0045] Step_Base = Round( (1 / f_rx) * 1e9 * 2^N),

[0046] The PID controller calculates the step correction value based on the phase deviation ΔT_actual[n] obtained by sampling and correcting the residuals per second (TDC). Using the PID control algorithm, ignoring the derivative term, the discrete representation is:

[0047] ;

[0048] The step correction value is:

[0049] ;

[0050] The actual accumulated value of Counter_Rx becomes:

[0051] Counter_Rx_Corrected[n+1] = Step_Base - Step_Correction[n]

[0052] Note: Step_Correction[n] is the step correction value calculated after the nth second. After using it to calculate Counter_Rx_Corrected[n+1], this step value is used on Counter_Rx[79+N:0] at the (n+1)th second. Frequency offset and phase deviation can be smoothly compensated through PID control algorithms or master clock driving algorithms, enabling the port Rx time engine to output a stable, low-jitter time signal.

[0053] S6. Synchronize the port Rx time engine module with the main time engine module through closed-loop control. This step involves closed-loop control until synchronization: select Kp = 1.8, Ki = 0.25, and the system continuously runs steps S4 and S5 to form a closed-loop control. The control period can be set as needed (in this invention, the deviation is detected once per second, and a step correction is applied once per second) until the phase deviation ΔT_actual between the port Rx time engine and the main time engine stabilizes within a preset threshold (e.g., ±1 ns), achieving a synchronization lock state.

[0054] An example illustrating steps S1-S6 above:

[0055] 1. The main time engine Counter_M[79:0] is initialized to 0 and runs freely, generating a second pulse signal 1PPS_OUT_M, whose rising edge precisely corresponds to the second flip time of the main time engine.

[0056] 2. The initial value of the Rx time engine Counter_Rx[111:0] is 0, and the step value Step_Base per clock cycle is 27,487,790,694.

[0057] 3. At the rising edge of the next 1PPS_OUT_M signal (2 seconds), increment this ToD value by 1 second (i.e., 2 seconds) and write the high 80 bits of the port Rx time engine counter Counter_Rx[111:32], while setting the low 32 bits of Counter_Rx[31:0] to 0. That is, at the 2nd second, coarse synchronization between the port Rx time engine and the main time engine is achieved, with a coarse synchronization accuracy of one cycle of 156.25MHz, or 6.4 nanoseconds.

[0058] 4. Starting from the third second, use TDC to measure the phase deviation ΔT between 1PPS_OUT_M and 1PPS_OUT_Rx. Assume that ΔT = 1001 nanoseconds is measured in the third second; when Counter_Rx[111:0] flips in the third second, assume that its count value is 3.000000005415 seconds, then the residual value is 5.415 nanoseconds. Use this residual as a correction amount to compensate for the original measurement result ΔT of TDC, thereby obtaining the true phase deviation ΔT_actual = ΔT + residual = 1006.415 nanoseconds.

[0059] 5. Calculate the step correction value: .

[0060] With Kp = 1.8, Ki = 0.25, ΔT_actual[1] and ΔT_actual[2] = 0, ΔT_actual[3] = 1006.415 nanoseconds, and f_rx = 156250000Hz, we can obtain Step_Correction[3] = 56711. Then, the step value of the 4th second, Counter_Rx_Corrected[n+1] = Step_Base - Step_Correction[n] = 27,487,790,694 – 56711 = 27,487,733,983.

[0061] 6. Continue running steps S4 and S5 to form a closed-loop control. In actual testing, when the actual frequency deviation of CLK_RX is +1ppm, the phase error between the Rx time engine and the main time engine converges to within ±1 nanosecond around the 80th second. When the actual frequency deviation of CLK_RX is within the range of 0ppm to 100ppm, the phase error can converge to within ±1 nanosecond within 150 seconds, and the performance meets expectations.

[0062] The above example is one of the embodiments described, and is not the only implementation method.

[0063] The high-precision phase deviation detection process includes the following steps: S41, measuring the phase deviation ΔT between 1PPS_OUT_M and 1PPS_OUT_Rx using a TDC; S42, latching the first count value of the Rx time engine counter after the second flip; S43, calculating the difference between the count value and the theoretical second value to obtain the residual; S44, adding the residual to the phase deviation ΔT measured by the TDC to obtain the actual phase deviation ΔT_actual = ΔT + residual. These high-precision phase deviation detection steps further improve the testing accuracy of the device.

[0064] The embodiments described in this specific implementation are preferred embodiments of this application and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A cross-clock domain high-precision PTP time engine synchronization system, characterized in that: It includes a master clock domain, in which a master time engine module is established. The master time engine module includes a master time engine counter. The master clock domain is used to drive the master time engine counter. The master time engine counter has a bit width of 80 bits and is used to generate master time information and a second pulse signal 1PPS_OUT_M. It also includes a port Rx clock domain, in which a port Rx time engine module is independently deployed. The port Rx time engine module includes a port Rx time engine counter. The port Rx clock domain is used to drive the port Rx time engine counter. The bit width of the port Rx time engine counter is 80+N bits, of which the high 48 bits Counter_Rx[79+N:32+N] represent the second digit, and the low 32+N bits Counter_Rx[31+N:0] represent the portion within the second. One LSB represents 2^-N nanoseconds. It also includes a time-to-digital converter (TDC), which measures the phase deviation ΔT between 1PPS_OUT_M and the second pulse signal 1PPS_OUT_Rx of the port Rx time engine module, and calculates the residual based on the count value of the port Rx time engine counter at the second flip-off moment.

2. A cross-clock domain high-precision PTP time engine synchronization method, applied to the cross-clock domain high-precision PTP time engine synchronization system described in claim 1 above, characterized in that, Includes the following steps: S1. The master clock domain establishes the master time engine module, using the master clock to drive the master time engine counter. The master time engine counter has a bit width of 80 bits and is used to generate master time information and second pulse signal 1PPS_OUT_M. S2. Deploy the port Rx time engine module independently in the port Rx clock domain, and use the port Rx clock to drive the port Rx time engine counter. The port Rx time engine counter has a bit width of 80+N bits, of which the high 48 bits represent seconds and the low 32+N bits represent the part within seconds. One LSB represents 2^-N nanoseconds, where N is a positive integer. S3. Perform coarse synchronization on the port Rx time engine module to align the port Rx time engine module with the main time engine module at the nanosecond level. S4. High-precision phase deviation detection: The phase deviation ΔT between 1PPS_OUT_M and the second pulse signal 1PPS_OUT_Rx of the port Rx time engine module is measured using a time-to-digital converter (TDC). The residual is calculated based on the count value of the port Rx time engine counter at the second flip time. The residual is used to correct ΔT to obtain the true phase deviation ΔT_actual. S5. Generate a step correction value based on the actual phase deviation ΔT_actual, which is used to adjust the step value of the port Rx time engine counter; S6. Synchronize the port Rx time engine module with the main time engine module through closed-loop control.

3. The method for high-precision PTP time engine synchronization across clock domains according to claim 2, characterized in that, The specific detection steps in the high-precision phase deviation detection process include: S41. Use TDC to measure the phase deviation ΔT between 1PPS_OUT_M and 1PPS_OUT_Rx; S42, the first count value of the latch port Rx time engine counter after the second toggle; S43. Calculate the difference between the count value and the theoretical second value to obtain the residual. S44. Add the residual to the phase deviation ΔT measured by TDC to obtain the true phase deviation ΔT_actual = ΔT + residual.

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