Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a gate electrode, and a second electrode. The gate electrode has a first region facing the second semiconductor region and a second region facing the third semiconductor region. The gate electrode has a first length from the lower surface to the upper surface of the second region and a second length from the lower surface to the upper surface of the first region, and the first length is greater than the second length.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2024-110936, filed on July 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] In summary, the embodiments described herein relate to semiconductor devices and methods of manufacturing them. Background Technology

[0004] Semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs) are used for power conversion and other related functions. When the voltage applied to the gate electrode is set to be equal to or higher than the threshold voltage Vth, a channel (inversion layer) is formed in the semiconductor layer to allow current to flow, and the semiconductor device becomes ON. When the voltage applied to the gate electrode is set to be lower than the threshold voltage Vth, no current flows, and the semiconductor device becomes OFF. Summary of the Invention

[0005] The purpose of this embodiment is to provide a semiconductor device that can improve switching performance while minimizing the increase in threshold voltage.

[0006] According to one embodiment, a semiconductor device includes: a first electrode; a first semiconductor region of a first conductivity type disposed on and electrically connected to the first electrode; a second semiconductor region of a second conductivity type disposed on the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region; and a gate electrode including: a first region facing the second semiconductor region across a gate insulating portion in a second direction intersecting a first direction from the first electrode toward the first semiconductor region; and a second region disposed on the first region and facing the third semiconductor region across the gate insulating portion in the second direction; and a second electrode electrically connected to the third semiconductor region, the gate electrode having: a first length in the first direction from a lower surface of the first region to an upper surface of the second region, and a second length from the lower surface of the first region to an upper surface of the first region in contact with the gate insulating portion, the first length being greater than the second length.

[0007] According to another embodiment, a semiconductor device includes: a first electrode; a first semiconductor region of a first conductivity type disposed on and electrically connected to the first electrode; a second semiconductor region of a second conductivity type disposed on the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region; a gate electrode including: a first region facing the second semiconductor region across a gate insulating portion in a second direction intersecting a first direction from the first electrode toward the first semiconductor region; a second region disposed on the first region and facing the third semiconductor region across the gate insulating portion in the second direction; and a second electrode electrically connected to the third semiconductor region, the gate electrode having stepped protrusions.

[0008] According to another embodiment, a method for manufacturing a semiconductor device includes: preparing a substrate, wherein a trench is formed in the substrate; forming an insulating film on the surface of the trench; forming a gate electrode in the trench, the gate electrode being opposite to the substrate, wherein the insulating film is disposed between the gate electrode and the substrate; selectively removing the gate electrode near the insulating film in a first direction along the interface between the gate electrode and the insulating film; and forming an insulating layer on the gate electrode and the insulating film. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view showing a semiconductor device according to the first embodiment;

[0010] Figure 2 This is a cross-sectional view of the gate electrode structure in the semiconductor device according to the first embodiment.

[0011] Figure 3 This is a graph showing the variation of the threshold voltage Vth in the semiconductor device according to the first embodiment.

[0012] Figure 4 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0013] Figure 5 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0014] Figure 6 This is a cross-sectional view of the semiconductor device according to the second embodiment.

[0015] Figures 7A to 7H This is a cross-sectional view of an example method for manufacturing a semiconductor device according to the first embodiment.

[0016] Figures 8A to 8E This is a cross-sectional view of an example method for manufacturing a semiconductor device according to the second embodiment. Detailed Implementation

[0017] In the following description, each embodiment will be illustrated with reference to the accompanying drawings.

[0018] It should be noted that the accompanying drawings are schematic or conceptual. The relationship between the thickness and width of each part, the dimensional ratios between parts, etc., may not be the same as the actual figures.

[0019] Furthermore, even when representing the same parts, dimensions and ratios can be shown differently depending on the accompanying drawings.

[0020] For example, the cross-sectional view in this specification shows a laminated structure, but the thickness ratio of each layer in the laminated structure may not be the same as the thickness ratio in the actual structure. Even if one layer is shown to be thicker than another in the cross-sectional view, in practice, there may be cases where one layer and another have substantially the same thickness, or one layer is thinner than the others. That is to say, dimensions such as thickness shown in the accompanying drawings of this specification may differ from the actual dimensions.

[0021] The direction from the first electrode 71 to the second electrode 72 is defined as the Z direction (first direction). The direction perpendicular to the Z direction is defined as the X direction (second direction), and the direction intersecting the X and Z directions is defined as the Y direction (third direction). It should be noted that in this embodiment, the X, Y, and Z directions are shown as being in a perpendicular relationship, but they are not limited to a perpendicular relationship and can be in any relationship as long as they intersect each other.

[0022] For ease of explanation, the positive direction in the Z-direction is called "up," and the negative direction in the Z-direction is called "down." However, the "up" and "down" directions are not limited to the direction of gravity or the direction when mounting semiconductor devices. When describing the perpendicular positional relationship between regions with different positions in the XY plane, the positions of each region in the Z-direction are compared.

[0023] In the following description, the symbol n + , n and n - and p + p and p - This indicates the relative level of impurity concentration for each type of conductivity. In other words, n + This indicates that the concentration of n-type impurities is relatively higher than that of n, n - This indicates that the concentration of n-type impurities is relatively lower than that of n. Furthermore, p... + This indicates that the concentration of p-type impurities is relatively higher than that of p-type impurities. - This indicates that the concentration of p-type impurities is relatively lower than that of p-type impurities. It should be noted that n... + type and n - The type can be simply referred to as the n-type, p + type and p- The type can be simply referred to as the p-type.

[0024] It should be noted that in this specification and the accompanying drawings, the same elements as those described above with reference to the previously described drawings are indicated by the same reference numerals, and their detailed descriptions will not be repeated.

[0025] (First Implementation)

[0026] Figure 1 This is a cross-sectional view of the semiconductor device 100 according to the first embodiment.

[0027] For example, Figure 1 The semiconductor device 100 shown is a MOSFET. The semiconductor device 100 includes a first semiconductor region 1(n) of a first conductivity type. - Drift region), second semiconductor region 2 of the second conductivity type (p) - Base region), third semiconductor region 3 (n) of the first conductivity type + Source region), fourth semiconductor region 4 (p) of the second conductivity type + Contact area), fifth semiconductor region 5 (n) of the first conductivity type + Drain region), first insulating part 10, second insulating part 20, conductive part 30, gate electrode 40, side insulating part 50, insulating layer 60, first electrode 71 (drain) and second electrode 72 (source).

[0028] A fifth semiconductor region 5 is disposed on the first electrode 71. A first semiconductor region 1 is disposed on the fifth semiconductor region 5 and is electrically connected to the first electrode 71 via the fifth semiconductor region 5. A second semiconductor region 2 is disposed on the first semiconductor region 1. A third semiconductor region 3 and a fourth semiconductor region 4 are selectively disposed on the second semiconductor region 2.

[0029] A conductive portion 30 is disposed in the first semiconductor region 1, separated from the conductive portion 30 by a first insulating portion 10. A gate electrode 40 is disposed at a position spaced apart from the conductive portion 30 in the positive direction along the Z direction. A second insulating portion 20 is disposed between the gate electrode 40 and the conductive portion 30. The specific structure of the gate electrode 40 will be described later.

[0030] A second electrode 72 is disposed above the third semiconductor region 3 and the fourth semiconductor region 4. Figure 1 In the example shown, an insulating layer 60 is disposed on the third semiconductor region 3. A portion of the second electrode 72 is electrically connected to the third semiconductor region 3 and the fourth semiconductor region 4 via a first plug P1 disposed in the insulating layer 60.

[0031] The gate electrode 40 is opposite to the second semiconductor region 2 and the third semiconductor region 3 in the X direction, separated by a lateral insulating portion 50. An insulating layer 60 is provided between the gate electrode 40 and the second electrode 72, and the gate electrode 40 is electrically insulated from the second electrode 71.

[0032] The gate electrode 40 includes a first region 41 and a second region 42 disposed on the first region 41. (See below for further details.) Figure 2 Describe the shape of the gate electrode 40 in detail.

[0033] For example, a plurality of second semiconductor regions 2, a plurality of third semiconductor regions 3, a plurality of fourth semiconductor regions 4, a plurality of conductive portions 30, a plurality of first insulating portions 10, a plurality of second insulating portions 20, a plurality of gate electrodes 40, and a plurality of side insulating portions 50 are provided in the X direction and extend along the Y direction. It should be noted that the shapes of the conductive portions 30 provided in the X direction can be different from each other. Furthermore, portions between the conductive portions 30 and the insulating layer 60 where no gate electrodes 40 are provided can be partially provided. For example, as described later... Figure 5 As shown, in the portion where the gate electrode 40 is not provided, the conductive portion 30 extends below the insulating layer 60 (between the second semiconductor regions 2 adjacent to each other in the X direction) in the positive direction of the Z direction.

[0034] Next, we will refer to Figure 2 Describe the structure of the gate electrode 40.

[0035] Figure 2 This is a cross-sectional view showing the area near the gate electrode 40 in the semiconductor device 100. The shaded portions of the first insulating portion 10, the second insulating portion 20, the lateral insulating portion 50, and the insulating layer 60 are not shown.

[0036] The first region 41 is the portion disposed above the conductive portion 30, separated by two insulating portions 20. The first region 41 is opposite to the first semiconductor region 1 and the second semiconductor region 2, separated by a lateral insulating portion 50. In order to suppress the increase of the threshold voltage Vth, it is preferable that the first region 41 is also opposite to the third semiconductor region 3, separated by a lateral insulating portion 50.

[0037] The lower surface 41b of the first region 41 is located in the Z direction at the same position as the interface between the first semiconductor region 1 and the second semiconductor region 2, or below the interface between the first semiconductor region 1 and the second semiconductor region 2. For example, the lower surface 41b of the first region 41 is located below a portion of the interface between the first semiconductor region 1 and the second semiconductor region 2 that contacts the lateral insulating portion 50. Furthermore, the portion of the lower surface 41b of the first region 41 located below the upper surface 42t of the second region 42 is preferably located below the interface between the first semiconductor region 1 and the second semiconductor region 2. The lower surface 41b of the first region 41 is a plane intersecting the Z direction. The lower surface 41b of the first region 41 is preferably formed as a planar shape perpendicular to the Z direction.

[0038] The insulating region that contacts the lower surface 41b of the first region 41 is called the lower insulating portion 52. Figure 2 In this configuration, the portion of the first insulating portion 10 and the second insulating portion 20 that contacts the lower surface 41b of the first region 41 is called the lower insulating portion 52. The gate electrode 40 is surrounded by the side insulating portion 50 and the lower insulating portion 52. The side insulating portion 50 and the lower insulating portion 52 are collectively referred to as the gate insulating portion 54. The gate electrode 40 is surrounded by the gate insulating portion 54 and is electrically insulated from the first semiconductor region 1, the second semiconductor region 2, and the third semiconductor region 3. Even without the conductive portion 30, the first insulating portion 10, and the second insulating portion 20, the lower insulating portion 52 is formed between the first semiconductor region 1 and the gate electrode 40, thereby insulating the gate electrode 40 from the first semiconductor region 2 through the lower insulating portion 52. In other words, regardless of the presence or absence of the conductive portion 30, the gate electrode 40 is surrounded by the gate insulating portion 54, thereby electrically insulating it from the first semiconductor region 1, the second semiconductor region 2, and the third semiconductor region 3.

[0039] The first region 41 of the gate electrode 40 has a side surface 41s. The side surface 41s is in direct contact with the gate insulating portion 54 in the X direction and is opposite to the second semiconductor region 2 in the X direction, separated by the gate insulating portion 54. The side surface 41s is in direct contact with the lateral insulating portion 50 and is opposite to the second semiconductor region 2 in the X direction, separated by the lateral insulating portion 50. Preferably, the side surface 41s is provided along the Z direction.

[0040] A second region 42 is disposed on the first region 41. The upper surface 41t of the first region 41 is in direct contact with the gate insulating portion 54. The upper surface 41t of the first region 41 is in direct contact with the side insulating portion 50. The upper surface 41t has a plane intersecting, for example, the Z direction. The side surface 41s of the first region 41 connects the lower surface 41b of the first region 41 and the upper surface 41t of the first region 41.

[0041] The side surface 42s of the second region 42 is in direct contact with the gate insulating portion 54. The side surface 42s of the second region 42 is opposite to the third semiconductor region 3 through the gate insulating portion 54. The side surface 42s of the second region 42 connects the upper surface 41t of the first region 41 and the upper surface 42t of the second region 42. The upper surface 41t of the first region 41 and the side surface 42s of the second region intersect each other. Preferably, the side surface 42s of the second region 42 is provided along the Z direction.

[0042] Gate electrode 40 in Figure 2 The XZ plane shown has stepped protrusions. Here, the stepped protrusions include, for example, surfaces having shapes corresponding to the lower surface 41b, side surface 41s, and upper surface 41t of the first region 41, and the side surface 42s and upper surface 42t of the second region 42. The gate electrode 40 may also be represented as having stepped protrusions or a stepped cross-section.

[0043] The upper surface 41t of the first region 41 is preferably located above the interface between the second semiconductor region 2 and the third semiconductor region 3. In the following, if A is positioned relative to B in the positive Z direction, then A is above B regardless of the relative positions of A and B in the XY plane. Similarly, if A is positioned relative to B in the negative Z direction, then A is below B regardless of the relative positions of A and B in the XY plane. Preferably, the upper surface 42t of the second region 42 is located below the upper surface of the third semiconductor region 3 (the interface between the third semiconductor region 3 and the insulating layer 60).

[0044] The length of the first region 41 in the X direction is represented by L1. The length of the second region 42 in the X direction is represented by L2. L1 is greater than L2.

[0045] The length of the first region 41 in the Z direction is denoted by L3. The length of the second region 42 in the Z direction is denoted by L4. Length L3 is the length of the side surface 41s of the first region 41 in the Z direction, which is the length from the lower surface 41b to the upper surface 41t in the Z direction. It should be noted that length L3 is equal to, but not limited to, the length of the portion of the first region 41 located below the second region 42 in the Z direction. Length L4 is the length of the side surface 42s in the Z direction, which is the length from the upper surface 41t of the first region 41 to the upper surface 42t of the second region 42 in the Z direction. L3 + L4 is called the first length, and L3 is called the second length. The first length is greater than the second length.

[0046] The length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 42t of the second region 42 is greater than the length in the Z direction from the lower surface 41a of the first region 41 to the upper surface 41t of the first region 41. Here, the length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 42t of the second region 42 is the length in the Z direction of the gate electrode 40 in the portion where the second region 41 is provided on the first region 41, and for example, is equal to L3 + L4, but is not limited to being equal to L3 + L4. The length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 42t of the second region 42 is, for example, the length in the Z direction at the center of the gate electrode 40 in the X direction. The length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 41t of the first region 41 is, for example, the length at the interface between the first region 41 and the side insulating portion 50, and is the length L3 in the Z direction of the side surface 41s of the first region 41.

[0047] The length in the Z direction of the interface between the third semiconductor region 3 and the side insulating portion 50 is represented by Ls. The length in the Z direction of the interface between the second semiconductor region 2 and the side insulating portion 50 is represented by Lb. The first length L3 + L4 is equal to or greater than Lb. Further, in order to reduce the on-resistance, L3 is preferably equal to or greater than Lb.

[0048] The upper surface 42t of the second region 42 is located in the negative Z direction from the upper surface of the third semiconductor region 3. The length in the Z direction from the upper surface 42t of the second region 42 to the upper surface of the third semiconductor region 3 is represented by Dz.

[0049] For example, Dz and Ls satisfy 0 < Dz ≤ Ls. In order to reduce the short circuit between the gate electrode 40 and the third semiconductor region 3, Dz and Ls preferably satisfy 40 nm ≤ Dz ≤ Ls. Dz and Ls more preferably satisfy 90 nm ≤ Dz ≤ Ls.

[0050] The length in the X direction of the side insulating portion 50 between the first region 41 and the second semiconductor region 2 is represented by the first distance D1. The length in the X direction of the side insulating portion 50 between the second region 42 and the third semiconductor region 3 is represented by the second distance D2. The first distance D1 is less than the second distance D2.

[0051] Figure 3The relationship between the second distance D2 and the threshold voltage Vth is shown. With the first distance D1 fixed and the second distance D2 varying, the simulated values of the threshold voltage Vth are plotted. Here, the threshold voltage Vth is the voltage of the gate electrode 40 required to turn on the semiconductor device 100. In other words, the threshold voltage Vth is the voltage of the gate electrode 40 required to form a channel in the second semiconductor region 2 near the lateral insulating portion 50. Depending on the type of device incorporating transistors such as MOSFETs, a value range of the threshold voltage Vth for device operation can be specified, for example, about 1.7V. It is desired to reduce the on-resistance, switching loss, and other factors while suppressing the variation of the threshold voltage Vth so as not to deviate from the value range specified for each device to be incorporated.

[0052] Figure 3 In [the figure], the horizontal axis represents the second distance D2 of the lateral insulating portion 50. The vertical axis represents the ratio of the change ΔVth of Vth based on the threshold voltage Vth (e.g., about 1.7V) at D2 = 50nm (the value is positive when Vth increases and negative when Vth decreases). The threshold voltage Vth can be, for example, about 3V or about 5V other than 1.7V. In addition, ΔVth / Vth is an index of the change amplitude of the threshold voltage Vth, which does not depend on the reference value of the threshold voltage Vth, and it is desired to reduce the absolute value of ΔVth / Vth.

[0053] As Figure 3 shown in [the figure], as the second distance D2 increases, the change of Vth increases in the positive direction. This is because as the portion where the lateral insulating portion 50 is formed with a larger length in the X direction increases, it becomes difficult to form a channel in the second semiconductor region 2. When the second distance D2 is greater than 150nm, the threshold voltage Vth increases rapidly.

[0054] To reduce the variation of the threshold voltage Vth, the second distance D2 preferably satisfies D1 < D2 ≤ 150nm. More preferably, the second distance D2 satisfies D1 < D2 ≤ 100nm.

[0055] Next, the cross-sectional structure of the semiconductor device 100 will be described with reference to Figure 4 [the figure]. Figure 4 is a cross-sectional view at a position different from the cross-section shown in Figure 1 [the figure] and shows the structure in which a voltage is applied to the gate electrode 40.

[0056] In Figure 4In the cross-section shown, a third electrode 73 is disposed on the insulating layer 60. The third electrode 73 is, for example, a gate wiring and is configured to be electrically isolated from the second electrode. The third electrode 73 is electrically connected to the gate electrode 40 via a second plug P2 formed in the insulating layer 60. The second plug P2 is connected to a second region 42 of the gate electrode 40 and has a length in the X direction that is less than the length of the second region 41.

[0057] like Figure 4 As shown, the third semiconductor region 3 is not necessarily located below the third electrode 73. That is, the second semiconductor region 2 and the insulating layer 60 can be in contact with each other.

[0058] Figure 5 Is with Figure 1 The diagram shows cross-sectional views at different locations and illustrates the structure for providing potential to the conductive portion 30. The second electrode 72 and the conductive portion 30 are electrically connected to each other via a third plug P3 formed in the insulating layer 60. The length of the third plug P3 in the X direction is less than the length of the upper end of the conductive portion 30 in the X direction.

[0059] exist Figure 5 In the region shown, the third semiconductor region 3 is not necessarily located below the second electrode 72. That is, the second semiconductor region 2 and the insulating layer 60 can be in contact with each other.

[0060] like Figure 1 As shown, the second electrode 72 is electrically connected to the third semiconductor region 3 via the first plug P1, as... Figure 5 As shown, it is electrically connected to the conductive part 30 via the third plug P3.

[0061] Figure 5 The upper end of the conductive portion 30 shown is preferably located at... Figure 5 Below the upper surface of the second semiconductor region 2 shown (in other words, in the negative Z direction). The upper end of the conductive portion 30 is preferably located below the upper surface of the second semiconductor region 2 shown (in other words, in the negative Z direction). Figure 1 It is located above the interface between the second semiconductor region 2 and the third semiconductor region 3 shown (in other words, in the positive direction of the Z direction) and is situated at... Figure 1 Below the upper surface of the third semiconductor region 3 shown. More preferably, the upper end of the conductive portion 30 is located below the upper surface of the third semiconductor region 3 shown. Figure 1 The upper surface 41t of the first region 41 of the gate electrode 40 shown (see...) Figure 2 Above.

[0062] Although the above has already been referenced Figure 5The conductive portion 30 connected to the second electrode 72 is described, but the second electrode 73 can be replaced by a fourth electrode 74 disposed separately from the second electrode 72 and the third electrode 73. For example, the fourth electrode 74 is an equivalent potential ring (EQPR) region located in the XY plane around the second electrode 72 and the third electrode 73. For example, the fourth electrode 74 has the same potential as the first electrode 71 (drain).

[0063] Semiconductor device 100 includes a plurality of electrodes separated from each other, such as a second electrode 72, a third electrode 73, and a fourth electrode 74, and has, for example, a surface below each electrode. Figure 1 , 4 and Figure 5 The structure shown.

[0064] Subsequently, refer to Figure 1 , 4 and Figure 5 The operation of the semiconductor device 100 is described. When a positive voltage is applied to the first electrode 71 (drain) relative to the second electrode 72 (source electrode), the semiconductor device 100 operates... Figure 4 The third electrode 73, as shown, applies a voltage equal to or higher than the threshold voltage Vth to the gate electrode 40. As a result, a channel (inversion layer) is formed in the second semiconductor region 2 (p-type base region) facing the side insulating portion 50 to conduct the semiconductor device 100.

[0065] Typically, in semiconductor devices such as MOSFETs, as the area of ​​the base region and gate electrode facing each other in the semiconductor region increases and the distance between them decreases, the threshold voltage Vth decreases, resulting in a decrease in resistance during conduction. That is, because the gate electrode 40 and the second semiconductor region 2 (p-type base region) face each other with a wider area and the side insulation 50 between them is thinner, a channel is easily formed in the base region. This can reduce the threshold voltage Vth, thereby reducing the on-resistance.

[0066] Electrons pass through the third semiconductor region 3(n) + (n-type source region), the channel formed in the second semiconductor region 2, and the first semiconductor region 1 (n-type source region). - Type drift region) and fifth semiconductor region 5 (n + The channel in the second semiconductor region 2 (type drain region) flows from the second electrode 72 to the first electrode 71. Subsequently, when the voltage applied to the gate electrode 40 is less than the threshold voltage Vth, the channel in the second semiconductor region 2 disappears, and the semiconductor device 100 is turned off.

[0067] When the semiconductor device 100 switches to the off state and the positive voltage applied to the first electrode 71 relative to the second electrode 72 increases, the depletion layer extends from the interface between the first insulating portion 10 and the first semiconductor region 1 toward the first semiconductor region 1. Because the depletion layer extends within the first semiconductor region 1, the breakdown voltage of the semiconductor device 100 in the off state can be increased. Figure 5 As shown, the conductive portion 30 connected to the second electrode 72 reduces the concentration of the electric field by extending a depletion layer in the first semiconductor region 1 in the Z direction. Furthermore, the conductive portion 30 connected to the fourth electrode 74 is provided at the end of the semiconductor device 100, thereby reducing the electric field concentration at the end.

[0068] Material examples for each component of the semiconductor device 100 will be described.

[0069] The first semiconductor region 1, the second semiconductor region 2, the third semiconductor region 3, the fourth semiconductor region 4, and the fifth semiconductor region 5 contain, for example, silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as a p-type impurity.

[0070] The conductive portion 30 and the gate electrode 40 contain a conductive material such as polysilicon. This conductive material may contain impurities.

[0071] The first insulating portion 10, the second insulating portion 20, the lateral insulating portion 50, and the insulating layer 60 comprise an insulating material such as silicon oxide. The second insulating portion 20 may be, for example, a borosilicate glass (BPSG) film. The advantage of BPSG films is that planarization can be easily achieved by heat treatment after film deposition to induce reflow.

[0072] The first electrode 71, the second electrode 72, the third electrode 73, and the fourth electrode 74 are metal layers comprising, for example, aluminum, gold, or other suitable metals. The first plug P1, the second plug P2, and the third plug P3 comprise metals such as aluminum. The first plug P1, the second plug P2, and the third plug P3 may comprise, for example, tungsten (W) or titanium nitride (TiN).

[0073] According to the semiconductor device 100 of this embodiment, the increase in threshold voltage Vth can be suppressed to reduce on-resistance, and switching losses can be reduced to improve switching performance. Suppressing the increase in threshold voltage Vth and reducing switching losses generally involve a trade-off, and according to this embodiment, the trade-off can be optimized based on the shape of the gate electrode 40. First, the reduction in on-resistance will be described.

[0074] exist Figure 1In the semiconductor device 100 shown, the lower surface of the first region 41 of the gate electrode 40 is located below the interface between the first semiconductor region 1 and the second semiconductor region 2, and the upper surface 41t of the first region 41 is located above the interface between the second semiconductor region 2 and the third semiconductor region 3. That is, in the gate electrode 40, the first region 41 is opposite to the second semiconductor region 2 across the lateral insulating portion 50. The first region 41 and the second semiconductor region 2 of the gate electrode 40 are positioned opposite each other across a portion of the lateral insulating portion 50 having a first distance D1. This can reduce the threshold voltage Vth, thereby reducing the on-resistance.

[0075] In addition, such as Figure 3 As shown, the threshold voltage tends to increase as the second distance D2 of the lateral insulation portion 50 in contact with the second region 42 increases. The increase in threshold voltage can be further suppressed by setting the second distance D2 to 150 nm or less.

[0076] Next, we will describe the improvements in switching performance. Generally, for semiconductor devices such as MOSFETs, when the capacitance between the source region and the gate electrode in the semiconductor region (hereinafter referred to as the gate-source capacitance) is large, that is, when the amount of stored charge is greater relative to the specified voltage difference, the switching speed decreases and the switching losses increase.

[0077] As the length of the lateral insulating portion 50 disposed between the gate electrode 40 and the third semiconductor region 3 in the X direction increases, the gate-source capacitance decreases. As the area of ​​the gate electrode 40 and the third semiconductor region 3 facing each other through the lateral insulating portion 50 decreases, the gate-source capacitance decreases.

[0078] exist Figure 1 In the semiconductor device 100 shown, the length of the lateral insulating portion 50 located between the second region 42 and the third semiconductor region 3 of the gate electrode 40 in the X direction is greater than the length of the lateral insulating portion 50 located between the first region 41 and the second semiconductor region 2 (D2>D1). For example, compared to the case where the lateral insulating portion 50 located between the gate electrode 40 and the third semiconductor region 3 is formed to be uniformly thin in the X direction, the capacitance between the second region 42 and the third semiconductor region 3 can be reduced, thereby reducing the gate-source capacitance.

[0079] Furthermore, since the side surface 42s of the second region 42 intersects the upper surface 41t of the first region 41, a lateral insulating portion 50 having a second distance D2 in the X direction can be provided in the wider portion between the second region 41 and the third semiconductor region 3. When the upper surface 41t of the first region 41 is perpendicular to the Z direction and the side surface 42s of the second region 42 is along the Z direction, a lateral insulating portion 50 having a second distance D2 in the X direction can be provided in the wider portion between the second region 42 and the third semiconductor region 3. By forming a longer lateral insulating portion 50 between the second region 42 and the third semiconductor region 3 in the X direction, the gate-source capacitance can be reduced. Since the side surface 42s of the second region 42 intersects the upper surface 41t of the first region 41, the gate-source capacitance can be reduced.

[0080] As described above, in the semiconductor device 100 according to this embodiment, since the first region 41 and the second region 42 of the gate electrode 40 are configured to contact the side insulating portion 50, wherein the side insulating portion 50 has different lengths in the X direction, the increase of the threshold voltage Vth can be suppressed to reduce the on-resistance and the gate-source capacitance can be reduced.

[0081] Furthermore, since the length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 42t of the second region 42 is greater than the length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 41t of the first region 41, and the length of the gate electrode 40 in the Z direction is greater in the portion of the second region 42 disposed on the first region 41, the resistance of the gate electrode 40 is reduced. If the portion of the lower surface 41b of the first region 41 located below the upper surface 42t of the second region 42 is located below the interface between the first semiconductor region 1 and the second semiconductor region 2, the length of the gate electrode 40 in the Z direction can be further increased to reduce the resistance of the gate electrode 40. Therefore, the time delay when applying a voltage to the gate electrode 40 to perform the switching of the semiconductor device 100 is reduced. That is, the semiconductor device 100 can reduce switching losses.

[0082] The lower surface of the first region 41 in the gate electrode 40 is preferably formed as a flat shape perpendicular to the Z direction. As the lower surface of the first region 41 becomes more flat, the radius of curvature of the lower surface of the gate electrode 40 increases (curvature decreases). Therefore, the electric field concentration at the interface between the gate electrode 40 and the surrounding insulating material (first insulating portion 10, second insulating portion 20, or side insulating portion 50) can be reduced.

[0083] In addition, since the upper surface 42t of the second region 42 in the gate electrode 40 is located below the upper surface of the third semiconductor region 3 (0 < Dz), a short circuit between the gate and the source can be suppressed. For comparison, when the upper surface 42t of the second region 42 in the gate electrode 40 is located above the upper surface of the third semiconductor region 3 and the gate electrode 40 is deformed in the X direction or the Y direction, the conductive material contained in the gate electrode 40 located above the upper surface of the third semiconductor region 3 may adhere to the upper surface of the third semiconductor region 3. That is, the gate electrode 40 and the third semiconductor region 3 may be electrically connected. On the other hand, in the semiconductor device according to the present embodiment, since the upper surface of the third semiconductor region is located above the gate electrode 40, the probability that the conductive material contained in the gate electrode 40 adheres to the upper surface of the third semiconductor region 3 can be reduced. By setting the length Dz to 40 nm or more, a short circuit between the gate and the source can be further suppressed.

[0084] In addition, in the semiconductor device 100 according to the present embodiment, the second plug P2 and the third plug P3 respectively connected to the conductive portion 30 and the gate electrode 40 can be formed simultaneously, and the manufacturing efficiency of the semiconductor device can be improved, wherein the conductive portion 30 can improve the breakdown voltage. This is because by reducing Figure 5 the positional difference in the Z direction between the upper surface 42t of the second region 42 in the gate electrode 40 shown in and the upper end of the conductive portion 30, the opening portions for embedding the second plug P2 and the third plug P3 can be formed in the same step.

[0085] For comparison, considering the case where the gate electrode 40 does not have the second region 42, the gate capacitance can be reduced, and the second plug P2 needs to be formed deeper than in the present embodiment. Therefore, it is necessary to separate the manufacturing step of the second plug P2 from the manufacturing step of the third plug P3.

[0086] (Second Embodiment)

[0087] Figure 6 is a cross-sectional view of a semiconductor device 200 according to the second embodiment. Some redundant descriptions of components common to the semiconductor device 100 according to the first embodiment will not be repeated.

[0088] In addition to the first region 41 and the second region 42, the gate electrode 40 of the semiconductor device 200 according to the present embodiment further includes a third region 43 provided in the first region 41.

[0089] The third region 43 contains a material different from that of the first region 41. The third region 43 contains an insulating material such as silicon oxide, for example. The third region 43 includes a tetraethoxysilane (TEOS) film, for example. It should be noted that the third region 43 is not limited to an insulating material and may contain a conductive material.

[0090] The semiconductor device 200 according to this embodiment can shorten the steps of forming the gate electrode 40 and improve manufacturing efficiency. Manufacturing costs can be reduced. These details will be described in the description of the manufacturing method.

[0091] According to at least one of the above embodiments, the increase of threshold voltage Vth can be suppressed, the on-resistance can be reduced, and the gate-source capacitance can be reduced to improve switching performance.

[0092] In the above description, an example has been described where the gate electrode 40 is located above the conductive portion 30; however, the conductive portion 30 and the gate electrode 40 can be separated from each other in the XY plane. For example, the conductive portion 30 can be configured as dots, spaced apart from each other in the X and Y directions, and extending in the Z direction; the gate electrode 40 can be configured as a grid-like structure surrounding each conductive portion 30 in the XY plane. The gate electrode 40 is covered by a gate insulating portion 54, which includes a side insulating portion 50 and a bottom insulating portion 52. Even when the gate electrode 40 is configured in a grid shape in the XY plane, the increase in the threshold voltage Vth can be suppressed, the on-resistance can be reduced, and the gate-source capacitance can be reduced to improve switching performance.

[0093] The following section describes a method for manufacturing a semiconductor device. Figure 1 The manufacturing method of the cross-sectional view shown is described. The manufacturing steps of the structure below the first semiconductor region 1 are not described in the description of the manufacturing method because these steps are not significantly different from general manufacturing methods.

[0094] Figures 7A to 7H This is a cross-sectional view showing a method for manufacturing a semiconductor device 100 according to the first embodiment.

[0095] First, a substrate Sub including a first semiconductor region 1 is fabricated. A portion of the substrate Sub is removed from its upper surface to form a trench T. For example, the upper surface can be removed by etching methods such as chemical dry etching (CDE) or reactive ion etching (RIE). Next, a first insulating portion 10 is formed on the upper surface of the substrate Sub and the surface of the trench T to obtain... Figure 7A The structure is as follows. The first insulating portion 10 includes, for example, an insulator such as silicon oxide obtained by thermal oxidation of the substrate Sub. Alternatively, the first insulating portion 10 can be formed by chemical vapor deposition (CVD).

[0096] Next, as Figure 7BAs shown, conductive portions 30 are formed on the first insulating portion 10 and in the trench T. The conductive portions 30 are formed by CVD, for example, using a conductive material such as polycrystalline silicon. Then, the conductive portions 30 are partially removed by CDE or other methods, and the upper end of the conductive portions 30 is retracted in the negative Z direction. As a result, conductive portions 30 are formed respectively... Figure 7B Multiple conductive portions 30 in the multiple trenches T shown.

[0097] It should be noted that in the plurality of conductive parts 30, the step of retracting the upper end by CDE or other methods may not be performed on some conductive parts 30. For example, Figure 7B Some conductive portions 30 arranged along the X direction, not shown in the figure, may include Figure 5 The conductive part 30 shown.

[0098] Furthermore, a second insulating portion 20 is formed on the first insulating portion 10 and the conductive portion 30. The second insulating portion 20 is an insulator comprising silicon oxide formed, for example, by CVD. Alternatively, the second insulating portion may be a BPSG film. In this manner, a... Figure 7B The structure shown.

[0099] Next, a portion of the first insulating portion 10 and a portion of the second insulating portion 20 are removed by wet etching or other methods. Since a portion of the first insulating portion 10 and a portion of the second insulating portion 20 have been removed, a portion of the first semiconductor region 1 is exposed. For example, an insulating film 55 is formed by thermal oxidation of the upper surface of the substrate Sub. The insulating film 55 comprises, for example, silicon oxide. In this way, a semiconductor region 1 is obtained. Figure 7C The structure shown.

[0100] Furthermore, a gate electrode 40 is formed on the first insulating portion 10, the second insulating portion 20, and the insulating film 55, and then partially removed to obtain, as shown in the figure. Figure 7D The gate electrode 40 is shown retained in the trench. The gate electrode 40 is formed, for example, by CVD, and the gate electrode 40 comprises polysilicon. Methods for partially removing the gate electrode 40 include, for example, chemical mechanical polishing (CMP). Alternatively, the gate electrode 40 can be partially removed by, for example, CDE or wet etching. It should be noted that... Figure 7D The shape of the gate electrode 40 shown is similar to Figure 1 The different shapes of the gate electrodes shown are due to the change in the shape of the gate electrode 40 in a subsequent step.

[0101] For example, Figure 2 The lower insulating portion 52 shown is defined as Figure 7DThe portion located between the gate electrode 40 and the first insulating portion 10 and the second insulating portion 20. That is, the area in the first insulating portion 10 and the second insulating portion 20 that contacts the lower surface 41b of the gate electrode 40 is renamed the lower insulating portion 52. Therefore, in Figure 7D In the steps shown, it is not necessary to further install the lower insulating part 52.

[0102] Furthermore, without the conductive portion 30, the first insulating portion 10, and the second insulating portion 20, a lower insulating portion 52 can be formed between the gate electrode 40 and the first semiconductor region 1 by forming an insulating film 55 that contacts the first semiconductor region 1 on the surface of the trench T, without needing to form the first insulating portion 10 or the second insulating portion 20 after forming the trench T. The step of forming the lower insulating portion 52 is unnecessary because even without the conductive portion 30, the first insulating portion 10, and the second insulating portion 20, the lower insulating portion 54 can be formed during the step of forming the insulating film 55.

[0103] A second semiconductor region 2 and a third semiconductor region 3 are obtained by sequentially ion implanting p-type and n-type impurities into the first semiconductor region 1 between trenches T. In this way, a... Figure 7D The structure of the substrate Sub is shown.

[0104] Next, an oxide film 80 is formed on the gate electrode 40 by selectively oxidizing the upper surface of the gate electrode 40. For example, the oxide film 80 can be a TEOS film, a BPSG film, or a film including both. Then, the portions of the upper surface of the gate electrode 40 where the oxide film 80 is not formed are selectively removed. Near the insulating film 55, the gate electrode 40 is partially removed from the upper surface of the gate electrode 40. For example, removal is performed by RIE or CDE. Alternatively, a photoresist can be used instead of the oxide film 80. In this way, a [material / structure] is obtained. Figure 7E The structure shown.

[0105] Subsequently, the oxide film 80 on the gate electrode 40 is removed. Additionally, the process may include removing the gate electrode 40 via RIE or CDE to adjust the position of the upper surface of the gate electrode 40 in the Z direction. Figure 7F The step of retracting the upper surface of the gate electrode 40 (the upper surface of the first region and the upper surface of the second region 42) in the negative direction of the Z direction is shown.

[0106] Next, an insulating layer 60 is formed on the gate electrode 40 and the insulating film 55. An opening portion OP is formed to extend from the insulating layer 60 to the second semiconductor region 2. P-type impurity ions are implanted into the second semiconductor region 2 through the opening portion OP to form a fourth semiconductor region 4. In this manner, a fourth semiconductor region 4 is obtained. Figure 7G The structure shown. A portion of the insulating layer 60 ( Figure 7G The region marked 60g can be located between the gate electrode 40 and the insulating film 55. The insulating film 55 and the insulating layer 60g located between the gate electrode 40 and the second semiconductor region 2 or the third semiconductor region 3 are collectively referred to as the side insulating portion 50.

[0107] Finally, a second electrode 72 is formed on the insulating layer 60. The first plug P1 is embedded in the opening portion OP by, for example, CVD. The second electrode 72 on the insulating layer 60 is formed, for example, by sputtering.

[0108] Although only the manufacturing process is described in the manufacturing steps shown in Figure 7. Figure 1 The steps of the cross-sectional structure shown are as follows, but when manufacturing a structure including the first plug P1, it is possible to manufacture the structure including the first plug P1 in parallel. Figure 4 and Figure 5 The structure of the second plug P2 and the third plug P3 is shown.

[0109] For example, it can be Figure 7G and 7H In the steps between, forming Figure 4 The third electrode 73 and the second plug P2 are shown. Furthermore, openings for inserting the second plug P2 and the third plug P3 are formed in the same step, and these plugs can also be inserted in the same step.

[0110] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Redundant descriptions of components common to the semiconductor device 100 according to the first embodiment will not be repeated. The manufacturing method of the semiconductor device 100 according to the first embodiment... Figure 7C The steps shown are the same as before, so they will not be described again.

[0111] Figures 8A to 8E This is a cross-sectional view showing a method for manufacturing a semiconductor device 200 according to the second embodiment.

[0112] Figure 8A It shows relative to Figure 7C The structure shown includes the step of forming a first conductive layer 91 on the first insulating portion 10, the second insulating portion 20, and the insulating film 55. For example, the first conductive layer 91 is formed by CVD from a conductive material containing polycrystalline silicon. It should be noted that the first conductive layer 91 can be formed by low-pressure CVD (LP-CVD).

[0113] Furthermore, an embedding layer 92 is formed on the first conductive layer 91 to obtain Figure 8A The structure is shown. The embedding layer 92 includes, for example, a TEOS film, and is formed by CVD from an insulating material comprising silicon oxide. It should be noted that a conductive material can be used for the embedding layer 92.

[0114] Next, the embedding layer 92 is planarized to obtain Figure 8B The structure is shown. The planarization step of the embedding layer 92 is performed, for example, by CMP. The embedding layer 92 is retained to embed the trench T.

[0115] Subsequently, as Figure 8C As shown, the first conductive layer 91 and the embedded layer 92 are selectively removed. For example, the first conductive layer 91 and the embedded layer 92 are removed individually at different removal rates by CDE. The first conductive layer 91 and the embedded layer 92 can be removed to different depths individually. The ratio of the removal rates of the individual films is called the removal ratio (selectivity ratio). The removal ratio (selectivity ratio) of the first conductive layer 91 to the embedded layer 92 is, for example, greater than 1, and the first conductive layer 92 is removed deeper than the embedded layer 92 in the Z direction. The first conductive layer 91 is, for example, conductive polycrystalline silicon containing impurities, and the embedded layer 92 is, for example, a TEOS film. The gas used for etching can be appropriately selected such that the etching rates of the first conductive layer 91 and the embedded layer 92 are different, and they are removed at different removal rates.

[0116] Subsequently, a second conductive layer 93 is further formed on the first conductive layer 91 and the embedding layer 92 to obtain the gate electrode 40. Here, for example, the additional formation of the second conductive layer 93 is achieved by selectively growing a conductive material containing polycrystalline silicon. Therefore, it is desirable that the embedding layer 92 be selectively grown with a silicon-containing material, such as an oxide film of TEOS. In this way, a... Figure 8D The structure shown.

[0117] According to this manufacturing method, the positions of the upper surface 41t of the first region 41 and the upper surface 42t of the second region 42 in the gate electrode 40 can be controlled by the thickness of the second conductive layer 93 formed on the first conductive layer 91 and the embedded layer 92 in the Z direction. Therefore, the step of retracting the upper surface of the gate electrode 40 in the negative Z direction can be omitted to suppress the adhesion of conductive material to the upper surface of the third semiconductor region 3. This reduces the number of manufacturing steps.

[0118] Finally, similar to the method used to manufacture the semiconductor device 100 according to the first embodiment, an insulating layer 60 is formed on the gate electrode 40 and the insulating film 55. Then, the first plug P1 and the second electrode 72 are formed by, for example, CVD or sputtering. In this way, a semiconductor device 100 is obtained. Figure 8E The structure shown.

[0119] The embodiments have been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. That is, those obtained by those skilled in the art through appropriate modifications to the design of these specific examples are also included within the scope of protection of the embodiments of the present invention, provided they have the features of these embodiments. Each element included in each specific example described above, as well as its arrangement, material, condition, shape, size, etc., are not limited to those illustrated and can be appropriately modified.

[0120] Furthermore, each element included in each of the embodiments described above can be combined as technically as possible, provided that such combinations include the features of the embodiments of the present invention, and such combinations are also included within the protection scope of these embodiments. Moreover, within the conceptual scope of these embodiments, various modifications and alterations can be conceived by those skilled in the art, and it should be understood that such modifications and alterations also fall within the protection scope of the embodiments of the present invention.

[0121] Although some embodiments of the invention have been described, these embodiments are merely examples and are not intended to limit the scope of protection of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the invention as described in the claims and their equivalents.

Claims

1. A semiconductor device, comprising: First electrode; A first semiconductor region of a first conductivity type is disposed on the first electrode and electrically connected to the first electrode; A second semiconductor region of a second conductivity type is disposed on the first semiconductor region; A third semiconductor region of the first conductivity type is disposed on the second semiconductor region; A gate electrode includes: a first region facing a second semiconductor region in a second direction intersecting a first direction from the first electrode toward the first semiconductor region, separated by a gate insulating portion; and a second region disposed on the first region and facing a third semiconductor region in the second direction, separated by the gate insulating portion; and The second electrode is electrically connected to the third semiconductor region. The gate electrode has: a first length from the lower surface of the first region to the upper surface of the second region in the first direction; and a second length from the lower surface of the first region to the upper surface of the first region in contact with the gate insulating portion, wherein the first length is greater than the second length.

2. The semiconductor device according to claim 1, wherein The second region includes a side surface that connects the upper surface of the first region and the upper surface of the second region; The upper surface of the first region and the side surface of the second region intersect each other.

3. The semiconductor device according to claim 1, wherein Below the upper surface of the second region, the lower surface of the first region is located below the interface between the first semiconductor region and the second semiconductor region.

4. The semiconductor device according to claim 3, wherein The lower surface of the first region has a flat area.

5. The semiconductor device according to claim 1, wherein The gate electrode has a center in the second direction; The first length is the length in the first direction passing through the center; The second length is the length of the side surface of the first region in the first direction, the side surface connecting the lower surface and the upper surface of the first region.

6. The semiconductor device according to claim 1, wherein The upper surface of the first region of the gate electrode is located above the interface between the second semiconductor region and the third semiconductor region.

7. The semiconductor device according to claim 1, wherein The upper surface of the second region of the gate electrode is located above the interface between the second semiconductor region and the third semiconductor region, and below the upper surface of the third semiconductor region.

8. The semiconductor device according to claim 7, further comprising: A conductive portion disposed below the gate electrode; A first insulating portion is disposed between the conductive portion and the first semiconductor region; as well as A second insulating portion is disposed between the conductive portion and the gate electrode.

9. A semiconductor device, comprising: First electrode; A first semiconductor region of a first conductivity type is disposed on the first electrode and electrically connected to the first electrode; A second semiconductor region of a second conductivity type is disposed on the first semiconductor region; A third semiconductor region of the first conductivity type is disposed on the second semiconductor region; A gate electrode includes: a first region facing a second semiconductor region in a second direction intersecting a first direction from the first electrode toward the first semiconductor region, separated by a gate insulating portion; and a second region disposed on the first region and facing a third semiconductor region in the second direction, separated by the gate insulating portion; and The second electrode is electrically connected to the third semiconductor region. The gate electrode has stepped protrusions.

10. The semiconductor device according to any one of claims 1 to 9, wherein The gate electrode further includes a third region in the first region, the third region comprising a material different from that in the first region.

11. The semiconductor device according to claim 9, wherein The second region includes a side surface that is opposite to the third semiconductor region and in contact with the gate insulating portion.

12. The semiconductor device according to claim 9, wherein The gate electrode has a center in the second direction; The first length is the length in the first direction passing through the center; The second length is the length of the side surface of the first region in the first direction, the side surface being opposite to the second semiconductor region and in contact with the gate insulating portion.

13. The semiconductor device according to claim 9, wherein The gate electrode further includes a third region in the first region, the third region comprising a material different from that in the first region.

14. A method for manufacturing a semiconductor device, comprising: An insulating film is formed on the surface of a trench formed by removing the upper surface of the substrate along the first direction; The gate electrode is formed in the trench; In the first direction, the gate electrode near the insulating film is selectively removed; as well as An insulating layer is formed on the gate electrode and the insulating film.

15. The semiconductor device manufacturing method according to claim 14, further comprising: The upper surfaces of the first region and the second region are moved back.

16. A method for manufacturing a semiconductor device, comprising: An insulating film is formed on the surface of a trench formed by removing the upper surface of the substrate along the first direction; A first conductive layer is formed on the insulating film; An embedding layer is formed, the embedding layer being disposed on the first conductive layer and embedded in the trench; A portion of the first conductive layer and a portion of the embedded layer are removed along the first direction at different removal rates; A second conductive layer is formed on the first conductive layer and the embedded layer to form the gate electrode; as well as An insulating layer is formed on the gate electrode and the insulating film.

17. A method for manufacturing a semiconductor device, comprising: Prepare a substrate, wherein trenches are formed in the substrate; An insulating film is formed on the surface of the trench; A gate electrode is formed in the trench, the gate electrode being opposite to the substrate, wherein the insulating film is provided between the gate electrode and the substrate; Along the interface between the gate electrode and the insulating film, the gate electrode near the insulating film is selectively removed in a first direction; as well as An insulating layer is formed on the gate electrode and the insulating film.

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