Semiconductor structure and preparation method thereof
By pretreating the inner wall of the groove with HCl and GeH4 gas to form a transition layer, the problem of dangling bond residue was solved, and the quality of the epitaxial layer and device performance were improved.
Patent Information
- Application Number
- CN202511296690.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-11
- Publication Date
- 2026-01-13
AI Technical Summary
In existing technologies, dangling bonds remaining on the silicon wafer surface are difficult to completely remove after high-temperature etching and cleaning, leading to interface defects and epitaxial layer dislocations, which affect device performance.
A pretreatment process using HCl and GeH4 gases is employed to pretreat the inner wall of the groove, forming a transition layer to eliminate dangling bonds, reduce interface defects and dislocations, and improve the quality of the epitaxial layer.
It effectively eliminates dangling bonds, reduces the incidence of interface defects and dislocations, and improves the lattice integrity of the epitaxial layer and device performance.
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Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a semiconductor structure and a preparation method thereof. BACKGROUND
[0002] In the field of semiconductor device manufacturing, silicon epitaxial deposition technology is one of the key processes for preparing high-performance device structures, and the deposition quality directly determines the electrical performance and reliability of the device. Since the interface state of the epitaxial layer and the silicon substrate significantly affects the deposition quality, the surface of the silicon wafer needs to be precisely cleaned before deposition.
[0003] The existing mainstream cleaning process is isotopic high-temperature HCl etching cleaning. The core advantages of this process are as follows: first, under high-temperature conditions, HCl can chemically react with the natural oxide layer (SiO2) or organic contaminants on the surface of the silicon wafer and volatilize away; second, the high-temperature etching process can also remove part of the silicon surface defects (such as slight scratches and lattice distortion), thereby providing a substrate with both flatness and cleanliness for subsequent epitaxial deposition.
[0004] However, the isotopic high-temperature etching cleaning process relying solely on HCl has obvious technical limitations: after the process, a large number of silicon dangling bonds remain on the surface of the silicon wafer. Such dangling bonds have very high chemical activity, not only easily reacting with impurities in the subsequent process environment, but also directly forming interface defects between the silicon substrate and the epitaxial layer. More importantly, the remaining dangling bond sites become weak areas of stress concentration. Since the lattice constant difference between high-Ge-content epitaxial materials (such as SiGe materials) and the silicon substrate is large, the epitaxial growth process itself is prone to lattice stress, and under the action of this lattice mismatch stress, the above-mentioned dangling bond sites are extremely prone to stress concentration or dislocation defects, ultimately destroying the lattice integrity of the epitaxial layer.
[0005] Therefore, how to provide a semiconductor structure and a preparation method thereof to eliminate dangling bonds generated during the cleaning process, reduce interface defects and dislocations of the epitaxial layer, and improve the quality of the epitaxial layer and the performance of the device, has become an important problem to be solved by those skilled in the art.
[0006] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY
[0007] In view of the above-mentioned defects of the prior art, the present application aims to provide a semiconductor structure and a preparation method thereof, which are used to solve the problem that the dangling bonds remaining in the groove of the silicon substrate are easy to form interface defects on the inner wall of the groove, and stress concentration or dislocation is generated in the growth process of the epitaxial layer.
[0008] To achieve the above object and other related objects, the present application provides a preparation method of a semiconductor structure, comprising the following steps:
[0009] providing a silicon substrate, wherein gate structures are formed on the silicon substrate and arranged at intervals;
[0010] etching the silicon substrate to form a groove between two adjacent gate structures;
[0011] preprocessing the inner wall of the groove by a preprocessing gas to clean the inner wall of the groove and form a transition layer on the inner wall of the groove, wherein the preprocessing gas comprises HCl gas and GeH4 gas, and the content of the HCl gas is greater than that of the GeH4 gas;
[0012] forming an epitaxial layer in the groove.
[0013] Optionally, in the preprocessing process, the content of the GeH4 gas in the preprocessing gas ranges from 0.9% to 1.1%, and the reaction temperature of the preprocessing gas ranges from 700°C to 900°C.
[0014] Optionally, the thickness of the transition layer is less than 1 nm, and the material of the transition layer comprises germanosilicon.
[0015] Optionally, the etching process for forming the groove comprises a dry etching process and a wet etching process.
[0016] Optionally, the longitudinal cross-sectional shape of the groove comprises a pentagon and a hexagon.
[0017] Optionally, the gate structure comprises a pseudo gate structure and a side wall structure on the sidewall of the pseudo gate structure.
[0018] Optionally, the pseudo gate structure comprises an amorphous silicon layer, a silicon nitride layer and a silicon oxide layer stacked in sequence from bottom to top.
[0019] Optionally, the material of the epitaxial layer comprises silicon germanium.
[0020] The present application also provides a semiconductor structure prepared by the preparation method of the semiconductor structure according to any one of the above-mentioned embodiments, comprising:
[0021] a silicon substrate, wherein gate structures are formed on the silicon substrate and arranged at intervals;
[0022] a groove formed in the silicon substrate and between two adjacent gate structures;
[0023] a transition layer formed on the inner wall of the groove;
[0024] an epitaxial layer formed on the transition layer and filling the groove.
[0025] Optionally, the material of the epitaxial layer comprises silicon germanium.
[0026] As described above, the method for preparing the semiconductor structure of the present application comprises the steps of providing a silicon substrate, forming gate structures on the silicon substrate, etching the silicon substrate to form a groove between two adjacent gate structures, pre-treating the inner wall of the groove by a pre-treatment gas to clean the inner wall of the groove and form a transition layer on the inner wall of the groove, the pre-treatment gas comprising HCl gas and GeH4 gas, and the content of the HCl gas being greater than that of the GeH4 gas, and forming an epitaxial layer in the groove. The method for preparing the semiconductor structure of the present application can eliminate the dangling bonds generated in the cleaning process by the reaction of the trace amount of GeH4 gas mixed in the pre-treatment gas with the dangling bonds, thereby reducing the interface defects and dislocations of the epitaxial layer, and improving the quality of the epitaxial layer and the performance of the device. BRIEF DESCRIPTION OF DRAWINGS
[0027] Figure 1 a schematic diagram of a semiconductor structure after cleaning by HCl gas.
[0028] Figure 2 a schematic diagram of a semiconductor structure after forming a transition layer in the groove of the structure shown in Figure 1 a schematic diagram of the structure obtained after forming an epitaxial layer in the groove of the structure shown in
[0029] Figure 3 a process flow chart of the method for preparing the semiconductor structure of the present application.
[0030] Figure 4 a schematic diagram of the structure of the substrate provided in the method for preparing the semiconductor structure of the present application.
[0031] Figure 5 a schematic diagram of the structure obtained after forming a groove in the method for preparing the semiconductor structure of the present application.
[0032] Figure 6 a schematic diagram of one state of the structure obtained after pre-treatment in the method for preparing the semiconductor structure of the present application.
[0033] Figure 7 a schematic diagram of another state of the structure obtained after pre-treatment in the method for preparing the semiconductor structure of the present application.
[0034] Figure 8The diagram shown is a schematic of the structure obtained after forming an epitaxial layer in the semiconductor structure fabrication method of the present invention.
[0035] Explanation of reference numerals in the attached figures
[0036] 101 and 201 silicon substrates
[0037] 102, 204 Grooves
[0038] 103 gate structure
[0039] 104, 205 Hanging keys
[0040] Epitaxial layers 105 and 207
[0041] 106 Interface Defects
[0042] 107 dislocations
[0043] 202 Pseudo-gate structure
[0044] 2021 Amorphous Silicon Layer
[0045] 2022 Silicon Nitride Layer
[0046] 2023 Silicon oxide layer
[0047] 203 Sidewall Structure
[0048] 2031 First side wall layer
[0049] 2032 Second side wall layer
[0050] 206 Transition Layer
[0051] Steps S1 to S4 Detailed Implementation
[0052] Even after a silicon wafer is cleaned using only HCl-based isotopic high-temperature etching, a large number of silicon dangling bonds remain on the surface. (See [link to relevant documentation]). Figure 1 The diagram shows a schematic of a semiconductor structure after being cleaned with HCl gas. This semiconductor structure includes a silicon substrate 101, a recess 102, a gate structure 103, and dangling bonds 104. The dangling bonds 104 are attached to the sidewalls of the recess 102 and possess extremely high chemical reactivity. During subsequent process transfer or the waiting period before epitaxial deposition, they readily react with impurities such as oxygen, water vapor, and hydrocarbons in the external environment. This not only causes them to re-adsorb impurities and contaminants but may also lead to the formation of a very thin natural oxide layer on the surface of the silicon substrate 101. Furthermore, even when entering the high-temperature environment of epitaxial deposition, the dangling bonds 104 will react with trace amounts of residual oxygen and water vapor in the reaction chamber, generating new oxides.
[0053] Please see againFigure 2 Displayed as in Figure 1 The diagram illustrates the structure obtained after forming an epitaxial layer 105 within the groove 102. The epitaxial layer 105 is formed through epitaxial growth within and outside the groove 102. During the growth of the epitaxial layer 105, interface defects 106 are formed between the silicon substrate 101 and the epitaxial layer 105 due to the reaction of the dangling bonds 104 with impurities in the external environment. Furthermore, when the epitaxial layer 105 contains a high Ge content, there is a significant difference in lattice constant between the epitaxial layer 105 and the silicon substrate 101. The dangling bond 104 sites become weak areas of stress concentration. Under the influence of lattice mismatch stress, dislocation defects are generated at the dangling bond 104 sites. These dislocation defects easily propagate along the growth direction of the epitaxial layer 105, eventually forming through dislocations 107, which severely damage the lattice integrity of the epitaxial layer 105, leading to fatal problems such as increased device leakage current and reduced breakdown voltage.
[0054] Therefore, the inventors of this application have improved the isotopic high-temperature etching cleaning process that relies solely on HCl, and provided a semiconductor structure and its preparation method. The preparation method of this semiconductor structure can eliminate dangling bonds generated during the cleaning process, reduce interface defects and dislocations in the epitaxial layer, thereby improving the quality of the epitaxial layer and the performance of the device.
[0055] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0056] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0057] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0058] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0059] For the sake of convenience, the terms "under", "below", "lower", "beneath", "above", "upper" and the like can be used herein to describe one element or feature's relationship to another element(s) or feature(s) as the devices are oriented in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a layer overlies another layer, it can be the case that the layer is the only layer between the other two layers, or that intervening layers exist. In addition, when a layer is referred to as being "between" two layers, it can be the case that there is only one intervening layer, or that there are intervening layers.
[0060] In the context of the present application, a structure described as being "on" another structure can include embodiments where the structures form direct contact, and can also include embodiments where additional structures are formed between the structures, such that the structures can not be in direct contact.
[0061] It should be noted that the drawings provided in the embodiments are only schematic and are intended to provide the basic understanding of the application. In the drawings, the thickness of layers, regions and / or areas can be exaggerated for clarity. The same or similar components are denoted by the same reference signs throughout the drawings.
[0062] Referring to Figure 3 , a process flow chart of a semiconductor structure preparation method is shown, which comprises the following steps:
[0063] S1: providing a silicon substrate, wherein gate structures are formed on the silicon substrate in a spaced manner;
[0064] S2: etching the silicon substrate to form a groove between two adjacent gate structures;
[0065] S3: pre-treating the inner wall of the groove by a pre-treatment gas to clean the inner wall of the groove and form a transition layer on the inner wall of the groove, wherein the pre-treatment gas comprises HCl gas and GeH4 gas, and the content of the HCl gas is greater than the content of the GeH4 gas;
[0066] S4: forming an epitaxial layer in the groove.
[0067] The steps of the semiconductor structure preparation method will be described in detail below. Figures 4 to 8
[0068] Referring to Figure 4 , step S1 is performed: a silicon substrate 201 is provided, wherein gate structures are formed on the silicon substrate 201 in a spaced manner.
[0069] As an example, the gate structure includes a dummy gate structure 202 and a sidewall structure 203 located on a sidewall of the dummy gate structure 202.
[0070] Specifically, the dummy gate structure 202 includes an amorphous silicon layer 2021, a silicon nitride layer 2022 and a silicon oxide layer 2023 stacked in sequence.
[0071] Specifically, the sidewall structure 203 includes a first sidewall layer 2031 and a second sidewall layer 2032, and the first sidewall layer 2031 is located between the second sidewall layer 2032 and the dummy gate structure 202.
[0072] Specifically, the thickness of the first sidewall layer 2031 is less than the thickness of the second sidewall layer 2032.
[0073] Please refer to Figure 5 , step S2 is performed: etching the silicon substrate 201 to form a groove 204 between two adjacent gate structures.
[0074] As an example, the etching process for forming the groove 204 includes dry etching process and wet etching process. However, due to the etching effect of the dry and wet etching process on the silicon substrate 201 of the inner wall of the groove 204 in the process of forming the groove 204, the inner surface of the groove 204 formed finally will appear small uneven structure. In the subsequent pretreatment process, since the HCl gas etches the surface of the silicon substrate 201, the pretreatment can remove the oxide and contaminants while eliminating the uneven structure.
[0075] As an example, the longitudinal cross-sectional shape of the groove 204 includes pentagon and hexagon. In this embodiment, the longitudinal cross-sectional shape of the groove 204 is pentagon.
[0076] Please refer to Figures 6 to 7 , step S3 is performed: the inner wall of the groove 204 is pretreated by a pretreatment gas to clean the inner wall of the groove 204 and form a transition layer 206 on the inner wall of the groove 204. The pretreatment gas includes HCl gas and GeH4 gas, and the content of the HCl gas is greater than the content of the GeH4 gas. Wherein, Figure 6 shows a state diagram of the structure obtained after pretreatment in the method for preparing a semiconductor structure of the present application, Figure 7 shows another state diagram of the structure obtained after pretreatment in the method for preparing a semiconductor structure of the present application.
[0077] Specifically, in the pre-treatment process, the content of GeH4 gas in the pre-treatment gas ranges from 0.9% to 1.1%, and the reaction temperature of the pre-treatment gas ranges from 700°C to 900°C.
[0078] The pre-treatment gas (containing HCl gas and GeH4 (germane) gas, the content of the GeH4 gas accounts for about 1% of the total amount of the pre-treatment gas) is introduced into an epitaxial furnace to etch the surface of the silicon substrate 201 in an environment of 700°C to 900°C (or a more suitable temperature), wherein the HCl gas is responsible for removing oxides and contaminants, thereby reducing the interface defects generated in the groove 204, and the GeH4 gas contains a small amount of Ge which forms an extremely thin passivation or transition layer 206 on the silicon surface after reaction, that is, the transition layer 206 shown in the figure. Figure 7 Specifically, when the surface of the silicon substrate 201 is etched by the HCl gas, a large number of dangling bonds 205 will be exposed (see Figure 6 ), and the trace Ge atoms in the low-content GeH4 gas fill or bind the dangling bonds 205 to generate more stable Si-Ge bonds (see Figure 7 ), that is, the transition layer 206, to eliminate the dangling bonds 205 generated in the cleaning process. The transition layer 206 also helps to reduce the risk of re-oxidation and re-contamination of the inner wall of the groove 204 and the surface of the silicon substrate 201, and provides stress buffering for lattice mismatch when growing high-Ge-content silicon germanium (SiGe), strained silicon or other heteroepitaxial layers 207 subsequently, avoids stress concentration, reduces the occurrence rate of dislocations or layer faults of the epitaxial layer 207, thereby inhibiting the generation of defects in the early stage of epitaxy, obtaining a more flat and high-crystal-quality epitaxial layer 207, and further improving the performance of the subsequent epitaxial layer 207 and device.
[0079] It should be noted that, Figure 6 Only one dangling bond 205 is shown, but during the pre-treatment process, the dangling bonds 205 will be left on the inner wall of the groove 204, and after the Ge atoms in the GeH4 gas react with them, the transition layer 206 covering the inner wall of the groove 204 is formed.
[0080] In particular, the pre-treatment process of the present application is also compatible with existing equipment, only a small amount of GeH4 gas path needs to be added to the original HCl cleaning system, which can upgrade the process, and the pre-treatment method is suitable for multi-zone temperature-controlled epitaxial furnaces, back laser temperature compensation means, etc., without affecting the main structure and process of the original equipment.
[0081] As an example, the thickness of the transition layer 206 is less than 1 nm, and the material of the transition layer 206 includes germanium silicide. Since the content of the GeH4 gas is about 0.9% to 1.1% of the total amount of the pretreatment gas, the thickness of the generated transition layer 206 is very thin, which is ensured to be below 1 nm, so that the transition layer 206 does not affect the conductive function of the semiconductor device while eliminating the dangling bonds 205 and avoiding stress concentration, that is, if the transition layer 206 is too thick, it will isolate the electrical connection between the channel and the source / drain of the semiconductor device, so that the device cannot work normally.
[0082] Referring back to Figure 8 , step S4 is performed to form an epitaxial layer 207 in the groove 204, and there is no interface defect between the epitaxial layer 207 and the groove 204, and no dislocation phenomenon occurs in the epitaxial layer 207.
[0083] Specifically, the material of the epitaxial layer 207 includes silicon germanium.
[0084] Thus, a semiconductor structure is manufactured, referring back to Figure 8 , which includes a silicon substrate 201, a groove 204, a transition layer 206, and an epitaxial layer 207. The silicon substrate 201 has a gate structure arranged at intervals thereon. The groove 204 is located in the silicon substrate 201 and between two adjacent gate structures. The transition layer 206 covers the inner wall of the groove 204. The epitaxial layer 207 is located on the transition layer 206 and fills the groove 204.
[0085] Specifically, the material of the epitaxial layer 207 includes silicon germanium.
[0086] As an example, the gate structure includes a pseudo gate structure 202 and a side wall structure 203 located on the sidewall of the pseudo gate structure 202.
[0087] As an example, the pseudo gate structure 202 includes an amorphous silicon layer 2021, a silicon nitride layer 2022, and a silicon oxide layer 2023 stacked in sequence.
[0088] As an example, the side wall structure 203 includes a first side wall layer 2031 and a second side wall layer 2032, and the first side wall layer 2031 is located between the second side wall layer 2032 and the pseudo gate structure 202.
[0089] As an example, the thickness of the first side wall layer 2031 is less than the thickness of the second side wall layer 2032.
[0090] As an example, the thickness of the transition layer 206 is less than 1 nm, and the material of the transition layer 206 includes germanium silicide.
[0091] In summary, the method for preparing the semiconductor structure comprises the steps of providing a silicon substrate, forming gate structures arranged at intervals on the silicon substrate, etching the silicon substrate to form a groove between two adjacent gate structures, pre-treating the inner wall of the groove by a pre-treatment gas to clean the inner wall of the groove and form a transition layer on the inner wall of the groove, the pre-treatment gas comprising HCl gas and GeH4 gas, and the content of the HCl gas being greater than the content of the GeH4 gas, and forming an epitaxial layer in the groove. The method for preparing the semiconductor structure can eliminate the dangling bonds generated in the cleaning process by the reaction of the trace GeH4 gas mixed in the pre-treatment gas with the dangling bonds, thereby reducing the interface defects and dislocations of the epitaxial layer, and improving the quality of the epitaxial layer and the performance of the device. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.
[0092] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a silicon substrate with gate structures arranged at intervals; etching the silicon substrate to form a groove between two adjacent gate structures; preprocessing the inner wall of the groove by a preprocessing gas to clean the inner wall of the groove and form a transition layer on the inner wall of the groove, the preprocessing gas comprising HCl gas and GeH4 gas, and the content of the HCl gas being greater than that of the GeH4 gas; forming an epitaxial layer in the groove.
2. The method of claim 1, wherein: During the preprocessing, the content of the GeH4 gas in the preprocessing gas ranges from 0.9% to 1.1%, and the reaction temperature of the preprocessing gas ranges from 700°C to 900°C.
3. The method of claim 1, wherein: The thickness of the transition layer is less than 1 nm, and the material of the transition layer comprises silicon germanium.
4. The method of claim 1, wherein: The etching process for forming the groove comprises dry etching and wet etching.
5. The method of claim 1, wherein: The longitudinal cross-sectional shape of the groove comprises a pentagon and a hexagon.
6. The method of claim 1, wherein: The gate structure comprises a dummy gate structure and a sidewall structure on the sidewall of the dummy gate structure.
7. The method of claim 6, wherein: The dummy gate structure comprises an amorphous silicon layer, a silicon nitride layer and a silicon oxide layer stacked in sequence from bottom to top.
8. The method of claim 1, wherein: The material of the epitaxial layer comprises silicon germanium.
9. A semiconductor structure, characterized by The semiconductor structure is prepared by the method of any one of claims 1-8, comprising: a silicon substrate with gate structures arranged at intervals; a groove in the silicon substrate and between two adjacent gate structures; a transition layer covering the inner wall of the groove; an epitaxial layer on the transition layer and filling in the groove.
10. The semiconductor structure of claim 9, wherein: The material of the epitaxial layer comprises silicon germanium.