Cathode stable sputtering OLED display device
By introducing conductive pillars and compensation layers into OLED display devices, the problem of cathode breakage caused by anode steps in traditional OLED display devices is solved, thereby improving the uniformity and stability of light emission.
Patent Information
- Application Number
- CN202511440588.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-10
- Publication Date
- 2026-01-13
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Figure CN121335366A_ABST
Abstract
Description
Technical Field
[0001] This invention patent belongs to the field of OLED display technology, specifically relating to a cathode-stable sputtering OLED display device, used to improve the light emission uniformity and lifespan of OLED display devices. Background Technology
[0002] As semiconductor display technology evolves towards miniaturization and high resolution, silicon-based organic light-emitting diodes (OLEDs) have become the core display devices for high-end devices such as AR / VR headsets and micro projectors due to their high compatibility with CMOS driving circuits, ultra-high pixel density, and low power consumption.
[0003] In traditional high-performance microcavity structures, the anode consists of a "high-reflectivity metal layer + transparent conductive layer." The thickness of the transparent conductive layer needs to be precisely designed according to the emission wavelengths of the R, G, and B sub-pixels: for example, the ITO thickness for red light (620nm) is approximately 120nm, for green light (550nm) it is approximately 100nm, and for blue light (450nm) it is approximately 80nm. This differentiated thickness design is a necessary condition to ensure the resonant matching of the microcavities for each color sub-pixel, but it also leads to serious structural defects.
[0004] Specifically, in traditional structures, the thickness difference of the transparent conductive layers of R, G, and B sub-pixels can reach 40-60 nm, resulting in a significant step-like height difference on the anode surface (maximum height difference > 50 nm). During the subsequent evaporation of OLED functional layers (such as hole transport layer, light-emitting layer, and electron transport layer), the film will "climb" along the step, forming uneven thickness: the film thickness at the step edge may be 20%-30% thicker than the flat area, causing abnormal local electric field distribution and resulting in a brightness deviation > 15%. More seriously, the cathode, as the top conductive layer of the device (usually an Ag:Mg alloy with a thickness of only 15-20 nm), needs to cover the entire anode surface: when the cathode film crosses the anode step, the film at the step edge will experience stress concentration due to stretching (stress value can reach 1-2 GPa), making it extremely prone to cracks or fractures.
[0005] Therefore, developing a novel anode structure that can accurately match the microcavity resonance requirements of R, G, and B sub-pixels, while eliminating anode surface steps and avoiding cathode cracks and water and oxygen intrusion, has become the key to overcoming current technological limitations. Summary of the Invention
[0006] The purpose of this invention is to provide a strong microcavity device structure and fabrication method suitable for silicon-based organic light-emitting diodes, so as to solve the problems existing in the prior art, and to provide a strong microcavity anode structure with uniform flatness, so as to improve the stability of the strong microcavity OLED cathode unit and reduce the risk of cathode breakage in the strong microcavity OLED unit device.
[0007] Based on the above concept, the technical solution adopted by this invention is as follows: A cathode-stabilized sputtering OLED display device includes a substrate, a CMOS, an insulating layer, conductive pillars, a metal layer, a total reflection layer, a pixel isolation layer, a compensation layer, an ITO layer, an OLED layer, a TFE layer, a first planarization layer, a CF layer, a second planarization layer, and a CG cover plate. The substrate, CMOS, insulating layer, metal layer, total reflection layer, compensation layer, ITO layer, OLED layer, cathode, TFE layer, first planarization layer, CF layer, second planarization layer, and CG cover plate are arranged sequentially from bottom to top. The conductive pillars are uniformly distributed in the insulating layer. The pixel isolation layer isolates the metal layer, total reflection layer, compensation layer, and ITO layer into several units, and the units formed by the separation of the metal layer are R, G, and B sub-pixels, arranged sequentially in the order R, G, and B.
[0008] Preferably, the conductive pillars are evenly distributed inside the insulating layer, and the top of the conductive pillars is connected to the bottom of the metal layer.
[0009] Preferably, the total reflection layer is a high-reflectivity metallic material layer prepared by physical vapor deposition.
[0010] Optionally, the physical vapor deposition process includes any one of magnetron sputtering, electron beam evaporation, and thermal evaporation.
[0011] Optionally, the high-reflectivity metallic material of the total reflection layer includes any one of silver, aluminum, and silver-magnesium alloy.
[0012] Preferably, the thickness of the total reflective layer is 100-200 nm.
[0013] Preferably, the thickness of the cathode is 15-20 nm.
[0014] Preferably, the compensation layer is disposed between the total reflection layer and the ITO layer, and the thickness of the compensation layer is different at corresponding positions above the R, G, and B sub-pixels.
[0015] Preferably, the compensation layer thickness H on the B sub-pixel B Satisfying the formula: H ITO(B1) *n ITO =H ITO(B2) *n ITO +H B *n B Among them, H ITO(B1) The thickness of the conventional B-subpixel ITO layer is 9, H ITO(B2) n represents the thickness of the B sub-pixel ITO layer 9 in this design structure. B Let n be the refractive index of the compensation layer material above the B sub-pixel.ITO is the refractive index of the ITO layer material.
[0016] Preferably, the compensation layer thickness H on the G sub-pixel G Satisfying the formula: H ITO(G1) *n ITO =H ITO(G2) *n ITO +H G *n G Among them, H ITO(G1) For the thickness of a standard G subpixel ITO layer 9, H ITO(G2) n is the thickness of the G sub-pixel ITO layer 9 in this design structure. G Let n be the refractive index of the compensation layer material above the G sub-pixel. ITO is the refractive index of the ITO layer material.
[0017] Preferably, the compensation layer thickness H on the R sub-pixel R Satisfying the formula: H ITO(R1) *n ITO =H ITO(R2) *n ITO +H R *n R Among them, H ITO(R1) For the thickness of the conventional R subpixel ITO layer 9, H ITO(R2) n is the thickness of the R sub-pixel ITO layer 9 in this design structure. R Let n be the refractive index of the compensation layer material above the R sub-pixel. ITO is the refractive index of the ITO layer material.
[0018] Preferably, the compensation layer above the R, G, and B sub-pixels satisfies the following formula: H ITO(B2) +H B =H ITO(G2) +H G =H ITO(R2) +H R .
[0019] Preferably, the material of the compensation layer includes conductive materials and non-conductive materials.
[0020] Optionally, the conductive material of the compensation layer includes any one of indium tin oxide, aluminum-doped zinc oxide, and antimony-doped tin dioxide; Optionally, the non-conductive material of the compensation layer includes any one of SiN, SiO2, and Al2O3.
[0021] Preferably, when the material of the compensation layer is a conductive material, there is no need to set conductive pillars inside the compensation layer, the upper surface of the compensation layer is bonded to the ITO layer, and the lower surface of the compensation layer is bonded to the total reflection layer.
[0022] Preferably, when the compensation layer is made of a non-conductive material, a conductive pillar is provided inside the compensation layer; the conductive pillar connects the total reflection layer and the ITO layer.
[0023] Preferably, the ITO layer is deposited on top of the compensation layer, and the upper surface of the ITO layer remains flush. Preferably, the thickness of the ITO layer is different at corresponding positions above the R, G, and B sub-pixels, which is adapted to the thickness difference of the compensation layer below.
[0024] Preferably, the CF layer is disposed between the first planarization layer and the second planarization layer, and the CF layer is aligned with the center of the R, G, and B sub-pixels to realize the color filtering function and improve the purity of the displayed colors. Preferably, the TFE layer is disposed between the OLED layer and the first planarization layer, and the TFE layer is any one of inorganic transparent film and organic-inorganic alternating film.
[0025] Preferably, the thickness of the inorganic transparent film is 1-3 μm.
[0026] Optionally, the material of the inorganic transparent film includes any one of silicon nitride, silicon oxide, and aluminum oxide.
[0027] Preferably, the thickness of the organic-inorganic alternating film is 2-10 μm, and the organic-inorganic alternating film is formed by alternating stacking of organic and inorganic layers; Optionally, the organic layer material includes any one of parylene, epoxy resin, and acrylic resin.
[0028] Optionally, the inorganic layer material includes any one of silicon nitride, silicon oxide, and titanium oxide. Preferably, the first planarization layer is disposed between the TFE layer and the CF layer, and the second planarization layer is disposed between the CF layer and the CG cover plate. The material of the planarization layer includes an organic insulating resin, which is used to eliminate the unevenness of the underlying structure and provide a smooth deposition surface.
[0029] Preferably, the CG cover plate is disposed above the second planarization layer, and the CG cover plate is transparent glass or a transparent flexible substrate.
[0030] Preferably, the CMOS is disposed between the substrate and the insulating layer. The CMOS is the driving circuit of the device and is used to control the lighting and extinguishing of the R, G, and B sub-pixels.
[0031] Preferably, the material of the insulating layer includes any one of inorganic insulating materials and organic insulating materials.
[0032] Optionally, the inorganic insulating material includes any one of silicon oxide, silicon nitride, and zirconium oxide.
[0033] Optionally, the organic insulating material includes either polyimide or photoresist.
[0034] The beneficial effects of this invention are as follows: 1. This invention overcomes the problem of thin cathode climbing and breakage caused by uneven anode heights in each sub-pixel due to the need to achieve enhanced luminous intensity in microcavities. It ensures that the anode layer thickness of the high-intensity microcavity device is consistent and the cathode layer can be sputtered smoothly, thereby achieving stable performance of the OLED device.
[0035] 2. While achieving anode planarization, this invention ensures that the microcavity resonance conditions of each sub-pixel are not affected by the thickness ratio design of the compensation layer and the transparent anode. This maintains the effect of the strong microcavity structure on improving luminous intensity and color gamut purity, while reducing local electric field anomalies and brightness deviations caused by uneven film thickness, thereby improving the luminous uniformity and overall performance stability of the OLED device. Attached Figure Description
[0036] Figure 1 This is a structural diagram of the cathode-stable sputtering OLED display device of the present invention.
[0037] Figure 2 This is a structural diagram of a traditional OLED display device.
[0038] Figure 3 This is a structural diagram of the compensation layer of the present invention when a non-conductive material is used.
[0039] In the figure: substrate 1, CMOS 2, insulating layer 3, conductive pillar 4, metal layer 5, total reflection layer 6, pixel isolation layer 7, compensation layer 8, ITO layer 9, OLED layer 10, TFE layer 11, first planarization layer 12, CF layer 13, second planarization layer 14, CG cover plate 15, and cathode 16. Detailed Implementation
[0040] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.
[0041] Example 1 like Figure 1As shown, the present invention includes a substrate, a CMOS, an insulating layer, conductive pillars, a metal layer, a total reflection layer, a pixel isolation layer, a compensation layer, an ITO layer, an OLED layer, a TFE layer, a first planarization layer, a CF layer, a second planarization layer, and a CG cover plate; wherein the substrate, CMOS, insulating layer, metal layer, total reflection layer, compensation layer, ITO layer, OLED layer, TFE layer, first planarization layer, CF layer, second planarization layer, and CG cover plate are arranged sequentially from bottom to top, and the conductive pillars are uniformly distributed in the insulating layer; the pixel isolation layer isolates the metal layer, total reflection layer, compensation layer, and ITO layer into several units, and the units formed by the separation of the metal layer are R, G, and B sub-pixels, which are arranged sequentially in the order of R, G, and B.
[0042] like Figure 1 As shown, in this embodiment, a single-crystal silicon substrate 1 with a CMOS driving circuit is selected, an insulating layer 3 is deposited on its surface and conductive pillars 4 are prepared; then a metal layer is deposited, and after photolithography-etching patterning, a pixel isolation layer material is coated and etched to form a pixel isolation layer 7, dividing the R / G / B sub-pixel regions.
[0043] A total reflection layer 6 is deposited by PVD within the sub-pixel region enclosed by the metal layer 5 and the pixel isolation layer 7; then, a compensation layer 8 is deposited on the R / G / B sub-pixels by CVD. The compensation layer 8 is made of a conductive material, specifically any one of indium tin oxide, aluminum-doped zinc oxide, and antimony-doped tin dioxide. The calculation formula for the compensation layer is as follows: H ITO(B1) *n ITO =H ITO(B2) *n ITO +H B *n B H ITO(G1) *n ITO =H ITO(G2) *n ITO +H G *n G H ITO(R1) *n ITO =H ITO(R2) *n ITO +H R *n R The thickness of the compensation layer for each sub-pixel is controlled by the formula described above.
[0044] Furthermore, if the anode total reflection layer 6 is too thin, pinholes or island-like defects may exist, leading to increased light transmittance and decreased reflectivity, thus weakening the microcavity enhancement effect. If the anode total reflection layer 6 is too thick, the increase in reflectivity is slight, while increasing material costs and processing time. Moreover, an excessively thick metal layer 5 may lead to stress accumulation, increasing the risk of peeling from the substrate. The thickness of the anode total reflection layer 6 is 100-200 nm. In this embodiment, the thickness of the anode total reflection layer 6 is 150 nm.
[0045] An ITO layer 9 was deposited on top of the compensation layer by PVD, and the deposition rate and time were adjusted to make the surface of the ITO layer flush. Subsequently, an OLED layer 10 was prepared by vacuum evaporation.
[0046] A cathode 16 with a thickness of 18 nm is deposited above the OLED layer 10 by vapor deposition; a 2 μm thick inorganic TFE layer 11 is deposited by ALD; a first planarization layer 12 is sequentially coated, a CF layer 13 is prepared by photolithography, and a second planarization layer 14 is coated; finally, a CG cover plate 15 is attached to complete the device fabrication.
[0047] Example 2 like Figure 3 As shown, the rest is the same as in Example 1, except that: The compensation layer 8 is made of a non-conductive material, specifically including any one of SiN, SiO2 and Al2O3.
[0048] The compensation layer 8 has a conductive pillar 4 inside, which connects the total reflection layer 6 and the ITO layer 9.
[0049] Comparative Example 1 Everything else is the same as in Example 1, except that: No compensation layer was set, and an ITO layer (metal oxide anode) was deposited directly on top of the total reflection layer.
[0050] Figure 2 This is the structure of a traditional OLED display device. The CMOS2, insulating layer, conductive pillars, metal layer, and total reflection layer above the substrate are the same as those in this invention. The deposition thickness of the metal oxide anode above the R / G / B sub-pixel regions is different. Therefore, the subsequent deposition process will result in a height difference between the OLED layer, cathode, and encapsulation layer in two adjacent sub-pixel regions, which can easily cause the risk of cathode overlap breakage.
[0051] The anode layer of this invention has a uniform thickness, and the cathode layer can be sputtered smoothly, thereby achieving stable performance of the OLED device.
[0052] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative and not exhaustive. All modifications within the scope of this invention or its equivalents are included in this invention.
Claims
1. A cathode-stabilized sputtering OLED display device, characterized in that, It includes a substrate (1), CMOS (2), insulating layer (3), conductive pillar (4), metal layer (5), total reflection layer (6), pixel isolation layer (7), compensation layer (8), ITO layer (9), OLED layer (10), TFE layer (11), first planarization layer (12), CF layer (13), second planarization layer (14), CG cover plate (15), and cathode (16); The substrate (1), CMOS (2), insulating layer (3), metal layer (5), total reflection layer (6), compensation layer (8), ITO layer (9), OLED layer (10), cathode (16), TFE layer (11), first planarization layer (12), CF layer (13), second planarization layer (14) and CG cover plate (15) are arranged from bottom to top. The conductive pillars (4) are uniformly distributed in the insulating layer (3), with the bottom connected to the CMOS (2) and the top connected to the metal layer (5); The pixel isolation layer (7) isolates the metal layer (5), the total reflection layer (6), the compensation layer (8) and the ITO layer (9) into several units, wherein the separating units of the metal layer (5) are R, G and B sub-pixels, and are arranged in the order of R, G and B.
2. The cathode-stabilized sputtering OLED display device according to claim 1, characterized in that, The material of the compensation layer (8) includes conductive materials and non-conductive materials; The conductive material includes any one of indium tin oxide, aluminum-doped zinc oxide, and antimony-doped tin dioxide. The non-conductive material includes any one of SiN, SiO2, and Al2O3.
3. The cathode-stabilized sputtering OLED display device according to claim 2, characterized in that, When the material of the compensation layer (8) is a non-conductive material, the interior of the compensation layer (8) is provided with conductive pillars (4); the conductive pillars (4) connect the total reflection layer (6) and the ITO layer (9).
4. The cathode-stabilized sputtering OLED display device according to claim 1, characterized in that, The thickness of the compensation layer (8) is different at corresponding positions above the R, G and B sub-pixels.
5. The cathode-stabilized sputtering OLED display device according to claim 1, characterized in that, The compensation layer thickness H on the B sub-pixel B Satisfying the formula: H ITO(B1) *n ITO =H ITO(B2) *n ITO +H B *n B Among them, H ITO(B1) H is the thickness of the conventional B-subpixel ITO layer (9). ITO(B2) n is the thickness of the B sub-pixel ITO layer (9) in this design structure. B Let n be the refractive index of the compensation layer material above the B sub-pixel. ITO is the refractive index of the ITO layer material.
6. The cathode-stabilized sputtering OLED display device according to claim 1, characterized in that, The compensation layer thickness H on the G sub-pixel G Satisfying the formula: H ITO(G1) *n ITO =H ITO(G2) *n ITO +H G *n G Among them, H ITO(G1) H is the thickness of the conventional G subpixel ITO layer (9). ITO(G2) n is the thickness of the G sub-pixel ITO layer (9) in this design structure. G Let n be the refractive index of the compensation layer material above the G sub-pixel. ITO is the refractive index of the ITO layer material.
7. The cathode-stabilized sputtering OLED display device according to claim 1, characterized in that, The compensation layer thickness H on the R sub-pixel R Satisfying the formula: H ITO(R1) *n ITO =H ITO(R2) *n ITO +H R *n R Among them, H ITO(R1) H is the thickness of the conventional R subpixel ITO layer (9). ITO(R2) n is the thickness of the R sub-pixel ITO layer (9) in this design structure. R Let n be the refractive index of the compensation layer material above the R sub-pixel. ITO is the refractive index of the ITO layer material.
8. The cathode-stabilized sputtering OLED display device according to claim 1, characterized in that, The ITO layer (9) is deposited on top of the compensation layer (8). The upper surface of the ITO layer (9) is flush with the surface. The thickness of the ITO layer (9) at the corresponding positions above the R, G and B sub-pixels is different.
9. The cathode-stabilized sputtering OLED display device according to claim 1, characterized in that, The CF layer (13) is aligned with the center of position of the R, G and B sub-pixels.
10. The cathode-stabilized sputtering OLED display device according to claim 1, characterized in that, The TFE film (11) is either an inorganic transparent film or an organic-inorganic cross-linked film; The thickness of the inorganic transparent film is 1-3 μm, and the thickness of the organic-inorganic cross-linked film is 2-10 μm.