Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. A layer of conductive material is formed over a bottommost layer of an interconnect structure in interconnect layers of a semiconductor device, and the layer of conductive material is etched to define a bottommost layer of a metallization structure from the layer of conductive material. To reduce the likelihood of collapse of the free-standing metallization structure, exposed sidewall surfaces of the free-standing metallization structure may be oxidized to form metal oxide sidewalls of the free-standing metallization structure. The metal oxide sidewalls may be formed using self-aligned oxidation techniques that specifically oxidize the sidewalls of the free-standing metallization structures. The metal oxide sidewalls may be formed from a metal oxide material that increases the mechanical strength of the free-standing metallization structure, which enables the free-standing metallization structure to resist collapse.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of forming the same. BACKGROUND

[0002] An interconnect layer (sometimes referred to as a back-end-of-line or back-end-of-line (BEOL) region) is a region of a semiconductor device that includes multiple layers of conductive structures arranged to carry signals and / or provide power distribution throughout the semiconductor device. The multiple layers of conductive structures can include various layers of vertically arranged interconnect structures (e.g., vias) and metallization structures (e.g., trenches, wires, traces). SUMMARY

[0003] According to a first aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a metal layer of an interconnect layer of the semiconductor device over a device layer of the semiconductor device; etching the metal layer to define a plurality of conductive structures in the interconnect layer, wherein at least one conductive structure of the plurality of conductive structures is electrically coupled to an interconnect structure over the device layer; performing an oxidation operation to oxidize sidewalls of the plurality of conductive structures; and sealing regions between the plurality of conductive structures with a dielectric plug.

[0004] According to a second aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a barrier layer over a device layer of the semiconductor device; forming a metal layer of an interconnect layer of the semiconductor device on the barrier layer; etching the metal layer and the barrier layer to define a plurality of conductive structures in the interconnect layer, wherein a conductive structure of the plurality of conductive structures is electrically coupled to an interconnect structure over the device layer; performing an oxidation operation on sidewalls of the plurality of conductive structures such that the sidewalls of the plurality of conductive structures are converted from a metal material to a metal oxide liner; and sealing regions between the metal oxide liner with a dielectric plug.

[0005] According to a third aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate layer; at least one of an integrated circuit device in the substrate layer or in the substrate layer; an interconnect structure in a dielectric layer over the substrate layer and electrically coupled to the integrated circuit device; a conductive structure over the dielectric layer and electrically coupled to the interconnect structure, wherein a body of the conductive structure comprises a metal material, and wherein sidewalls of the conductive structure comprise a metal oxide material; and an isolation region along at least one sidewall of the conductive structure, wherein the isolation region comprises: an air spacer along a first portion of the sidewall; and a dielectric plug along a second portion of the sidewall over the first portion. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can best be understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. Figures 1-6, below, are block diagrams of example semiconductor devices.

[0007] Figure 1 is an illustration of an example semiconductor device described herein.

[0008] Figures 2A-2C is an illustration of an example implementation that forms part of a semiconductor device described herein.

[0009] Figures 3A-3M is an illustration of an example implementation that forms part of a semiconductor device described herein.

[0010] Figure 4 is a flow diagram of an example process associated with forming a semiconductor device described herein.

[0011] Figure 5 is a flow diagram of an example process associated with forming a semiconductor device. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. For simplicity, in the following description, a particular embodiment or example can be described solely in terms of its components or steps. Moreover, these offerings have not necessarily been described with reference to absolute times. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0013] Moreover, spatially relative terms (e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like) can be used herein for ease of describing one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. Such spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] Interconnect layers for semiconductor devices can be formed above the device layers of the semiconductor device. The device layers may include substrate layers of semiconductor devices and integrated circuit devices (e.g., transistors, capacitors, diodes, memory cells) in and / or on a semiconductor substrate. Layers of contact structures (e.g., source / drain contacts, gate contacts) may be included within the device layers, and the bottom layer of interconnect structures (e.g., source / drain interconnect structures, gate interconnect structures, sometimes referred to as via-0 or V0 layers) may be located at the bottom of the interconnect layers between the contact structures and higher layers. The bottom layers of the contact structures and interconnect structures can electrically connect the integrated circuit devices and the higher layers of conductive structures in the interconnect layers.

[0015] The bottom layer of the metallization structure in the interconnect layer (sometimes referred to as the metal-0 or M0 layer) can be included above the bottom layer of the interconnect structure. The bottom layer of the metallization structure can be formed by forming a recess in the dielectric layer above the bottom layer of the interconnect structure, such that the top surface of the bottom layer of the interconnect structure is exposed through the recess, and depositing the material of the bottom layer of the metallization structure in the recess, so that the bottom layer of the metallization structure is electrically coupled to the bottom layer of the interconnect structure.

[0016] However, as the size of integrated circuit devices decreases, the dimensions and spacing between metallization structures in the interconnect layers also decrease. Therefore, the reduced dimensions and spacing between metallization structures in the bottom layer of the metallization structure can lead to decreased gap-filling performance. This can result in voids and / or other discontinuities in the bottom layer of the metallization structure, which may increase the contact resistance of the bottom layer and / or potentially cause electrical disconnection between the bottom layer of the metallization structure and the bottom layer of the interconnect structure. Including a liner in the recess can worsen the gap-filling performance; the liner prevents material migration from the bottom layer of the metallization structure and / or provides enhanced adhesion between the bottom layer of the metallization structure and the dielectric layer.

[0017] In some implementations described herein, a layer of conductive material is formed above the bottom layer of the interconnect structure in the interconnect layer of the semiconductor device, and the layer of conductive material is etched to define the bottom layer of the metallization structure from the conductive material layer, rather than forming the bottom layer of the metallization structure in a recess of the dielectric layer. The region between the individual metallization structures can then be sealed with low-k dielectric plugs, leaving an air gap between the metallization structures as low-k electrical isolation. This air gap allows the bottom layer of the metallization structure to be electrically isolated without a liner, providing a larger area and lower contact resistance for the bottom layer of the metallization structure.

[0018] To reduce the likelihood of collapse in freestanding metallized structures, the exposed sidewall surfaces of the freestanding metallized structures can be oxidized to form metal oxide sidewalls. Self-aligned oxidation techniques can be used to form these metal oxide sidewalls, specifically targeting the sidewalls of the freestanding metallized structures. The metal oxide sidewalls can be formed from metal oxide materials that increase the mechanical strength of the freestanding metallized structure (making it resistant to collapse) and have low resistance (minimizing its impact on the overall resistance of the freestanding metallized structure). In this way, the low resistance of the bottom layer of the realized metallized structure, alone or in combination with the low-k electrical isolation provided by the air gap, enables a low capacitance time constant (RC time constant) for the bottom layer of the metallized structure. In other examples, a low RC time constant enables faster signal propagation speeds through the bottom layer of the metallized structure; and / or enables faster switching speeds for integrated circuit devices in semiconductor devices; and so on.

[0019] Figure 1 This is an illustration of an example semiconductor device 100 described herein. Semiconductor device 100 may include: a system-on-a-chip (SoC) device, a logic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)), a memory device (e.g., a high-bandwidth memory (HBM) device), an image sensor device (e.g., a complementary metal-oxide-semiconductor (CMOS) image sensor device), a display device (e.g., an organic light-emitting diode (OLED) display device), and / or other types of semiconductor devices.

[0020] like Figure 1 As shown, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104, wherein the interconnect layer 104 is disposed above the device layer 102 in the z-direction of the semiconductor device 100. For example, the interconnect layer 104 may be located above the device layer 102. As another example, the interconnect layer 104 may be located below the device layer 102.

[0021] Device layer 102 may also be referred to as the front-end region or front-end process (FEOL) region of semiconductor device 100. Interconnect layer 104 may also be referred to as the back-end region or back-end process (BEOL) region of semiconductor device 100 and may include conductive structures arranged to transmit signals and / or provide power distribution throughout semiconductor device 100. In some implementations, semiconductor device 100 includes interconnect layers 104 above and below device layer 102. A first interconnect layer 104 on a first side of device layer 102 may be used for signal propagation throughout semiconductor device 100, and a second interconnect layer 104 on a opposite second side of device layer 102 may be used for power distribution within semiconductor device 100.

[0022] Device layer 102 includes a substrate layer 106 of semiconductor device 100. Substrate layer 106 may correspond to a portion of a semiconductor wafer on which semiconductor device 100 is formed. Substrate layer 106 may include: a silicon (Si) substrate (a substrate formed of a material including silicon), a III-V compound semiconductor material substrate (e.g., gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates. Substrate layer 106 may extend in the semiconductor device 100 in the x-direction and / or y-direction such that the top and bottom surfaces of substrate layer 106 are substantially orthogonal to the z-direction in semiconductor device 100.

[0023] A dielectric layer 108 is included on the substrate layer 106. The dielectric layer 108 includes an interlayer dielectric (ILD) layer (e.g., an ILD0 layer), an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 108 includes one or more dielectric materials that allow portions of the substrate layer 106 to be selectively etched or protected from etching, and / or to electrically isolate integrated circuit devices 110 in the device layer 102. The dielectric layer 108 includes silicon nitride (Si). x N y ), oxides (e.g., silicon dioxide (SiO2) x (and / or other oxide materials), and / or other types of dielectric materials. The dielectric layer 108 may extend in the semiconductor device 100 in the x-direction and / or y-direction.

[0024] Integrated circuit device 110 may be included in and / or on substrate 106, and / or in dielectric layer 108 of device layer 102 of semiconductor device 100. Integrated circuit device 110 includes: transistors (e.g., planar transistors, fin field-effect transistors (finFETs), nanostructure transistors (e.g., gate-all-around (GAA) transistors and / or nanosheet transistors), complementary nanostructure nanostructures (CFETs)), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, and / or other types of semiconductor devices.

[0025] Integrated circuit device 110 may include multiple source / drain regions 112, which are grown and / or otherwise formed on and / or around portions of substrate 106. "(one or more) source / drain regions" may refer to a single source or drain, or collectively to both, depending on the context. Source / drain regions 112 may be formed by epitaxial growth of doped semiconductor regions and / or by other semiconductor processes. In some implementations, source / drain regions 112 are formed in recessed portions of substrate 106. These recessed portions may be formed by strained source / drain (SSD) etching and / or other types of etching operations on substrate 106.

[0026] The integrated circuit device 110 may further include a gate dielectric layer 114 between the gate structure 116 and the substrate layer 106. In some implementations, the gate dielectric layer 114 also extends along the sidewalls of the gate structure 116. In some implementations, the gate dielectric layer 114 comprises a low dielectric constant (low k) dielectric material, such as silicon oxide (SiO2). x In some implementations, the gate dielectric layer 114 comprises a high dielectric constant (high k) dielectric material, such as hafnium oxide (HfO). x High-k dielectric materials can be dielectric materials with a dielectric constant greater than approximately 9.

[0027] The gate structure 116 may be laterally located between the source / drain regions 112. In some implementations, the gate structure 116 is formed of polysilicon. In these implementations, the polysilicon may be doped with one or more types of dopants (e.g., p-type dopants, n-type dopants) to modulate the work function of the gate structure 116.

[0028] In some implementations, the gate structure 116 is formed of one or more metallic materials (e.g., tungsten (W), titanium (Ti), cobalt (Co), and / or other metals). In these implementations, the gate structure 116 may include one or more work function metal layers 118 (e.g., p-type metal layers, n-type metal layers) for tuning the work function of the gate structure 116. One or more work function metal layers 118 may be included between the gate dielectric layer 114 and the gate structure 116.

[0029] The p-type work function metal layer may include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or other metals having a work function greater than about 4.7 electron volts (eV). The p-type work function metal layer may include elements to tune the work function of the gate structure 116 such that the work function is adjusted to be close to the valence band of the material of the substrate layer 106.

[0030] The n-type work function metal layer may include one or more metallic materials that tune or adjust the work function of the gate structure 116 to be near the conduction band of the substrate layer 106 of the semiconductor device 100. In some implementations, the n-type work function metal layer may include titanium aluminum (TiAl). In some implementations, the n-type work function metal layer includes titanium aluminum carbon (TiAlC). In some implementations, the n-type work function metal layer includes other aluminum-containing metals. In some implementations, other n-type metallic materials are included in the n-type work function metal layer.

[0031] Sidewall spacers 120 may be included on the sidewalls of the gate structure 116 to provide electrical isolation for the gate structure 116, etc. In some implementations, the sidewall spacers 120 are in contact with the gate dielectric layer 114. In some implementations, the sidewall spacers 120 are in contact with the work function metal layer 118. In some implementations, the sidewall spacers 120 are in direct contact with the gate structure 116. The sidewall spacers 120 may include silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon carbide (SiOC), silicon carbonitride (SiOCN), and / or other suitable materials. In some implementations, the dielectric material of the sidewall spacer 120 may have a dielectric constant that is less than that of the dielectric material of the gate dielectric layer 114.

[0032] The source / drain region 112 is electrically coupled and / or physically coupled to the source / drain contact structure 122. The source / drain contact structure 122 may include contact vias, contact plugs, and / or other types of contact structures that electrically connect the source / drain region 112 of the integrated circuit device 110 to the interconnect layer 104 of the semiconductor device 100. The source / drain contact structure 122 includes cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), copper (Cu), and / or other conductive or metallic materials. One or more liner layers 124 may be included on the sidewalls of the source / drain contact structure 122. The liner layers 124 may include: a barrier layer included to prevent or minimize the diffusion of material from the source / drain contact structure 122 to the surrounding dielectric layer; an adhesive layer or glue layer included to promote adhesion between the source / drain contact structure 122 and the surrounding dielectric layer; and / or other types of liners. Examples of materials for the lining layer 124 include titanium nitride (TiN), tantalum nitride (TaN), and / or other suitable lining materials.

[0033] Interconnect layer 104 of semiconductor device 100 is included in semiconductor device 100 above substrate layer 106 and integrated circuit device 110 in the z-direction. Interconnect layer 104 includes a plurality of dielectric layers arranged in a direction generally perpendicular to substrate layer 106 (e.g., z-direction). These dielectric layers may include ILD layer 126 and ESL 128 arranged alternately in the z-direction. ILD layer 126 and ESL 128 may extend in the x-direction and / or y-direction in semiconductor device 100.

[0034] ILD layers 126 may each comprise: oxides (e.g., silicon oxide (SiO2)). x The dielectric material can be an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS), silsesquioxane (HSQ), and / or other suitable dielectric materials. In some implementations, the ILD layer 126 comprises an extremely low dielectric (ELK) dielectric material having a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x ), amorphous fluorinated carbon (aC) x F y ), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon carbide (SiOC) polymers, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylene ether (PAE), and / or porous silica (SiO2) x )wait.

[0035] ESL 128 can each include silicon nitride (Si). x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some implementations, ILD layers 126 and ESL 128 include different dielectric materials to provide etch selectivity, allowing various structures to be formed in interconnect layer 104.

[0036] Interconnect layer 104 includes a plurality of back-end conductive structures disposed in multiple layers. The back-end conductive structures may be electrically coupled and / or physically coupled to one or more integrated circuit devices 110 in device layer 102. The back-end conductive structures provide electrical wiring that enables the supply of signals and / or power to and / or the supply of signals and / or power from integrated circuit devices 110.

[0037] The back-end conductive structure layer may include multiple layers 130a to 130e, which are vertically arranged in the z-direction and alternate with multiple layers 132a to 132e (e.g., vertically alternating). Each of layers 130a to 130e includes an interconnect structure layer, and each of layers 132a to 132e includes a metallization structure layer. The interconnect structure layers 130a to 130e may be referred to as V layers. The metallization structure layers 132a to 132e may be referred to as M layers.

[0038] like Figure 1 As shown, layer 130a of the interconnect structure can be the bottom layer of the interconnect structure in the interconnect layer and can be referred to as the via-0 (V0) layer. The interconnect structure of layer 130a may include a source / drain interconnect structure 134 and a gate interconnect structure 136. The source / drain interconnect structure 134 is electrically coupled and / or physically coupled to the source / drain contact structure 122, and the gate interconnect structure 136 is electrically coupled and / or physically coupled to the gate structure 116. In some implementations, a gate contact (not shown) is included between the gate structure 116 and the gate interconnect structure 136. In some implementations, the source / drain interconnect structure 134 is referred to as a source / drain via (VD), and the gate interconnect structure 136 is referred to as a gate via (VG).

[0039] The source / drain interconnect structure 134 and the gate interconnect structure 136 may each include vias, conductive blocks, conductive pillars, and / or other types of conductive structures extending in the z-direction. The source / drain interconnect structure 134 and the gate interconnect structure 136 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials. In some implementations, the source / drain interconnect structure 134 and the gate interconnect structure 136 include one or more of the same material. In some implementations, the source / drain interconnect structure 134 includes one or more materials different from those of the gate interconnect structure 136. In some implementations, one or more liner layers are included between surrounding dielectric layers in the interconnect layer 104. The source / drain interconnect structure 134 and the gate interconnect structure 136 may be located within the ILD layer 126 and / or the ESL 128.

[0040] In some implementations, one or more liner layers are included between these layers and the source / drain interconnect structure 134 and the gate interconnect structure 136. Each of the liner layers may include a barrier liner, an adhesive liner, and / or other types of liner. Examples of materials for the one or more liners include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0041] In some implementations, the source / drain interconnect structure 134 and the gate interconnect structure 136 are linerless. In these implementations, a bottom-up deposition technique can be used to form the source / drain interconnect structure 134 and the gate interconnect structure 136. The bottom-up deposition technique may include selectively depositing material for the source / drain interconnect structure 134 and the gate interconnect structure 136 on the source / drain contact 122 and the gate structure 116, respectively. In this way, the material for the source / drain interconnect structure 134 and the gate interconnect structure 136 accumulates (e.g., "grows") from the bottom of the recess in which the source / drain interconnect structure 134 and the gate interconnect structure 136 are formed, rather than accumulating on the sidewalls and the bottom of the recess. The bottom-up growth of the source / drain interconnect structure 134 and the gate interconnect structure 136 allows the source / drain interconnect structure 134 and the gate interconnect structure 136 to be formed seamlessly. Because it grows from bottom to top, there are no seams in the source / drain interconnect structure 134 and the gate interconnect structure 136, but seams may appear if material accumulates on the sidewalls of the recess (the seams may merge at the top of the recess before the recess can be completely filled with the material of the source / drain interconnect structure 134 and the gate interconnect structure 136).

[0042] like Figure 1 As further shown, layer 132a of the metallization structure can be the bottom layer of the metallization structure in the interconnect layer, and can be referred to as the metal-0 (M0) layer. The metallization structure in layer 132a (e.g., the M0 layer) can be located above and coupled to the source / drain interconnect structure 134 and the gate interconnect structure 136 in layer 130a (e.g., the V0 layer).

[0043] The metallization structure in layer 132a may be formed by a barrier layer 138 and a metal layer 140. The barrier layer 138 may be located above and / or on the ILD layer 126 of layer 130a, and the metal layer 140 may be located above and / or on the barrier layer 138. The barrier layer 138 may include a tantalum nitride (TaN) barrier layer and / or a titanium nitride (TiN) barrier layer, etc. The barrier layer 138 may be included between the metal layer 140 and the source / drain interconnect structure 134 and the gate interconnect structure 136 in layer 130a to prevent, minimize, and / or otherwise reduce the diffusion of material from the source / drain interconnect structure 134 and the gate interconnect structure 136 upward into the metal layer 140.

[0044] The metal layer 140 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials. Figures 3A-3MAs described, the metal layer 140 can be patterned and etched to form an isolation region 142 in the metal layer 140. The isolation region 142 extends vertically through the metal layer 140 and the barrier layer 138, and defines a metallization structure 144 in a layer 132a of the metallization structure.

[0045] like Figure 1 As shown, the metallization structure 144 may have an inverted cross-sectional profile relative to the source / drain interconnect structure 134 and gate interconnect structure 136 in layer 130a of the interconnect structure. Specifically, the top width of the metallization structure 144 may be smaller than the bottom width of the metallization structure 144, while the top width of the source / drain interconnect structure 134 and gate interconnect structure 136 may be larger than the bottom width of the source / drain interconnect structure 134 and gate interconnect structure 136 in layer 130a. This occurs due to the different processes and techniques used to form layers 130a and 132a. For example, and as combined with Figures 3A-3M In more detail, the source / drain interconnect structure 134 and gate interconnect structure 136 in layer 130a can be formed by forming ESL 128 and ILD 126 of layer 130a, etching these layers to form recesses through these layers, and forming the source / drain interconnect structure 134 and gate interconnect structure 136 in the recesses. Conversely, and as combined Figures 3A-3M In more detail, a barrier layer 138 and a metal layer 140 are formed and then etched to form an isolation region 142, which defines a metallized structure 144. Therefore, the isolation region 142 has a cross-sectional profile similar to that of the source / drain interconnect structure 134 and the gate interconnect structure 136.

[0046] The isolation region 142 may include an air spacer 146 defined by a barrier layer 138 and a metal layer 140, and the air spacer 146 is sealed at its top by a dielectric plug 148. The dielectric plug 148 may include a low-k dielectric material, such as silicon oxide (SiO2). The low-k dielectric material of the dielectric plug 148, together with the air in the air spacer 146, enables low parasitic capacitance between the electrically isolated metallized structures 144 of the isolation region 142. However, other dielectric materials may be used for the dielectric plug 148.

[0047] The isolation region 142 may include a support layer 150, which is formed during the process of forming the air spacer 146 and the dielectric plug 148 of the isolation region 142. The support layer 150 may include supporting the material of the dielectric plug 148 during deposition to prevent the material of the dielectric plug 148 from filling a conformal layer in the air spacer 146. The support layer 150 may include a dielectric material. For example, the support layer 150 may include an oxide material, such as a silicon oxide-based material. Examples of such materials include silicon dioxide (SiO2), silicon carbide (SiOC), silicon oxynitride (SiON), and / or silicon carbonitride (SiOCN), etc.

[0048] like Figure 1 As further shown, the sidewall of the metallized structure 144 facing the isolation region 142 may correspond to a metal oxide liner 152. The metal oxide liner 152 is the portion of the sidewall of the metallized structure 144 exposed by the air spacer 146 formed during the process of forming the isolation region 142. With the recess open, the sidewall of the metallized structure 144 is oxidized to form the metal oxide liner 152. Therefore, the metal oxide liner 152 may comprise a metal oxide of the metal layer 140. For example, the metal layer 140 may comprise ruthenium (Ru), and the metal oxide liner 152 may comprise ruthenium oxide (RuO₂). x For example, ruthenium dioxide (RuO2). The ruthenium in the metal layer 140 corresponding to the body of the metallization structure 144 can have a polycrystalline structure, while the ruthenium oxide material of the metal oxide liner 152 can have a single-crystal structure. As another example, the metal layer 140 may include cobalt (Co), and the metal oxide liner 152 may include cobalt oxide (CoO2). x (e.g., CoO2). Figures 3A-3M An example of the process is described in more detail.

[0049] Compared to if the metallized structure 144 were formed in a recess in the dielectric layer, etching the metal layer 140 to define the metallized structure 144 allows the metallized structures 144 to be spaced more closely together, and the metal oxide liner 152 provides increased strength to the metallized structure 144 to reduce the likelihood of the metallized structure 144 collapsing before the air spacer 146 is sealed by the dielectric plug 148 (which could otherwise collapse due to the reduced size of the metallized structure 144). The increased mechanical strength can be provided by the single-crystal structure of the metal oxide liner 152, because the absence of grain boundaries in the single-crystal structure provides a more uniform stress distribution and resistance to deformation; therefore, the single-crystal structure of the metal oxide liner 152 can have higher mechanical strength than the polycrystalline structure of the bulk of the metallized structure 144.

[0050] Furthermore, the metal oxide liner 152 can have a low resistivity close to that of the metallic material of the metallized structure 144, thus having minimal impact on the overall resistance of the metallized structure 144. For example, if the body of the metallized structure 144 is formed of ruthenium (Ru), the body of the metallized structure 144 can have a resistivity ranging from about 1 microohm-cm to about 10 microohm-cm. The metal oxide liner 152 (which corresponds to the sidewall of the metallized structure 144) can be formed of ruthenium oxide, which can have a resistivity ranging from about 20 microohm-cm to about 50 microohm-cm. However, other values ​​and ranges are also within the scope of this disclosure.

[0051] like Figure 1 As further shown, layer 130b of interconnect structure 154 (e.g., via-1 (V1) layer) may be included above and electrically coupled to layer 132a (e.g., M0 layer). Layer 132b of metallization structure 156 (e.g., metal-1 (M1) layer) may be located above and electrically coupled to layer 130b (e.g., V1 layer) in interconnect layer 104. Layer 130c of interconnect structure 154 (e.g., via-2 (V2) layer) may be included above and electrically coupled to layer 132b (e.g., M1 layer). Layer 132c of metallization structure 154 (e.g., metal-2 (M2) layer) may be located above and electrically coupled to layer 130c (e.g., V2 layer) in interconnect layer 104. Layer 130d of interconnect structure 154 (e.g., via-3 (V3) layer) may be included above and electrically coupled to layer 132c (e.g., M2 layer). Layer 132d of metallization structure 156 (e.g., metal-3 (M3) layer) may be located above and electrically coupled to layer 130d (e.g., V3 layer) in interconnect layer 104. Layer 130e of interconnect structure 154 (e.g., via-4 (V4) layer) may be included above and electrically coupled to layer 132d (e.g., M3 layer). Layer 132e of metallization structure 156 (e.g., metal-4 (M4) layer) may be located above and electrically coupled to layer 130e (e.g., V4 layer) in interconnect layer 104.

[0052] In some implementations, with Figure 1 Compared to the examples shown, the interconnect structure may include different numbers (e.g., more, less) of layers 130a to 130e (e.g., V layers) of interconnect structure, and / or may include different numbers (e.g., more, less) of layers 132a to 132e (e.g., M layers) of metallization structure.

[0053] Interconnect structure 154 may include vias, interconnects, and / or combinations of other types of conductive structures. Metallization structure 156 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. Interconnect structure 154 and metallization structure 156 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials. In some implementations, one or more liner layers 158 are included between the dielectric layer of interconnect layer 104 and interconnect structure 154, and / or between the dielectric layer of interconnect layer 104 and metallization structure 156. One or more liner layers 158 may include barrier liners, adhesive liners, and / or other types of liners. Examples of materials for one or more liner layers 158 include tantalum nitride (TaN) and / or titanium nitride (TiN), etc. In some implementations, the conductivity of the material of one or more liners 158 (e.g., TaN) may be less than that of the material of the metal oxide liner 152 (e.g., ruthenium oxide (RuO2)). x The conductivity of )).

[0054] In some implementations, the top layer of the back-end conductive structure (e.g., the top layer of metallization structure 156, the top layer of interconnect structure 154) may be coupled to a connection structure at the top of semiconductor device 100. The connection structure may include solder balls, solder bumps, contact pads (e.g., connection pad grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under-bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, and / or other types of connection structures. In some implementations, the top layer of the back-end conductive structure (e.g., the top layer of metallization structure 156, the top layer of interconnect structure 154) may be coupled to bonding structures, such as bonding pads and / or bonding vias.

[0055] As pointed out above, Figure 1 Provided as an example. Other examples may be provided in relation to... Figure 1 The descriptions are different.

[0056] Figures 2A-2C This is an illustration of an example implementation 200 that forms part of the semiconductor device 100 described herein. Specifically, example implementation 200 includes examples of forming a device layer 102 (e.g., a front-end region or FEOL region) of the semiconductor device 100. In some implementations, the bonding may be performed using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor processing tools). Figures 2A-2COne or more operations in the semiconductor processing operations described.

[0057] like Figure 2A As shown, a substrate layer 106 is provided. The substrate layer 106 may be provided in the form of a semiconductor wafer (e.g., a silicon (Si) wafer, a silicon-on-insulator (SOI) wafer, and / or other types of semiconductor workpieces). The semiconductor device 100 may be formed on the semiconductor wafer together with other semiconductor devices.

[0058] like Figure 2B As shown, integrated circuit device 110 can be formed in and / or on substrate layer 106 of device layer 102 of semiconductor device 100. One or more semiconductor processing tools can be used to form one or more portions of integrated circuit device 110. For example, one or more regions in substrate layer 106 can be doped with one or more types of dopants using an ion implantation tool to form source / drain regions 112 in substrate layer 106 of integrated circuit device 110. As another example, deposition tools can be used to perform various deposition operations to deposit layers and / or structures of integrated circuit device 110, and / or deposit photoresist layers for etching substrate layer 106 and / or portions of the deposited layers. Such layers may include gate dielectric layer 114, gate structure 116, and / or work function metal layer 118.

[0059] like Figure 2C As shown, a dielectric layer 108 is deposited over and / or on a substrate layer 106 and over and / or on an integrated circuit device 110 using a deposition tool, and an ESL 128 is deposited over and / or on the dielectric layer 108. Each of the dielectric layer 108 and ESL 128 can be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. In some implementations, a planarization operation (e.g., chemical mechanical planarization (CMP)) can be performed using a planarization tool after depositing the dielectric layer 108 and / or ESL 128 to planarize the dielectric layer 108 and / or ESL 128.

[0060] like Figure 2CAs further shown, the source / drain contact structure 122 of the integrated circuit device 110 can be formed through the dielectric layer 108 and the ESL 128. The source / drain contact structure 122 can be formed in recesses in the dielectric layer 108 and the etch stop layer 128. In some implementations, a pattern in a photoresist layer is used to etch the dielectric layer 108 and / or the ESL 128 to form the recess. In these implementations, a photoresist layer can be formed on the ESL 128 using a deposition tool. The photoresist layer can be exposed to a radiation source using an exposure tool to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 108 and / or the ESL 128 based on the pattern to form the recess. In some implementations, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some implementations, the remaining portion of the photoresist layer can be removed using photoresist removal tools (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative technique for pattern-based etching of the dielectric layer 108 to form recesses.

[0061] Source / drain contact structure 122 can be formed in a recess such that the source / drain contact structure 122 rests on the source / drain region 112. Material for the source / drain contact structure 122 can be deposited in the recess using deposition tools employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. Material for the source / drain contact structure 122 can be deposited in one or more deposition operations. In some implementations, a seed layer is first deposited, and material for the source / drain contact structure 122 is deposited on the seed layer. In some implementations, one or more liner layers 124 are deposited in the recess, and the source / drain contact structure 122 is deposited on the liner layers(s) 124. In some implementations, after depositing the source / drain contact structure 122, a planarization tool is used to perform a planarization operation (e.g., a CMP operation) to planarize the source / drain contact structure 122 such that the top of the source / drain contact structure 122 is substantially coplanar with the top of the ESL 128.

[0062] As pointed out above, Figures 2A-2C Provided as an example. Other examples may be provided in relation to... Figures 2A-2C The descriptions are different.

[0063] Figures 3A-3MThis is an illustration of an example implementation 300 that forms part of the semiconductor device 100 described herein. Specifically, example implementation 300 includes an example of an interconnect layer 104 (e.g., a back-end region or BEOL region) forming the semiconductor device 100. In some implementations, it is possible to combine Figures 2A-2C The combination is performed after one or more processes described. Figures 3A-3M The described semiconductor processing operations include one or more operations. In some implementations, the combined operation may be performed using one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor processing tools). Figures 3A-3M One or more operations in the semiconductor processing operations described.

[0064] like Figure 3A As shown, the interconnect layer 104 of the semiconductor device 100 is formed over the dielectric layer 108 of the device layer 102. An interconnect structure layer 130a (e.g., the bottom layer of the interconnect structure in interconnect layer 104) may be formed over and / or on the dielectric layer 108. To form layer 130a, an ESL 128 may be formed over and / or on the dielectric layer 108, such that the ESL 128 covers the gate structure 116 and the source / drain contact structure 122 of the integrated circuit device 110. An ILD layer 126 may be formed over and / or on the ESL 128.

[0065] ESL 128 and / or ILD layers 126 can be deposited using deposition tools employing PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. ESL 128 and / or ILD layers 126 can be deposited in one or more deposition operations. In some implementations, after depositing ESL 128 and / or ILD layers 126, a planarization operation (e.g., CMP operation) can be performed using planarization tools to planarize the ESL 128 and / or ILD layers 126.

[0066] like Figure 3BAs shown, the source / drain interconnect structure 134 and / or gate interconnect structure 136 in layer 130a (e.g., VO layer) of the interconnect structure can be formed in and / or through ILD layer 126 and ESL 128. To form the source / drain interconnect structure 134 and / or gate interconnect structure 136, recesses can be formed in and / or through ILD layer 126 and ESL 128. In some implementations, one or more recesses can be formed over one or more source / drain contact structures 122, such that one or more source / drain contact structures 122 are exposed through these recesses. In some implementations, one or more recesses can be formed over one or more gate structures 116, such that one or more gate structures 116 are exposed through these recesses.

[0067] In some implementations, the ILD layer 126 and / or ESL 128 of layer 130a are etched using a pattern in the photoresist layer to form a recess. In these implementations, the photoresist layer can be formed on the ILD layer 126 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The ILD layer 126 and / or ESL 128 can be etched based on the pattern using an etching tool to form the recess. In some implementations, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some implementations, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some implementations, hard mask layers are used as an alternative technique for pattern-based recess formation.

[0068] Source / drain interconnect structures 134 and / or gate interconnect structures 136 can be formed in the recessed layer 130a. The source / drain interconnect structures 134 and / or gate interconnect structures 136 can be deposited using deposition tools employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The source / drain interconnect structures 134 and / or gate interconnect structures 136 can be deposited in one or more deposition operations. In some implementations, a seed layer is first deposited, and the source / drain interconnect structures 134 and / or gate interconnect structures 136 are deposited on the seed layer. In some implementations, after depositing the source / drain interconnect structures 134 and / or gate interconnect structures 136, a planarization tool is used to perform a planarization operation (e.g., CMP operation) to planarize the source / drain interconnect structures 134 and / or gate interconnect structures 136.

[0069] like Figures 3C-3L As shown, layer 132a (e.g., M0 layer) of the metallization structure in interconnect layer 104 can be formed above layer 130a of the interconnect structure. Figure 3C As shown, the barrier layer 138 of layer 132a may be formed above and / or on the ILD layer 126, such that the barrier layer 138 covers the source / drain interconnect structure 134 and / or the gate interconnect structure 136. The metal layer 140 of layer 132a may be formed above and / or on the barrier layer 138.

[0070] The barrier layer 138 can be deposited using deposition tools employing CVD, PVD, ALD, and / or other suitable deposition techniques. In some implementations, after depositing the barrier layer 138, a planarization tool is used to perform a planarization operation (e.g., a CMP operation) to planarize the barrier layer 138.

[0071] The metal layer 140 can be deposited using deposition tools employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. In some implementations, after depositing the metal layer 140, a planarization operation (e.g., CMP) is performed using a planarization tool to planarize the metal layer 140. The metal layer 140 may have a deposited polycrystalline structure. In some implementations, the metal layer 140 is deposited to a thickness ranging from about 15 nanometers to about 45 nanometers. Figure 3C (This is represented as dimension D1). However, other values ​​and ranges are also within the scope of this disclosure.

[0072] like Figure 3DAs shown, a patterned stack 302 can be formed on and / or on the metal layer 140. The patterned stack 302 may include one or more patterned layers 304 to 308. The patterned layers 304 to 308 may include different materials to allow patterns to be formed in the patterned stack 302 and used to etch the metal layer 140 to define the metallization structure 144 in layer 132a. In some implementations, the patterned layer 304 may include a titanium nitride (TiN) layer, and the patterned layer 306 may include silicon nitride (Si). x N y The layer and / or patterned layer 308 may include silicon oxide (SiO2). x (layer). However, other combinations of materials used for patterning layers 304 to 308 are within the scope of this disclosure.

[0073] Patterned layers 304 to 308 of the patterned stack 302 can be deposited using deposition tools employing CVD, PVD, ALD, oxidation, and / or other suitable deposition techniques. In some implementations, after depositing patterned layers 304, 306, and / or 308, a planarization tool is used to perform a planarization operation (e.g., a CMP operation) to planarize the patterned layers 304, 306, and / or 308.

[0074] like Figure 3E As shown, patterned layers 304 to 308 of the patterned stack 302 can be used to form a recess 310 through the metal layer 140 and through the barrier layer 138 to define a metallization structure 144 in layer 132a of the metallization structure. In some implementations, the recess 310 is formed adjacent to and / or around the source / drain interconnect structure 134 to define a metallization structure 144 over and / or on the source / drain interconnect structure 134. In some implementations, the recess 310 is formed adjacent to and / or around the gate interconnect structure 136 to define a metallization structure 144 over and / or on the gate interconnect structure 136.

[0075] In some implementations, a pattern in the photoresist layer is used to etch patterned layers 304 to 308 of the patterned stack 302 to transfer the pattern to the patterned layers 304 to 308 of the patterned stack 302. In these implementations, a photoresist layer can be formed on the patterned stack 302 (e.g., on patterned layer 308) using a deposition tool (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch patterned layers 304 to 308 of the patterned stack 302 based on the pattern to transfer the pattern to the patterned stack 302.

[0076] The metal layer 140 and the barrier layer 138 can be etched using the pattern of the patterned layers 304 to 308 transferred to the patterned stack 302 to form the recess 310. In some implementations, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0077] like Figure 3E As shown, the recess 310 may have a tapered cross-sectional profile similar to the source / drain interconnect structure 134 and the gate interconnect structure 136 in layer 130a. Specifically, the top width of the recess 310 may be greater than the bottom width of the recess 310, such that the width of the recess 310 decreases from the top to the bottom of the recess 310.

[0078] Conversely, the metallization structure 144 has an inverted cross-sectional profile relative to the recess 310, the source / drain interconnect structure 134, and the gate interconnect structure 136. Specifically, the bottom width of the metallization structure 144 (in Figure 3E The dimension D2 (represented in the middle) can be greater than the top width of the metallized structure 144 (in the middle). Figure 3E The width of the metallized structure 144 is represented as dimension D2, such that the width increases from the top to the bottom of the metallized structure 144. In some implementations, the bottom width (dimension D2) of the metallized structure 144 is included in the range of about 8 nanometers to about 12 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some implementations, the top width (dimension D3) of the metallized structure 144 is included in the range of about 6 nanometers to about 10 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some implementations, the ratio of the bottom width to the top width (D2:D3) is included in the range of about 4:3 to about 6:5. However, other values ​​and ranges are also within the scope of this disclosure.

[0079] likeFigure 3F As shown, the sidewalls of the metallized structure 144 exposed through the recess 310 are oxidized to form a metal oxide liner 152 from the sidewalls of the metallized structure 144. In other words, the oxidation of the sidewalls of the metallized structure 144 transforms the sidewalls of the metallized structure 144 from a metallic material to a metal oxide material. To oxidize the sidewalls of the metallized structure 144, a semiconductor processing tool (e.g., an annealing tool, an etching tool, an oxidation tool, a deposition tool, a plasma tool) can be used to perform the oxidation operation in which the sidewalls of the metallized structure 144 are exposed to oxygen (O) through the recess 310. In some implementations, a barrier layer 138 resists oxidation during the oxidation operation.

[0080] In some implementations, the oxidation operation includes an annealing operation in which the semiconductor device 100 is exposed to a high ambient temperature in a processing chamber of a semiconductor processing tool, while an oxygen-based gas is supplied to the recess 310 to oxidize the sidewalls of 144 to form a metal oxide liner 152. The oxygen-based gas may include carbon monoxide (CO) gas, carbon dioxide (CO2) gas, oxygen (O2) gas, and / or ozone (O3) gas, etc. In some implementations, the semiconductor device 100 is exposed to an ambient temperature in the processing chamber ranging from about 400 degrees Celsius to about 800 degrees Celsius to facilitate the oxidation of the sidewalls of the metallized structure 144 using an oxygen-based gas. However, other values ​​and ranges are also within the scope of this disclosure.

[0081] In some implementations, the oxidation operation includes a plasma processing operation, wherein the semiconductor device 100 is exposed to plasma in a processing chamber of a semiconductor processing tool while an oxygen-based gas is supplied to the recess 310 to oxidize the sidewalls of the metallization structure 144 to form a metal oxide liner 152. The oxygen-based gas may include carbon monoxide (CO), carbon dioxide (CO2), oxygen (O2), and / or ozone (O3), etc. In some implementations, the plasma may include oxygen plasma, carbon dioxide plasma, and / or other oxygen-containing plasmas. In some implementations, the plasma may include other types of plasma.

[0082] Oxidation operations can allow the metal oxide liner 152 to be formed to a thickness greater than 0 nanometers and up to about 1 nanometer (in Figure 3F (represented as dimension D4). If the metal oxide liner 152 is formed to a thickness within this range, the metal oxide liner 152 can provide sufficient structural support for the metallized structure 144 to reduce and / or minimize the possibility of collapse of the metallized structure 144, while achieving a relatively low resistance of the metallized structure 144. However, other values ​​and ranges are also within the scope of this disclosure.

[0083] Because the sidewalls of the metallized structure 144 are oxidized to form a metal oxide liner 152, the recess 310 experiences a minimum reduction in lateral width, or no reduction at all. This allows for a greater amount of electrical insulation between the metallized structures 144 and a smaller amount of parasitic capacitance between them, compared to if the liner were deposited in the recess (e.g., by CVD or ALD).

[0084] like Figure 3G As shown, the recess 310 may be filled with a sacrificial layer 312. The sacrificial layer 312 may comprise a polymeric material and / or other types of materials that allow the sacrificial layer 312 to be subsequently removed while minimizing or eliminating the removal of material surrounding the sacrificial layer 312. For example, the sacrificial layer 312 may comprise a silicon-based polymeric material, such as an organosilane (e.g., a silicon-based hydrocarbon (C...). x H y However, other polymer materials are also within the scope of this disclosure.

[0085] In some implementations, a deposition tool is used to deposit material for the sacrificial layer 312 using CVD, PVD, ALD, and / or other suitable deposition techniques. In some implementations, the deposition tool is used to dispense material for the sacrificial layer 312 into the recess 310, such that the sacrificial layer 312 contacts the metal oxide liner 152 in the recess 310. In some implementations, the deposition tool is used to dispense material for the sacrificial layer 312 into the recess 310, and a curing agent is dispensed into the recess 310 to cure the material of the sacrificial layer 312. The sacrificial layer 312 can be formed such that it completely fills the recess 310 and extends over (and merges over) the recess 310.

[0086] like Figure 3H As shown, a portion of the sacrificial layer 312 (e.g., a sacrificial polymer layer) may be removed to form a sacrificial plug 314 in the recess 310. The sacrificial plug 314 (e.g., a sacrificial polymer plug) partially fills the recess 310, leaving space at the top of the recess 310 for depositing additional material into the recess 310.

[0087] In some implementations, an etching tool may be used to perform an etching operation (e.g., an etch-back operation) to remove this portion of the sacrificial layer 312 to form the sacrificial plug 314. In some implementations, the etching operation includes a wet etching operation, a dry etching operation, a plasma-based etching operation, and / or other suitable etching operations.

[0088] like Figure 3IAs shown, a support layer 150 can be formed in the recess 310. The support layer 150 may include a conformal layer that conforms to the contour of the remaining region in the recess 310. The support layer 150 may be formed on the top surface of the sacrificial plug 314 in the recess 310 and on the sidewalls of the recess 310 (which correspond to the exposed portion of the metal oxide liner 152). Thus, the support layer 150 may contact the top surface of the sacrificial plug 314 in the recess 310 and contact the exposed portion of the metal oxide liner 152 in the recess 310.

[0089] Without the sacrificial plug 314, the support layer 150 would otherwise be formed on the bottom of the recess 310. The sacrificial plug 314 allows the support layer 150 to be formed higher in the recess 310, so that the sacrificial plug 314 can be subsequently removed to form the air spacer 146.

[0090] In some implementations, a deposition tool can be used to deposit the support layer 150 using a conformal deposition technique such as ALD. In other implementations, a deposition tool can be used to deposit the support layer 150 using other deposition techniques such as CVD and / or PVD.

[0091] The support layer 150 may include a dielectric material. For example, the support layer 150 may include an oxide material, such as a silicon oxide-based material. Examples of such materials include silicon dioxide (SiO2), silicon carbide (SiOC), silicon oxynitride (SiON), and / or silicon carbonitride (SiOCN), etc.

[0092] like Figure 3I As further shown, the sacrificial plug 314 may have a dimension D5, which corresponds to the height or vertical (z-direction) thickness of the sacrificial plug 314. The height or vertical (z-direction) thickness of the sacrificial plug 314 may be less than the height from the recess 310 to the top of the metal layer 140 to provide space for a dielectric plug to be formed in the remaining area of ​​the recess 310. The greater the height or vertical (z-direction) thickness (dimension D5) of the sacrificial plug 314, the greater the space provided for the air spacer 146 of the isolation structure 142, which enables a lower dielectric constant of the isolation structure 142 to reduce parasitic capacitance.

[0093] However, the greater the height or vertical (z-direction) thickness (dimension D5) of the sacrificial plug 314, the higher the position of the support layer 150 in the recess 310 (in Figure 3I(This is indicated by dimension D6). The higher the support layer 150 is positioned within the recess 310, the wider the gap that the support layer 150 must traverse within the recess 310, because the taper of the recess 310 causes the width of the recess 310 to be greater at the top than at the bottom. The wider the gap that the support layer 150 must traverse within the recess 310, the higher the likelihood that the support layer 150 will collapse under the weight of the dielectric plug formed on the support layer 150 within the recess 310.

[0094] In some implementations, the ratio of the height or vertical (z-direction) thickness of the sacrificial plug 314 to the remaining vertical (z-direction) area in the recess 310 can be included in the range of about 2:1 to about 10:1 to provide sufficient area for the air spacer 146 (e.g., to enable a low dielectric constant) while minimizing the likelihood of collapse of the support layer 150. However, other values ​​and ranges are also within the scope of this disclosure.

[0095] like Figure 3J As shown, after the support layer 150 is formed, the sacrificial plug 314 can be removed from the recess 310. The removal of the sacrificial plug 314 results in the formation of an air spacer 146 of an isolation region 142 between the bottom of the recess 310 and the sacrificial layer 314.

[0096] To remove the sacrificial plug 314, a high-temperature operation (referred to as a burn-off operation) can be performed to remove the material from the sacrificial plug 314. For example, the sacrificial plug 314 can be heated to a temperature of about 400 degrees Celsius or higher to induce or trigger thermal cracking in the sacrificial plug 314. This destroys the sacrificial plug 314 and makes it possible to remove the material of the sacrificial plug 314 from the recess 310 through the support layer 150.

[0097] The material of the support layer 150 can have a higher density than the material of the sacrificial plug 314. This allows the sacrificial plug 314 to withstand high-temperature operation. In some implementations, holes can be formed in the support layer 150, and the holes allow the sacrificial plug 314 to be removed from the support layer 150. Specifically, the material of the sacrificial plug 314 can be removed through the holes in the support layer 150.

[0098] like Figure 3K As shown, a dielectric plug layer 318 is formed in the top portion of the recess 310 on the support layer 150. This seals the recess 310 at the top, which in turn forms air spacers 146 for the isolation regions 142 between the metallized structures 144. The support layer 150 prevents, minimizes, and / or otherwise reduces the amount of material of the dielectric plug layer 318 deposited further down into the recess 310 (e.g., at the bottom of the recess 310).

[0099] The dielectric plug layer 318 can be deposited using deposition tools employing PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. The dielectric plug layer 318 can be deposited in one or more deposition operations.

[0100] Because the sidewalls of the metallized structure 144 are oxidized to form the metal oxide liner 152, the recess 310 experiences a minimum reduction in lateral width, or no reduction at all. This provides a larger area within the recess 310 where material can be deposited for the dielectric plug layer 318, thereby enabling greater gap-filling performance than if the liner were deposited in the recess 310 (e.g., by CVD or ALD) (and therefore, a lower likelihood of voids forming in the dielectric plug layer 318).

[0101] like Figure 3L As shown, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the dielectric plug layer 318 to remove excess material from the dielectric plug layer 318. Patterned layers 304 to 308 of the patterned stack 302 can also be removed during the planarization operation. Removing excess material from the dielectric plug layer 318 results in the formation of a dielectric plug 148 over the air spacer 146 of the isolation region 142.

[0102] In some implementations, the remaining vertical (z-direction) region in the air spacer 146 (in Figure 3L The dimension (D5) can be included in the range of about 10 nanometers to about 20 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some implementations, the vertical (z-direction) thickness of the dielectric plug 148 (in Figure 3L The dimension (D6) can be included in the range of about 5 nanometers to about 20 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some implementations, the ratio of the remaining vertical (z-direction) region in the air spacer 146 to the vertical (z-direction) thickness of the dielectric plug 148 can be included in the range of about 2:1 to about 10:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0103] like Figure 3MAs shown, additional layers 130b to 130e and 132b to 132e of interconnect layer 104 can be formed over layer 132a. Copper interconnect formation techniques can be used to form layers 130b to 130e and 132b to 132e. For example, alternating layers of ILD layer 126 and ESL 128 can be deposited in interconnect layer 104 using one or more deposition tools for layers 130b to 130e and 132b to 132e. As another example, various operations can be performed using deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form interconnect structure 154 of layers 130b to 130e and / or form metallization structure 156 of layers 132b to 132e.

[0104] ILD layers 126 and ESL layers 128 can be arranged in the z-direction of semiconductor device 100. Each ILD layer 126 and each ESL layer 128 can be deposited using one or more deposition tools employing PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some implementations, after depositing ILD layers 126 and / or ESL layers 128, planarization tools can be used to planarize the ILD layers 126 and / or ESL layers 128.

[0105] In some implementations, interconnect layers 104 can be formed in multiple layers. For example, ILD layers 126 and ESL 128 of layers 130b (e.g., V1 layer) and / or layer 132b (e.g., M1 layer) can be formed (e.g., using one or more deposition tools and / or one or more planarization tools), recesses can be formed in and / or through ILD layers 126 and ESL 128 (e.g., using exposure tools, development tools, and / or etching tools), and interconnect structures 154 of layer 130b and / or metallization structures 156 of layer 132b can be formed in ILD layers 126 and ESL 128 (e.g., using one or more deposition tools and / or one or more planarization tools). This process can be referred to as a dual damascene process. Alternatively, a single damascene process can be performed to form the interconnect structures 154 of layer 130b and the metallization structures 156 of layer 132b.

[0106] Another ILD layer 126 and another ESL 128 of layer 130c (e.g., V2 layer) and / or layer 132c (e.g., M2 layer) can be formed (e.g., using one or more deposition tools and / or one or more planarization tools). Recesses can be formed in and / or through ILD layers 126 and ESL 128 (e.g., using exposure tools, development tools, and / or etching tools). Interconnection structure 154 of layer 130c and / or metallization structure 156 of layer 132c can be formed in ILD layers 126 and ESL 128 (e.g., using one or more deposition tools and / or one or more planarization tools).

[0107] The interconnect structure 154 and / or metallized structure 156 can be deposited using one or more deposition tools employing PVD, ALD, CVD, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some implementations, after depositing the interconnect structure 154 and / or metallized structure 156, a planarization tool can be used to planarize the interconnect structure 154 and / or metallized structure 156.

[0108] Additional layers of interconnect layer 104 can be formed in a similar manner.

[0109] As pointed out above, Figures 3A-3M Provided as an example. Other examples may be provided in relation to... Figures 3A-3M The descriptions are different.

[0110] Figure 4 This is a flowchart of an example process 400 associated with forming the semiconductor device described herein. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor processing tools) are used to perform the process. Figure 4 One or more process frames.

[0111] like Figure 4 As shown, process 400 may include forming a metal layer (140) of an interconnect layer of a semiconductor device over a device layer of a semiconductor device (box 410). For example, one or more semiconductor processing tools may be used to form a metal layer (e.g., metal layer 140) of an interconnect layer (e.g., interconnect layer 104) of a semiconductor device (e.g., semiconductor device 100) over a device layer (e.g., device layer 102), as described herein.

[0112] like Figure 4As further shown, process 400 may include etching a metal layer to define a plurality of conductive structures in an interconnect layer (block 420). For example, one or more semiconductor processing tools may be used to etch the metal layer to define a plurality of conductive structures in the interconnect layer (e.g., metallization structure 144), as described herein. In some implementations, at least one of the plurality of conductive structures is electrically coupled to an interconnect structure above the device layer (e.g., source / drain interconnect structure 134, gate interconnect structure 136).

[0113] like Figure 4 As further shown, process 400 may include performing an oxidation operation to oxidize the sidewalls of a plurality of conductive structures (block 430). For example, one or more semiconductor processing tools may be used to perform the oxidation operation to oxidize the sidewalls of the plurality of conductive structures, as described herein.

[0114] like Figure 4 As further shown, process 400 may include sealing a region between multiple conductive structures using a dielectric plug (box 440). For example, one or more semiconductor processing tools may be used to seal the region between multiple conductive structures using a dielectric plug (e.g., dielectric plug 148), as described herein.

[0115] Process 400 may include additional implementations, such as any single implementation or any combination of one or more other process descriptions described below and / or in combination with those described elsewhere herein.

[0116] In the first implementation, performing the oxidation operation includes: using oxygen-containing gas to perform an annealing operation to oxidize the sidewalls of the plurality of conductive structures.

[0117] In the second implementation, the oxidation operation, either alone or in combination with the first implementation, includes: using oxygen-containing gas to perform a plasma-based operation to oxidize the sidewalls of a plurality of conductive structures.

[0118] In a third implementation, either alone or in combination with one or more of the first and second implementations, process 400 includes: forming a bottom barrier layer (e.g., barrier layer 138) over a device layer, and forming a metal layer includes: forming a metal layer on the bottom barrier layer, wherein the bottom barrier layer resists oxidation during oxidation operations.

[0119] In the fourth embodiment, either alone or in combination with one or more of the first to third implementations, the metal layer comprises ruthenium (Ru), and oxygen (O) from the oxidation operation reacts with the sidewalls of the plurality of conductive structures to convert the sidewalls from ruthenium to ruthenium oxide (RuO). x ).

[0120] In the fifth implementation, sealing the region between the plurality of conductive structures, either alone or in combination with one or more of the first to fourth implementations, includes: forming a support layer (e.g., support layer 150) in the region between the plurality of conductive structures, and forming a dielectric plug on the support layer in the region between the plurality of conductive structures, wherein the support layer is formed on a portion of the sidewalls of the plurality of conductive structures after an oxidation operation.

[0121] In the sixth implementation, sealing the region between the plurality of conductive structures, either alone or in combination with one or more of the first to fifth implementations, includes forming a dielectric plug on the support layer.

[0122] although Figure 4 An example box of process 400 is shown, but in some implementations, process 400 includes... Figure 4 The boxes depicted in the diagram may be additional boxes, fewer boxes, different boxes, or boxes with different arrangements. Alternatively, two or more boxes of process 400 may be performed in parallel.

[0123] Figure 5 This is a flowchart of an example process 500 associated with the formation of a semiconductor device. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor processing tools) are used to perform the process. Figure 5 One or more process frames.

[0124] like Figure 5 As shown, process 500 may include forming a barrier layer (block 510) over a device layer of a semiconductor device. For example, a barrier layer (e.g., barrier layer 138) may be formed over a device layer (e.g., device layer 102) of a semiconductor device (e.g., semiconductor device 100) using one or more semiconductor processing tools, as described herein.

[0125] like Figure 5 As further shown, process 500 may include: forming a metal layer (box 520) of an interconnect layer (104) of a semiconductor device on the barrier layer. For example, a metal layer (e.g., metal layer 140) of an interconnect layer (e.g., interconnect layer 104) of a semiconductor device may be formed on the barrier layer using one or more semiconductor processing tools, as described herein.

[0126] like Figure 5As further shown, process 500 may include etching a metal layer and a barrier layer to define a plurality of conductive structures in an interconnect layer (block 530). For example, one or more semiconductor processing tools may be used to etch the metal layer and barrier layer to define a plurality of conductive structures (e.g., metallization structure 144) in the interconnect layer, as described herein. In some implementations, the conductive structures (e.g., metallization structure 144) in the plurality of conductive structures are electrically coupled to interconnect structures (e.g., source / drain interconnect structure 134, gate interconnect structure 136) above the device layer.

[0127] like Figure 5 As further shown, process 500 may include performing an oxidation operation on the sidewalls of the plurality of conductive structures, such that the sidewalls of the plurality of conductive structures are transformed from a metallic material to a metal oxide liner (box 540). For example, one or more semiconductor processing tools may be used to perform the oxidation operation on the sidewalls of the plurality of conductive structures, such that the sidewalls of the plurality of conductive structures are transformed from a metallic material to a metal oxide liner (e.g., metal oxide liner 152), as described herein.

[0128] like Figure 5 As further shown, process 500 may include sealing the region between metal oxide liner segments with a dielectric plug (box 550). For example, one or more semiconductor processing tools may be used to seal the region between metal oxide liner segments using a dielectric plug (e.g., dielectric plug 148), as described herein.

[0129] Process 500 may include additional implementations, such as any single implementation or any combination of one or more other process descriptions described below and / or in combination with those described elsewhere herein.

[0130] In the first implementation, performing the oxidation operation includes performing an annealing operation using at least one of carbon monoxide (CO) gas, carbon dioxide (CO2) gas, or oxygen (O2) gas.

[0131] In the second implementation, performing the oxidation operation, either alone or in combination with the first implementation, includes performing a plasma-based operation using at least one of carbon monoxide (CO), carbon dioxide (CO2), or oxygen (O2).

[0132] In a third implementation, sealing the region between metal oxide liners with a dielectric plug, either alone or in combination with one or more of the first and second implementations, comprises: partially filling the region between the metal oxide liners with a sacrificial polymer plug; forming a support layer on the metal oxide liners and on top of the sacrificial polymer plug in the unfilled region between the metal oxide liners, wherein the support layer is in contact with the metal oxide liners; and forming a dielectric plug on the support layer in the unfilled region between the metal oxide liners.

[0133] In the fourth implementation, the polymer plug is contacted with the metal oxide liner, either alone or in combination with one or more of the first to third implementations.

[0134] In the fifth implementation, partially filling the region between the metal oxide liner with a sacrificial polymer plug, either alone or in combination with one or more of the first to fourth implementations, includes: forming a polymer layer in the region between the metal oxide liner, wherein the polymer layer contacts the metal oxide liner, and etching the polymer layer to form the sacrificial polymer plug.

[0135] In the sixth implementation, either alone or in combination with one or more of the first to fifth implementations, process 500 includes: performing a burn-off operation to remove the sacrificial polymer plug after forming the dielectric plug, wherein after removing the sacrificial polymer plug, the support layer remains in contact with the metal oxide liner, and wherein the burn-off operation is a thermal operation performed to induce thermal cracking in the sacrificial polymer plug so that the material of the sacrificial polymer plug is removed through the support layer.

[0136] In the seventh implementation, the barrier layer resists oxidation during oxidation operations, either alone or in combination with one or more of the first to sixth implementations.

[0137] although Figure 5 An example box of process 500 is shown, but in some implementations, process 500 includes... Figure 5 The frames depicted in the diagram may be additional frames, fewer frames, different frames, or frames with different arrangements. Alternatively, two or more frames of process 500 may be executed in parallel.

[0138] In this manner, a layer of conductive material is formed above the bottom layer of the interconnect structure in the interconnect layer of the semiconductor device, and the layer of conductive material is etched to define the bottom layer of the metallization structure from the layer of conductive material, rather than forming the bottom layer of the metallization structure in the recess of the dielectric layer. To reduce the possibility of collapse of the freestanding metallization structure, the exposed sidewall surfaces of the freestanding metallization structure can be oxidized to form metal oxide sidewalls of the freestanding metallization structure. Self-aligned oxidation techniques can be used to form the metal oxide sidewalls, which are specifically designed for oxidizing the sidewalls of the freestanding metallization structure. The metal oxide sidewalls can be formed from a metal oxide material that increases the mechanical strength of the freestanding metallization structure (which enables the freestanding metallization structure to resist collapse) and has low resistance (which has minimal impact on the resistance of the freestanding metallization structure). In this way, the low resistance of the bottom layer of the realized metallization structure, alone or in combination with the low-k electrical isolation provided by the air gap, enables the realization of a low resistance capacitance (RC) time constant of the bottom layer of the metallization structure. In other examples, a low RC time constant enables faster signal propagation through the bottom layer of the metallized structure; and / or enables faster switching speeds for integrated circuit devices that realize semiconductor devices; and so on.

[0139] As described in more detail above, some implementations described herein provide a method. The method includes: forming a metal layer of an interconnect layer of a semiconductor device above a device layer of the semiconductor device. The method includes: etching the metal layer to define a plurality of conductive structures in the interconnect layer, wherein at least one of the plurality of conductive structures is electrically coupled to an interconnect structure above the device layer. The method includes: performing an oxidation operation to oxidize the sidewalls of the plurality of conductive structures. The method includes: sealing the region between the plurality of conductive structures with dielectric plugs.

[0140] As described in more detail above, some implementations described herein provide a method. The method includes: forming a barrier layer over a device layer of a semiconductor device. The method includes: forming a metal layer of an interconnect layer of the semiconductor device on the barrier layer. The method includes: etching the metal layer and the barrier layer to define a plurality of conductive structures of the interconnect layer, wherein conductive structures of the plurality of conductive structures are electrically coupled to interconnect structures over the device layer. The method includes: performing an oxidation operation on the sidewalls of the plurality of conductive structures, such that the sidewalls of the plurality of conductive structures are transformed from a metallic material to a metal oxide liner. The method includes: sealing the regions between the metal oxide liners with dielectric plugs.

[0141] As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a substrate layer. The semiconductor device includes at least one of the following: an integrated circuit device in the substrate layer, or an integrated circuit device on the substrate layer. The semiconductor device includes an interconnect structure in a dielectric layer above the substrate layer and electrically coupled to the integrated circuit device. The semiconductor device includes a conductive structure above the dielectric layer and electrically coupled to the interconnect structure, wherein the body of the conductive structure comprises a metallic material, and wherein the sidewalls of the conductive structure comprise a metal oxide material. The semiconductor device includes an isolation region along at least one sidewall of the conductive structure. The isolation region includes: an air spacer along a first portion of the sidewall; and a dielectric plug along a second portion of the sidewall above the first portion.

[0142] The terms “about” and “substantially” can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and not intended to be limiting. It should be understood that, according to this disclosure, the terms “about” and “substantially” can refer to a percentage of the value of a given quantity.

[0143] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0144] Example

[0145] Example 1. A method for forming a semiconductor device, comprising: forming a metal layer of an interconnect layer of the semiconductor device over a device layer of the semiconductor device; etching the metal layer to define a plurality of conductive structures in the interconnect layer, wherein at least one of the plurality of conductive structures is electrically coupled to an interconnect structure over the device layer; performing an oxidation operation to oxidize the sidewalls of the plurality of conductive structures; and sealing a region between the plurality of conductive structures with a dielectric plug.

[0146] Example 2. The method according to Example 1, wherein performing the oxidation operation includes: using oxygen-containing gas to perform an annealing operation to oxidize the sidewalls of the plurality of conductive structures.

[0147] Example 3. The method according to Example 1, wherein performing the oxidation operation includes: using oxygen-containing gas to perform a plasma-based operation to oxidize the sidewalls of the plurality of conductive structures.

[0148] Example 4. The method according to Example 1 further includes: forming a bottom barrier layer over the device layer, wherein forming the metal layer includes: forming the metal layer on the bottom barrier layer, and wherein the bottom barrier layer resists oxidation during the oxidation operation.

[0149] Example 5. The method according to Example 1, wherein the metal layer comprises ruthenium (Ru); and wherein oxygen (O) from an oxidation operation reacts with the sidewalls of the plurality of conductive structures to convert the sidewalls from ruthenium to ruthenium oxide (RuO). x ).

[0150] Example 6. The method according to Example 1, wherein sealing the region between the plurality of conductive structures comprises: forming a support layer in the region between the plurality of conductive structures; and forming the dielectric plug in the region between the plurality of conductive structures on the support layer, wherein the support layer is formed on a portion of the sidewall of the plurality of conductive structures after the oxidation operation.

[0151] Example 7. The method according to Example 6, wherein sealing the region between the plurality of conductive structures comprises: forming the dielectric plug on the support layer.

[0152] Example 8. A method for forming a semiconductor device, comprising: forming a barrier layer over a device layer of the semiconductor device; forming a metal layer of an interconnect layer of the semiconductor device on the barrier layer; etching the metal layer and the barrier layer to define a plurality of conductive structures in the interconnect layer, wherein a conductive structure of the plurality of conductive structures is electrically coupled to an interconnect structure over the device layer; performing an oxidation operation on the sidewalls of the plurality of conductive structures such that the sidewalls of the plurality of conductive structures are transformed from a metallic material to a metal oxide liner; and sealing a region between the metal oxide liners with a dielectric plug.

[0153] Example 9. The method according to Example 8, wherein performing the oxidation operation comprises: performing the annealing operation using at least one of the following gases: carbon monoxide (CO) gas, carbon dioxide (CO2) gas, or oxygen (O2) gas.

[0154] Example 10. The method according to Example 8, wherein performing the oxidation operation comprises: using at least one of the gases to perform a plasma-based operation: carbon monoxide (CO) gas, carbon dioxide (CO2) gas, or oxygen (O2) gas.

[0155] Example 11. The method according to Example 8, wherein sealing the region between the metal oxide liner with the dielectric plug comprises: partially filling the region between the metal oxide liner with a sacrificial polymer plug; forming a support layer on the metal oxide liner and on top of the sacrificial polymer plug in the unfilled region between the metal oxide liner, wherein the support layer is in contact with the metal oxide liner; and forming the dielectric plug on the support layer in the unfilled region between the metal oxide liner.

[0156] Example 12. The method according to Example 11, wherein the sacrificial polymer plug is in contact with the metal oxide liner.

[0157] Example 13. The method according to Example 11, wherein partially filling the region between the metal oxide liner with the sacrificial polymer plug comprises: forming a polymer layer in the region between the metal oxide liner, wherein the polymer layer is in contact with the metal oxide liner; and etching the polymer layer to form the sacrificial polymer plug.

[0158] Example 14. The method according to Example 11 further includes: performing a burn-off operation to remove the sacrificial polymer plug after forming the dielectric plug, wherein after removing the sacrificial polymer plug, the support layer remains in contact with the metal oxide liner, and wherein the burn-off operation is a thermal operation performed to induce thermal cracking in the sacrificial polymer plug so that the material of the sacrificial polymer plug is removed through the support layer.

[0159] Example 15. The method according to Example 8, wherein the barrier layer resists oxidation during the oxidation operation.

[0160] Example 16. A semiconductor device comprising: a substrate layer; at least one of an integrated circuit device in the substrate layer or an integrated circuit device on the substrate layer; an interconnect structure in a dielectric layer above the substrate layer and electrically coupled to the integrated circuit device; a conductive structure above the dielectric layer and electrically coupled to the interconnect structure, wherein the body of the conductive structure comprises a metallic material, and wherein the sidewalls of the conductive structure comprise a metal oxide material; and an isolation region along at least one sidewall of the conductive structure, wherein the isolation region comprises: an air spacer along a first portion of the sidewall; and a dielectric plug along a second portion of the sidewall above the first portion.

[0161] Example 17. The semiconductor device according to Example 16, wherein the first lateral width of the top of the conductive structure is smaller than the second lateral width of the bottom of the conductive structure.

[0162] Example 18. A semiconductor device according to Example 16, wherein the metal oxide material is an oxide of the metal material of the body of the conductive structure.

[0163] Example 19. The semiconductor device according to Example 16, wherein the metal material has a polycrystalline structure; and wherein the metal oxide material has a single-crystal structure.

[0164] Example 20. The semiconductor device according to Example 16, wherein the metal material comprises ruthenium (Ru); and wherein the metal oxide material comprises ruthenium dioxide (RuO2).

Claims

1. A method for forming a semiconductor device, comprising: A metal layer of the interconnect layer of the semiconductor device is formed above the device layer of the semiconductor device; The metal layer is etched to define a plurality of conductive structures in the interconnect layer. Wherein, at least one of the plurality of conductive structures is electrically coupled to an interconnect structure above the device layer; Perform an oxidation operation to oxidize the sidewalls of the plurality of conductive structures; and The area between the plurality of conductive structures is sealed using dielectric plugs.

2. The method according to claim 1, wherein, Performing the oxidation operation includes: An annealing operation is performed using oxygen-containing gas to oxidize the sidewalls of the plurality of conductive structures.

3. The method according to claim 1, wherein, Performing the oxidation operation includes: Oxygen-containing gas is used to perform plasma-based operations to oxidize the sidewalls of the plurality of conductive structures.

4. The method according to claim 1, further comprising: A bottom barrier layer is formed above the device layer. The formation of the metal layer includes: The metal layer is formed on the bottom barrier layer, and The bottom barrier layer resists oxidation during the oxidation operation.

5. The method according to claim 1, wherein, The metal layer comprises ruthenium (Ru); and In this process, oxygen (O) from the oxidation operation reacts with the sidewalls of the plurality of conductive structures to convert the sidewalls from ruthenium to ruthenium oxide (RuO). x ).

6. The method according to claim 1, wherein, Sealing the region between the plurality of conductive structures includes: A support layer is formed in the region between the plurality of conductive structures; and The dielectric plug is formed on the support layer in the region between the plurality of conductive structures. The support layer is formed on a portion of the sidewall of the plurality of conductive structures after the oxidation operation.

7. The method according to claim 6, wherein, Sealing the region between the plurality of conductive structures includes: The dielectric plug is formed on the support layer.

8. A method for forming a semiconductor device, comprising: A barrier layer is formed above the device layer of a semiconductor device; A metal layer on which the interconnect layer of the semiconductor device is formed in the barrier layer; The metal layer and the barrier layer are etched to define a plurality of conductive structures in the interconnect layer. Among them, the conductive structures in the plurality of conductive structures are electrically coupled to the interconnect structure above the device layer; An oxidation operation is performed on the sidewalls of the plurality of conductive structures, such that the sidewalls of the plurality of conductive structures are transformed from a metallic material to a metal oxide liner; and The area between the metal oxide linings is sealed with a dielectric plug.

9. The method according to claim 8, wherein, Performing the oxidation operation includes: The annealing operation is performed using at least one of the following gases: Carbon monoxide (CO) gas, Carbon dioxide (CO2) gas, or Oxygen (O2) gas.

10. A semiconductor device, comprising: Substrate layer; At least one of the integrated circuit devices in the substrate or the integrated circuit devices on the substrate; An interconnect structure is located in a dielectric layer above the substrate and is electrically coupled to the integrated circuit device; A conductive structure is located above the dielectric layer and electrically coupled to the interconnect structure. The conductive structure mainly comprises a metallic material, and Wherein, the sidewalls of the conductive structure comprise a metal oxide material; and An isolation region, along at least one sidewall of the conductive structure, The isolation area includes: Air spacer, along the first portion of the sidewall; and A dielectric plug, along the second portion of the sidewall above the first portion.

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