Package substrate and manufacturing method thereof, semiconductor device and electronic equipment

Abstract

The embodiment of the invention relates to the technical field of semiconductors, in particular to a packaging substrate and a manufacturing method thereof, a semiconductor device and electronic equipment. The invention aims to solve the problem that the reliability of the packaging substrate is reduced due to the fact that the interconnection density and strength of the packaging substrate cannot be ensured at the same time. The packaging substrate comprises a substrate body, a first glass core plate and a first wiring layer, a plurality of first conductive through holes are formed in the substrate body at intervals, a plurality of second conductive through holes are formed in the first glass core plate at intervals, and the radial size of the second conductive through holes is smaller than that of the first conductive through holes. Under the same area, the number of the second conductive through holes arranged in the first glass core plate is greater than the number of the first conductive through holes arranged in the substrate, and the interconnection density of the packaging substrate is increased. The strength of the substrate is greater than that of the first glass core plate, so that the strength of the packaging substrate is increased, the interconnection density and strength of the packaging substrate are ensured, and the reliability of the packaging substrate is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a packaging substrate and its manufacturing method, semiconductor devices, and electronic devices. Background Technology

[0002] In chip packaging technology, when organic materials are used as the core board of the packaging substrate, the interconnect density of the packaging substrate is low, resulting in low signal transmission efficiency. Using glass materials as the core board can increase the interconnect density of the packaging substrate. However, when glass materials are used as the core board of the packaging substrate, the glass core board is prone to cracking and breakage during processing and use, and the strength of the packaging substrate is low. It is impossible to simultaneously guarantee the interconnect density and strength of the packaging substrate, resulting in reduced reliability. Summary of the Invention

[0003] This application provides a packaging substrate and its manufacturing method, a semiconductor device, and an electronic device, which can ensure the interconnection density and strength of the packaging substrate and improve the reliability of the packaging substrate.

[0004] In a first aspect, embodiments of this application provide a packaging substrate, including a substrate, a first glass core plate, and a first wiring layer. A plurality of first conductive vias are spaced apart within the substrate. A first receiving hole is provided through the substrate, and the first glass core plate is disposed within the first receiving hole. A plurality of second conductive vias are spaced apart within the first glass core plate, the radial dimension of each second conductive via being smaller than the radial dimension of the first conductive via. The first wiring layer is disposed on the same side of the first glass core plate and the substrate. The first conductive vias are connected to the first wiring layer, and the second conductive vias are also connected to the first wiring layer.

[0005] With the above configuration, the radial dimension of the second conductive via is smaller than that of the first conductive via. For the same area, the number of second conductive vias within the first glass core is greater than the number of first conductive vias within the substrate, increasing the interconnect density of the encapsulation substrate. Simultaneously, the first glass core is positioned within the first receiving hole of the substrate, and the strength of the substrate is greater than that of the first glass core, thus increasing the strength of the encapsulation substrate and making it less prone to cracking and breakage. This ensures both the interconnect density and strength of the encapsulation substrate, improving its reliability.

[0006] In some embodiments that may include the above embodiments, the dielectric material of the first wiring layer located on the first glass core is different from the dielectric material of the first wiring layer located on the substrate.

[0007] When different dielectric materials are used for the first wiring layer, the line width and spacing of the first wiring layer will also be different, resulting in different interconnection densities. A suitable dielectric material for the first wiring layer can be selected based on the interconnection density of the first glass core board and the substrate.

[0008] In some embodiments that may include the above embodiments, the linewidth of the first wiring layer located on the first glass core is d1, and the linewidth of the first wiring layer located on the substrate is d2, where d1 is less than d2.

[0009] The linewidth d1 of the first wiring layer on the first glass core is smaller than the linewidth d2 of the first wiring layer on the substrate. The wiring density of the first wiring layer on the first glass core is greater than the wiring density of the first wiring layer on the substrate. The interconnection density of the first wiring layer on the first glass core is greater than the interconnection density of the first wiring layer on the substrate. This allows it to be adapted to the interconnection densities of the first glass core and the substrate, respectively, thus ensuring the signal transmission efficiency from the first wiring layer to the first glass core and from the first wiring layer to the substrate.

[0010] In some embodiments that may include the above embodiments, the line spacing of the first wiring layer on the first glass core is s1, and the line spacing of the first wiring layer on the substrate is s2, where s1 is less than s2.

[0011] The line spacing s1 of the first wiring layer on the first glass core board is smaller than the line spacing s2 of the first wiring layer on the substrate. The wiring density of the first wiring layer on the first glass core board is greater than the wiring density of the first wiring layer on the substrate. The interconnection density of the first wiring layer on the first glass core board is greater than the interconnection density of the first wiring layer on the substrate. This can be adapted to the interconnection density of the first glass core board and the substrate respectively, ensuring the signal transmission efficiency from the first wiring layer to the first glass core board and from the first wiring layer to the substrate.

[0012] In some embodiments that may include the above embodiments, the packaging substrate further includes a second wiring layer, which is disposed on the other side of the first glass core and the substrate; a first conductive via is connected to the second wiring layer; a first protrusion is provided on the side of the first glass core away from the first wiring layer, and the second conductive via is connected to the second wiring layer through the first protrusion.

[0013] The first conductive via is connected to the second wiring layer, enabling the connection between the first conductive via and the circuit board. The second conductive via is connected to the second wiring layer through the first bump, enabling the connection between the second conductive via and the circuit board, thereby achieving vertical signal transmission between the chip and the circuit board.

[0014] In some embodiments that may include the above embodiments, the thickness of the first wiring layer on the first glass core is less than the thickness of the first wiring layer on the substrate.

[0015] The thinner thickness of the first wiring layer on the first glass core substrate results in a thinner packaging substrate and a smaller overall volume. The first wiring layer also makes the surface of the packaging substrate smoother, which is beneficial for precise chip wiring and packaging.

[0016] In some embodiments that may include the above embodiments, the dielectric material of the first wiring layer located on the first glass core is the same as the dielectric material of the first wiring layer located on the substrate.

[0017] The dielectric material of the first wiring layer located on the first glass core is the same as the dielectric material of the first wiring layer located on the substrate, so that the interconnection density of the two first wiring layers is the same, which facilitates signal transmission between the two first wiring layers.

[0018] In some embodiments that may include the above embodiments, the linewidth of the first wiring layer on the first glass core is d3, the linewidth of the first wiring layer on the substrate is d4, d3 equals d4, and / or; the line spacing of the first wiring layer on the first glass core is s3, the line spacing of the first wiring layer on the substrate is s4, s3 equals s4.

[0019] The line width d3 of the first wiring layer on the first glass core is equal to the line width d4 of the first wiring layer on the substrate, and / or the line spacing of the first wiring layer on the first glass core is s3, and the line spacing of the first wiring layer on the substrate is s4. Since s3 equals s4, the wiring density of the first wiring layer on the first glass core is equal to the wiring density of the first wiring layer on the substrate, thus ensuring the lateral signal transmission efficiency between the two first wiring layers.

[0020] In some embodiments that may include the above embodiments, the packaging substrate further includes a third wiring layer, which is disposed on the other side of the first glass core and the substrate; the first conductive via and the second conductive via are connected to the third wiring layer.

[0021] The first and second conductive vias are connected to the third wiring layer, enabling vertical signal transmission on the packaging substrate. In some embodiments that may include the above examples, the first wiring layer located on the first glass core and the first wiring layer located on the substrate are fabricated using a back-end process.

[0022] The first wiring layer, fabricated using back-end processes, has a smaller minimum linewidth and minimum line spacing, allowing for a higher interconnect density and providing more traces for the packaging substrate.

[0023] Secondly, embodiments of this application also provide a semiconductor device, including a chip and a packaging substrate as described in any of the above embodiments, wherein the chip is disposed on a first wiring layer of the packaging substrate.

[0024] The semiconductor device provided in this application includes the packaging substrate in any of the above embodiments. Therefore, both can solve the same technical problem and achieve the same technical effect.

[0025] Thirdly, embodiments of this application also provide an electronic device, including a circuit board and a semiconductor device as described in any of the above embodiments, wherein the semiconductor device is disposed on the circuit board.

[0026] The electronic devices provided in this application include the semiconductor devices in any of the above embodiments, so both can solve the same technical problems and achieve the same technical effects.

[0027] Fourthly, embodiments of this application also provide a method for manufacturing a packaging substrate, comprising: forming a first receiving hole through the substrate, wherein a plurality of first conductive vias are spaced apart in the substrate; placing a first glass core plate in the first receiving hole, wherein a plurality of second conductive vias are spaced apart in the first glass core plate, wherein the radial dimension of the second conductive vias is smaller than the radial dimension of the first conductive vias, and a first wiring layer is provided on the same side of the first glass core plate and the substrate.

[0028] The packaging substrate fabrication method provided in this application produces a packaging substrate in which the radial dimension of the second conductive via is smaller than that of the first conductive via. For the same area, the number of second conductive vias on the first glass core plate is greater than the number of first conductive vias on the substrate, increasing the interconnect density of the packaging substrate. Simultaneously, the first glass core plate is disposed within the first receiving hole of the substrate, and the strength of the substrate is greater than that of the first glass core plate, increasing the strength of the packaging substrate and making it less prone to cracking and breakage. This ensures both the interconnect density and strength of the packaging substrate, improving its reliability. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0030] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0031] Figure 3 Schematic diagram of the packaging substrate provided in the embodiments of this application Figure 1 ;

[0032] Figure 4 Schematic diagram of the packaging substrate provided in the embodiments of this application Figure 2 ;

[0033] Figure 5 Schematic diagram of the packaging substrate provided in the embodiments of this application Figure 3 ;

[0034] Figure 6 Schematic diagram of the packaging substrate provided in the embodiments of this application Figure 4 ;

[0035] Figure 7 Schematic diagram of the packaging substrate provided in the embodiments of this application Figure 5 ;

[0036] Figure 8 Schematic diagram of the packaging substrate provided in the embodiments of this application Figure 6 ;

[0037] Figure 9 Schematic diagram of the packaging substrate provided in the embodiments of this application Figure 7 ;

[0038] Figure 10 Schematic diagram of the packaging substrate provided in the embodiments of this application Figure 8 ;

[0039] Figure 11 A flowchart illustrating the packaging substrate fabrication method provided in this application embodiment;

[0040] Figure 12 A flowchart illustrating the packaging substrate fabrication method provided in the embodiments of this application. Figure 1 ;

[0041] Figure 13 A flowchart illustrating the packaging substrate fabrication method provided in the embodiments of this application. Figure 2 ;

[0042] Figure 14 A schematic diagram of the process for filling the gap between the first glass core and the substrate with thermosetting material, provided in an embodiment of this application;

[0043] Figure 15 A flowchart illustrating the packaging substrate fabrication method provided in this application embodiment. Figure 3 ;

[0044] Figure 16 A flowchart illustrating the packaging substrate fabrication method provided in the embodiments of this application. Figure 4 ;

[0045] Figure 17 This application provides a schematic diagram of the chip mounting process on a packaging substrate. Figure 1 ;

[0046] Figure 18 This application provides a schematic diagram of the chip mounting process on a packaging substrate. Figure 2 ;

[0047] Figure 19A flowchart illustrating the packaging substrate fabrication method provided in the embodiments of this application. Figure 5 .

[0048] Explanation of reference numerals in the attached figures:

[0049] 10: Electronic device; 11: Circuit board; 12: Power supply; 20: Semiconductor device; 21: Chip; 211: First chip; 212: Second chip; 213: Third chip; 30: Packaging substrate; 31: Substrate; 311: First conductive via; 312: First accommodating hole; 313: Second accommodating hole; 32: First glass core board; 321: Second conductive via; 322: First bump; 33: First wiring layer; 34: Second wiring layer; 35: Third wiring layer; 36: Solder ball; 37: Second glass core board; 371: Third conductive via; 38: Thermosetting material. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0051] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0052] Furthermore, in the embodiments of this application, directional terms such as "up," "down," "left," "right," "horizontal," and "vertical" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0053] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, an electrical connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0054] Please refer to Figure 1This application provides an electronic device 10. This application does not limit the scope of the electronic device 10; for example, the electronic device 10 may include a mobile phone, computer, tablet computer, smart bracelet, smartwatch, etc. In this application embodiment, the electronic device 10 includes a circuit board 11 and a semiconductor device 20. The semiconductor device 20 is disposed on the circuit board 11 and electrically connected to the circuit board 11. For example, the semiconductor device 20 can be electrically connected to the circuit board 11 (Printed Circuit Board, PCB) through a ball grid array (BGA) or multiple arrays of copper pillar bumps (CPBs), thereby enabling signal transmission between the semiconductor device 20 and other devices or device stacks on the circuit board 11.

[0055] It is understood that the number of semiconductor devices 20 on the circuit board 11 can be one or more, and the semiconductor devices 20 may include a central processing unit, memory, etc. The electronic device 10 also includes a power supply 12, which can be connected to the circuit board 11 to supply power to the devices on the circuit board 11.

[0056] Please refer to Figure 2 This application also provides a semiconductor device 20, including a chip 21 and a packaging substrate 30. The chip 21 is disposed on the first wiring layer 33 of the packaging substrate 30 and connected to the packaging substrate 30. This application does not limit the chip 21. For example, the chip 21 may include a processing chip with data processing capabilities, such as a central processing unit (CPU), a graphics processing unit (GPU), a memory chip, or an input / output (I / O) chip. The chip 21 also includes a singlet chip 21, or it may include a stacked structure of chip 21 (i.e., multiple singlet chips 21 stacked). For example, a die-on-interposer unit (DOI unit) can be used as the chip 21, or a fan-out unit (FO unit) can be used.

[0057] This application does not limit the semiconductor device 20. It is understood that the function of the semiconductor device 20 corresponds to that of the chip 21. For example, in an embodiment where the chip 21 includes a central processing chip, the semiconductor device 20 may include a central processing unit, which can transmit control signals to other devices, and the control devices operate according to the control signals; in an embodiment where the chip 21 includes a memory chip, the semiconductor device 20 may include a memory, which can store data and programs to assist program operation; in an embodiment where the chip 21 includes a graphics processing chip, the semiconductor device 20 may include a graphics processor, which can execute image processing algorithms.

[0058] Please refer to Figure 3 In some implementations, chip 21 includes a first chip 211 and a second chip 212, the first chip 211 and the second chip 212 being aligned with the packaging substrate 30 (e.g., ...). Figure 2 The chips are arranged in a direction parallel to the surface of the circuit board 11 (as shown). The packaging substrate 30 is connected to the first chip 211 and the second chip 212. The first chip 211 and the second chip 212 can be connected to the circuit board 11 through the packaging substrate 30. Figure 1 The connection of other lines on the circuit board 11 (as shown) can also be achieved through the packaging substrate 30 to connect the first chip 211 and the second chip 212. In other implementations, the number of chips 21 can be more than two. The packaging substrate 30 can realize the connection of multiple chips 21 to the lines on the circuit board 11, and can also realize the connection between multiple chips 21.

[0059] It is understood that the first chip 211 and the second chip 212 can be the same type of chip 21 or different types of chip 21. When the first chip 211 and the second chip 212 use different types of chip 21, the semiconductor device 20 has multiple functions. For example, when the first chip 211 is a CPU and the second chip 212 is a memory chip, the semiconductor device 20 can simultaneously have the functions of a central processing unit and a memory.

[0060] The first chip 211 and the second chip 212 are arranged in a direction parallel to the surface of the packaging substrate 30, which can realize the connection between the first chip 211 and the second chip 212 as well as the connection between the first chip 211 and the second chip 212 and other lines on the circuit board 11.

[0061] Please refer to Figure 4This application provides a packaging substrate 30, including a substrate 31 and a first glass core plate 32. This application does not limit the materials of the first glass core plate 32 and the substrate 31. For example, the material of the first glass core plate 32 may include quartz glass, high-silica glass, etc.; the material of the substrate 31 may include glass fiber, resin, ceramic, etc. A plurality of first conductive vias 311 are spaced apart within the substrate 31, and a first receiving hole 312 is provided through the substrate 31. The first glass core plate 32 is disposed within the first receiving hole 312, and a plurality of second conductive vias 321 are spaced apart within the first glass core plate 32. The radial dimension of the second conductive vias 321 is smaller than the radial dimension of the first conductive vias 311.

[0062] It is understood that the first conductive via 311 and the second conductive via 321 may include metal sidewalls disposed on the walls of the first conductive via 311 and the second conductive via 321, with one end of the metal sidewall connected to the chip 21. In embodiments where the first conductive via 311 and the second conductive via 321 are cylindrical, the radial dimension of the first conductive via 311 and the second conductive via 321 is the diameter. The diameter of the second conductive via 321 includes 20-100 μm, and the aspect ratio includes 4:1-10:1. The aspect ratio refers to the ratio of the length of the second conductive via 321 (i.e., the thickness of the first glass core plate 32) to the diameter of the second conductive via 321. The larger the aspect ratio, the longer the length of the second conductive via 321, the thicker the first glass core plate 32, the greater the strength of the first glass core plate 32, and the less prone the first glass core plate 32 is to cracking.

[0063] The packaging substrate 30 also includes a first wiring layer 33, which is disposed on the same side of the first glass core plate 32 and the substrate 31. A first conductive via 311 is connected to the first wiring layer 33, and a second conductive via 321 is connected to the first wiring layer 33. It can be understood that the chip 21 is connected to the first conductive via 311 and the second conductive via 321 through the first wiring layer 33, thus realizing the chip 21 (… Figure 3 Signal transmission from the first wiring layer 33 to the packaging substrate 30 (as shown). It is understood that the first wiring layer 33 may include one or more layers; for example, the number of layers in the first wiring layer 33 may include one, two, three, etc. The more layers the first wiring layer 33 has, the larger the wiring area, enabling the transmission of more lines, improving wiring efficiency, and allowing different lines to be separated. In the event of a failure in one layer, other layers can still function normally, effectively reducing the failure rate of the first wiring layer 33.

[0064] The radial dimension of the second conductive via 321 is smaller than that of the first conductive via 311. For the same area, the number of second conductive vias 321 on the first glass core plate 32 is greater than the number of first conductive vias 311 in the substrate 31, increasing the interconnect density of the encapsulation substrate 30. Simultaneously, the first glass core plate 32 is disposed within the first receiving hole 312 of the substrate 31. Since the strength of the substrate 31 is greater than that of the first glass core plate 32, the strength of the encapsulation substrate 30 is increased, making it less prone to cracking and breakage. This ensures both the interconnect density and strength of the encapsulation substrate 30, improving its reliability.

[0065] Continue to refer to Figure 4 In some implementations, the dielectric material of the first wiring layer 33 located on the first glass core plate 32 is different from the dielectric material of the first wiring layer 33 located on the substrate 31. It is understood that the first wiring layer 33 located on the first glass core plate 32 and the first wiring layer 33 located on the substrate 31 are different types of first wiring layers 33.

[0066] In some implementations, the dielectric material of the first wiring layer 33 located on the first glass core plate 32 includes at least one of PI (polyimide), benzocyclobutene (BCB), polybenzoxazole (PBO), SiO2, and Si3N4, while the dielectric material of the first wiring layer 33 located on the substrate 31 includes resin. It is understood that the interconnect material of the first wiring layer 33 can be Cu. When different dielectric materials are used for the first wiring layer 33, the linewidth and line spacing of the first wiring layer 33 are different, and the interconnection density of the first wiring layer 33 is different. A suitable dielectric material for the first wiring layer 33 can be selected according to the interconnection density of the first glass core plate 32 and the substrate 31.

[0067] Please refer to Figure 5 In some implementations, the linewidth of the first wiring layer 33 located on the first glass core board 32 is d1, and the linewidth of the first wiring layer 33 located on the substrate 31 is d2, where d1 is less than d2. It can be understood that the linewidth refers to the width of the traces in the first wiring layer 33. The smaller the linewidth, the more traces can be placed within the first wiring layer 33 of the same thickness, and the greater the interconnection density of the first wiring layer 33.

[0068] The linewidth d1 of the first wiring layer 33 located on the first glass core plate 32 is smaller than the linewidth d2 of the first wiring layer 33 located on the substrate 31. The wiring density of the first wiring layer 33 located on the first glass core plate 32 is greater than the wiring density of the first wiring layer 33 located on the substrate 31. The interconnection density of the first wiring layer 33 located on the first glass core plate 32 is greater than the interconnection density of the first wiring layer 33 located on the substrate 31. This can be adapted to the interconnection densities of the first glass core plate 32 and the substrate 31 respectively, ensuring the signal transmission efficiency from the first wiring layer 33 to the first glass core plate 32 and from the first wiring layer 33 to the substrate 31.

[0069] In some implementations, 1μm≤d1≤5μm, 5μm≤d2≤25μm. The first wiring layer 33 on the first glass core plate 32 has a smaller linewidth, resulting in a higher interconnect density. The first wiring layer 33 on the first glass core plate 32 can connect to the signal pins of the chip 21, ensuring signal transmission efficiency of the packaging substrate 30 while reducing its thickness. The first wiring layer 33 on the substrate 31 has a larger linewidth, allowing connection to the power supply pins of the chip 21, ensuring power supply while reducing the fabrication difficulty of the first wiring layer 33.

[0070] Continue to refer to Figure 5 In some implementations, the line spacing of the first wiring layer 33 located on the first glass core board 32 is s1, and the line spacing of the first wiring layer 33 located on the substrate 31 is s2, where s1 is less than s2. It can be understood that the line spacing refers to the distance between adjacent traces in the first wiring layer 33. The smaller the line spacing, the more traces can be set in the same area of ​​the first wiring layer 33, and the greater the interconnection density of the first wiring layer 33.

[0071] The line spacing s1 of the first wiring layer 33 located on the first glass core plate 32 is smaller than the line spacing s2 of the first wiring layer 33 located on the substrate 31. The wiring density of the first wiring layer 33 located on the first glass core plate 32 is greater than the wiring density of the first wiring layer 33 located on the substrate 31. The interconnection density of the first wiring layer 33 located on the first glass core plate 32 is greater than the interconnection density of the first wiring layer 33 located on the substrate 31. This can be adapted to the interconnection density of the first glass core plate 32 and the substrate 31 respectively, ensuring the signal transmission efficiency from the first wiring layer 33 to the first glass core plate 32 and from the first wiring layer 33 to the substrate 31.

[0072] In some implementations, 1μm≤s1≤5μm, 5μm≤s2≤25μm. The first wiring layer 33 on the first glass core plate 32 has a small line spacing, resulting in a high interconnection density. The first wiring layer 33 on the first glass core plate 32 can be connected to the signal pins of the chip 21, ensuring signal transmission efficiency of the packaging substrate 30 while reducing the thickness of the packaging substrate 30. The first wiring layer 33 on the substrate 31 has a larger line spacing, allowing connection to the power supply pins of the chip 21, ensuring power supply while reducing the fabrication difficulty of the first wiring layer 33.

[0073] Continue to refer to Figure 4 In some implementations, the packaging substrate 30 further includes a second wiring layer 34, which is disposed on the other side of the first glass core plate 32 and the substrate 31; a first conductive via 311 is connected to the second wiring layer 34; a first bump 322 is provided on the side of the first glass core plate 32 facing away from the first wiring layer 33, and the second conductive via 321 is connected to the second wiring layer 34 through the first bump 322. The second wiring layer 34 can be connected to the circuit board 11 ( Figure 1 As shown, the second conductive via 321 is connected to the second wiring layer 34 via the first bump 322, which enables the connection between the second conductive via 321 and the circuit board 11, thereby realizing the connection between the chip 21 (as shown). Figure 3 (As shown) the longitudinal signal transmission to the circuit board 11. The second wiring layer 34 can serve as a transition between the packaging substrate 30 and the circuit on the circuit board 11, improving the feasibility of directly mounting the packaging substrate 30 onto the circuit board 11, and enabling the packaging substrate 30 to be adapted to more specifications of circuit boards 11.

[0074] It is understood that the second wiring layer 34 may include one or more layers. For example, the number of layers in the second wiring layer 34 may include one, two, three, etc. The more layers the second wiring layer 34 has, the larger the wiring area, which can realize the transmission of more lines, improve wiring efficiency, and also separate different lines. In the event of a failure in one layer, other layers can still work normally, which can effectively reduce the failure rate of the second wiring layer 34.

[0075] In some implementations, the thickness of the first wiring layer 33 on the first glass core plate 32 is less than the thickness of the first wiring layer 33 on the substrate 31. It is understood that having a greater thickness for the first glass core plate 32 than for the substrate 31, and a thinner thickness for the first wiring layer 33 on the first glass core plate 32 than for the substrate 31, allows for a smoother surface on the packaging substrate 30, facilitating precise wiring and packaging of the chip 21.

[0076] The thinner thickness of the first wiring layer 33 on the first glass core plate 32 results in a thinner packaging substrate 30 and a smaller overall volume of the packaging substrate 30. The first wiring layer 33 also makes the surface of the packaging substrate 30 smoother, which is beneficial for the precise wiring and packaging of the chip 21.

[0077] Please refer to Figure 6 In some implementations, the dielectric material of the first wiring layer 33 located on the first glass core plate 32 is the same as the dielectric material of the first wiring layer 33 located on the substrate 31. It is understood that when the first wiring layer 33 located on the first glass core plate 32 and the first wiring layer 33 located on the substrate 31 use the same dielectric material, the line width and line spacing of the two first wiring layers 33 are the same, and the interconnection density of the two first wiring layers 33 is the same.

[0078] The dielectric material of the first wiring layer 33 located on the first glass core plate 32 is the same as the dielectric material of the first wiring layer 33 located on the substrate 31, so that the interconnection density of the two first wiring layers 33 is the same, which facilitates signal transmission between the two first wiring layers 33.

[0079] In some implementations, the dielectric material of the first wiring layer 33 includes resin. It is understood that in embodiments where resin is used as the dielectric material, the interconnect density of the first wiring layer 33 is relatively low, which can be adapted to the interconnect density of the substrate 31, ensuring signal transmission efficiency while avoiding processing difficulties and resource waste in the first wiring layer 33.

[0080] Please refer to Figure 7 In some implementations, the linewidth of the first wiring layer 33 on the first glass core plate 32 is d3, the linewidth of the first wiring layer 33 on the substrate 31 is d4, d3 equals d4, and / or; the line spacing of the first wiring layer 33 on the first glass core plate 32 is s3, the line spacing of the first wiring layer 33 on the substrate 31 is s4, s3 equals s4.

[0081] It is understood that in some embodiments, d3 equals d4 and s3 equals s4; in some embodiments, s3 equals s4; and in some embodiments, d3 equals d4. In the above embodiments, the wiring density of the first wiring layer 33 located on the first glass core plate 32 is equal to the wiring density of the first wiring layer 33 located on the substrate 31, which ensures the lateral signal transmission efficiency between the two first wiring layers 33.

[0082] In some implementations, 5μm≤d3≤25μm, and / or, 5μm≤s3≤25μm. The first glass core board 32 uses the same first wiring layer 33 as the substrate 31. The first wiring layer 33 has a larger line width and line spacing, and a lower interconnection density. Compared with this embodiment, the above-mentioned embodiments with s1 less than s2 and d1 less than d2 correspond to a higher interconnection density and higher signal transmission efficiency in the packaging substrate 30.

[0083] Continue to refer to Figure 6 In some implementations, the packaging substrate 30 further includes a third wiring layer 35, which is disposed on the other side of the first glass core plate 32 and the substrate 31. The first conductive via 311 and the second conductive via 321 are connected to the third wiring layer 35. It is understood that the third wiring layer 35 is connected to the circuit board 11 (…). Figure 1 As shown, the first conductive via 311 and the second conductive via 321 are connected to the third wiring layer 35, which enables the connection of the first conductive via 311 and the second conductive via 321 to the circuit board 11, thereby realizing the connection of chip 21 (as shown). Figure 3 (As shown) the longitudinal signal transmission to the circuit board 11. The third wiring layer 35 can serve as a transition between the packaging substrate 30 and the circuit on the circuit board 11, improving the feasibility of directly mounting the packaging substrate 30 onto the circuit board 11, and enabling the packaging substrate 30 to be adapted to more specifications of circuit boards 11.

[0084] It is understood that the third wiring layer 35 may include one or more layers. For example, the number of layers in the third wiring layer 35 may include one, two, three, etc. The more layers the third wiring layer 35 has, the larger the wiring area, which can realize the transmission of more lines, improve wiring efficiency, and also separate different lines. In the event of a failure in one layer, other layers can still work normally, which can effectively reduce the failure rate of the third wiring layer 35.

[0085] In some implementations, the first wiring layer 33 located on the first glass core plate 32 and the first wiring layer 33 located on the substrate 31 are fabricated using back-end processes. In embodiments where the first wiring layer 33 is located on the substrate 31, the back-end processes may include: pre-treating the surface of the substrate 31; vacuum bonding of the dielectric material; laser drilling; surface cleaning; seed layer deposition; dry film photoresist bonding; exposure; development; electroplating; photoresist removal; and seed layer etching. In embodiments where the first wiring layer 33 is located on the first glass core plate 32, the back-end processes may include: pre-treating the surface of the first glass core plate 32; dielectric material coating; exposure; development; curing; seed layer deposition; photoresist coating; exposure; development; electroplating; photoresist removal; and seed layer etching.

[0086] The first wiring layer 33, which is fabricated using a back-end process, has a smaller minimum line width and minimum line spacing, allowing the first wiring layer 33 to have a greater interconnect density and provide more traces for the packaging substrate 30.

[0087] Please refer to Figure 8 and Figure 9 In some implementations, the packaging substrate 30 further includes a plurality of solder balls 36, which are disposed on the second wiring layer 34 or the third wiring layer 35 away from the substrate 31 (e.g., Figure 7 On the surface of (as shown). It is understood that the package substrate 30 can be electrically connected to an external circuit via solder balls 36. For example, the solder balls 36 can enable the package substrate 30 to connect to the circuit board 11 (as shown). Figure 1 The connection between (as shown).

[0088] Continue to refer to Figure 8 and Figure 9 In some implementations, the packaging substrate 30 further includes a second glass core plate 37. A second receiving hole 313 is provided through the substrate 31, and the second glass core plate 37 is disposed within the second receiving hole 313. A plurality of third conductive vias 371 are spaced apart within the second glass core plate 37, and each third conductive via 371 penetrates the second glass core plate 37. It is understood that in the chip 21 (e.g., Figure 3 In the embodiments shown (including multiple examples), the first glass core plate 32 has a large area, but the large area of ​​the first glass core plate 32 makes it prone to cracking during processing. This implementation replaces the large area of ​​the first glass core plate 32 with a second glass core plate 37 on the substrate 31, resulting in a smaller area for each glass core plate on the substrate 31. The smaller the area of ​​the glass core plate, the larger the relative stress-bearing area, and the greater the resistance. During processing, it can withstand greater stress and is therefore less prone to cracking.

[0089] Multiple glass core plates can be set according to the number of chips 21 and the wiring area. Compared with the entire glass core plate, setting a second glass core plate 37 on the substrate 31 can make the area of ​​each glass core plate on the substrate 31 smaller. The smaller the area of ​​the glass core plate, the larger the relative stress-bearing area, the greater the resistance, and the greater the stress that can be withstood during processing, thus making it less prone to cracking.

[0090] Please refer to Figure 10In some implementations, chip 21 further includes a third chip 213, with the second chip 212 located between the first chip 211 and the third chip 213. The first chip 211, the second chip 212, and the third chip 213 are arranged in a direction parallel to the surface of the packaging substrate 30. It is understood that the second glass core plate 37 is connected to the second chip 212 and the third chip 213, enabling connection between them. The second glass core plate 37 can be positioned midway between the second chip 212 and the third chip 213, thereby shortening the lateral connection distance between the chips 21 and improving the signal transmission efficiency between the chips 21.

[0091] The position of the second glass core plate 37 can be adjusted according to the positions of the second chip 212 and the third chip 213, so that the distance between the second glass core plate 37 and the second chip 212 and the third chip 213 is reduced, thereby improving the signal transmission efficiency of the packaging substrate 30.

[0092] Please refer to Figure 11 and Figure 12 This application embodiment also provides a packaging substrate 30 (such as...). Figure 6 The manufacturing method (as shown) includes:

[0093] S102: A first receiving hole is formed through the substrate, and a plurality of first conductive vias are spaced apart in the substrate.

[0094] S104: The first glass core plate is placed in the first receiving hole. A plurality of second conductive through holes are provided at intervals in the first glass core plate. The radial dimension of the second conductive through holes is smaller than the radial dimension of the first conductive through holes. The first glass core plate and the substrate have a first wiring layer on the same side.

[0095] With the above configuration, the radial dimension of the second conductive via 321 in the packaging substrate 30 manufactured by the packaging substrate 30 manufacturing method provided in this application embodiment is smaller than the radial dimension of the first conductive via 311. For the same area, the number of second conductive vias 321 provided on the first glass core plate 32 is greater than the number of first conductive vias 311 provided on the substrate 31, thus increasing the interconnection density of the packaging substrate 30. Simultaneously, since the first glass core plate 32 is disposed within the first receiving hole 312 of the substrate 31, the strength of the substrate 31 is greater than the strength of the first glass core plate 32, thereby increasing the strength of the packaging substrate 30 and making it less prone to cracking and breakage. This ensures the interconnection density and strength of the packaging substrate 30 and improves its reliability.

[0096] Please refer to Figure 12In some embodiments, a groove can be formed on the surface of the substrate 31 by mechanical, dry, or wet methods to create a first receiving hole 312 penetrating through it. It is understood that a support plate can be added to the bottom of the substrate 31 before grooving to ensure the strength of the substrate 31 and prevent it from breaking. The embodiments of this application do not limit the material of the support plate; for example, the support plate can be made of glass, silicon, etc.

[0097] Continue to refer to Figure 12 In an embodiment where the encapsulation substrate 30 includes a second glass core plate 37, when a first receiving hole 312 is formed through the substrate 31, a second receiving hole 313 is also formed through the substrate 31, and the second glass core plate 37 is placed in the second receiving hole 313.

[0098] Please refer to Figure 13 In some implementations, before forming the first through-hole 312 in the substrate 31, the fabrication method further includes:

[0099] S101: A first wiring layer is formed on one side of a substrate having a plurality of first conductive vias;

[0100] A first receiving hole is formed through it on the substrate, including:

[0101] A first receiving hole is formed, which penetrates the first wiring layer and the substrate.

[0102] It is understood that while a first wiring layer 33 is formed on one side of a substrate 31 having multiple first conductive vias 311, a second wiring layer 34 can be formed on the opposite side of the substrate 31.

[0103] Please refer to Figure 14 In some embodiments, after the first glass core plate 32 is placed in the first receiving hole 312, a thermosetting material 38 is filled in the gap between the first glass core plate 32 and the substrate 31 to fix the position of the first glass core plate 32.

[0104] In some implementations, the first glass core plate 32 has a first wiring layer 33 on one side and a first protrusion 322 on the other side.

[0105] Placing the first glass core plate 32 into the first receiving hole 312 includes:

[0106] The first wiring layer of the first glass core board and the first wiring layer of the substrate are located on the same side.

[0107] Please refer to Figure 15 In some implementations, after placing the first glass core plate 32 into the first receiving hole 312, the manufacturing method further includes:

[0108] S106: A first wiring layer is formed on the same side of a substrate having a plurality of first conductive vias and a first glass core having a plurality of second conductive vias;

[0109] A first receiving hole 312 is formed through the substrate 31, including:

[0110] A first receiving hole is made, and the first receiving hole penetrates the substrate.

[0111] It is understood that while a first wiring layer 33 is formed on the same side of a substrate 31 having multiple first conductive vias 311 and a first glass core plate 32 having multiple second conductive vias 321, a third wiring layer 35 is formed on the opposite side.

[0112] Please refer to Figure 16 In some implementations, the packaging substrate 30 (e.g.) Figure 6 The manufacturing method (as shown) also includes:

[0113] A dielectric material for the first wiring layer 33 is coated on the surfaces of the substrate 31 and the first glass core plate 32. The surfaces are smoothed by chemical mechanical polishing, and the surface pins are exposed using methods such as dry etching. It is understood that a smooth surface on the packaging substrate 30 is beneficial for the chip 21 (e.g., ...). Figure 3 As shown in the figure, the chip 21 pins are exposed on the surface, which facilitates the connection between the pins of the chip 21 and the pins of the package substrate 30.

[0114] Please refer to Figure 17 and Figure 18 In some implementations, after the chip 21 is mounted on the packaging substrate 30, a thermosetting material 38 can be used to fill the gap between the bottom of the chip 21 and the chip 21. This application does not limit the thermosetting material; for example, the thermosetting material may include chip 21 underfill, molding compound, molding underfill (MUF), etc. It is understood that the thermosetting material can fix the chip 21, effectively reducing the overall temperature expansion mismatch between the chip 21 and the packaging substrate 30 or the impact caused by external forces, and can cure quickly when heated.

[0115] Please refer to Figure 17 and Figure 19 In some embodiments, the method for manufacturing the packaging substrate 30 further includes:

[0116] Solder balls 36 are formed on the side of the second wiring layer 34 or the third wiring layer 35 away from the chip 21.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A package substrate, characterized by, The package substrate comprises: a substrate, a plurality of first conductive vias are arranged in the substrate at intervals; a first glass core plate, a first accommodating hole is arranged in the substrate and penetrates the first glass core plate, the first glass core plate is arranged in the first accommodating hole, a plurality of second conductive vias are arranged in the first glass core plate at intervals, and a radial dimension of the second conductive vias is smaller than a radial dimension of the first conductive vias; a first wiring layer, the first wiring layer is arranged on the same side of the first glass core plate and the substrate, the first conductive vias are connected with the first wiring layer, and the second conductive vias are connected with the first wiring layer.

2. The package substrate of claim 1, wherein A dielectric material of the first wiring layer on the first glass core plate is different from a dielectric material of the first wiring layer on the substrate.

3. The package substrate according to claim 2, wherein the dielectric material of the first wiring layer on the first glass core plate comprises at least one of PI, SiO2, and Si3N4; and the dielectric material of the first wiring layer on the substrate comprises resin.

4. The package substrate according to claim 2 or 3, wherein A line width of the first wiring layer on the first glass core plate is d1, a line width of the first wiring layer on the substrate is d2, and d1 is less than d2.

5. The package substrate of claim 4, wherein, 1 μm≤d1≤5 μm, and 5 μm≤d2≤25 μm.

6. The package substrate of any one of claims 2-5, wherein, A line spacing of the first wiring layer on the first glass core plate is s1, a line spacing of the first wiring layer on the substrate is s2, and s1 is less than s2.

7. The package substrate of claim 6, wherein, 1 μm≤s1≤5 μm, and 5 μm≤s2≤25 μm.

8. The package substrate of any one of claims 2-7, wherein, The package substrate further comprises: a second wiring layer, the second wiring layer is arranged on the other side of the first glass core plate and the substrate; the first conductive vias are connected with the second wiring layer; a first bump is arranged on a side of the first glass core plate away from the first wiring layer, and the second conductive vias are connected with the second wiring layer through the first bump.

9. The package substrate of any one of claims 2-8, wherein, The package substrate further comprises: a thickness of the first wiring layer on the first glass core plate is less than a thickness of the first wiring layer on the substrate.

10. The package substrate of claim 1, wherein, A dielectric material of the first wiring layer on the first glass core plate is the same as a dielectric material of the first wiring layer on the substrate.

11. The package substrate according to claim 10, wherein the dielectric material of the first wiring layer comprises resin.

12. The package substrate of claim 10 or 11, wherein, A line width of the first wiring layer on the first glass core plate is d3, a line width of the first wiring layer on the substrate is d4, d3 is equal to d4, and / or; A line spacing of the first wiring layer on the first glass core plate is s3, a line spacing of the first wiring layer on the substrate is s4, s3 is equal to s4.

13. The package substrate of claim 12, wherein, 5 μm≤d3≤25 μm; and / or, 5 μm≤s3≤25 μm.

14. The package substrate of any one of claims 10-13, wherein, The package substrate further comprises: a third wiring layer, the third wiring layer is arranged on the other side of the first glass core plate and the substrate; the first conductive vias and the second conductive vias are connected with the third wiring layer.

15. The package substrate of any one of claims 10-14, wherein, The first wiring layer on the first glass core plate and the first wiring layer on the substrate are formed by a post-process.

16. A semiconductor device, characterized by comprising: The semiconductor device comprises a chip and the package substrate according to any one of claims 1-15, wherein the chip is disposed on the first wiring layer of the package substrate.

17. The semiconductor device of claim 16, wherein, The chip comprises a first chip and a second chip, and the first chip and the second chip are arranged in a direction parallel to a surface of the package substrate.

18. An electronic device, comprising: The semiconductor device comprises a chip and the package substrate according to any one of claims 1-15, wherein the chip is disposed on the first wiring layer of the package substrate. The semiconductor device comprises a chip and the package substrate according to any one of claims 1-15, wherein the chip is disposed on the first wiring layer of the package substrate.

19. A method for fabricating a package substrate, the method comprising: The semiconductor device comprises a chip and the package substrate according to any one of claims 1-15, wherein the chip is disposed on the first wiring layer of the package substrate. A first accommodating hole is formed in the substrate, and a plurality of first conductive vias are arranged in the substrate at intervals; The first glass core plate is placed in the first accommodating hole, the first glass core plate is arranged with a plurality of second conductive vias at intervals, the radial size of the second conductive vias is smaller than the radial size of the first conductive vias, and the same side of the first glass core plate and the substrate has a first wiring layer.

20. The method of claim 19, wherein Before the first accommodating hole is formed in the substrate, the manufacturing method further comprises: A first wiring layer is formed on one side of the substrate with the plurality of first conductive vias; A first accommodating hole is formed in the substrate, comprising: The first accommodating hole is formed, and the first accommodating hole penetrates the first wiring layer and the substrate.

21. The method of claim 20, wherein One side of the first glass core plate has a first wiring layer, and the other side has a first bump, The first glass core plate is placed in the first accommodating hole, comprising: The first wiring layer of the first glass core plate and the first wiring layer of the substrate are on the same side.

22. The method of claim 19, wherein After the first glass core plate is placed in the first accommodating hole, the manufacturing method further comprises: A first wiring layer is formed on the same side of the substrate with the plurality of first conductive vias and the first glass core plate with the plurality of second conductive vias; A first accommodating hole is formed in the substrate, comprising: The first accommodating hole is formed, and the first accommodating hole penetrates the substrate.

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