Packaging structure, sensor and terminal equipment

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and discloses a packaging structure, a sensor and terminal equipment. The invention discloses a packaging structure, and the structure comprises a substrate which comprises a ball grid array located on the first surface of the substrate, and the ball grid array comprises a power supply ball; the chip comprises a salient point array located on the active region surface of the chip, and the chip is connected with the second surface of the substrate through the salient point array; wherein the second surface is a surface, directly facing the first surface, on the substrate, and at least one NC salient point on the salient point array is connected with the power supply ball. And the working of the chip can be better supported at least.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a packaging structure, sensor, and terminal device. Background Technology

[0002] With the continuous development of the electronics industry, the requirements for integrated circuit (IC) packaging technology are becoming increasingly stringent. Ball grid array (BGA) packaging technology replaces the pins of ICs with bumps and arranges the bumps in an array pattern, achieving high density and high performance, and has been widely used.

[0003] However, current BGA packaging structures cannot adequately support chip operation. For example, without increasing the package area, it is difficult to meet the power supply and current requirements of chip growth, or different types of grounds require common ground design. Summary of the Invention

[0004] This application provides a packaging structure, sensor, and terminal device, which at least helps to better support chip operation.

[0005] According to some embodiments of this application, a first aspect of this application provides a packaging structure, including: a substrate, including a ball grid array located on a first surface of the substrate, the ball grid array including power balls; a chip, including a bump array located on an active surface of the chip, the chip being connected to a second surface of the substrate through the bump array; wherein the second surface is a surface on the substrate directly opposite the first surface, and at least one NC bump on the bump array is connected to the power balls.

[0006] In some embodiments, the power ball is also connected to at least one non-NC bump in the bump array.

[0007] In some embodiments, the non-NC bumps are located at the edge of the bump array.

[0008] In some embodiments, the non-NC bump includes at least one non-NC bump adjacent to the NC bump.

[0009] In some embodiments, only the NC bumps in the bump array are connected to the power ball.

[0010] According to some embodiments of this application, a second aspect of this application also provides a packaging structure, including: a substrate, including a ball grid array located on a first surface of the substrate, the ball grid array including a digital ground plane and an analog ground plane; a chip, including a bump array located on an active surface of the chip, the chip being connected to a second surface of the substrate through the bump array; wherein, the bump array includes a first region and a second region, the first region and the second region do not overlap, the digital ground plane is connected only to the bumps located in the first region of the bump array, and the analog ground plane is connected only to the bumps located in the second region of the bump array.

[0011] In some embodiments, the ball grid array further includes a power ball, and the bumps in the bump array connected to the power ball are located at the edge of the bump array, and the bumps in the first region and the second region are not connected to the power ball.

[0012] In some embodiments, the first region surrounds the second region, or the second region surrounds the first region.

[0013] According to some embodiments of this application, a third aspect of this application also provides a sensor, including: a carrier; and an encapsulation structure disposed on the carrier, wherein the encapsulation structure is the encapsulation structure described in any of the first aspects of this application, or the encapsulation structure described in any of the second aspects of this application.

[0014] According to some embodiments of this application, a fourth aspect of this application also provides a terminal device, including: a device body; and a sensor disposed on the device body as described in the third aspect of this application; wherein the sensor is used for target detection and / or communication to provide reference information to the operation of the device body.

[0015] The technical solution provided in this application has at least one of the following advantages:

[0016] 1. By connecting the NC bumps on the bump array to the power ball, the power flow rate can be supported through the NC bumps. This achieves the goal of meeting the power flow rate requirements without increasing the package area to set more bumps to connect the power ball.

[0017] 2. Connect the digital ground and analog ground to the convex points in two different non-overlapping regions of the convex point array, so that the digital ground and analog ground can be clearly distinguished, generating non-overlapping digital ground planes and analog ground planes, thus eliminating the need for a common ground design for digital ground and analog ground. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 This is a cross-sectional view of the packaging structure provided in the embodiments of this application;

[0020] Figure 2 This is a schematic diagram of the NC bump arrangement of the bump array involved in the packaging structure provided in the embodiments of this application;

[0021] Figure 3 This is another cross-sectional view of the packaging structure provided in the embodiments of this application;

[0022] Figure 4 This is a schematic diagram of a bump arrangement of the bump array involved in the packaging structure provided in the embodiments of this application;

[0023] Figure 5 This is a schematic diagram of another bump arrangement of the bump array involved in the packaging structure provided in the embodiments of this application;

[0024] Figure 6 This is another schematic diagram of the bump array involved in the packaging structure provided in the embodiments of this application;

[0025] Figure 7 This is a schematic diagram of a bump array layout involving the bump array provided in the embodiments of this application;

[0026] Figure 8 yes Figure 7 A partial schematic diagram of the circuit routing corresponding to the schematic diagram of the bump layout shown;

[0027] Figure 9 This is another cross-sectional view of the packaging structure provided in the embodiments of this application;

[0028] Figure 10 This is a schematic diagram showing the distribution of the first and second regions involved in the packaging structure provided in the embodiments of this application;

[0029] Figure 11 This is another schematic diagram showing the distribution of the first and second regions involved in the packaging structure provided in the embodiments of this application;

[0030] Figure 12 This is another schematic diagram showing the distribution of the first and second regions involved in the packaging structure provided in the embodiments of this application;

[0031] Figure 13This is a schematic diagram of another bump arrangement of the bump array involved in the packaging structure provided in the embodiments of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable readers to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0033] The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0034] This application provides a packaging structure in one aspect, which connects the power balls in the spherical grid array to the NC bumps on the bump array, thereby supporting power flow through the NC bumps. This achieves the goal of meeting power flow requirements without increasing the number of bumps or the package area. To facilitate a better understanding of the packaging structure described above by those skilled in the art, the following will refer to... Figures 1-8 Explain and clarify it. Among them, Figure 1 and Figure 3 These are two different cross-sectional views of the above-described packaging structure. Figure 2 , Figures 4-7 This is a schematic diagram showing different arrangements (partial) of the bumps in the above packaging structure. Figure 8 for Figure 7 The schematic diagram of the convex dot layout shown corresponds to a partial schematic diagram of the circuit routing.

[0035] refer to Figure 1 and Figure 3 The package structure includes a substrate 101 and a chip 102. The substrate 101 includes a first surface 103 and a second surface 104 facing each other, and a ball grid array 105 located on the first surface 103. The chip 102 includes an active region surface 106 and a bump array 107 (an array of bumps) located on the active region surface 106. The chip 102 is connected to the second surface 104 of the substrate 101 via the bump array 107. The ball grid array 105 includes power balls 115, and the bump array 107 includes NC (non-contact) bumps 117, wherein at least one NC bump 117 is connected to the power ball 115.

[0036] It should be noted that the "NC bump 117" mentioned in this application embodiment refers to the bump in the bump array 107 that is not connected to the solder balls in the ball grid array 105 in the existing BGA package structure and is not used in the operation of the chip 102. For example, in order to meet the electrostatic discharge (ESD) test standards of integrated circuits (ICs) in the existing BGA package structure, the bumps on the four corners of the package are set as unconnected (not connected to the chip) and unusable (cannot be used by the chip during operation). At this time, these four unconnected and unusable bumps can be used as the "NC bump" mentioned in this application embodiment, that is... Figure 2 The NC bump 117 is shown. For example, for some special designs, such as isolating different bumps, some unconnected and unusable bumps may be designed in addition to the bump array. In this case, these unconnected and unusable bumps can be used as "NC bumps" in the embodiments of this application, etc. The different cases of NC bumps in the bump array 103 will not be listed one by one here. For the convenience of those skilled in the art, the package structure diagram provided in the accompanying drawings uses the bumps set in the four corners to meet the ESD testing standards of the IC as examples of non-NC bumps.

[0037] Correspondingly, the bumps in the bump array 107 other than the NC bump 117 are non-NC bumps.

[0038] As mentioned earlier, the number of NC bumps 117 in the bump array 107 is variable. Generally, the number may be four (i.e., four bumps set at the four corners of the bump array to meet the ESD test of the IC), or more than four. This application embodiment does not limit the number of non-NC bumps. This application can select the specific number of NC bumps connected to the chip power leads based on the chip's power overload requirements.

[0039] Based on this, in some embodiments, the side view of the packaging structure can be as follows: Figure 1 As shown, only the NC bump 117 in the bump array 107 is connected to the power ball 115.

[0040] In this way, since the non-NC point is not occupied when the power supply overcurrent requirement of chip 102 is met, other functions can be provided by using the non-NC point, which is beneficial to support requirements or functions other than power supply overcurrent requirements without increasing the package area.

[0041] in, Figure 1This is merely a simplified illustration of a bump array 107 with only NC bumps 117 connected to the power ball 115, and does not imply that the side view of the bump array 107 with only NC bumps 117 connected to the power ball 115 must be as shown. Figure 1 As shown, specifically, the number of NC bumps 117 connected to the power ball 115 can be determined by the power overload requirement of the chip 102, and the position of the NC bumps 117 connected to the power ball 115 can be set according to the connection relationship of other bumps or the design requirements of the package structure, etc., which will not be elaborated here.

[0042] certainly, Figure 1 This is merely an illustration of a connection established between the bumps in the bump array 107 and the power ball 115; other implementations are possible in some embodiments. For example, in some embodiments, the side view of the package structure may also be as shown... Figure 3 As shown, while the NC bumps 117 in the bump array 107 are connected to the power ball 115, there are also non-NC bumps in the bump array 107 that are connected to the power ball 115.

[0043] In this way, the NC bumps 117 and non-NC bumps in the bump array 107 together bear the power overcurrent requirements of the chip 102, further improving the power supply's overcurrent capability.

[0044] in, Figure 3 This is merely a simplified illustration of NC bumps 117 and non-NC bumps in a bump array 107 simultaneously connected to a power ball 115, and does not imply that the side view of NC bumps 117 and non-NC bumps in the bump array 107 simultaneously connected to the power ball 115 must be as shown. Figure 3 As shown, specifically, the number of NC bumps 117 and non-NC bumps connected to the power ball 115 in the bump array 107 can be determined by the power overload requirement of the chip 102. The positions of the NC bumps 117 and non-NC bumps connected to the power ball 115 can be set according to the connection relationship of other bumps or the design requirements of the package structure, etc., which will not be elaborated here.

[0045] also, Figure 1 and Figure 3 The connection between the power ball 115 and the bumps (whether NC bumps 117 or non-NC bumps) in the bump array 107 is achieved through the traces 108 on the substrate 101 and the through holes 109 inside the substrate 101, which is only an example. It is understood that when implementing the connection between the power ball 115 and the bumps in the bump array 107, one or a combination of methods such as drilling, traces, and copper pouring can be used. The implementation methods of connecting the power ball 115 and the bumps in the bump array 107 will not be listed one by one here.

[0046] It should also be noted that the embodiments of this application do not limit the substrate 101, chip 102, ball grid array 105 and bump array 107.

[0047] The shape and material of the substrate 101 involved in the embodiments of this application are not limited.

[0048] In some examples, substrate 101 can be a multilayer board made of organic materials, i.e., a plastic substrate.

[0049] In some examples, substrate 101 can also be a ceramic substrate.

[0050] In some examples, substrate 101 may also be a strip-shaped flexible printed circuit board (PCB).

[0051] Of course, the above is only an exemplary description of the materials used in the substrate 101. In some embodiments, the substrate 101 may also be made of other materials, which will not be described in detail here.

[0052] In some examples, the substrate 101 is rectangular in shape.

[0053] In some examples, the substrate 101 is square in shape.

[0054] Of course, the above is only an exemplary description of the shape of the substrate 101. In some embodiments, the substrate 101 may also adopt other shapes. This application does not limit this, and will not be described in detail here.

[0055] Regarding the chip 102 involved in the embodiments of this application, the embodiments of this application do not limit its function, shape, etc. Any bare die (or "bare die" or "DIE") with packaging requirements will not be described in detail here.

[0056] The ball grid array 105 provided in this application embodiment can be an array composed of several solder balls. The shape of the array is not limited and can be set according to requirements. Furthermore, the deployment positions of various solder balls in the ball grid array 105 are not limited and can be deployed according to the requirements of the wiring 108 on the surface of the substrate 101, the through holes 109 etc., which will not be described in detail here.

[0057] Regarding the bump array 107 involved in the embodiments of this application, the embodiments of this application do not limit the arrangement of the bumps therein.

[0058] In some examples, the convex dot array 107 can be as follows: Figure 4 The peripheral array shown. In this case, other structures, such as antenna structures, can be deployed in the central area surrounded by the bumpless array 107.

[0059] In some examples, the convex dot array 107 can also be as follows: Figure 5 The shown is an interleaved array.

[0060] In some examples, the convex dot array 107 can also be as follows: Figure 6 The full array shown.

[0061] in, Figures 4-6 A circle in the diagram represents a convex point.

[0062] In the convex array 107, the following is adopted Figure 5 or Figure 6 In the arrangement shown, the bump located at the center of the bump array 107 can be selected as the non-NC bump of the power ball 115. However, when using a similar arrangement... Figure 4 In the arrangement shown, compared to the traditional method of distributing power balls in the central area of ​​a BGA, due to structural or antenna designs in the central area of ​​the second surface 104 of the substrate 101, the vias provided in the central area of ​​the substrate 101 cannot connect the ground ball and the power ball. In this case, only the outermost two rings of bumps in the bump array 107 can be wired through the vias. Therefore, the existing scheme of connecting the power ball to the bumps arranged in the inner ring (excluding the outermost two rings) of the bump array cannot be used; otherwise, the electrical connection will fail because the bumps in the inner ring of the bump array cannot produce wires. In other words, when using... Figure 4 In the peripheral array shown, when the antenna and other structures are placed in the central area of ​​the substrate 101, the non-NC bumps 117 connected to the power ball 115 are located at the edge of the bump array 107 (the outermost ring or the outermost two rings of the bump array 107). That is, the bumps are selected from the non-NC bumps in the outermost ring or the outermost two rings of the bump array 107 and connected to the power ball 115. In this way, the structural interference problem of the BGA area in the PCB design can be solved by changing the arrangement of the power balls in the package.

[0063] In some cases, when selecting non-NC bumps connected to the power ball 115, non-NC bumps surrounding the NC bump 117 connected to the power ball 115 can be preferentially selected. That is, non-NC bumps connected to the power ball 115 include at least one non-NC bump adjacent to the NC bump 117. Taking the bump at the corner of the bump array 107 as an example, such as... Figure 7A partial bump array 107 is shown. In this case, non-NC bumps connected to the power ball 115 can be identified from the non-NC bumps 127 and non-NC bumps 137 on either side of the NC bump 117. Of course, not every non-NC bump adjacent to every NC bump 117 needs to be connected to the power ball 115. In this case, compared to the existing situation where ordinary bumps (i.e., bumps not connected to the power ball 115) are placed around the NC bump 117, the package structure connects at least one NC bump 117 and at least one surrounding non-NC bump to the power ball 115 simultaneously. Thus, when routing on the substrate 101, an entire power pattern can be laid using the NC bump 113 and its surrounding non-NC bumps, for example... Figure 7 The local NC bump 117 shown and the non-NC bumps 127 and non-NC bumps 137 on both sides thereof can be correspondingly formed as follows: Figure 8 The irregular polygon shown represents a whole power supply pattern, in which, Figure 8 The circular vias corresponding to the protrusions described above are cross-sections on the second surface 104. Therefore, this simplifies the wiring design of the package structure.

[0064] Of course, the above is only an exemplary description of the arrangement of bumps in the bump array 107. In some examples, other arrangements can also be used, which will not be elaborated here.

[0065] It should be noted that the embodiments of this application do not limit the bumps constituting the bump array 107. Figures 1-8 The bumps shown are provided as an example only, using a spherical bump formed by solder balls. In some embodiments, the bumps can also be other shapes, such as cylindrical shapes, which will not be described in detail here.

[0066] Another aspect of this application embodiment provides a packaging structure in which the digital ground lead and analog ground lead of the chip are respectively connected to bumps in two different non-overlapping regions of the bump array, so that the digital ground and analog ground can be clearly distinguished, generating non-overlapping digital ground planes and analog ground planes, thereby eliminating the need for a common ground design for digital ground and analog ground. To facilitate a better understanding of the packaging structure described above by those skilled in the art, the following will refer to... Figures 4-6 , Figures 9-12 This will be explained. Among them, Figures 4-6 The diagram shows different arrangements of the bumps in the above packaging structure. Figure 9 This is a cross-sectional view of the above-mentioned packaging structure. Figures 10-12 This is a schematic diagram showing the different distributions of the first and second regions in the bump array of the above-mentioned packaging structure.

[0067] refer to Figure 9The packaging structure includes a substrate 201 and a chip 202. The substrate 201 includes a first surface 203 and a second surface 204 facing each other, and a ball grid array 205 located on the first surface 203. The chip 202 includes an active region surface 206 and a bump array 207 (an array of bumps) located on the active region surface 206. The chip 202 is connected to the second surface 204 of the substrate 201 via the bump array 207. The ball grid array 205 includes a digital ground plane 215 and an analog ground plane 225. The bump array 207 includes a first region 217 and a second region 227, which do not overlap. The digital ground plane 215 is connected only to the bumps located in the first region 217 of the bump array 207, and the analog ground plane 225 is connected only to the bumps located in the second region 227 of the bump array 207.

[0068] In other words, compared to the existing scheme that sequentially bumps and connects bumps according to the die pad order of the chip without considering the distribution of bumps connected to analog ground plane and digital ground plane, the bump array 207 is divided into two types of bumps belonging to different regions, which are used to connect digital ground plane 215 and analog ground plane 225 respectively. This allows for the generation of non-overlapping and clearly distinguishable digital ground plane and analog ground plane, thus eliminating the need for common ground design. This overcomes the dependence on common ground design caused by the aforementioned existing schemes that do not consider the distribution of bumps connected to analog ground leads and digital ground leads, which is beneficial to simplifying the design of the package structure and thus better supporting the operation of chip 202 through design.

[0069] It should be noted that the embodiments of this application do not limit the first region 217 and the second region 227, which can be any two non-overlapping regions covered by the convex dot array 207.

[0070] It should also be noted that the embodiments of this application do not limit the substrate 201, chip 202, ball grid array 205 and bump array 207.

[0071] The shape and material of the substrate 201 involved in the embodiments of this application are not limited.

[0072] In some examples, substrate 201 can be a multilayer board made of organic materials, i.e., a plastic substrate.

[0073] In some examples, substrate 201 can also be a ceramic substrate.

[0074] In some examples, substrate 201 can also be a strip-shaped flexible PCB.

[0075] Of course, the above is only an exemplary description of the materials used in the substrate 201. In some embodiments, the substrate 201 may also be made of other materials, which will not be described in detail here.

[0076] In some examples, the substrate 201 is rectangular in shape.

[0077] In some examples, the substrate 201 is square in shape.

[0078] Of course, the above is only an exemplary description of the shape of the substrate 201. In some embodiments, the substrate 201 may also adopt other shapes. This application does not limit this, and will not elaborate on them here.

[0079] Regarding the chip 202 involved in the embodiments of this application, the embodiments of this application do not limit its function, shape, etc. Any bare die (or "bare die" or "DIE") with packaging requirements will not be described in detail here.

[0080] The ball grid array 205 provided in this application embodiment can be an array composed of several solder balls. The shape of the array is not limited and can be set according to requirements. Furthermore, the deployment position of various solder balls in the ball grid array 205 is not limited and can be deployed according to the requirements of the wiring on the surface of the substrate 201, the internal through holes, etc., which will not be elaborated here.

[0081] Regarding the bump array 207 involved in the embodiments of this application, the embodiments of this application do not limit the arrangement of the bumps therein.

[0082] In some examples, the convex array 207 can be as follows: Figure 4 The peripheral array shown. In this case, other structures, such as antenna structures, can be deployed in the central area surrounded by the bumpless array 203.

[0083] In some examples, the convex dot array 207 can also be such as Figure 5 The shown is an interleaved array.

[0084] In some examples, the convex dot array 207 can also be such as Figure 6 The full array shown.

[0085] In the convex array 207 Figure 5 or Figure 6 In the arrangement shown, the central bump in the bump array 207 can be selected as the bump connecting the digital ground plane 215 and the analog ground plane 225. However, when using... Figure 4In the arrangement shown, because the central region of the second surface 204 of the substrate 201 has structural or antenna designs, the vias provided in the central region of the substrate 201 cannot be used for grounding and power lines. In this case, only the outermost two rings of the bump array 207 can be wired through the vias. Therefore, the existing method of connecting the power ball to the bumps arranged in the inner ring (excluding the outermost two rings) of the bump array cannot be used; otherwise, the electrical connection will fail because the bumps in the inner ring of the bump array cannot provide wires. In other words, when using… Figure 4 In the peripheral array shown, when the antenna and other structures are placed in the central area of ​​the substrate 201, the bumps that connect to the digital ground plane 215 and the analog ground plane 225 are located at the edge of the bump array 207 (the outermost ring or the outermost two rings of the bump array 207). That is, bumps are selected from the bumps in the outermost ring or the outermost two rings of the bump array 207 and connected to the digital ground plane 215 and the analog ground plane 225.

[0086] It is understood that the ball grid array 205 should include not only grounding balls (including digital grounding ball 215 and analog grounding ball 225) but also power balls. Therefore, to avoid interference between grounding and power connection, bumps located in different regions of the bump array 207 can be selected to connect the grounding ball and the power ball respectively. For example, in some embodiments, the bumps connected to the power ball are located at the edge of the bump array 207, and the bumps in the first region 217 and the second region 227 are not connected to the power ball.

[0087] Of course, the above is only an exemplary description of the arrangement of bumps in the bump array 207. In some examples, other arrangements can be used, which will not be elaborated here.

[0088] It should be noted that the embodiments of this application do not limit the bumps constituting the bump array 207; they can be spherical, cylindrical, etc.

[0089] Furthermore, this application embodiment does not limit the distribution of the protrusions connected to the digital earth 215 in the first region 217, nor does it limit the distribution of the protrusions connected to the analog earth 225 in the second region 227. For example, in some embodiments, such as Figure 10 As shown, the first region 217, represented by the non-shaded area, surrounds the second region 227, represented by the shaded area, or, as... Figure 11 As shown, the second region 227, represented by the non-shaded area, surrounds the first region 217, represented by the shaded area. Alternatively, in some embodiments, as shown... Figure 12 As shown, the first region 217, represented by the shaded area on the left, and the second region 227, represented by the shaded area on the right, are separated by a distance, etc., which will not be described in detail here.

[0090] To help those skilled in the art better understand the distribution of bumps with different connection relationships in the bump array of the packaging structure provided in the above embodiments, the following will be combined with Figure 13 The arrangement diagram of the aforementioned convex dot array is provided for illustration. It should be noted that... Figure 13 This is for illustrative purposes only and does not imply that the bump array must be arranged as shown.

[0091] like Figure 13 As shown, the bump array 207 adopts a peripheral distribution. The bumps connected to the power balls in the ball grid array 205 are black-filled circles, the bumps connected to the digital ground in the ball grid array 205 are diagonally filled circles, and the bumps connected to the analog ground in the ball grid array 205 are square-patterned circles.

[0092] In this way, the bumps arranged in the outermost ring of the bump array 207 are connected to the power balls in the ball grid array 205, and the NC bumps and the non-NC bumps around the NC bumps are connected to the power balls in the ball grid array 205. This allows a complete power pattern to be laid out at the corresponding position on the substrate 201. At the same time, by using the NC bumps, the power flow requirements can be met without increasing the number of bumps or the package area. Furthermore, the bumps arranged in the innermost ring of the bump array 207 are connected to the digital ground plane 215 in the ball grid array 205, and the bumps arranged near the outermost ring are connected to the analog ground plane 225 in the ball grid array 205. This allows the digital ground to be laid out in the central area where the bumps arranged in the innermost ring of the bump array 207 are located, and the area outside the central area to be laid out as analog ground. This divides the ground plane on the substrate into two ground planes, thus eliminating the need for a common ground design.

[0093] Of course, the accompanying drawings are merely illustrative examples of the packaging structure. In some cases, the packaging structure can also be implemented in other ways, which will not be elaborated here.

[0094] Based on the aforementioned encapsulation structure, another aspect of this application provides a sensor, including: a carrier and an encapsulation structure disposed on the carrier. The encapsulation structure is the same as the one provided in the aforementioned embodiments.

[0095] Since the specific structure and working principle of the sensor's packaging structure have been described in detail in the above embodiments, they will not be repeated here.

[0096] It is not difficult to see that this embodiment is a device embodiment corresponding to the structural embodiment, and this embodiment can be implemented in conjunction with the structural embodiment. The relevant technical details mentioned in the structural embodiment are still valid in this embodiment, and will not be repeated here to reduce repetition. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the structural embodiment.

[0097] Furthermore, in order to highlight the innovative aspects of this application, no units that are not closely related to solving the technical problems proposed in this application are introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0098] This application provides a terminal device, which may include: a device body; and a sensor as described above disposed on the device body; wherein the sensor is used for target detection and / or communication to provide reference information for the operation of the device body.

[0099] In some embodiments, the sensor may be disposed on the exterior of the device body; in other embodiments, the sensor may be disposed on the interior of the device body; and in still other embodiments, the sensor may be partially disposed on the interior and partially disposed on the exterior of the device body. This application does not limit the specific embodiments; the choice depends on the circumstances.

[0100] It should be noted that sensors can achieve functions such as target detection by transmitting and receiving radio signals, providing measurement information of the detected target to the device body, thereby assisting or even controlling the operation of the device body. Examples of measurement information include at least one of relative distance, relative speed, and relative angle.

[0101] In some embodiments, the device body described above can be a component or product applied in fields such as transportation, consumer electronics, monitoring, in-cabin detection, and healthcare. For example, the device body can be intelligent transportation equipment (such as automobiles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, etc.), smart home devices (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments used to detect vital signs parameters and various devices equipped with such instruments, such as in-cabin detection in automobiles, indoor personnel monitoring, intelligent medical devices, and consumer electronic devices.

[0102] In some embodiments, when the aforementioned device body is applied to an Advanced Driving Assistance System (ADAS), the electromagnetic wave sensor, as an on-board sensor, can provide various functional safety guarantees for the ADAS system, such as Automatic Emergency Braking (AEB), Blind Spot Detection (BSD), Lane Changing Assist (LCA), and Rear Cross Traffic Alert (RCTA).

[0103] Furthermore, the examples mentioned in the above embodiments can be freely combined, and any combination can be understood as an embodiment. The terms "embodiment" or "example" appearing in various locations in the specification do not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments.

[0104] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A packaging structure, characterized in that, include: A substrate, including a ball grid array located on a first surface of the substrate, the ball grid array including power balls; A chip, including a bump array located on the active surface of the chip, the chip being connected to a second surface of the substrate via the bump array; The second surface is the surface on the substrate that is directly opposite the first surface, and at least one NC bump on the bump array is connected to the power ball.

2. The packaging structure according to claim 1, characterized in that, The power ball is also connected to at least one non-NC bump in the bump array.

3. The packaging structure according to claim 2, characterized in that, The non-NC bumps are located at the edge of the bump array.

4. The packaging structure according to claim 2 or 3, characterized in that, The non-NC bump includes at least one non-NC bump adjacent to the NC bump.

5. The packaging structure according to claim 1, characterized in that, Only the NC bumps in the bump array are connected to the power ball.

6. A packaging structure, characterized in that, include: A substrate, including a ball grid array located on a first surface of the substrate, the ball grid array including a digital ground plane and an analog ground plane; A chip, including a bump array located on the active surface of the chip, the chip being connected to a second surface of the substrate via the bump array; The bump array includes a first region and a second region, the first region and the second region do not overlap, the digital globe is connected only to the bumps in the first region of the bump array, and the analog globe is connected only to the bumps in the second region of the bump array.

7. The packaging structure according to claim 6, characterized in that, The ball grid array also includes a power ball, and the bumps in the bump array that are connected to the power ball are located at the edge of the bump array. The bumps in the first region and the second region are not connected to the power ball.

8. The packaging structure according to claim 6 or 7, characterized in that, The first region surrounds the second region, or the second region surrounds the first region.

9. A sensor, characterized in that, include: Carrier; An encapsulation structure is disposed on a carrier, wherein the encapsulation structure is the encapsulation structure as described in any one of claims 1 to 5, or the encapsulation structure as described in any one of claims 6 to 8.

10. A terminal device, characterized in that, include: Equipment body; And the sensor as described in claim 9, disposed on the device body; The sensor is used for target detection and / or communication to provide reference information for the operation of the device body.

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