Embedded process deviation monitoring device and compensation equipment

Abstract

The invention relates to the technical field of semiconductor chips, and provides an embedded process deviation monitoring device and compensation equipment, the device is integrated in a semiconductor chip, and the device comprises an excitation module, N groups of switch assemblies, a signal receiving module and a control module; the excitation module comprises at least one of a current source and a voltage source, and is used for providing an excitation signal for a to-be-detected object so as to obtain a response signal; the switch assembly comprises a fixed potential end, a first switch and a second switch; the control module is used for controlling the on-off of the first switch and the second switch in each group of switch assembly so as to selectively connect the excitation module and the signal receiving module to one of N objects to be tested; the signal receiving module comprises at least one of a current measuring unit and a voltage measuring unit, and is used for receiving the response signal and performing measurement according to the response signal to obtain a measured value; the measured value is used for calculating the process deviation of the to-be-measured object. The device and the method are used for realizing process monitoring and dynamic compensation with few ports and high efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip, and particularly relates to an embedded process deviation monitoring device and compensation equipment. BACKGROUND

[0002] In the related art, process deviations such as line width variation, doping concentration fluctuation and oxide layer thickness unevenness are inevitable in the manufacturing process of semiconductor integrated circuits, which can cause key parameters such as transistor threshold voltage and carrier mobility to deviate from the design values, thereby affecting the performance, power consumption and reliability of the chip. Therefore, it is of great significance to introduce a process deviation monitoring mechanism in the chip design stage for process correction, dynamic parameter adjustment and reliability management. Traditional process deviation detection schemes usually rely on electrical test (ET) or probe station in the wafer factory to measure the test structure (Test Key) externally. However, such traditional schemes have the following significant defects: Firstly, the test port resource is occupied, increasing the packaging and board cost. In the prior art, each test structure usually needs to be independently introduced to the chip pad for external probe contact measurement. When multiple positions or multiple types of devices need to be monitored, a large number of test pins will be occupied, which not only increases the chip packaging cost, but also leads to the increase of PCB board complexity, which is not conducive to miniaturization design.

[0003] Secondly, the external probe test needs to contact different test structures one by one, and the test process is complicated and time-consuming. Especially in the wafer level test and post-packaging test stage, the test time increases linearly with the number of test structures, which seriously affects the production rhythm and is not conducive to efficient mass production and rapid process feedback.

[0004] Therefore, there is an urgent need for an embedded process deviation monitoring device and compensation equipment to improve the above problems. SUMMARY

[0005] The present application provides an embedded process deviation monitoring device and compensation equipment for realizing process monitoring and dynamic compensation with few ports and high efficiency through on-chip integration, resource sharing and automatic switching.

[0006] According to a first aspect of an embodiment of the present application, there is provided an in-die process variation monitoring device integrated in a semiconductor chip, comprising: an excitation module, N groups of switch components, a signal receiving module and a control module, N being a positive integer; the excitation module comprises at least one of a current source and a voltage source, for providing an excitation signal to a to-be-tested object, so that the to-be-tested object outputs a response signal; each group of switch components is connected to one to-be-tested object, and comprises a fixed potential end, a first switch and a second switch; a first end of the first switch is connected to a first test point, and a first end of the second switch is connected to a second test point; the first test point is connected to the excitation module; at least one of the first test point and the second test point is connected to the signal receiving module; a second end of the first switch and a second end of the second switch are commonly connected to a first end of the to-be-tested object; a second end of the to-be-tested object is connected to the fixed potential end; the control module is configured to control the on-off of the first switch and the second switch in each group of switch components, so as to selectively connect the excitation module and the signal receiving module to one of the N to-be-tested objects; the signal receiving module comprises at least one of a current measurement unit and a voltage measurement unit, for receiving the response signal and measuring the response signal to obtain a measurement value; the measurement value is used to calculate the process variation of the to-be-tested object.

[0007] In an embodiment, when the current source and the voltage measurement unit are in a working state at the same time, the current source is configured to provide a current excitation signal to the to-be-tested object, so that the to-be-tested object outputs a voltage response signal; and the voltage measurement unit is configured to acquire the voltage response signal and measure a voltage measurement value.

[0008] In an embodiment, when the voltage source and the current measurement unit are in a working state at the same time, the voltage source is configured to provide a voltage excitation signal to the to-be-tested object, so that the to-be-tested object outputs a current response signal; and the current measurement unit is configured to acquire the current response signal and measure a current measurement value.

[0009] In an embodiment, the first switch and the second switch adopt a Complementary Metal-Oxide-Semiconductor (CMOS) switch structure, which comprises: a first transistor and a second transistor, the conductive types of the first transistor and the second transistor being opposite; a gate of the first transistor is connected to the control module through a first control signal line, a source of the first transistor is connected to a first end of the excitation module, and a drain of the first transistor is connected to a first end of the to-be-tested object; a gate of the second transistor is connected to the control module through a second control signal line, a source of the second transistor is connected to the first end of the excitation module, and a drain of the second transistor is connected to the first end of the to-be-tested object; wherein the two signals transmitted by the first control signal line and the second control signal line are complementary signals.

[0010] In one embodiment, the object under test is an N-type transistor, whose gate and drain are shorted to the second terminal of a first switch, and whose source is connected to a fixed potential terminal; an excitation module is used to provide a constant current as an excitation signal, and a signal receiving module is used to measure the voltage measurement value; a control module calculates the process deviation based on the comparison between the voltage measurement value and the expected voltage value; if the voltage measurement value is higher than the expected voltage value, it is determined that the switching speed of the N-type transistor is too slow; if the voltage measurement value is lower than the expected voltage value, it is determined that the switching speed of the N-type transistor is too fast.

[0011] In one embodiment, the object under test is a P-type transistor, with its drain connected to a fixed potential terminal, its gate connected to a fixed potential terminal, and its source connected to a second switch; an excitation module is used to provide a constant current as an excitation signal, and a signal receiving module is used to measure the voltage measurement value; a control module calculates the process deviation based on the comparison between the voltage measurement value and the expected voltage value; if the voltage measurement value is higher than the expected voltage value, it is determined that the switching speed of the P-type transistor is too slow; if the voltage measurement value is lower than the expected voltage value, it is determined that the switching speed of the P-type transistor is too fast.

[0012] In one embodiment, the object under test is a resistor, one end of which is connected to a fixed potential terminal, and the other end is connected to a first switch and a second switch; the excitation module is used to provide a constant current as an excitation signal, and the signal receiving module is used to measure the voltage measurement value; the control module calculates the process deviation based on the comparison result between the voltage measurement value and the expected voltage value; if the voltage measurement value is higher than the expected voltage value, it is determined that the resistance value of the resistor is too large; if the voltage measurement value is lower than the expected voltage value, it is determined that the resistance value of the resistor is too small.

[0013] In one embodiment, the object under test is a capacitor, one end of which is connected to a fixed potential terminal, and the other end is connected to a first switch and a second switch; the excitation module is used to provide a constant current as an excitation signal to charge the capacitor; the signal receiving module is used to measure the voltage across the capacitor at a first time and a second time, respectively; the control module calculates the process deviation based on the comparison between the difference between the voltage measurements at the two times and the expected voltage difference.

[0014] In one embodiment, the object under test is an N-type transistor, with its source and gate connected to a fixed potential terminal, and its drain connected to the second terminal of a first switch. An excitation module provides a constant voltage as an excitation signal, and a signal receiving module measures the current flowing through the object under test via the first switch to obtain a current measurement value. A control module calculates the process deviation based on a comparison between the current measurement value and the expected current value. If the current measurement value is higher than the expected current value, it is determined that the leakage current of the N-type transistor is too large, posing a risk of leakage. If the current measurement value is lower than or equal to the expected current value, it is determined that the leakage performance of the N-type transistor is normal.

[0015] In one embodiment, the object under test is a P-type transistor, whose drain is connected to a fixed potential terminal, and whose gate and source are shorted and connected to the second terminal of a first switch. The excitation module provides a constant voltage as an excitation signal, and the signal receiving module measures the current flowing through the object under test through the first switch to obtain the current measurement value. The control module calculates the process deviation based on the comparison between the current measurement value and the expected current value. If the current measurement value is higher than the expected current value, it is determined that the leakage current of the P-type transistor is too large, and there is a risk of leakage. If the current measurement value is lower than or equal to the expected current value, it is determined that the leakage performance of the P-type transistor is normal.

[0016] In one embodiment, the first terminal of the first switch is connected to the excitation module or the signal receiving module through a first test point; the first terminal of the second switch is connected to the signal receiving module through a second test point.

[0017] In one embodiment, the device further includes a filter network connected to the first test point and / or the second test point, with the other end of the filter network connected to a fixed potential terminal; the filter network is used to filter out switching transient noise.

[0018] In one implementation, the control module is further configured to compare the measured value with the expected value and generate a comparison result; divide the measured value into multiple preset segment intervals according to the comparison result; the segment intervals correspond to different levels of process deviation and are used to measure the process status of the object under test.

[0019] In one embodiment, the device further includes a storage module for storing the segment number of the segmented interval in which the measured value is located; the segment number is used to be read during the power-on self-test or operation of the semiconductor chip, and the operating parameters of the semiconductor chip are adjusted according to the segment number to compensate for the process deviation of the object under test.

[0020] According to a second aspect of the present invention, a process deviation compensation device is provided, comprising an embedded process deviation monitoring device and a configuration module as described in any of the first aspects; the configuration module is connected to the embedded process deviation monitoring device and is used to acquire process deviations and adjust the operating parameters of the semiconductor chip to compensate for the process deviations of the object under test.

[0021] In one implementation, the configuration module is used to read the segment number stored in the device and adjust the operating parameters of the semiconductor chip according to the segment number; the segment number corresponds one-to-one with the segment interval of the measured value.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: Since the embedded process deviation monitoring device proposed in the present invention is integrated inside the chip, and N objects under test share the same set of excitation module and signal receiving module, multi-target measurement can be achieved through the shared excitation signal path and response signal path, reducing the need for external test pads or dedicated test pins, which is conducive to reducing package size, board layout complexity and testing cost.

[0023] By controlling the on / off state of the first and second switches in each group of switching components through the control module, different objects under test can be selectively connected, enabling automated and batch measurement processes. This mechanism avoids the tedious process of traditional probe stations contacting each object individually, significantly shortening the time for wafer-level testing and post-packaging testing, and is suitable for efficient process monitoring in mass production environments. Attached Figure Description

[0024] Figure 1 This is a structural block diagram of an embedded process deviation monitoring device according to an embodiment.

[0025] Figure 2 This is a schematic diagram of the circuit structure of an embedded process deviation monitoring device when a current source is used to test an N-type transistor, according to an exemplary embodiment.

[0026] Figure 3 This is a schematic diagram of the circuit structure of an embedded process deviation monitoring device when a current source is used to test a P-type transistor, according to another exemplary embodiment.

[0027] Figure 4 This is a schematic diagram of the circuit structure of an embedded process deviation monitoring device when the current source is used to test the resistor, according to yet another exemplary embodiment.

[0028] Figure 5 This is a schematic diagram of the circuit structure of an embedded process deviation monitoring device when the current source is used to test the capacitor, according to another exemplary embodiment.

[0029] Figure 6 This is a schematic diagram of the circuit structure of an embedded process deviation monitoring device when the voltage source is activated to test an N-type transistor, according to an exemplary embodiment.

[0030] Figure 7 This is a schematic diagram of the circuit structure of an embedded process deviation monitoring device when a voltage source is activated to test a P-type transistor, according to another exemplary embodiment.

[0031] Figure 8 This is a schematic diagram of a circuit structure of a CMOS switch according to an exemplary embodiment.

[0032] Figure 9 This is a structural block diagram of a process deviation compensation device according to an embodiment.

[0033] Figure 10 This is a distribution diagram of test values ​​for leakage current testing of a batch of chips according to an exemplary embodiment.

[0034] Figure 11 This is a flowchart illustrating a group testing method according to an exemplary embodiment.

[0035] Explanation of the reference numerals in the figure: 1. Excitation module; 2. Switching assembly; 3. Signal receiving module; 4. Control module; 5. Storage module; 6. Embedded process deviation monitoring device; 7. Configuration module; 8. Process deviation compensation device; 11. Current source; 12. Voltage source; 31. Ammeter; 32. Voltmeter; 61. First transistor; 62. Second transistor; 71. First filter network; 72. Second filter network; 81. First test point; 82. Second test point; 9. Object under test. Detailed Implementation

[0036] Unless otherwise defined, the technical or scientific terms used in this specification should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. Specific embodiments of the invention will be described below with reference to the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot provide a detailed description of all features of the actual embodiments. Without departing from the spirit and scope of the invention, those skilled in the art can make modifications and substitutions to the embodiments of the invention, and the resulting embodiments are also within the protection scope of the invention.

[0037] like Figure 1As shown, the first embodiment of the present invention provides an embedded process deviation monitoring device 6, integrated inside a semiconductor chip, including: an excitation module 1, N sets of switch components 2, a signal receiving module 3, and a control module 4, where N is a positive integer; the excitation module 1 includes at least one of a current source 11 and a voltage source 12, used to provide an excitation signal to a test object 9, so that the test object 9 outputs a response signal; each set of switch components 2 is connected to a test object 9, including a fixed potential terminal, a first switch, and a second switch; the first end of the first switch is connected to a first test point 81, and the first end of the second switch is connected to a second test point 82; the first test point 81 is connected to the excitation module 1; the first test point 81... The signal receiving module 3 is connected to at least one of the first and second test points 82; the second end of the first switch and the second end of the second switch are connected to the first end of the test object 9; the second end of the test object 9 is connected to the fixed potential terminal; the control module 4 is used to control the on / off state of the first and second switches in each group of switch assemblies 2, so as to selectively connect the excitation module 1 and the signal receiving module 3 to one of the N test objects 9; the signal receiving module 3 includes at least one of a current measurement unit and a voltage measurement unit, used to receive the response signal and perform measurement according to the response signal to obtain a measurement value; the measurement value is used to calculate the process deviation of the test object 9.

[0038] In some examples, the object under test 9 is a semiconductor integrated circuit, which contains various types of devices, including different categories of transistors, resistors, and capacitors. Taking transistors as an example, they can be divided into two categories: thin-gate oxide transistors (LTTs) and thick-gate oxide transistors (ULVTs). LTTs are typically used in core circuits and operate at lower voltages. Based on their threshold voltages, they are further classified into low-threshold voltage (Low-Vt, LVT), standard-threshold voltage (SVT), high-threshold voltage (HVT), and ultra-low-threshold voltage (ULVT) to meet the balance between performance and power consumption. Thick-gate oxide transistors are mainly used in I / O interfaces or high-voltage modules. In addition to having different threshold voltages, they also support multiple operating voltage levels, such as native, 1.8V, 2.5V, and 3.3V, to adapt to different input and output levels.

[0039] Resistive devices mainly include polysilicon resistors, diffused resistors, and well resistors. Their resistance accuracy, temperature coefficient, and matching characteristics vary depending on the process conditions. They are often used in bias circuits, feedback networks, or matching structures.

[0040] Capacitors include metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, metal-oxide-semiconductor (MOS) capacitors, and trap capacitors. Among them, MIM capacitors have high precision, low parasitics, and good linearity, making them suitable for high-frequency analog circuits. MOM capacitors are formed by multi-layer metal coupling, occupying a large area but requiring no additional mask. MOS capacitors and trap capacitors are based on transistor structures and are often used for large-capacity decoupling or integrated filtering.

[0041] The aforementioned devices may be affected by process fluctuations during manufacturing, causing their electrical parameters to deviate from the design expectations. By applying the embedded monitoring device of this embodiment to these critical devices, accurate sensing and subsequent compensation of process deviations can be achieved, improving the consistency and reliability of the overall chip performance.

[0042] The operating frequency of digital circuits is affected by the speed of components and the supply voltage. When components are faster or the voltage is higher, the circuit can operate at a higher frequency, but power consumption increases; when components are slower or the voltage is lower, the frequency is limited, but power consumption is lower. To improve performance consistency, the voltage is often increased to compensate for slower chips, or the voltage is decreased to optimize the power consumption of faster chips. Therefore, accurately identifying the process deviations of each chip and adjusting the operating voltage accordingly can achieve a balance between performance and power consumption: increasing the frequency of slower chips to ensure reliability, and reducing the voltage of faster chips to save energy.

[0043] In some embodiments, when the current source 11 and the voltage measurement unit are both in operation, the current source 11 is used to provide a current excitation signal to the object under test 9, so that the object under test 9 outputs a voltage response signal, and the voltage measurement unit is used to acquire the voltage response signal and to measure the voltage measurement value.

[0044] In some specific embodiments, the fixed potential terminal is the ground terminal GND. In some examples, the ground terminal is the analog circuit ground terminal (AGND). Further, the analog circuit ground terminal can be coupled to the chip's digital ground (DGND) at the power input through a single-point connection or a ferrite bead to isolate high-frequency noise generated by the digital circuit and prevent it from crosstalking to sensitive measurement nodes through the common ground line.

[0045] like Figure 2As shown, in some specific embodiments, the test object 9 is an N-type transistor, whose gate and drain are shorted to the second terminal of the first switch, and whose source is connected to the fixed potential terminal; the excitation module 1 is used to provide a constant current as an excitation signal, and the signal receiving module 3 is used to measure the voltage measurement value; the control module 4 calculates the process deviation based on the comparison result between the voltage measurement value and the expected voltage value; if the voltage measurement value is higher than the expected voltage value, it is determined that the switching speed of the N-type transistor is too slow; if the voltage measurement value is lower than the expected voltage value, it is determined that the switching speed of the N-type transistor is too fast.

[0046] In some examples, the object under test 9 is an N-type metal-oxide-semiconductor field-effect transistor (NMOS), whose source is connected to the fixed potential terminal, and whose gate and drain are shorted together and connected to the second terminal of the first switch SW1, i.e., the excitation signal input terminal.

[0047] The current source 11 in the excitation module 1 provides a constant amplitude current excitation signal I to the NMOS transistor. in The signal flows through its channel; the voltage measurement unit in the signal receiving module 3, such as an analog-to-digital converter (ADC), voltmeter 32, or oscilloscope, is connected to the second test point 82 via the second switch SW2 to measure the NMOS gate voltage V. out The corresponding voltage measurement value is obtained. In this connection configuration, the NMOS operates in the saturation region, and its current-voltage relationship satisfies: I in =0.5*W / L*μ*C ox (V out -V th ) 2 ; Where W is the channel width of the N-type transistor, L is the channel length of the N-type transistor, μ is the carrier mobility, and C is the channel width of the N-type transistor. ox It is the gate oxide thickness, V th It is the threshold voltage.

[0048] like Figure 3As shown, in some other specific embodiments, the test object 9 is a P-type transistor, with its drain connected to a fixed potential terminal, its gate connected to a fixed potential terminal, and its source connected to a second switch; the excitation module 1 is used to provide a constant current as an excitation signal, and the signal receiving module 3 is used to measure the voltage measurement value; the control module 4 calculates the process deviation based on the comparison result between the voltage measurement value and the expected voltage value; if the voltage measurement value is higher than the expected voltage value, it is determined that the switching speed of the P-type transistor is too slow; if the voltage measurement value is lower than the expected voltage value, it is determined that the switching speed of the P-type transistor is too fast.

[0049] In some examples, the object under test 9 is a P-type metal-oxide-semiconductor field-effect transistor (PMOS), whose drain and gate are connected to a fixed potential terminal, and whose source is connected to the second terminal of the first switch SW1, and is also connected to the voltage measurement unit of the signal receiving module 3 through the second switch SW2.

[0050] The current source 11 in the excitation module 1 provides a constant amplitude current excitation signal I to the PMOS transistor. in Current flows in from the source and through the channel to the grounded drain; the signal receiving module 3 is connected to the source terminal voltage V via the second switch. out The corresponding voltage measurement value is obtained by using measurement equipment such as ADC, voltmeter 32 or oscilloscope.

[0051] In this connection configuration, the PMOS operates in the saturation region, and its current-voltage relationship satisfies: I in =0.5*W / L*μ*C ox (V out -V th ) 2 ; Where W is the channel width of the P-type transistor, L is the channel length of the P-type transistor, μ is the carrier mobility, and C is the channel width of the P-type transistor. ox It is the gate oxide thickness, V th It is the threshold voltage.

[0052] like Figure 4As shown, in some specific embodiments, the object under test 9 is a resistor, one end of which is connected to a fixed potential terminal, and the other end is connected to a first switch and a second switch; the excitation module 1 is used to provide a constant current as an excitation signal, and the signal receiving module 3 is used to measure the voltage measurement value; the control module 4 calculates the process deviation based on the comparison result between the voltage measurement value and the expected voltage value; if the voltage measurement value is higher than the expected voltage value, it is determined that the resistance value of the resistor is too large; if the voltage measurement value is lower than the expected voltage value, it is determined that the resistance value of the resistor is too small.

[0053] In some examples, the object under test 9 is an on-chip resistor, one end of which is connected to a fixed potential terminal, and the other end is connected to the common node of the first switch SW1 and the second switch SW2. The excitation module 1 provides a constant current to the resistor as an excitation signal I. in The signal receiving module 3 is connected to the node through the second switch to measure its voltage response signal and obtain the corresponding voltage measurement value V. out .

[0054] Under this configuration, the voltage-current relationship of the resistor under test satisfies Ohm's law: V out =I in *R; Where R is the actual resistance value of the resistor to be measured. Due to the excitation current I... in Given a constant value, the measured voltage value V out It is directly proportional to the resistance value R, and therefore can directly reflect its process deviation status. The control module 4 will measure the V... out Compare the voltage with the preset expected value to determine the trend of deviation: If the measured voltage value is higher than the expected voltage value, the resistance value of the resistor is determined to be too large; if the measured voltage value is lower than the expected voltage value, the resistance value of the resistor is determined to be too small.

[0055] The judgment result can be used to generate resistor process deviation information, supporting subsequent compensation equipment to dynamically calibrate analog circuits, such as amplifier gain or filter cutoff frequency.

[0056] like Figure 5 As shown, in some specific embodiments, the object under test 9 is a capacitor, one end of which is connected to a fixed potential terminal, and the other end is connected to a first switch and a second switch; the excitation module 1 is used to provide a constant current as an excitation signal to charge the capacitor; the signal receiving module 3 is used to measure the voltage across the capacitor at the first time and the second time respectively; the control module 4 calculates the process deviation based on the comparison between the difference of the voltage measurements at the two times and the expected voltage difference.

[0057] In some examples, excitation module 1 provides a constant current I. in During capacitor charging, signal receiving module 3 measures the voltage at the second test point 82 at time t1 and time t2 > t1, respectively, to obtain the voltage V at time t1. out1 Voltage V at the second moment out2 According to the basic principle of capacitor charging, its capacitance C satisfies the following relationship: (V out2 -V out1 )*C=I in *(t2-t1); If the voltage difference V out2 -V out1 If the value is higher than expected, it means the capacitance value is smaller than expected; if the voltage difference V out2 -V out1 If it is lower than expected, it means that the capacitance value is larger than expected.

[0058] In some embodiments, when the voltage source 12 and the current measurement unit are both in operation, the voltage source 12 is used to provide a voltage excitation signal to the object under test 9, so that the object under test 9 outputs a current response signal, and the current measurement unit is used to acquire the current response signal and measure the current measurement value.

[0059] like Figure 6 As shown, in some specific embodiments, the object under test 9 is an N-type transistor, with its source connected to the fixed potential terminal, its gate connected to the fixed potential terminal, and its drain connected to the second terminal of the first switch; the excitation module 1 provides a constant voltage as an excitation signal, and the signal receiving module 3 measures the current flowing through the object under test 9 through the first switch to obtain a current measurement value; the control module 4 calculates the process deviation based on the comparison result between the current measurement value and the expected current value; if the current measurement value is higher than the expected current value, it is determined that the leakage current of the N-type transistor is too large, and there is a risk of leakage; if the current measurement value is lower than or equal to the expected current value, it is determined that the leakage performance of the N-type transistor is normal.

[0060] In some examples, the test object 9 is an N-type metal-oxide-semiconductor transistor, whose source and gate are connected to a fixed potential terminal, and whose drain is connected to the second terminal of the first switch SW1.

[0061] The excitation module 1 provides a constant voltage signal V. in For example, 0.1V or 0.5V is used as an excitation, which is applied to the drain of the NMOS through the first switch; the signal receiving module 3 measures the current flowing through the transistor at the first test point 81 to obtain the corresponding current measurement value I. inThis current is the current at zero gate-to-source voltage condition (V0). GS Off-state leakage current under the condition of 0.

[0062] Under ideal manufacturing conditions, when the gate and source of an NMOS are grounded, the device should be completely off, and the leakage current should approach zero. However, due to process deviations such as gate oxide defects, uneven doping, and increased interface states that may occur during manufacturing, unexpected leakage currents may arise between the drain and source or between the drain and the substrate, such as subthreshold leakage or gate-induced drain leakage (GIDL).

[0063] The fixed potential terminal is ground (GND), specifically the grounding terminal of the analog circuit, to reduce noise interference and improve the accuracy of small current measurements; the excitation voltage V in The voltage is a DC voltage, the amplitude of which is set according to the process node under test, with a typical value of 0.1V to 1.2V. The signal receiving module 3 includes a high-precision ammeter 31, a transimpedance amplifier (TIA) or an integrated current-to-digital converter (IDC) to quantify weak leakage currents in the nanoampere (nA) or even picoampere (pA) range. Since the leakage current is typically in the nA to μA range, even if the first switch SW1 has an on-resistance R... on1 The resulting IR voltage drop is also extremely small and will not significantly change the actual voltage applied to the transistor under test, thus not affecting the test accuracy.

[0064] like Figure 7 As shown, in some other specific embodiments, the test object 9 is a P-type transistor, with its drain connected to a fixed potential terminal, and its gate and source shorted and connected to the second terminal of the first switch; the excitation module 1 provides a constant voltage as an excitation signal, and the signal receiving module 3 measures the current flowing through the test object 9 through the first switch to obtain a current measurement value; the control module 4 calculates the process deviation based on the comparison result between the current measurement value and the expected current value; if the current measurement value is higher than the expected current value, it is determined that the leakage current of the P-type transistor is too large, and there is a risk of leakage; if the current measurement value is lower than or equal to the expected current value, it is determined that the leakage performance of the P-type transistor is normal.

[0065] In some examples, the test object 9 is a P-type metal-oxide-semiconductor transistor, whose drain is connected to a fixed potential terminal, and whose gate and source are shorted together and connected to the second terminal of the first switch SW1.

[0066] The excitation module 1 provides a constant voltage signal V. in (For example, 0.1V, 0.5V, or VDD) is applied as an excitation to the source / gate node of the PMOS via the first switch; the signal receiving module 3 measures the current flowing through the transistor at the first test point 81 to obtain the corresponding current measurement value I. in This current is at V GS Off-state leakage current under the condition of =0.

[0067] Under ideal manufacturing conditions, when the drain of a PMOS is grounded and the source and gate are at the same potential, the device should be in the off state, and the leakage current should be close to zero. However, due to process deviations such as gate oxide defects, increased interface states, or abnormal doping during manufacturing, unexpected leakage currents may occur between the source / drain and the substrate, such as subthreshold leakage, gate-induced drain leakage, or diode-based leakage / drain-bias-induced leakage (DBL).

[0068] It is worth noting that the device under test (DUT) 9 not only includes basic components but can also be expanded into integrated functional circuit modules, such as Static Random-Access Memory (SRAM), latches, flip-flops, and delay chains. By testing the operating characteristics of these circuits, the overall process status and power consumption performance of the chip can be more comprehensively reflected.

[0069] In some specific embodiments, the object under test 9 is an SRAM cell or SRAM array, whose power supply terminal is connected to the power supply network via a switch. The word lines, bit lines, and control signals are configured by the control module 4. The excitation module 1 provides the operating voltage, and the signal receiving module 3 is used to measure the operating current of the SRAM under read / write operations or the leakage current in standby mode. The control module 4 compares the measured current value with the expected value. If the operating current is too large, it indicates that the process is too fast. If the leakage current is too high, it reflects that the threshold voltage is too low or the device leakage is serious. Further, the control module 4 divides the current deviation into multiple segments, such as segment 0 to segment M−1, and only stores the segment number to reduce the amount of data. Based on this, it generates compensation information to adjust the core power supply voltage (DigitalCore VDD, or VDDC) or trigger aging warning. Similarly, when the object under test 9 is a delay chain or trigger, by measuring its propagation delay or setup time, timing performance and process deviation can also be evaluated, realizing fine monitoring and management of key functional modules.

[0070] like Figure 8 As shown, in some embodiments, the first switch and the second switch adopt a CMOS switch structure, which includes a first transistor 61 and a second transistor 62, wherein the first transistor 61 and the second transistor 62 have opposite conductivity types; the gate of the first transistor 61 is connected to the control module 4 through a first control signal line, its source is connected to the first terminal of the excitation module 1, and its drain is connected to the first terminal of the object under test 9; the gate of the second transistor 62 is connected to the control module 4 through a second control signal line, its source is connected to the first terminal of the excitation module 1, and its drain is connected to the first terminal of the object under test 9.

[0071] In some examples, the first transistor 61 is an N-type transistor and the second transistor 62 is a P-type transistor; in other examples, the first transistor 61 is a P-type transistor and the second transistor 62 is an N-type transistor. The two signals EN and EN_b used to transmit on the first and second control signal lines are complementary signals. That is, when the first control signal line is high, the second control signal line is low, and vice versa.

[0072] For example, when the first switch is used to connect to the excitation module 1, the control module 4 outputs a high-level signal to the gate of the N-type transistor and a low-level signal to the gate of the P-type transistor, so that the N-type transistor and the P-type transistor are turned on at the same time, thereby transmitting the excitation signal completely to the object under test 9; when the control signal is reversed, both transistors are turned off, realizing the isolation of the excitation path.

[0073] Similarly, when the second switch is connected to the signal receiving module 3, the same CMOS switch structure can also be used to ensure lossless transmission of the response signal over a wide voltage range and improve measurement accuracy.

[0074] It is worth noting that by adopting the aforementioned CMOS switch structure, the threshold voltage loss problem caused by a single type of transistor during conduction can be effectively avoided, enabling full-range signal transmission from ground potential to power supply voltage. Simultaneously, the complementary control signal is generated by the inverter inside control module 4, ensuring symmetrical timing, reliable driving, and suitability for high-precision analog measurement scenarios.

[0075] In some embodiments, the first end of the first switch is connected to the excitation module 1 or the signal receiving module 3 via a first test point 81; the first end of the second switch is connected to the signal receiving module 3 via a second test point 82.

[0076] In some embodiments, the device further includes a filter network connected to the first test point 81 and / or the second test point 82, with the other end of the filter network connected to the fixed potential terminal; the filter network is used to filter out switching transient noise.

[0077] In some specific embodiments, the filtering network includes a first filtering network 71 and a second filtering network 72. A first end of the first filtering network 71 is connected to a first test point 81, and a second end of the first filtering network is connected to the fixed potential terminal. A first end of the second filtering network 72 is connected to a second test point 82, and a second end of the second filtering network 72 is connected to the fixed potential terminal.

[0078] In some examples, the filtering network is a capacitor connected between the test point and a fixed potential terminal to filter out high-frequency transient interference.

[0079] In other examples, the filtering network is an RC low-pass filter, comprising a series resistor and a parallel capacitor, used to suppress switching noise and improve measurement accuracy.

[0080] In some embodiments, the control module 4 is further configured to compare the measured value with the expected value and generate a comparison result; divide the measured value into a preset number of segment intervals according to the comparison result; the segment intervals correspond to different levels of process deviation and are used to measure the process status of the object to be measured 9.

[0081] In some examples, each segment interval corresponds to a process deviation level, which is used to characterize the process status of the test object 9.

[0082] In some embodiments, the device further includes a storage module 5 for storing the segment number of the segment interval in which the measured value is located; the segment number is used to be read during the power-on self-test or operation of the semiconductor chip, and the operating parameters of the semiconductor chip are adjusted according to the segment number to compensate for the process deviation of the test object 9.

[0083] In some examples, storage module 5 is a memory that, after completing a process deviation measurement, saves the segment number in a non-volatile or volatile manner for subsequent use. During the power-on self-test (POST) or runtime phase of the semiconductor chip, this segment number can be read by the system controller, firmware, or dedicated compensation circuitry and used to dynamically adjust the chip's operating parameters to compensate for process deviations and improve the consistency and reliability of circuit performance.

[0084] like Figure 9 As shown, according to a second embodiment of the present invention, a process deviation compensation device 8 is provided, including an embedded process deviation monitoring device 6 and a configuration module 7 as described in any of the above embodiments; the configuration module 7 is connected to the embedded process deviation monitoring device 6 and is used to acquire the process deviation and adjust the operating parameters of the semiconductor chip to compensate for the process deviation of the test object 9.

[0085] In some examples, the operating parameters include supply voltage, clock frequency, drive strength, reference voltage, or bias current; the configuration module 7 performs compensation operations during chip power-on self-test or normal operation to achieve real-time response to process fluctuations and performance optimization.

[0086] In some embodiments, the configuration module 7 is used to read the segment number stored in the device and adjust the operating parameters of the semiconductor chip according to the segment number; the segment number corresponds one-to-one with the segment interval of the measured value.

[0087] In some examples, due to the large number of objects under test (9) and circuits, and the fact that the current or voltage values ​​measured by the signal receiving module 3 are usually floating-point numbers, directly storing all the raw test data would occupy a large amount of storage space. To reduce storage overhead, this embodiment adopts a segmented encoding strategy.

[0088] Specifically, for each test object 9, its expected test value is known. The actual measured value is compared with the expected value, and it is divided into M levels according to a preset segmentation interval, with segment numbers 0 to M−1. Only the segment number to which the measured value belongs needs to be stored to characterize its degree of deviation. Each test object 9 only requires log2M bits of storage space, significantly reducing the amount of data.

[0089] like Figure 9As shown, in some embodiments, the process deviation compensation device 8 detects process deviations through an embedded process deviation monitoring device 6 and transmits the information to the configuration module 7. This module generates a control signal PMU_Cntl based on the received information to adjust the voltage VDDC output by the power management unit (PMU). This voltage supplies power to the digital circuit module (DIG) and SRAM to ensure they operate under suitable conditions. The system may also include a closed-loop feedback mechanism that dynamically adjusts VDDC by testing the operating states of the DIG and SRAM, thereby optimizing the overall system performance.

[0090] It's worth noting that VDDC is generated by the PMU and used to power the DIG. Typically, the PMU supports multiple adjustable levels for VDDC output, allowing its voltage to be dynamically adjusted within a certain range. When process monitoring detects that the device is running too fast, the PMU is controlled to reduce the VDDC voltage; if the device is running too slow, the VDDC voltage is increased to compensate for the performance deviation.

[0091] Furthermore, based on the segment number (0 to M−1) to which the measured value belongs, different voltage adjustment ranges can be set: for extremely fast devices, such as those with a segment number close to 0, VDDC is significantly reduced, resulting in a substantial decrease in power consumption; for slightly fast devices, such as those with a segment number close to the typical value, the voltage is slightly reduced to achieve fine optimization; for slow devices, VDDC is increased accordingly based on the segment number, with the increase ranging from minor to major, ensuring timing convergence and reliable operation. Through the above-mentioned hierarchical adjustment strategy, fast chips can reduce power consumption while meeting performance requirements, while slow chips can increase their operating speed, enhancing the overall performance consistency and reliability of the system.

[0092] like Figure 10 The example shown is a distribution chart of test values ​​for leakage current testing of a batch of chips. The horizontal axis represents the test values, and the vertical axis represents the frequencies corresponding to the test values. The curve exhibits a bell-shaped distribution, indicating that the test values ​​are symmetrically distributed around the expected values. By comparing the test values ​​with the expected values ​​and categorizing them into the corresponding sections, efficient data management and deviation analysis can be achieved.

[0093] The segmented intervals do not need to be equally spaced; they can be flexibly set according to the actual distribution characteristics of the measured values, process statistical laws, or calibration accuracy requirements. For different types of objects under test 9, such as transistors, resistors, or capacitors, the total number of segments M and the interval boundaries can be configured independently to achieve better quantization results.

[0094] In some examples, the embedded process deviation monitoring device 6 tests SRAM cells or SRAM arrays by measuring their operating current during read / write operations or their leakage current in standby mode, and comparing it with preset expected values ​​to generate segment number information (0 to M−1) reflecting the degree of process deviation. This segment number information is transmitted to the configuration module, which parses the deviation direction and magnitude based on the received segment number: if the operating current is too high or the leakage current is too high, the device is judged to be too fast, and the corresponding threshold voltage is too low; if the operating current is too low or the delay chain propagation delay is significantly increased, the device is judged to be too slow. Based on this judgment result, the configuration module dynamically adjusts the operating parameters of the semiconductor chip, specifically including adjusting the core power supply voltage VDDC, changing the clock frequency, and enabling or disabling some functional modules to achieve a balance between power consumption and performance. For example, when the device is detected to be too fast, the configuration module sends a command to the PMU to reduce the VDDC voltage level, reducing dynamic power consumption while ensuring correct functionality; when the device is detected to be too slow, the VDDC voltage is increased to enhance the driving capability and ensure critical path timing convergence. Furthermore, the configuration module can also use process deviation information for aging prediction and reliability management, tracking the deviation trends of the same chip at different stages of use over a long period, and triggering early warnings or initiating adaptive repair mechanisms in advance. Through these methods, this embodiment achieves closed-loop control from process deviation perception to system-level compensation, improving the chip's energy efficiency and operational stability throughout its entire lifecycle.

[0095] To address the challenges of a large number of objects under test and long testing times in large-scale integrated circuits, such as... Figure 11 As shown, the third embodiment provides a group testing method, which is applied to the embedded process deviation monitoring device 6 as described in the above embodiments, and includes the following steps: S1. Divide multiple devices under test into several groups. Devices in each group are of the same type or have similar electrical properties and share the same excitation module configuration. The excitation module configuration includes at least one of constant voltage, constant current, or frequency parameters. S2. Turn on the excitation module corresponding to the first group and keep it continuously conducting during the test of this group. S3. Close the switch of the current device under test and turn off the other switches. S4. Acquire the response signal through the signal receiving module and store the measured value. S5. Determine whether the test of this group is complete. If yes, proceed to S6. If no, return to S3 to test the next device. S6. Turn off the current excitation module and turn on the excitation module corresponding to the next group. S7. Repeat S3 to S5 to complete the test of subsequent groups.

[0096] In some examples, the LVT NMOS devices in the chip are divided into two groups, using a constant voltage of 0.8V for the first group and a constant voltage of 1.2V for the second group. During testing, the 0.8V excitation is activated first, and all LVT NMOS devices are tested sequentially. After completion, the excitation is switched to 1.2V, and then the HVT PMOS devices are tested. No changes to the excitation module are required within each group; all tests are completed simply by switching the excitation module. This method improves testing efficiency in mass production by grouping the devices under test and sharing the same excitation module configuration within each group, reducing latency caused by frequent excitation module switching.

[0097] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0098] The above description of the embodiments is intended to enable those skilled in the art to understand and apply the present invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, the present invention is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope and spirit of the invention are within the scope of the present invention.

Claims

1. An inline process variation monitoring device, characterized by, The integrated semiconductor chip comprises an excitation module, N groups of switch components, a signal receiving module and a control module, wherein N is a positive integer; The excitation module comprises at least one of a current source and a voltage source, and is configured to provide an excitation signal to a to-be-tested object so that the to-be-tested object outputs a response signal; Each group of switch components is connected to one to-be-tested object, and comprises a fixed potential end, a first switch and a second switch; a first end of the first switch is connected to a first test point, and a first end of the second switch is connected to a second test point; the first test point is connected to the excitation module; at least one of the first test point and the second test point is connected to the signal receiving module; a second end of the first switch and a second end of the second switch are commonly connected to a first end of the to-be-tested object; a second end of the to-be-tested object is connected to the fixed potential end; The control module is configured to control the on-off of the first switch and the second switch in each group of switch components, so as to selectively connect the excitation module and the signal receiving module to one of the N to-be-tested objects; The signal receiving module comprises at least one of a current measurement unit and a voltage measurement unit, and is configured to receive the response signal and measure the response signal to obtain a measurement value; the measurement value is used to calculate a process deviation of the to-be-tested object.

2. The apparatus of claim 1, wherein, When the current source and the voltage measurement unit are in a working state at the same time, the current source is configured to provide a current excitation signal to the to-be-tested object, so that the to-be-tested object outputs a voltage response signal; the voltage measurement unit is configured to acquire the voltage response signal and measure a voltage measurement value.

3. The apparatus of claim 1, wherein, When the voltage source and the current measurement unit are in a working state at the same time, the voltage source is configured to provide a voltage excitation signal to the to-be-tested object, so that the to-be-tested object outputs a current response signal; the current measurement unit is configured to acquire the current response signal and measure a current measurement value.

4. The apparatus of claim 1, wherein, The first switch and / or the second switch adopt a CMOS switch structure, and the CMOS switch structure comprises: a first transistor and a second transistor, the first transistor and the second transistor are opposite in conduction type; a gate of the first transistor is connected to the control module through a first control signal line, a source of the first transistor is connected to a first end of the excitation module, and a drain of the first transistor is connected to a first end of the to-be-tested object; a gate of the second transistor is connected to the control module through a second control signal line, a source of the second transistor is connected to the first end of the excitation module, and a drain of the second transistor is connected to the first end of the to-be-tested object; wherein the first control signal line and the second control signal line are used to transmit two-way signals which are complementary signals.

5. The apparatus of claim 2, wherein, The to-be-tested object is an N-type transistor, a gate and a drain of the N-type transistor are short-circuited to the second end of the first switch, and a source of the N-type transistor is connected to the fixed potential end; The excitation module is configured to provide a constant current as the excitation signal, and the signal receiving module is configured to measure the voltage measurement value; The control module calculates the process deviation according to a comparison result of the voltage measurement value and an expected voltage value.

6. The apparatus of claim 2, wherein, The to-be-tested object is a P-type transistor, a drain of the P-type transistor is connected to the fixed potential end, a gate of the P-type transistor is connected to the fixed potential end, and a source of the P-type transistor is connected to the second switch; The excitation module is configured to provide a constant current as an excitation signal, and the signal receiving module is configured to measure a voltage measurement value; The control module is configured to calculate the process deviation according to a comparison result of the voltage measurement value and an expected voltage value.

7. The apparatus of claim 2, wherein, The to-be-measured object is a resistor, one end of which is connected to a fixed potential terminal, and the other end of which is connected to the first switch and the second switch; The excitation module is configured to provide a constant current as an excitation signal, and the signal receiving module is configured to measure a voltage measurement value; The control module is configured to calculate the process deviation according to a comparison result of the voltage measurement value and an expected voltage value.

8. The apparatus of claim 2, wherein, The to-be-measured object is a capacitor, one end of which is connected to a fixed potential terminal, and the other end of which is connected to the first switch and the second switch; The excitation module is configured to provide a constant current as an excitation signal, and the signal receiving module is configured to measure a voltage measurement value; The control module is configured to calculate the process deviation according to a comparison result of the voltage measurement value and an expected voltage value. The to-be-measured object is an N-type transistor, the source of which is connected to the fixed potential terminal, the gate of which is connected to the fixed potential terminal, and the drain of which is connected to the second end of the first switch; 9. The apparatus of claim 3, wherein, The excitation module is configured to provide a constant voltage as an excitation signal, and the signal receiving module is configured to measure a current flowing through the to-be-measured object through the first switch to obtain a current measurement value; The control module is configured to calculate the process deviation according to a comparison result of the current measurement value and an expected current value. The to-be-measured object is a P-type transistor, the drain of which is connected to a fixed potential terminal, and the gate and the source of which are short-circuited to the second end of the first switch; 10. The apparatus of claim 3, wherein, The excitation module is configured to provide a constant voltage as an excitation signal, and the signal receiving module is configured to measure a current flowing through the to-be-measured object through the first switch to obtain a current measurement value; The control module is configured to calculate the process deviation according to a comparison result of the current measurement value and an expected current value. The device further comprises a filter network connected to the first test point and / or the second test point, and the other end of the filter network is connected to the fixed potential terminal; the filter network is configured to filter out switch transient noise.

11. The apparatus of claim 1, wherein, The control module is further configured to compare the measurement value with an expected value to generate a comparison result; divide the measurement value into a plurality of preset segmented intervals according to the comparison result; and the segmented intervals correspond to different levels of process deviation, and are used to measure the process state of the to-be-measured object.

12. The apparatus of claim 1, wherein, The device further comprises a storage module configured to store a segment number of the segmented interval in which the measurement value is located; the segment number is used to be read during a power-on self-test or operation of the semiconductor chip, and the working parameters of the semiconductor chip are adjusted according to the segment number to compensate for the process deviation of the to-be-measured object.

13. The apparatus of claim 12, wherein, The device comprises the in-line process deviation monitoring device and the configuration module according to any one of claims 1 to 13; and the configuration module is connected to the in-line process deviation monitoring device, and is configured to obtain the process deviation, and adjust the working parameters of the semiconductor chip to compensate for the process deviation of the to-be-measured object.

14. A process variation compensation apparatus, characterized by, ​ 15. The apparatus of claim 14, wherein, The configuration module is configured to read a segment number stored in the device, and adjust the working parameter of the semiconductor chip according to the segment number; the segment number corresponds to a segmented interval of the measurement value one by one.

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