Automatic alarm method and system for integrated circuit test

Abstract

The invention discloses an integrated circuit test automatic alarm method and system, and belongs to the technical field of computers. The method comprises the following steps: acquiring multi-dimensional data in an integrated circuit test process; wherein the multi-dimensional data comprises test resource data, environment interference data and chip test data; inputting the multi-dimensional data into a pre-constructed fusion algorithm to obtain a test expected value; and under the condition that the performance data of the to-be-tested chip does not meet the test expectation value, generating alarm prompt information. According to the technical scheme, the test resource data, the environment interference data, the chip test data and other multi-dimensional data are collected and input into the pre-constructed fusion algorithm to obtain the test expected value, and the alarm prompt information is generated when the performance data of the to-be-tested chip do not meet the expected value. The technical effects that the alarm accuracy is improved, the universality of the method is enhanced, potential risks are effectively captured, and therefore the chip testing quality and efficiency are guaranteed can be achieved.

Description

Technical Field

[0001] This application belongs to the field of computer technology, specifically relating to an automatic alarm method and system for integrated circuit testing. Background Technology

[0002] With the rapid development of integrated circuit technology, chip complexity is constantly increasing, placing ever higher demands on the accuracy and timeliness of the testing process. As a crucial step in ensuring chip quality, integrated circuit testing requires real-time monitoring and anomaly warning systems to prevent substandard products from entering the market.

[0003] In existing technologies, integrated circuit test alarms are mostly based on single-dimensional data judgment, such as triggering an alarm by whether parameters such as chip operating voltage or current exceed a fixed threshold.

[0004] These practices have obvious drawbacks: on the one hand, they ignore the impact of test resources on chip testing, as well as the huge differences between test scenarios and usage scenarios, which leads to the problem that the test passes but the chip cannot be used in the usage scenario; on the other hand, fixed alarm thresholds cannot adapt to the differences in different chip models and test scenarios, have poor universality, and are difficult to capture the potential risks brought about by subtle fluctuations in parameters, thus affecting test efficiency and accuracy. Summary of the Invention

[0005] The purpose of this application is to provide an automatic alarm method and system for integrated circuit testing. The aim is to address the problems of existing integrated circuit testing alarm methods, which rely on single-dimensional data for judgment, ignore the impact of test resources and differences between test and usage scenarios, leading to false alarms, missed alarms, poor versatility, and difficulty in capturing potential risks. By collecting multi-dimensional data such as test resource data, environmental interference data, and chip test data, and inputting it into a pre-built fusion algorithm to obtain the expected test value, an alarm message is generated when the performance data of the chip under test does not meet this expected value. This improves alarm accuracy, enhances method versatility, and effectively captures potential risks, thereby ensuring the quality and efficiency of chip testing.

[0006] In a first aspect, embodiments of this application provide an automatic alarm method for integrated circuit testing, the method comprising: Collect multi-dimensional data during the integrated circuit testing process; wherein, the multi-dimensional data includes test resource data, environmental interference data, and chip test data; The multi-dimensional data is input into a pre-built fusion algorithm to obtain the expected test value; If the performance data of the chip under test does not meet the expected test values, an alarm message will be generated.

[0007] Furthermore, the multi-dimensional data collected during the integrated circuit testing process includes: Collect test resource data, which includes test task type, test task priority, test duration, and test step sequence; Collect environmental interference data, including ambient temperature, humidity, electromagnetic interference intensity, and power supply ripple coefficient. Collect chip test data, which includes chip operating voltage, operating current, signal transmission delay, and timing jitter parameters.

[0008] Furthermore, the method also includes: Determine test resource data based on test task type.

[0009] Furthermore, the construction process of the pre-built fusion algorithm includes: Collect historical test data, which includes historical test resource data, historical environmental interference data, historical chip test data, and corresponding chip pass / fail judgment results; Using historical test resource data and historical environmental interference data as input, and the pass index from historical chip test data as output, a fusion algorithm is trained. The fusion algorithm adopts a random forest or neural network model.

[0010] Furthermore, the step of generating an alarm message when the performance data of the chip under test does not meet the expected test value includes: If the fluctuation of the chip's operating voltage exceeds ±5% of the voltage stability threshold in the test expectation, a voltage abnormality alarm will be generated. If the chip's operating temperature exceeds the expected temperature threshold by 5°C, a temperature over-limit alarm will be generated. If the signal transmission delay exceeds the expected delay threshold of 10%, a timing anomaly alarm will be generated.

[0011] Furthermore, the method also includes: If the performance data of the chip under test does not meet the expected test value, an alarm prompt level is determined based on the difference between the performance data and the expected test value, as well as the type of the performance data itself, and an alarm prompt message is generated based on the alarm prompt level.

[0012] Secondly, embodiments of this application provide an automatic alarm system for integrated circuit testing, the system comprising: A multi-dimensional data acquisition module is used to acquire multi-dimensional data during the integrated circuit testing process; wherein, the multi-dimensional data includes test resource data, environmental interference data, and chip test data; The test expectation value calculation module is used to input the multi-dimensional data into a pre-built fusion algorithm to obtain the test expectation value; The alarm notification module is used to generate alarm notification information when the performance data of the chip under test does not meet the expected test value.

[0013] Furthermore, the multi-dimensional data acquisition module is specifically used for: Collect test resource data, which includes test task type, test task priority, test duration, and test step sequence; Collect environmental interference data, including ambient temperature, humidity, electromagnetic interference intensity, and power supply ripple coefficient. Collect chip test data, which includes chip operating voltage, operating current, signal transmission delay, and timing jitter parameters.

[0014] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0015] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0016] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0017] The technical solution provided in this application collects multi-dimensional data during the integrated circuit testing process. This multi-dimensional data includes test resource data, environmental interference data, and chip test data. The multi-dimensional data is input into a pre-built fusion algorithm to obtain a test expectation value. If the performance data of the chip under test does not meet the test expectation value, an alarm message is generated. This technical solution, by collecting multi-dimensional data such as test resource data, environmental interference data, and chip test data, inputting it into a pre-built fusion algorithm to obtain a test expectation value, and generating an alarm message when the performance data of the chip under test does not meet the expectation value, can achieve the technical effect of improving alarm accuracy, enhancing method versatility, and effectively capturing potential risks, thereby ensuring the quality and efficiency of chip testing. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the automatic alarm method for integrated circuit testing provided in Embodiment 1 of this application; Figure 2This is a schematic diagram of the integrated circuit testing automatic alarm system provided in Embodiment 2 of this application; Figure 3 This is a schematic diagram of the structure of the electronic device provided in Embodiment 3 of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but may also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0022] The automatic alarm method and system for integrated circuit testing provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0023] Example 1 Figure 1 This is a flowchart illustrating the automatic alarm method for integrated circuit testing provided in Embodiment 1 of this application. Figure 1As shown, the specific steps include the following: S101: Collect multi-dimensional data during the integrated circuit testing process; wherein, the multi-dimensional data includes test resource data, environmental interference data, and chip test data; First, the implementing entity of this solution can be an integrated circuit testing system or equipment. This equipment can be a smart terminal device, such as a desktop computer, laptop computer, tablet computer, or smartphone, or a server, or other automatic alarm devices used for testing and the testing process.

[0024] The integrated circuit testing process refers to the entire process of the chip under test from power-on startup and functional verification to performance evaluation. It covers the parameter acquisition and status monitoring of the chip under different operating conditions, such as the high and low temperature performance testing process of MCU (Micro Controller Unit) chips in the automotive electronics field.

[0025] Multi-dimensional data refers to a collection of multiple types of data that can reflect the test status of integrated circuits. By collecting multi-dimensional data, the influencing factors in the test process can be fully captured, avoiding abnormal misjudgments or omissions caused by a single data dimension.

[0026] Test resource data refers to resource configuration and process information related to the execution of test tasks, such as the functional test task types and task priority rankings for a certain batch of chips.

[0027] Environmental interference data refers to data on external factors in the testing environment that may affect the chip testing results, such as temperature fluctuations and electromagnetic radiation intensity in the testing laboratory.

[0028] Chip test data refers to core parameter data that directly reflects the working status and performance of the chip under test, such as the chip's real-time operating voltage and signal transmission delay during operation.

[0029] In this solution, the multi-channel data acquisition module of the test system performs the task. This module is equipped with various sensors and data interfaces. For example, it acquires chip test data through a voltage sensor, acquires environmental interference data through a temperature and humidity sensor, and exports test resource data through a test task management system. The acquisition frequency can be set according to test requirements. For example, environmental interference data can be acquired at a frequency of 1 time / second, and chip test data can be acquired at a frequency of 10 times / second.

[0030] S102: Input the multi-dimensional data into a pre-built fusion algorithm to obtain the expected test value; Among them, the pre-built fusion algorithm refers to a mathematical model that is trained based on historical test data and can perform comprehensive analysis and prediction of multi-dimensional test data, such as a test data fusion model built based on the random forest algorithm.

[0031] The expected value of the test refers to the range of parameters and performance indicators that the chip under test should achieve under normal working conditions, as predicted by the fusion algorithm based on the multi-dimensional input data. For example, the expected range of the working voltage of a certain type of chip at 25℃ is 3.2V-3.4V.

[0032] This solution can be implemented through the data transmission interface of the test system. The collected multi-dimensional data is encapsulated in a preset format (such as JSON) and transmitted to the server deploying the fusion algorithm. Data transmission latency is controlled within 100ms to ensure real-time processing by the algorithm. The fusion algorithm performs feature extraction, weight allocation, and comprehensive calculations on the input multi-dimensional data. For example, by combining the task type in the test resource data and the temperature value in the environmental interference data, it calculates the reasonable expected range of the chip test data and finally outputs the expected test value.

[0033] S103: If the performance data of the chip under test does not meet the expected test value, generate an alarm message.

[0034] Among them, the performance data of the chip under test refers to the real-time performance parameters and status data generated by the chip under test during the actual testing process, such as the actual operating current and timing jitter value of the chip when executing a specific instruction.

[0035] Alarm messages are notifications generated by the system when an abnormality occurs during chip testing. These messages include the type of abnormality, abnormal parameters, and suggested handling. For example, a message might say, "The chip's operating voltage exceeds the expected range. The current voltage is 3.6V. It is recommended to check the power supply module."

[0036] This solution can be executed by the anomaly detection module of the testing system. This module compares the performance data of the chip under test with the expected test value in real time. For example, if the chip's operating current performance data is 150mA, while the expected test value range is 100mA-120mA, it is determined that the expected value is not met. After determining that the performance data does not meet the expected test value, the system's alarm information generation module automatically matches the corresponding alarm template according to the anomaly type, fills in the anomaly parameters and timestamp, and generates an alarm prompt message, which can be pushed through system interface pop-ups, SMS, or email.

[0037] The technical solution provided in this embodiment achieves accurate identification and real-time early warning of integrated circuit testing anomalies through the synergistic effect of multi-dimensional data acquisition, fusion algorithm analysis, and automatic alarm. For example, in industrial control chip testing, if only chip test data is collected, abnormal chip current caused by excessively high ambient temperature may be misjudged as a chip malfunction. However, by collecting environmental interference data and inputting it into the fusion algorithm, a more realistic test expectation value can be obtained, significantly reducing the anomaly misjudgment rate. Simultaneously, the automatic alarm mechanism can notify test personnel immediately when anomalies occur during chip testing, preventing test accidents or defective chips from entering the market due to untimely manual monitoring.

[0038] In this embodiment, optionally, the acquisition of multi-dimensional data during the integrated circuit testing process includes: Collect test resource data, which includes test task type, test task priority, test duration, and test step sequence; Collect environmental interference data, including ambient temperature, humidity, electromagnetic interference intensity, and power supply ripple coefficient. Collect chip test data, which includes chip operating voltage, operating current, signal transmission delay, and timing jitter parameters.

[0039] Test task type refers to the classification of chip test tasks according to the test purpose. For example, functional test tasks, such as verifying whether the chip has achieved the preset function; performance test tasks, such as evaluating the chip's computing speed, power consumption and other performance indicators; and reliability test tasks, such as testing the chip's stability after long-term operation.

[0040] Test task priority refers to the ranking of the importance of multiple parallel test tasks. For example, the test task for chips used in medical devices is set as the highest priority to ensure the test progress of this type of chip.

[0041] Test duration refers to the time required to complete a test task. For example, the functional test task for a chip takes 30 minutes, and the performance test task takes 60 minutes.

[0042] The test step sequence refers to the specific operational flow order of performing a test task. For example, the step sequence of chip functional testing is: power-on initialization, instruction issuance, data acquisition, functional verification, and power-off.

[0043] The test environment temperature refers to the temperature value of the environment in which the chip under test is located during the test. For example, when testing in a high and low temperature test chamber, the test environment temperature can be adjusted within the range of -40℃ to 125℃.

[0044] Electromagnetic interference intensity refers to the degree to which electromagnetic radiation in the test environment interferes with chip testing. It is usually measured by electric field strength or magnetic field strength. For example, the electromagnetic interference intensity of a certain test environment is 20 dBμV / m.

[0045] The power supply ripple factor refers to the degree of fluctuation of the AC component in the power supply of the test system, reflecting the stability of the power supply. For example, the ripple factor of a certain test power supply is 0.1%.

[0046] Chip operating voltage refers to the power supply voltage required for a chip to operate normally. Different types of chips have different operating voltages. For example, the operating voltage of a mobile phone processor chip is usually 1.0V-1.2V.

[0047] Operating current refers to the current consumed by a chip during operation. For example, the operating current of a certain type of Bluetooth chip in data transmission mode is 20mA.

[0048] Signal transmission delay refers to the time required for signal transmission within a chip or between a chip and an external device. For example, the SPI (Serial Peripheral Interface) signal transmission delay of a certain chip is 50ns.

[0049] Timing jitter refers to the range of fluctuation in signal timing that deviates from the ideal time during transmission. For example, the timing jitter of a chip's clock signal is 10ps.

[0050] In this solution, the configuration information of all test tasks is recorded through the test task management system. Testers can use the system's export function to extract data such as test task type, priority, duration and step sequence by test batch or task number. For example, the resource data of test task number "TEST-2024-001" can be exported.

[0051] Temperature and humidity are collected by a temperature and humidity sensor at a frequency of 1 time per minute; electromagnetic interference intensity is collected by an electromagnetic interference detector at a frequency of 1 time per 5 minutes; power supply ripple coefficient is collected by a power supply ripple tester at a frequency of 1 time per 10 minutes. All collected data are uploaded to the test system database in real time.

[0052] The test fixture connects the chip under test to the test system. The data acquisition card acquires the chip's operating voltage through a voltage probe, acquires the operating current through a current probe, and acquires signal transmission delay and timing jitter parameters through an oscilloscope. The acquisition frequency is set according to the test items, for example, the operating voltage is acquired at a frequency of 10 times / second.

[0053] This technical solution makes data acquisition more targeted and standardized by clearly defining multi-dimensional data, avoiding incomplete test data caused by ambiguous data acquisition dimensions. For example, when collecting environmental interference data, it explicitly includes electromagnetic interference intensity and power supply ripple coefficient, which can effectively capture the impact of these two key interference factors on chip test results. When collecting chip test data, it covers signal transmission delay and timing jitter parameters, which can accurately assess the signal integrity of the chip. At the same time, detailed data classification facilitates the subsequent fusion algorithm to differentiate between different types of data, improves the accuracy of the calculation of expected test values, and provides more reliable data support for subsequent anomaly alarms.

[0054] In this embodiment, optionally, the method further includes: Determine test resource data based on test task type.

[0055] This solution can filter and match the corresponding test resource configuration information based on the specific type of test task, ensuring that the test resource data is highly consistent with the test task requirements. For example, for the radiation test task type of radio frequency chip, the corresponding test resource data can be determined.

[0056] Test resource data can include tag information related to test task execution, such as test task type, test task priority, test duration, and test step sequence.

[0057] This solution can be executed by the resource matching module of the testing system. For example, when the test task type is chip high-temperature aging test, the system automatically retrieves the standard test duration for this type of task from the corresponding relational database, such as 100 hours. It also retrieves the test step sequence, including high-temperature environment setting, chip power-on, continuous operation, parameter monitoring, post-aging performance testing, and recommended priorities, matching the resource data for this test task. If there are special customized test task types, testers can manually supplement or modify the resource data through the system interface to ensure the accuracy of the resource data.

[0058] This technical solution establishes a correlation between test task types and resource data, enabling rapid matching and determination of test resource data, thus significantly improving test preparation efficiency. For example, in chip mass production testing, when functional testing, performance testing, and reliability testing need to be performed simultaneously, the system can automatically determine the corresponding resource data based on different task types, eliminating the need for testers to manually configure each one, reducing manual operation time. Furthermore, resource data determined based on task type better meets test requirements, avoiding low test efficiency or test result deviations caused by unreasonable resource configuration. For instance, for performance testing tasks of high-precision ADC (Analog-to-Digital Converter) chips, determining a longer test duration and a more detailed sequence of test steps ensures the accuracy of test results.

[0059] In this embodiment, optionally, the construction process of the pre-built fusion algorithm includes: Collect historical test data, which includes historical test resource data, historical environmental interference data, historical chip test data, and corresponding chip pass / fail judgment results; Using historical test resource data and historical environmental interference data as input, and the pass index from historical chip test data as output, a fusion algorithm is trained. The fusion algorithm adopts a random forest or neural network model.

[0060] Historical test data refers to all data accumulated from integrated circuit tests completed over a period of time, including test records of different batches and models of chips. For example, automotive electronic chip test data from the past three years can be used as the basic data for training fusion algorithms.

[0061] Historical test resource data refers to data related to resource configuration in historical test tasks, such as the task priority and test duration of a certain batch of chip functional tests in 2023.

[0062] Historical environmental interference data refers to environmental factor data recorded during historical testing, such as environmental temperature changes and electromagnetic interference intensity during chip testing in 2023.

[0063] Historical chip test data refers to chip performance parameter data collected during historical tests, such as historical data on the operating voltage and signal transmission delay of a certain model of chip in 2023.

[0064] The qualification index refers to the parameter range and performance standard corresponding to the determination of chip qualification in historical chip test data. For example, the working current index of a certain model of chip is 80mA-100mA when it is qualified.

[0065] Random forest models, which train and predict data by constructing multiple decision trees, have strong resistance to overfitting and high prediction accuracy, such as the random forest fusion algorithm based on 100 decision trees.

[0066] Neural network models process and predict data through nonlinear transformations of multiple layers of neurons, such as neural network fusion algorithms using a 3-layer fully connected structure.

[0067] This solution can be executed by the historical data management module of the testing system. This module extracts all historical test records from the test database, including historical test resource data, historical environmental interference data, historical chip test data, and corresponding pass / fail judgment results. Simultaneously, it cleans the collected data, removing invalid and duplicate data to ensure data quality. The amount of data collected must meet the algorithm training requirements; for example, at least 10,000 valid historical test data records should be collected.

[0068] First, the cleaned historical test data is divided into training and validation sets in a 7:3 ratio. Then, historical test resource data and historical environmental interference data from the training set are used as input features, and the pass / fail indicators from the historical chip test data are used as output labels. This data is then fed into a random forest or neural network model for training. During training, the model parameters are adjusted in real time using the validation set until the model's prediction error on the validation set falls below a preset threshold, such as 5%, at which point the training of the fusion algorithm is complete.

[0069] This technical solution trains a fusion algorithm based on historical test data, enabling the algorithm to predict chip pass / fail indicators based on test resources and environmental interference data, significantly improving the accuracy of test expectation values. For example, the fusion algorithm built using a random forest model can effectively handle complex nonlinear relationships between multi-dimensional data, and can still output accurate test expectation values ​​when facing different test environments and resource configurations. At the same time, training with pass / fail indicators from historical chip test data as output ensures that the algorithm's predicted expectation values ​​meet actual pass / fail standards. In addition, two optional algorithm models provide flexible choices for different test scenarios. For example, when the amount of historical data is large and the data relationships are complex, choosing a neural network model can achieve higher prediction accuracy; when the algorithm's interpretability requirements are high, choosing a random forest model is easier to analyze the prediction logic, providing reliable algorithmic support for subsequent anomaly alarms.

[0070] In this embodiment, optionally, generating an alarm message when the performance data of the chip under test does not meet the expected test value includes: If the fluctuation of the chip's operating voltage exceeds ±5% of the voltage stability threshold in the test expectation, a voltage abnormality alarm will be generated. If the chip's operating temperature exceeds the expected temperature threshold by 5°C, a temperature over-limit alarm will be generated. If the signal transmission delay exceeds the expected delay threshold by more than 10%, a timing anomaly alarm will be generated.

[0071] The fluctuation range of the chip's operating voltage refers to the difference between the maximum and minimum values ​​of the chip's operating voltage during the test. For example, if the operating voltage of a chip fluctuates between 3.2V and 3.4V, the fluctuation range is 0.2V.

[0072] The voltage stability threshold refers to the upper or lower limit of the allowable stable range of the chip's operating voltage set in the test expectation. For example, if the voltage stability threshold of a chip is 3.3V, the allowable fluctuation range is determined based on this threshold.

[0073] Voltage anomaly alarm refers to the alarm message generated when the chip's operating voltage fluctuation exceeds the allowable range, such as "Chip operating voltage fluctuation reaches 8%, exceeding the ±5% threshold, indicating a voltage anomaly."

[0074] Chip operating temperature refers to the chip's own temperature during operation, typically collected by a temperature sensor attached to the chip's surface. For example, a chip's operating temperature during testing might be 65°C. Temperature threshold refers to the highest or lowest temperature allowed for normal chip operation as set in the expected test values. For example, a chip's temperature threshold might be 85°C. Over-temperature alarm is an alarm message generated when the chip's operating temperature exceeds the specified temperature threshold range. For example, "Chip operating temperature reaches 92°C, exceeding the 85°C threshold by 7°C, indicating an over-temperature condition."

[0075] The delay threshold refers to the maximum allowable signal transmission delay of a chip as set in the expected test values. For example, the signal transmission delay threshold of a certain chip is 50ns.

[0076] Timing anomaly alarms are alarm messages generated when the chip signal transmission delay exceeds the specified delay threshold, such as "Chip signal transmission delay reaches 65ns, exceeding the 50ns threshold by 30%, indicating a timing anomaly."

[0077] This solution can be executed by the voltage monitoring module of the test system. This module calculates the fluctuation range of the chip's operating voltage in real time and compares it with the voltage stability threshold in the test expectation. For example, if the voltage stability threshold is 3.3V, and the calculated fluctuation range is 3.3V × 6% = 0.198V, it is determined to exceed the ±5% threshold. When the voltage monitoring module determines that the voltage fluctuation range exceeds the limit, it automatically calls the voltage anomaly alarm template, fills in the current voltage fluctuation range, threshold range, and anomaly occurrence time, and generates an alarm message, such as "May 20, 2024, 14:30, the chip operating voltage fluctuation range reaches 6%, exceeding the ±5% threshold, there is a voltage anomaly, please check the power supply module," and pushes it to the test personnel through a system pop-up window. The temperature monitoring module of the test system calculates the difference between the real-time collected chip operating temperature and the temperature threshold in the test expectation. For example, if the temperature threshold is 85℃ and the current chip operating temperature is 91℃, the difference is 6℃, which is determined to exceed 5℃. When the temperature monitoring module determines that the temperature exceeds the limit, it calls the temperature over-limit alarm template, fills in the current temperature value, threshold, temperature difference, and abnormal time, and generates an alarm message, such as "May 20, 2024, 14:35, chip operating temperature reached 91℃, exceeding the 85℃ threshold by 6℃, indicating an over-limit temperature. Please check the heat dissipation system." Simultaneously, it sends an SMS to the test supervisor. The timing monitoring module of the test system calculates the percentage difference between the real-time signal transmission delay and the delay threshold. For example, if the delay threshold is 50ns and the current transmission delay is 56ns, the percentage difference is (56-50) / 50×100%=12%, which is determined to exceed 10%. It then calls the timing anomaly alarm template, fills in the current transmission delay, threshold, percentage difference, and abnormal time, and generates an alarm message, such as "May 20, 2024, 14:40, chip signal transmission delay reached 56ns, exceeding the 50ns threshold by 12%, indicating a timing anomaly. Please check the signal lines." Detailed anomaly information is recorded in the system log.

[0078] This technical solution achieves precise classification and alarm alerts for chip testing anomalies by clearly defining the judgment criteria and alarm generation rules for different types of anomalies. This facilitates testers in quickly locating the cause of anomalies and taking targeted measures. For example, for voltage anomalies, a ±5% fluctuation threshold is defined to avoid unnecessary alarms caused by minor voltage fluctuations, while ensuring that significant voltage anomalies are detected in a timely manner. For temperature over-limit, a 5°C difference standard is set to issue a warning before the chip temperature approaches a dangerous value, preventing chip damage due to high temperatures. For timing anomalies, a 10% percentage threshold is set to accommodate the differences in delay thresholds of different chips, ensuring the universality of alarm judgment. In addition, the classified alarm alerts enable testers to quickly distinguish the type of anomaly. For example, after receiving a voltage anomaly alarm, the power supply module can be checked first, and after receiving a temperature over-limit alarm, the heat dissipation system can be checked first, greatly improving the efficiency of anomaly handling.

[0079] In this embodiment, optionally, the method further includes: If the performance data of the chip under test does not meet the expected test value, an alarm prompt level is determined based on the difference between the performance data and the expected test value, as well as the type of the performance data itself, and an alarm prompt message is generated based on the alarm prompt level.

[0080] The difference between the performance data and the expected test value refers to the absolute or relative difference between the actual performance data of the chip under test and the expected test value calculated by the fusion algorithm. For example, if the chip's operating current performance data is 130mA and the expected test value range is 100mA-120mA, the absolute difference is 10mA and the relative difference is (130-120) / 120×100%≈8.3%.

[0081] The type of performance data refers to the parameter category to which the performance data belongs. Different types of performance data have different degrees of impact on the chip's operating state. For example, the chip's operating voltage is a core power supply parameter that has a great impact on the normal operation of the chip, while the signal transmission delay is a performance parameter and has a relatively smaller impact.

[0082] Alarm alert level: refers to the alarm level divided according to the severity of the abnormality. It is usually divided into three levels: Level 1 (urgent), Level 2 (important), and Level 3 (general). Different levels correspond to different alarm response mechanisms. For example, Level 1 alarms require immediate handling by testers, Level 2 alarms require handling within 1 hour, and Level 3 alarms can be handled after the test is completed.

[0083] The alarm level determination module of the testing system has a built-in rule table that maps difference ranges, data types, and alarm levels. For example, when the data type is the chip operating voltage and the relative difference between the displayed data and the expected test value exceeds 10%, it is determined as a Level 1 alarm; when the data type is signal transmission delay and the relative difference is between 5% and 10%, it is determined as a Level 2 alarm; when the data type is timing jitter parameters and the relative difference is between 3% and 5%, it is determined as a Level 3 alarm. In special cases, testers can manually adjust the determination rules through the system interface to ensure the rationality of the alarm level.

[0084] This technical solution introduces alarm level classification to achieve tiered response and management of chip testing anomalies, avoiding the distraction of test personnel and the neglect of important anomalies caused by indiscriminately pushing all anomaly alarms. For example, when a chip experiences a severe abnormality in operating voltage, an emergency push notification ensures that test personnel can handle it immediately, preventing chip damage or escalation of testing accidents. When a chip only experiences minor timing jitter, it is summarized through log recording, avoiding frequent disruptions to the normal work of test personnel. Simultaneously, alarm levels are determined based on differences and data types, making alarm level classification more objective and scientific. For example, stricter difference standards and higher alarm levels are set for anomalies in core chip power supply parameters, while relatively lenient standards are set for secondary performance parameters, ensuring that alarm resources are tilted towards critical anomalies, improving the overall efficiency and accuracy of test anomaly handling.

[0085] Example 2 Figure 2 This is a schematic diagram of the integrated circuit testing automatic alarm system provided in Embodiment 2 of this application. Figure 2 As shown, the system includes: The multi-dimensional data acquisition module 201 is used to acquire multi-dimensional data during the integrated circuit testing process; wherein, the multi-dimensional data includes test resource data, environmental interference data, and chip test data; The test expectation value calculation module 202 is used to input the multi-dimensional data into a pre-built fusion algorithm to obtain the test expectation value; The alarm notification module 203 is used to generate alarm notification information when the performance data of the chip under test does not meet the test expectation value.

[0086] In this embodiment, a multi-dimensional data acquisition module is used to collect multi-dimensional data during integrated circuit testing; wherein, the multi-dimensional data includes test resource data, environmental interference data, and chip test data; a test expectation value calculation module is used to input the multi-dimensional data into a pre-built fusion algorithm to obtain the test expectation value; and an alarm prompting module is used to generate an alarm prompting message when the performance data of the chip under test does not meet the test expectation value. This technical solution achieves accurate identification and real-time early warning of integrated circuit testing anomalies through the synergistic effect of multi-dimensional data acquisition, fusion algorithm analysis, and automatic alarm. For example, in industrial control chip testing, if only chip test data is collected, abnormal chip current caused by excessively high ambient temperature may be misjudged as a chip malfunction. However, by collecting environmental interference data and inputting it into the fusion algorithm, a more realistic test expectation value can be obtained, significantly reducing the anomaly misjudgment rate. At the same time, the automatic alarm mechanism can notify test personnel immediately when an anomaly occurs during chip testing, avoiding test accidents or unqualified chips entering the market due to untimely manual monitoring.

[0087] The automatic alarm system for integrated circuit testing in this application embodiment can be a system, or a component, integrated circuit, or chip in a terminal. The system can be a mobile electronic device or a non-mobile electronic device. For example, mobile electronic devices can be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc., while non-mobile electronic devices can be servers, network-attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This application embodiment does not impose specific limitations.

[0088] The automatic alarm system for integrated circuit testing in this application embodiment can be a system with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit it.

[0089] The integrated circuit testing automatic alarm system provided in this application embodiment can realize the various processes of the above embodiments, and will not be described again here to avoid repetition.

[0090] Example 3 like Figure 3 As shown, this application embodiment also provides an electronic device 300, including a processor 301, a memory 302, and a program or instructions stored in the memory 302 and executable on the processor 301. When the program or instructions are executed by the processor 301, they implement the various processes of the above-described integrated circuit test automatic alarm method embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0091] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0092] Example 4 This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described automatic alarm method for integrated circuit testing and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0093] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0094] Example 5 This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described automatic alarm method embodiment for integrated circuit testing, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0095] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0096] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element. Furthermore, it should be noted that the scope of the methods and systems in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0097] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0098] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0099] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the claims.

Claims

1. An automatic alarm method for integrated circuit testing, characterized in that, The method includes: Collect multi-dimensional data during the integrated circuit testing process; wherein, the multi-dimensional data includes test resource data, environmental interference data, and chip test data; The multi-dimensional data is input into a pre-built fusion algorithm to obtain the expected test value; If the performance data of the chip under test does not meet the expected test values, an alarm message will be generated.

2. The automatic alarm method for integrated circuit testing according to claim 1, characterized in that, The multi-dimensional data collected during the integrated circuit testing process includes: Collect test resource data, which includes test task type, test task priority, test duration, and test step sequence; Collect environmental interference data, including ambient temperature, humidity, electromagnetic interference intensity, and power supply ripple coefficient. Collect chip test data, which includes chip operating voltage, operating current, signal transmission delay, and timing jitter parameters.

3. The automatic alarm method for integrated circuit testing according to claim 2, characterized in that, The method further includes: Determine test resource data based on test task type.

4. The automatic alarm method for integrated circuit testing according to claim 1, characterized in that, The construction process of the pre-built fusion algorithm includes: Collect historical test data, which includes historical test resource data, historical environmental interference data, historical chip test data, and corresponding chip pass / fail judgment results; Using historical test resource data and historical environmental interference data as input, and the pass index from historical chip test data as output, a fusion algorithm is trained. The fusion algorithm adopts a random forest or neural network model.

5. The automatic alarm method for integrated circuit testing according to claim 1, characterized in that, When the performance data of the chip under test does not meet the expected test value, an alarm message is generated, including: If the fluctuation of the chip's operating voltage exceeds ±5% of the voltage stability threshold in the test expectation, a voltage abnormality alarm will be generated. If the chip's operating temperature exceeds the expected temperature threshold by 5°C, a temperature over-limit alarm will be generated. If the signal transmission delay exceeds the expected delay threshold of 10%, a timing anomaly alarm will be generated.

6. The automatic alarm method for integrated circuit testing according to claim 1, characterized in that, The method further includes: If the performance data of the chip under test does not meet the expected test value, an alarm prompt level is determined based on the difference between the performance data and the expected test value, as well as the type of the performance data itself, and an alarm prompt message is generated based on the alarm prompt level.

7. An automatic alarm system for integrated circuit testing, characterized in that, The system includes: A multi-dimensional data acquisition module is used to acquire multi-dimensional data during the integrated circuit testing process; wherein, the multi-dimensional data includes test resource data, environmental interference data, and chip test data; The test expectation value calculation module is used to input the multi-dimensional data into a pre-built fusion algorithm to obtain the test expectation value; The alarm notification module is used to generate alarm notification information when the performance data of the chip under test does not meet the expected test value.

8. The automatic alarm system for integrated circuit testing according to claim 7, characterized in that, The multi-dimensional data acquisition module is specifically used for: Collect test resource data, which includes test task type, test task priority, test duration, and test step sequence; Collect environmental interference data, including ambient temperature, humidity, electromagnetic interference intensity, and power supply ripple coefficient. Collect chip test data, which includes chip operating voltage, operating current, signal transmission delay, and timing jitter parameters.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the automatic alarm method for integrated circuit testing as described in any one of claims 1-6.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the automatic alarm method for integrated circuit testing as described in any one of claims 1-6.

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