A voltage-calibrated distributed digital low-dropout linear regulator

Abstract

This application relates to a distributed digital low-dropout linear regulator (DLDO) with voltage calibration, belonging to the field of integrated circuit power management technology. This distributed digital low-dropout linear regulator employs a master-slave dual-loop control architecture. The master loop provides a rapid response to the voltage sampling feedback of each local DLDO, thereby achieving fast and high-precision voltage regulation in the power network. The calibration loop analyzes the shift register values ​​of the control power transistor groups in each local DLDO to obtain the current supply to the load, and sequentially calibrates the reference voltage in each local DLDO to change the sampling point voltage. This, in turn, adjusts the load current supply based on the circulating current caused by uneven power network operation, thus achieving accurate and uniform current supply.

Description

Technical Field

[0001] This application relates to the field of integrated circuit power management technology, and in particular to a distributed digital low-dropout linear regulator with voltage calibration. Background Technology

[0002] With the development of multi-core processors and system-on-a-chip (SoC), on-chip power management faces increasingly severe challenges. Providing stable, accurate, and dynamically adjustable supply voltages for various functional modules has become crucial. While dynamic voltage frequency scaling (DPMS) technology can effectively optimize power consumption, it places higher demands on the response speed and regulation accuracy of voltage regulators. Digital low-dropout linear regulators (DLDOs) are gradually becoming the preferred solution for on-chip power management due to their good compatibility with advanced CMOS (Complementary Metal-Oxide-Semiconductor) processes and ease of integration. However, when a single DLDO is used to power a large-scale power grid, the IR voltage drop generated by the current on the grid metal interconnects can lead to severe voltage unevenness at the load. Furthermore, the feedback mechanism of a single sensing point cannot detect voltage errors in non-sensing areas, resulting in decreased regulation accuracy, and the long feedback path significantly slows down transient response speed.

[0003] To overcome the aforementioned problems, a distributed DLDO architecture was proposed. This architecture distributes multiple DLDO cells in an array on the power grid, reducing IR voltage drop and accelerating local response by supplying power from the nearest point. Early distributed DLDOs used independent control, meaning each DLDO cell had its own complete feedback loop. However, this approach suffers from inherent process mismatches in the comparators, reference voltage sources, and other circuits within each loop, leading to inconsistent static operating points among the DLDO cells. This results in severe load unevenness and static errors, failing to achieve uniform power supply. Subsequent research has led to technical solutions employing a global control architecture, which uses a single central regulator to manage all LDLDO (local DLDO) cells, aiming to improve current density and distribution consistency. Such architectures are typically based on single-point voltage sampling or multi-point voltage sampling and averaging methods. All LDLDO control signals are generated based on the same sampling results, resulting in each LDLDO outputting the same current value. However, in the presence of non-uniform power networks, unbalanced loads, or process mismatches, this architecture struggles to achieve uniform power supply to the voltage network, leading to an imbalance where a few LDLDOs are under heavy load while the majority are under light load.

[0004] Therefore, there is an urgent need in this field for a distributed DLDO that can achieve fast and high-precision voltage regulation and accurate and uniform current distribution in large-scale power networks. Summary of the Invention

[0005] Therefore, it is necessary to provide a distributed digital low-dropout linear regulator with voltage calibration to address the aforementioned technical problems.

[0006] A distributed digital low-dropout linear regulator with voltage calibration includes a fully digital voltage calibration controller and multiple local DLDOs connected in parallel to the same power network. The multiple local DLDOs are evenly arranged on the power network, each local DLDO supplies power to its adjacent load, and the connection node between them serves as a voltage sampling point; any two adjacent voltage sampling points are connected by a wire with parasitic resistance.

[0007] Each local DLDO is connected to its corresponding sampling point to form a main loop. Each main loop is used to compare the voltage of the corresponding sampling point with the reference voltage. Based on the comparison result, a control signal is generated to adjust the conduction level of the power transistor group in the local DLDO, thereby stabilizing the sampling point voltage to the reference voltage. The reference voltage is obtained by digital-to-analog conversion of the reference voltage by the digital-to-analog converter in the local DLDO. All local DLDOs share the same reference voltage.

[0008] The all-digital voltage calibration controller, together with multiple local DLDOs, forms a calibration loop. The calibration loop is used to acquire the shift register value of the control power transistor group conduction scale in each local DLDO via the data line to obtain the current supply status to the load. The all-digital voltage calibration controller compares the individual shift register value with the calculated average value, generates a calibration signal based on the comparison result, and sends the calibration signal to the corresponding local DLDO via the control line to control the level of the reference voltage output by the digital-to-analog converter. In turn, the magnitude of the sampling point voltage is adjusted by the change of the reference voltage, and the load current supply is adjusted by the circulating current generated when the sampling point voltage is inconsistent due to the parasitic resistance of the wires.

[0009] Furthermore, the local DLDO includes a high-precision comparator, a digital-to-analog converter, a thermometer code to binary code converter, a power transistor group, and two 10-bit shift registers, SR_C and SR_D; wherein, SR_D is used to control the power transistor group, and SR_C is used to control the digital-to-analog converter.

[0010] One end of the digital-to-analog converter is connected to a reference voltage, and the other end, under the control of SR_C, outputs a reference voltage to a high-precision comparator. SR_C is used to receive the calibration signal sent by the all-digital voltage calibration controller through the control line, and controls the level of the reference voltage output by the digital-to-analog converter according to the calibration signal.

[0011] The thermometer code to binary code converter is connected between the digital-to-analog converter and the SR_C. It is used to convert the thermometer code output by the digital-to-analog converter into binary code that is compatible with the SR_C, so that the SR_C can control the digital-to-analog converter.

[0012] The non-inverting input of the high-precision comparator is used to receive the reference voltage output by the digital-to-analog converter, and the inverting input of the high-precision comparator is used to receive the sampling point voltage corresponding to the local DLDO. By comparing the sampling point voltage with the reference voltage, a control signal is output to SR_D.

[0013] One end of SR_D is connected to the output of a high-precision comparator, and the other end is connected to a power transistor group. It is used to perform a shift operation according to the control signal and adjust the conduction level of the power transistor group according to the shift result.

[0014] The power transistor group is formed by multiple power transistors connected in parallel. It is used to adjust the sampling point voltage corresponding to the local DLDO to stabilize the reference voltage by changing the conduction scale. The sources of all power transistors are connected in parallel to the power supply voltage, the drains of all power transistors are connected in parallel to serve as the voltage output terminal of the local DLDO, and the gate of each power transistor is independently connected to the output terminal of SR_D.

[0015] Furthermore, when the sampling point voltage is lower than the reference voltage, the high-precision comparator outputs a high-level control signal to control SR_D to perform a left shift and increment operation, thereby controlling the conduction scale of the power transistor group to increase accordingly, and correspondingly increasing the sampling point voltage corresponding to the local DLDO; when the sampling point voltage is higher than the reference voltage, the high-precision comparator outputs a low-level control signal to control SR_D to perform a right shift and decrement operation, thereby controlling the conduction scale of the power transistor group to decrease accordingly, and correspondingly decreasing the sampling point voltage corresponding to the local DLDO.

[0016] Furthermore, the all-digital voltage calibration controller includes an averaging module, a digital comparator module, and three data selectors;

[0017] The averaging module is used to collect the SR_D value of the conduction scale of the control power transistor group in all local DLDOs through the data line and calculate the average value, and output the average value to the digital comparator module.

[0018] The first data selector is used to select a local DLDO to be adjusted and transmit the SR_D value of the local DLDO to be adjusted to the digital comparator module.

[0019] The digital comparator module compares the currently accessed SR_D value with the average value. Based on the comparison result, it outputs a calibration signal to the second or third data selector. The second or third data selector then sends the calibration signal to the corresponding local DLDO via the control line to control the level of the reference voltage output by the digital-to-analog converter. This, in turn, adjusts the magnitude of the sampling point voltage by changing the reference voltage, and regulates the load current supply by utilizing the circulating current generated when the sampling point voltage is inconsistent due to the parasitic resistance of the conductor.

[0020] Furthermore, the digital comparator module in the all-digital voltage calibration controller is specifically used for, including:

[0021] When the SR_D value is less than the average value, it indicates that the current supply of the local DLDO to the load is lower than the average level of the power network. At this time, the digital comparator module outputs the C_dac calibration signal to the second data selector. The second data selector selects to turn on the C_dac control line connected to the local DLDO to be adjusted. The C_dac calibration signal is sent to the shift register SR_C of the control digital-to-analog converter in the local DLDO to be adjusted through the C_dac control line. The SR_C controls the digital-to-analog converter to increase the reference voltage level. Then, according to the high-level reference voltage, the high-precision comparator outputs a high-level control signal. Based on the high-level control signal, the SR_D is controlled to perform a left shift and increment operation, which in turn increases the conduction scale of the power transistor group, increases the sampling point voltage of the local DLDO to be adjusted, increases the current supply of the local DLDO to the load, and through the parasitic resistance of the wires in the power network, the circulating current flowing from the high sampling point voltage to the low sampling point voltage is generated. At the same time, the current supply of other local DLDOs to the load is reduced accordingly, so that the output current of all local DLDOs tends to be uniform.

[0022] When the SR_D value is greater than the average value, it indicates that the current supply of the local DLDO to the load is higher than the average level of the power network. At this time, the digital comparator module outputs the Rst_sr calibration signal to the third data selector. The third data selector selects to turn on the Rst_sr control line connected to the local DLDO to be regulated. The Rst_sr calibration signal is output through the Rst_sr control line to reset the SR_C in the local DLDO to be regulated. The reset SR_C controls the digital-to-analog converter to restore the output reference voltage to the default value, thereby limiting the current supply capability of the local DLDO to be regulated. At this time, the output voltage of the local DLDO to be regulated does not actively decrease, but waits for the current supply of other local DLDOs to the load to increase. Then, through the circulating current in the power network from the high sampling point voltage to the low sampling point voltage, the current supply of the local DLDO to the load is reduced accordingly, so that the output current of all local DLDOs tends to be uniform.

[0023] Furthermore, the digital-to-analog converter and two shift registers in the local DLDO work together under the control of the clock signal CLK, and the three data selectors in the all-digital voltage calibration controller work together under the control of the clock signal CLK_cal.

[0024] Furthermore, the frequency of the clock signal CLK is higher than the frequency of the clock signal CLK_cal.

[0025] The aforementioned distributed digital low-dropout linear regulator (DLDO) with voltage calibration employs a master-slave dual-loop control architecture. The master loop provides rapid response to voltage sampling feedback from each local DLDO, enabling fast and high-precision voltage regulation of the power network. The calibration loop analyzes the shift register values ​​of the control power transistor groups in each local DLDO to obtain the current supply to the load, and sequentially calibrates the reference voltage in each local DLDO to change the sampling point voltage. This, in turn, adjusts the load current supply based on the circulating current caused by uneven power network operation, achieving accurate and uniform current supply. Furthermore, by comparing the value of a single shift register in the calibration loop with the average value, a calibration signal is generated to adjust the reference voltage of the local DLDO. This eliminates the need for complex analog circuitry, reduces noise interference, and enables dynamic balancing of the local DLDO output current, thus improving the power network's stability. In summary, this application effectively overcomes the problem of uneven output voltage of distributed DLDOs caused by process mismatch and IR voltage drop, as well as the problem of work imbalance caused by uneven output voltage of distributed DLDOs and concentrated load current, where a few LDLDOs are under heavy load while most LDLDOs are under light load. It realizes fast and high-precision voltage regulation and accurate and uniform current supply in large-scale power networks. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the logic topology of a distributed digital low-dropout linear regulator with voltage calibration in one embodiment;

[0027] Figure 2 This is a schematic diagram of the overall architecture of a distributed digital low-dropout linear regulator with voltage calibration in one embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] In one embodiment, a voltage-calibrated distributed digital low-dropout linear regulator (DLDO) is provided, illustrated using four local DLDOs as an example. The logic topology and overall architecture of this voltage-calibrated distributed digital low-dropout linear regulator are as follows: Figure 1 and Figure 2 As shown, the system includes a fully digital voltage calibration controller and four local DLDOs (LDLDO1-LDLDO4) connected in parallel to the same power network (VDD). The power network includes four loads of different sizes (Load1-Load4). The four local DLDOs are evenly distributed on the power network and connected one-to-one with the loads corresponding to their numbers. Each local DLDO prioritizes supplying power to the load corresponding to its number to quickly respond to dynamic changes in each load and to provide auxiliary power to other loads when the load current distribution is uneven. The connection nodes between each local DLDO and its corresponding load serve as voltage sampling points (Vout_1-Vout_4), and any two adjacent voltage sampling points are connected by a wire with parasitic resistance. Specifically, as... Figure 2 As shown, the parasitic resistance of the wire between any two adjacent sampling points is approximately 0.5. The parasitic resistance of the conductor causes circulating current when the sampling point voltages are inconsistent, leading to unbalanced power supply to each LDLDO. In severe cases, this can cause a few LDLDOs to operate under heavy load while most LDLDOs operate under light load, resulting in an imbalance. This application addresses this by adjusting the voltage and output current supply at each sampling point, ensuring that all LDLDOs operate in a balanced voltage and current state. Figure 1 and Figure 2 The " / " on the signal line indicates that the bit width of the signal line is greater than 1, meaning that multiple signals are transmitted simultaneously on the signal line. Figure 2 China DAC B <3:0> represents a 4-bit binary coded control signal used to control the digital-to-analog converter (DAC) in the local DLDO. T <9:0> represents the 10-bit temperature-encoded control signal output by SR_C used to control the digital-to-analog converter in the local DLDO, and D_avg<9:0> represents the 10-bit data obtained by averaging the output value of SR_D in the local DLDO used. T <9:0> indicates the SR_D output signal selected from the local DLDO by the first selector.

[0030] Each local DLDO is connected to its corresponding sampling point to form a main loop. Each main loop is used to compare the voltage at the corresponding sampling point with the reference voltage DAC_ref. Based on the comparison result, a control signal is generated to adjust the conduction level of the power transistor group in the local DLDO, thereby stabilizing the sampling point voltage at the reference voltage DAC_ref. The reference voltage DAC_ref is obtained by digital-to-analog conversion of the reference voltage Vref by the digital-to-analog converter (DAC) in the local DLDO. All local DLDOs share the same reference voltage Vref. The all-digital voltage calibration controller and multiple local DLDOs form a calibration loop. The calibration loop is used to acquire the shift register value of the control power transistor group conduction scale in each local DLDO through data lines D_cal_1 to D_cal_4 to obtain the current supply status to the load. In the all-digital voltage calibration controller, the individual shift register value is compared with the calculated average value. Based on the comparison result, a calibration signal is generated and sent to the corresponding local DLDO through control lines C_cal_1 to C_cal_4 to control the level of the reference voltage DAC_ref output by the digital-to-analog converter. The magnitude of the sampling point voltage is adjusted by the change of the reference voltage DAC_ref, and the load current supply is adjusted by the circulating current generated when the sampling point voltage is inconsistent due to the parasitic resistance of the wires.

[0031] Furthermore, the local DLDO includes a high-precision comparator, a digital-to-analog converter, a thermometer code to binary code converter (T2B), a power transistor array, and two 10-bit shift registers, SR_C and SR_D. SR_D controls the power transistor array, and SR_C controls the digital-to-analog converter. The local DLDO can provide a maximum output current of 200mA. Its main function is to effectively mitigate IR voltage drop and achieve fast, high-precision voltage regulation in response to local load changes.

[0032] The digital-to-analog converter (DAC) is connected to a reference voltage Vref at one end, and outputs a reference voltage DAC_ref to a high-precision comparator at the other end under the control of the SR_C. The SR_C receives calibration signals sent by the fully digital voltage calibration controller via control lines and controls the level of the reference voltage DAC_ref output by the DAC based on these signals. A thermometer code to binary code converter is connected between the DAC and the SR_C, converting the thermometer code output by the DAC into binary code compatible with the SR_C, enabling the SR_C to control the DAC. The non-inverting input of the high-precision comparator receives the reference voltage DAC_ref output by the DAC, and the inverting input receives the reference voltage DAC_ref output by the DAC. The corresponding sampling point voltage is compared with the reference voltage, and a control signal is output to SR_D. One end of SR_D is connected to the output of a high-precision comparator, and the other end is connected to a power transistor group. It is used to perform a shift operation according to the control signal and adjust the conduction level of the power transistor group according to the shift result. The power transistor group is formed by multiple power transistors connected in parallel. It is used to adjust the sampling point voltage corresponding to the local DLDO to stabilize it with the reference voltage by changing the conduction level. The sources of all power transistors are connected in parallel to the power supply voltage, the drains of all power transistors are connected in parallel to serve as the voltage output terminal of the local DLDO, and the gate of each power transistor is independently connected to the output terminal of SR_D and controlled by one bit output of SR_D.

[0033] Furthermore, when the sampling point voltage is lower than the reference voltage DAC_ref, the high-precision comparator outputs a high-level control signal, controlling SR_D to perform a left shift and increment operation (e.g., changing from 0000011111 to 0000111111), thereby increasing the conduction scale of the power transistor group (adding one more power transistor to conduct), and correspondingly increasing the sampling point voltage corresponding to the local DLDO. When the sampling point voltage is higher than the reference voltage DAC_ref, the high-precision comparator outputs a low-level control signal, controlling SR_D to perform a right shift and decrement operation, thereby decreasing the conduction scale of the power transistor group, and correspondingly decreasing the sampling point voltage corresponding to the local DLDO. The number of power transistors that are conducting is determined by the number of "1" bits in SR_D.

[0034] Furthermore, the all-digital voltage calibration controller includes an averaging module, a digital comparator module, and three data selectors; the averaging module is used to acquire the SR_D value (D_1) of the conduction scale of the control power transistor group in all local DLDOs via the data line. T To D_4 TThe average value D_avg is then output to the digital comparator module. The first data selector selects a local DLDO to be adjusted and transmits the SR_D value of the local DLDO to the digital comparator module. The digital comparator module compares the currently input SR_D value with the average value D_avg, and outputs a calibration signal to the second or third data selector based on the comparison result. The second or third data selector sends the calibration signal to the corresponding local DLDO through the control line to control the level of the reference voltage output by the digital-to-analog converter. This allows the magnitude of the sampling point voltage to be adjusted by the change in the reference voltage, and the load current supply is adjusted by the circulating current generated when the sampling point voltage is inconsistent due to the parasitic resistance of the conductor.

[0035] Furthermore, the digital comparator module in the all-digital voltage calibration controller is specifically used for, including:

[0036] When the SR_D value is less than the average value D_avg, it indicates that the current supply of the local DLDO to the load is lower than the average level of the power network. At this time, the digital comparator module outputs the C_dac calibration signal to the second data selector. The second data selector selects to turn on the C_dac control line connected to the local DLDO to be adjusted. The C_dac calibration signal is sent to the shift register SR_C of the control digital-to-analog converter in the local DLDO to be adjusted. SR_C controls the digital-to-analog converter to increase the reference voltage DAC_ref level. Then, based on the high-level reference voltage DAC_ref, the high-precision comparator outputs a high-level control signal. Based on the high-level control signal, SR_D is controlled to perform a left shift and increment operation, which in turn increases the conduction scale of the power transistor group, increases the sampling point voltage of the local DLDO to be adjusted, increases the current supply of the local DLDO to the load, and through the parasitic resistance of the wires in the power network, the circulating current flowing from the high sampling point voltage to the low sampling point voltage is generated. At the same time, the current supply of other local DLDOs to the load is reduced accordingly, so that the output current of all local DLDOs tends to be uniform.

[0037] When the SR_D value is greater than the average value D_avg, it indicates that the current supply of the local DLDO to the load is higher than the average level of the power network. At this time, the digital comparator module outputs the Rst_sr calibration signal to the third data selector. The third data selector selects to turn on the Rst_sr control line connected to the local DLDO to be adjusted. The Rst_sr calibration signal is output through the Rst_sr control line to reset the SR_C in the local DLDO to be adjusted. The reset SR_C controls the digital-to-analog converter to restore the output reference voltage DAC_ref to the default value, thereby limiting the current supply capability of the local DLDO to be adjusted. At this time, the output voltage of the local DLDO to be adjusted does not actively decrease, but waits for the current supply of other local DLDOs to the load to increase. Then, through the circulating current in the power network from the high sampling point voltage to the low sampling point voltage, the current supply of the local DLDO to the load is reduced accordingly, so that the output current of all local DLDOs tends to be uniform.

[0038] The fully digital voltage calibration controller achieves precise control of the output voltage of each LDLDO through the above mechanism, ultimately achieving a more accurate and uniform current distribution effect.

[0039] Furthermore, the digital-to-analog converter and two shift registers in the local DLDO work together under the control of the clock signal CLK, and the three data selectors in the all-digital voltage calibration controller work together under the control of the clock signal CLK_cal.

[0040] Furthermore, the frequency of the clock signal CLK is higher than the frequency of the clock signal CLK_cal.

[0041] The aforementioned distributed digital low-dropout linear regulator (DLDO) with voltage calibration employs a master-slave dual-loop control architecture. The master loop provides rapid response to voltage sampling feedback from each local DLDO, enabling fast and high-precision voltage regulation of the power network. The calibration loop analyzes the shift register values ​​of the control power transistor groups in each local DLDO to obtain the current supply to the load, and sequentially calibrates the reference voltage in each local DLDO to change the sampling point voltage. This, in turn, adjusts the load current supply based on the circulating current caused by uneven power network operation, achieving accurate and uniform current supply. Furthermore, by comparing the value of a single shift register in the calibration loop with the average value, a calibration signal is generated to adjust the reference voltage of the local DLDO. This eliminates the need for complex analog circuitry, reduces noise interference, and enables dynamic balancing of the local DLDO output current, thus improving the power network's stability. In summary, this application effectively overcomes the problem of uneven output voltage of distributed DLDOs caused by process mismatch and IR voltage drop, as well as the problem of work imbalance caused by uneven output voltage of distributed DLDOs and concentrated load current, where a few LDLDOs are under heavy load while most LDLDOs are under light load. It realizes fast and high-precision voltage regulation and accurate and uniform current supply in large-scale power networks.

[0042] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0043] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A distributed digital low-dropout linear voltage regulator with voltage calibration, characterized in that, The application relates to a full-digital voltage calibration controller and a plurality of local DLDOs connected in parallel to the same power supply network, wherein the plurality of local DLDOs are uniformly arranged on the power supply network, each local DLDO supplies power to its adjacent load, and the connection node between the two serves as a voltage sampling point; and any two adjacent voltage sampling points are connected through a wire with parasitic resistance. Each local DLDO is connected with the corresponding sampling point to form a main loop, each main loop is used for comparing the size of the corresponding sampling point voltage and a reference voltage, generating a control signal according to the comparison result, adjusting the on-scale of the power transistor group in the local DLDO, and thus adjusting the sampling point voltage to be stabilized at the reference voltage; wherein the reference voltage is obtained by digitally-analog converting a reference voltage through a digital-analog converter in the local DLDO, and all the local DLDOs share the same reference voltage. The full-digital voltage calibration controller and the plurality of local DLDOs form a calibration loop, the calibration loop is used for collecting the shift register value of the control power transistor group in each local DLDO through a data line to obtain the current supply condition of the load, comparing the single shift register value with the average value in the full-digital voltage calibration controller, generating a calibration signal according to the comparison result, sending the calibration signal to the corresponding local DLDO through a control line to control the gear of the reference voltage output by the digital-analog converter, and thus adjusting the size of the sampling point voltage through the change of the reference voltage and the circulating current generated when the sampling point voltages are inconsistent due to the parasitic resistance of the wire, and adjusting the load current supply. The local DLDO comprises a high-precision comparator, a digital-analog converter, a thermometer code to binary code converter, a power transistor group and two 10-bit shift registers, SR_C and SR_D; wherein SR_D is used for controlling the power transistor group, and SR_C is used for controlling the digital-analog converter. One end of the digital-analog converter is connected with a reference voltage, and the other end outputs a reference voltage to the high-precision comparator under the control of the SR_C; the SR_C is used for receiving the calibration signal sent by the full-digital voltage calibration controller through a control line, and controlling the gear of the reference voltage output by the digital-analog converter according to the calibration signal. The thermometer code to binary code converter is connected between the digital-analog converter and the SR_C, and is used for converting the thermometer code output by the digital-analog converter into binary code suitable for the SR_C, so that the SR_C can control the digital-analog converter. The non-inverting input end of the high-precision comparator is used for receiving the reference voltage output by the digital-analog converter, the inverting input end of the high-precision comparator is used for receiving the sampling point voltage corresponding to the local DLDO, and the high-precision comparator outputs a control signal to the SR_D by comparing the sampling point voltage with the reference voltage. ​ One end of the SR_D is connected with the output end of the high-precision comparator, and the other end is connected with the power transistor group, for performing a shift operation according to the control signal, and adjusting the on-scale of the power transistor group according to the shift result; The power transistor group is formed by a plurality of power transistors in parallel, for adjusting the sampling point voltage corresponding to the local DLDO to be stable at the reference voltage through the change of the on-scale; wherein the source levels of all the power transistors are connected in parallel to the power supply voltage, the drains of all the power transistors are connected in parallel to serve as the voltage output end of the local DLDO, and the gates of each power transistor are independently connected with the output end of the SR_D; The all-digital voltage calibration controller comprises a mean value module, a digital comparator module and three data selectors; The mean value module is used for collecting the SR_D values of the control power transistor groups in all the local DLDOs through the data line and calculating the average value, and outputting the average value to the digital comparator module; The first data selector is used for selecting a local DLDO to be adjusted, and transmitting the SR_D value of the local DLDO to be adjusted to the digital comparator module; The digital comparator module is used for comparing the size of the currently accessed SR_D value and the average value, and outputting a calibration signal to the second data selector or the third data selector according to the comparison result, so that the second data selector or the third data selector sends the calibration signal to the corresponding local DLDO through the control line, to control the gear of the reference voltage output by the digital-to-analog converter, and then adjust the load current supply through the circulating current caused by the inconsistency of the sampling point voltage due to the parasitic resistance of the wire; The digital comparator module in the all-digital voltage calibration controller is specifically used for comprising: When the SR_D value is less than the average value, it indicates that the current supply of the local DLDO to be adjusted to the load is lower than the average level of the power supply network, at this time, the digital comparator module outputs a C_dac calibration signal to the second data selector, the second data selector selects the C_dac control line connected with the local DLDO to be adjusted, and sends the C_dac calibration signal to the shift register SR_C of the control digital-to-analog converter in the local DLDO to be adjusted through the C_dac control line, so that the SR_C controls the digital-to-analog converter to increase the gear of the reference voltage, and then controls the high-precision comparator to output a high-level control signal based on the high-gear reference voltage, and controls the SR_D to perform a left shift and plus one operation based on the high-level control signal, so as to control the on-scale of the power transistor group to increase, increase the sampling point voltage corresponding to the local DLDO to be adjusted, increase the current supply of the local DLDO to be adjusted to the load, and at the same time, reduce the current supply of other local DLDOs to the load, so as to make the output currents of all the local DLDOs tend to be uniform. When the SR_D value is greater than the average value, it indicates that the current supply of the local DLDO to be adjusted to the load is higher than the average level of the power network, at this time the digital comparator module outputs the Rst_sr calibration signal to the third data selector, the third data selector selects the Rst_sr control line connected with the local DLDO to be adjusted, and outputs the Rst_sr calibration signal through the Rst_sr control line to reset the SR_C in the local DLDO to be adjusted, so that the output reference voltage of the digital-analog converter controlled by the reset SR_C is restored to the default value, thereby limiting the current supply capacity of the local DLDO to be adjusted, at this time the output voltage of the local DLDO to be adjusted is not actively reduced, but waits for the current supply of other local DLDOs to the load to increase, and through the circulating current in the power network from the high sampling point voltage to the low sampling point voltage, the current supply of the local DLDO to be adjusted to the load is correspondingly reduced, so that the output currents of all local DLDOs tend to be uniform.

2. The distributed digital low-dropout linear voltage regulator with voltage calibration of claim 1, wherein, When the sampling point voltage is lower than the reference voltage, the high-precision comparator outputs a high-level control signal to control the SR_D to perform left shift and add 1 operation, and then control the on-scale of the power transistor group to correspondingly increase, and correspondingly increase the sampling point voltage corresponding to the local DLDO; when the sampling point voltage is higher than the reference voltage, the high-precision comparator outputs a low-level control signal to control the SR_D to perform right shift and subtract 1 operation, and then control the on-scale of the power transistor group to correspondingly decrease, and correspondingly decrease the sampling point voltage corresponding to the local DLDO.

3. The distributed digital low-dropout linear voltage regulator with voltage calibration of claim 1, wherein, The digital-analog converter and the two shift registers in the local DLDO work cooperatively under the control of the clock signal CLK, and the three data selectors in the all-digital voltage calibration controller work cooperatively under the control of the clock signal CLK_cal.

4. The distributed digital low-dropout linear voltage regulator with voltage calibration of claim 3, wherein, The frequency of the clock signal CLK is higher than the frequency of the clock signal CLK_cal.

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