A method for processing a synchronization signal and an artificial intelligence chip

Abstract

The application provides a processing method of a synchronization signal and an artificial intelligence chip, and comprises the following steps: receiving a synchronization signal reading request with a prompt flag sent by a first processing core; confirming that the synchronization signal reading request is a synchronization operation according to the prompt flag; confirming that there is a storage address in an effective state, and determining whether there is a target storage address matched with a target program segment identifier and a target synchronization address identifier from the storage address in the effective state; if there is the target storage address, returning a synchronization success message to the first processing core when a synchronization value in the target storage address is the same as a target synchronization value, and adjusting the number of readable times in the target storage address; the time spent in the synchronization signal reading is greatly reduced, time is saved, delay is reduced, and the processing efficiency of the processing core is improved; and bandwidth can be saved, bandwidth waste is avoided, and the working efficiency of the whole system is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence chips, and in particular to a synchronization signal processing method and an artificial intelligence chip. BACKGROUND

[0002] Currently, in order to improve parallelism, maximize computing throughput and data exchange efficiency, an artificial intelligence chip generally adopts an architecture in which a plurality of processing cores are connected to a network-on-chip (NoC) through a crossbar and are connected to a memory unit or a cache unit through the network-on-chip. In the above architecture, when the plurality of processing cores need to be synchronized, a part of the processing cores need to perform a fence operation to ensure that data has been written to the memory unit or the cache unit and need to write a synchronization signal, and another part of the processing cores can start reading the data written to the memory unit or the cache unit only after reading the synchronization signal. However, the overall process takes a long time, which is not conducive to better supporting large-scale parallel computing, and thus the computing potential of the architecture of the plurality of processing cores cannot be fully utilized. SUMMARY

[0003] Embodiments of the present application provide a synchronization signal processing method and an artificial intelligence chip, which are used to reduce the time spent in reading or writing a synchronization signal, that is, to save time, reduce delay, and improve the processing efficiency of a processing core.

[0004] In a first aspect, embodiments of the present application provide a synchronization signal processing method, which includes:

[0005] receiving a synchronization signal reading request with a prompt flag sent by a first processing core, the synchronization signal reading request carrying a target program segment identifier, a target synchronization address identifier, and a target synchronization value;

[0006] confirming that the synchronization signal reading request is a synchronization operation according to the prompt flag;

[0007] confirming that there is a storage address in an active state, and determining whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier from the storage address in the active state;

[0008] if the target storage address exists, returning a synchronization success message to the first processing core when a synchronization value in the target storage address is the same as the target synchronization value, and adjusting a readable number of times in the target storage address; wherein the synchronization value represents the number of second processing cores that have completed data writing, and the readable number of times is the readable number of times of the synchronization value.

[0009] Optionally, when the readable times is adjusted to 0, the target storage address is adjusted to invalid state.

[0010] Optionally, when the synchronization value in the target storage address is different from the target synchronization value, a synchronization failure message is returned to the first processing core.

[0011] Optionally, further comprising: if the target storage address does not exist, distributing the synchronization signal read request to a data scheduling unit, and the synchronization signal read request is distributed to a storage unit by the data scheduling unit.

[0012] Optionally, further comprising: receiving a synchronization signal write request with a prompt flag sent by a second processing core, the synchronization signal write request carrying a program segment identifier, a synchronization address identifier, the synchronization value and the readable times;

[0013] According to the prompt flag, it is confirmed that the synchronization signal write request is a synchronization operation, an invalid storage address is allocated to the synchronization signal write request, the program segment identifier, the synchronization address identifier, the synchronization value and the readable times in the synchronization signal write request are written into the storage address, and the storage address is adjusted from invalid state to valid state.

[0014] Optionally, further comprising: distributing the synchronization signal write request to the data scheduling unit at the same time, and the synchronization signal write request is distributed to a storage unit by the data scheduling unit.

[0015] Optionally, further comprising: receiving an empty instruction of the target program segment identifier, determining whether there is a target storage address matching the target program segment identifier from the storage address in the valid state, and if there is, adjusting the target storage address to invalid state.

[0016] In a second aspect, an embodiment of the present application provides an artificial intelligence chip, comprising: a plurality of processing cores, a data distribution unit, a data scheduling unit and a storage unit;

[0017] The plurality of processing cores comprise: a first processing core; the first processing core is configured to read target data from the storage unit through the data distribution unit and the data scheduling unit, and before reading the target data, send a synchronization signal read request with a prompt flag;

[0018] The data distribution unit is configured to confirm that the synchronization signal read request is a synchronization operation according to the prompt flag, and confirm that there is a storage address in the valid state, and determine whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier from the storage address in the valid state.

[0019] The data distribution unit is further configured to confirm the existence of the target storage address, determine that the synchronization value in the target storage address is the same as the target synchronization value, return a synchronization success message to the first processing core, and adjust the number of read times in the target storage address.

[0020] Optionally, the data distribution unit is further configured to, when the number of read times is adjusted to 0, adjust the target storage address to an invalid state.

[0021] Optionally, the data distribution unit is further configured to, when the synchronization value in the target storage address is different from the target synchronization value, return a synchronization failure message to the first processing core.

[0022] Optionally, the plurality of processing cores further include a second processing core; the second processing core is configured to write the target data into the storage unit through the data distribution unit and the data scheduling unit, and send a synchronization signal write request with a prompt flag after confirming that the target data is written.

[0023] The data distribution unit includes a synchronization signal cache module, and the synchronization signal cache module includes a plurality of storage addresses; the storage addresses are configured to store the synchronization signal write request.

[0024] The data distribution unit is further configured to, according to the prompt flag, confirm that the synchronization signal write request is a synchronization operation, assign an invalid storage address to the synchronization signal write request, write the program segment identifier, the synchronization address identifier, the synchronization value and the number of read times in the synchronization signal write request into the storage address, and adjust the storage address from the invalid state to the valid state.

[0025] In a third aspect, an embodiment of the present application provides a computer device, including a memory, an artificial intelligence chip, and a computer program stored on the memory and executable on the artificial intelligence chip; the artificial intelligence chip implements the steps of the instruction synchronization method when executing the computer program.

[0026] The embodiments of the present application realize the writing and reading of target data through the mutual cooperation of the plurality of processing cores, the data distribution unit, the data scheduling unit and the storage unit, and through the data distribution unit confirming that the synchronization signal reading request is a synchronization operation according to the prompt flag, confirming that there is a valid storage address, determining whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier from the storage address in the valid state, and confirming that there is a target storage address, determining that the synchronization value in the target storage address is the same as the target synchronization value, returning a synchronization success message to the first processing core, and adjusting the number of readable times in the target storage address, that is, by determining whether the synchronization value is the same as the target synchronization value in the data distribution unit, the synchronization processing of the plurality of processing cores is realized, and the path of the first processing core reading the synchronization signal is shortened, that is, the first processing core can directly read the synchronization signal in the data distribution unit, and each first processing core avoids reading the synchronization signal from the storage unit through the data scheduling unit, thereby saving time and reducing the delay transmission of the synchronization signal, and improving the processing efficiency of the processing core.

[0027] And since the data distribution unit confirms that the synchronization signal reading request is a synchronization operation according to the prompt flag, it can be ensured that the data scheduling unit and the storage unit do not need to be accessed again, but the storage address in the data distribution unit is directly accessed, thereby saving the bandwidth of the data scheduling unit and the storage unit, avoiding bandwidth waste, and further improving the working efficiency of the entire system. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 Structure schematic diagrams of some artificial intelligence chips provided by the embodiments of the present application;

[0029] Figure 2 Structure schematic diagrams of some artificial intelligence chips provided by the embodiments of the present application;

[0030] Figure 3 Structure schematic diagrams of some artificial intelligence chips provided by the embodiments of the present application;

[0031] Figure 4 Structure schematic diagrams of some artificial intelligence chips provided by the embodiments of the present application;

[0032] Figure 5 Flow schematic diagrams of some synchronization signal processing methods provided by the embodiments of the present application;

[0033] Figure 6 Flow schematic diagrams of some synchronization signal processing methods provided by the embodiments of the present application;

[0034] Figure 7 Structure schematic diagrams of some artificial intelligence chips provided by the embodiments of the present application;

[0035] Figure 8 Structure schematic diagram of some computer devices provided by the embodiments of the present application. DETAILED DESCRIPTION

[0036] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments of the present application. And the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0037] Unless otherwise defined, technical terms or scientific terms used in the present application should be understood as their common meanings to those of ordinary skill in the art. The terms “first”, “second” and similar words used in the present application do not represent any order, number or importance, but are only used to distinguish different components. The terms “include” or “contain” and similar words mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, without excluding other elements or objects. In addition, in the description of the embodiments of the present application, the meaning of “a plurality of” is two or more, unless otherwise stated.

[0038] In the related art, as shown in Figure 1 To improve parallelism, maximize computing throughput and data exchange efficiency, the artificial intelligence chip 100 generally adopts an architecture in which multiple processing cores are connected to a Network-on-Chip (NoC) through a crossbar and to a memory unit or a cache unit through the Network-on-Chip. For example, when processing cores 1 and 2 execute a certain program instruction together, taking the processing core 1 as a producer and the processing core 2 as a consumer for example,

[0039] After the processing core 1 completes data calculation, it needs to write the data to the shared memory unit or cache unit through the crossbar and the Network-on-Chip, perform a Fence operation to ensure that the data is visible to the processing core 2, wait for a response to all write operations, and after confirming that the data has been persistently written to the memory unit or cache unit, write a synchronization signal to the memory unit or cache unit through the crossbar and the Network-on-Chip to indicate that the data is ready.

[0040] Similarly, the processing core 2 also needs to poll the synchronization signal from the memory unit or the cache unit through the crossbar and the network on chip, and once it is determined that the synchronization signal is set, it starts to read the data written by the processing core 1 into the shared memory unit or cache unit;

[0041] However, in the above scheme, at least the following problems exist:

[0042] I. The processing core 1 writes the synchronization signal into the memory unit or cache unit M through the crossbar and the network on chip, and the processing core 2 polls the synchronization signal from the memory unit or cache unit through the crossbar and the network on chip, which takes a long time, resulting in a delay in reading the synchronization signal written by the processing core 1 by the processing core 2, and further resulting in a reduction in the processing efficiency of the processing core;

[0043] II. And the processing core 2 needs to read the synchronization signal in a loop, which will frequently occupy the bandwidth of the network on chip, which may affect the memory access request of other processing cores; and in the cross-chip reading scenario, it may occupy a large amount of bandwidth between artificial intelligence chips, resulting in bandwidth waste and affecting the working efficiency of the entire system.

[0044] In view of the above problems, the present application provides an artificial intelligence chip 100, as shown in Figure 2 Specifically, it comprises a plurality of processing cores 10, a data distribution unit 20, a data scheduling unit 30 and a storage unit 40.

[0045] The plurality of processing cores 10 comprises first processing cores 101 and 102; the first processing cores 101 and 102 are configured to read target data from the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, and before reading the target data, send a synchronization signal reading request with a prompt flag;

[0046] The data distribution unit 20 is configured to confirm that the synchronization signal reading request is a synchronization operation according to the prompt flag, and confirm that there is a storage address in the active state, and determine whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier from the storage address in the active state;

[0047] The data distribution unit 20 is further configured to confirm that there is a target storage address, determine that the synchronization value in the target storage address is the same as the target synchronization value, return a synchronization success message to the first processing cores 101 and 102, and adjust the number of readable times in the target storage address.

[0048] The embodiments of the present application realize the writing and reading of target data through the mutual cooperation of the plurality of processing cores, the data distribution unit, the data scheduling unit and the storage unit, and through the data distribution unit confirming that the synchronization signal reading request is a synchronization operation according to the prompt flag, confirming that there is a valid storage address, determining whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier from the storage address in the valid state, and confirming that there is a target storage address, determining that the synchronization value in the target storage address is the same as the target synchronization value, returning a synchronization success message to the first processing core, and adjusting the number of readable times in the target storage address, that is, by determining whether the synchronization value and the target synchronization value are the same in the data distribution unit, the synchronization processing of the plurality of processing cores is realized, and the path of the first processing core reading the synchronization signal is shortened, that is, the first processing core can directly read the synchronization signal in the data distribution unit, avoiding each first processing core reading the synchronization signal from the storage unit through the data scheduling unit, thereby saving time and reducing the delay transmission of the synchronization signal, and improving the processing efficiency of the processing core.

[0049] And since the data distribution unit confirms that the synchronization signal reading request is a synchronization operation according to the prompt flag, it can be ensured that there is no need to access the data scheduling unit and the storage unit again, but to directly access the storage address in the data distribution unit, thereby saving the bandwidth of the data scheduling unit and the storage unit, avoiding bandwidth waste, and further improving the working efficiency of the entire system.

[0050] Illustratively, the artificial intelligence chip 100 can include a graphics processor (Graphics Processing Unit, referred to as GPU), a general-purpose graphics processor (General-Purpose Graphics Processing Units, referred to as GPGPU), a domain specific architecture (Domain Specific Architecture, referred to as DSA), etc.

[0051] Illustratively, the processing core 10 is highly specialized for artificial intelligence chips, and usually has the ability of artificial intelligence related calculations, such as matrix multiplication, convolution operation, etc. These operations are common calculation operations in artificial intelligence models, and a single processing core can achieve extremely high calculation density.

[0052] Exemplarily, the data distribution unit 20 includes a crossbar, which provides the shortest data path and extremely high internal bandwidth for a plurality of processing cores, memory controllers and other units in the artificial intelligence chip, and is a key to realize high-speed data sharing among cores. The crossbar provides non-blocking full connection between the ports connected thereto. This means that as long as the input and output ports are idle at any time, multiple data streams can pass through the crossbar simultaneously and in parallel without waiting.

[0053] Exemplarily, the data scheduling unit 30 can be a network-on-chip (NoC), which connects all components (including a processing core cluster, a high-bandwidth memory controller, an off-chip interface, etc.) on the artificial intelligence chip together, and constitutes a “system-on-chip network”. When the number of processing cores is very large, a fully connected crossbar will become physically (wiring complexity and power consumption) unfeasible, and the network-on-chip (for example, Mesh, Torus, Fat-Tree, etc.) provides a more scalable interconnection solution.

[0054] Exemplarily, the storage unit 40 can be a memory unit or a cache unit, both of which are used for storing data. Whether to use a memory unit or a cache unit can be adjusted according to design requirements, which is not limited here.

[0055] In the embodiment of the present application, the data distribution unit 20 is further configured to adjust the target storage address to an invalid state when the number of readable times is adjusted to 0.

[0056] In the embodiment of the present application, the data distribution unit 20 is further configured to return a synchronization failure message to the first processing cores 101 and 102 when the synchronization value in the target storage address is different from the target synchronization value.

[0057] In the embodiment of the present application, as shown in Figure 2 The plurality of processing cores 10 further include second processing cores 103 and 104, which are configured to write target data into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, and send a synchronization signal write request with a prompt flag after confirming that the target data is written.

[0058] In the embodiment of the present application, as shown in Figure 3 The data distribution unit 20 includes a synchronization signal cache module 201, which includes a plurality of storage addresses 2010, and the storage addresses 2010 are configured to store the synchronization signal write request.

[0059] The data distribution unit 20 is further configured to confirm that the synchronization signal write request is a synchronization operation according to the prompt flag, assign an invalid state storage address 2010 to the synchronization signal write request, write a program segment identifier (kernel id), a synchronization address identifier (addr), a synchronization value (value), and a readable number of times in the synchronization signal write request into the storage address 2010, and adjust the storage address 2010 from the invalid state to the valid state.

[0060] The application stores the synchronization signal write request in the storage address in the data distribution unit, so that the path of the second processing core writing the synchronization signal can be shortened, that is, the second processing core can directly write the synchronization signal in the data distribution unit, without the need to write the synchronization signal into the storage unit through the data scheduling unit again, so that time can be saved, the delay transmission of the synchronization signal is reduced, and the processing efficiency of the processing core is improved.

[0061] Moreover, since the storage address is only used for storing the synchronization signal write request, the area overhead is small and does not occupy much space.

[0062] For example, the program segment identifier (kernel id) is used to distinguish different computing tasks; the synchronization address identifier (addr) indicates the position of the data that needs to be written into the storage unit by the second processing core; the synchronization value (value) indicates the value to be written or increased; and the readable number of times indicates how many first processing cores need to read the synchronization signal.

[0063] For example, as shown in Figure 3 each row of the storage address 2010 is configured with a valid bit (valid); the values of the valid bits are different, and the meanings represented thereby are also different; for example, when the valid bit is 1, it indicates that the row of the storage address 2010 is in the valid state and cannot be used to store the synchronization signal write request; and when the valid bit is 0, it indicates that the row of the storage address 2010 is in the invalid state and can be used to store the synchronization signal write request.

[0064] In the embodiment of the application, as shown in Figure 4 the processor 50 is further configured to send a target program segment identifier emptying instruction to the data distribution unit 20.

[0065] The data distribution unit 20 can determine whether there is a target storage address matching the target program segment identifier from the storage address in the valid state according to the target program segment identifier emptying instruction, and adjust the target storage address to the invalid state if there is.

[0066] In addition to the above structure, the artificial intelligence chip in the application can also include other structures, which are not limited in the application.

[0067] The flow of the method for processing a synchronization signal provided by the present application will be described in detail below in combination with the architecture diagram of an artificial intelligence chip as shown in Figures 2 to 4 Figure 5 The method is executed by a data distribution unit in an artificial intelligence chip, and the method comprises the following steps:

[0068] S100, receiving a synchronization signal reading request with a prompt flag sent by a first processing core;

[0069] Specifically, the first processing core first processes the synchronization signal reading request, sets a prompt flag on the synchronization signal reading request, and then sends the synchronization signal reading request carrying a target program segment identifier, a target synchronization address identifier and a target synchronization value.

[0070] S200, confirming that the synchronization signal reading request is a synchronization operation according to the prompt flag;

[0071] Specifically, the data distribution unit receives the synchronization signal reading request and detects that the synchronization signal reading request has a prompt flag, so as to determine that the synchronization signal reading request sent by the first processing core is a synchronization operation. Then, the data distribution unit first searches the multiple rows of storage addresses in the synchronization signal buffer module for whether there is a storage address in an effective state, i.e., determines the value of the valid bit of the multiple rows of storage addresses. When detecting that the valid bit is 1, it is judged that the storage address is in an effective state; when detecting that the valid bit is 0, it is judged that the storage address is in an ineffective state.

[0072] S300, confirming that there is a storage address in an effective state, and determining whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier from the storage address in an effective state;

[0073] Specifically, when the data distribution unit determines that there is a storage address in an effective state, i.e., determines that there is a storage address with a valid bit of 1, it means that there is a second processing core that has completed a data writing operation. However, these second processing cores that have completed the data writing operation may not be the ones that the first processing core needs to synchronize, and the storage addresses in an effective state may exist in multiple rows. Therefore, the data distribution unit needs to further determine the program segment identifier and the synchronization address identifier in each row of storage addresses. If it is determined that the program segment identifier and the synchronization address identifier in a certain row of storage addresses can match the target program segment identifier and the target synchronization address identifier in the synchronization signal reading request, the data distribution unit determines that the row of storage addresses is the target storage address.

[0074] In some embodiments, if there is no target storage address, the synchronization signal reading request is distributed to a data scheduling unit, and the synchronization signal reading request is written to the storage unit through the data scheduling unit.​

[0075] Specifically, when the data distribution unit determines that there is no storage address with a valid state, it is determined that there is no target storage address, indicating that none of the second processing cores has completed the data write operation in the storage unit; or, the data distribution unit determines that there is a storage address with a valid state, but cannot find a storage address that matches both the target program segment identifier and the target synchronization address identifier in the synchronization signal read request from the storage address with a valid state, indicating that the synchronization signal required by the first processing core is not written into the storage address, but is written in the storage unit; then the data distribution unit needs to distribute the synchronization signal read request to the data scheduling unit, and the data scheduling unit distributes the synchronization signal read request to the storage unit, so that the data scheduling unit can further determine whether there is a synchronization signal required by the second processing core in the storage unit.

[0076] Such a setting can ensure the accuracy of synchronization signal reading, avoid errors in the storage address in the data distribution unit, and cause the synchronization signal to be stored in the storage unit.

[0077] S400, if there is a target storage address, when the synchronization value in the target storage address is the same as the target synchronization value, return a synchronization success message to the first processing core, and adjust the readable times in the target storage address;

[0078] Specifically, the synchronization value represents the number of second processing cores that have completed data write, and the readable times are the readable times of the synchronization value.

[0079] Specifically, when the data distribution unit determines that there is a target storage address, the data distribution unit further determines the synchronization value in the target storage address and determines whether the synchronization value in the target storage address is the same as the target synchronization value in the synchronization signal read request; if the data distribution unit determines that the synchronization value in the target storage address is the same as the target synchronization value, it indicates that all second processing cores have completed the data write operation in the storage unit, therefore, the data distribution unit returns a synchronization success message to the first processing core, and the data distribution unit needs to adjust the readable times in the target storage address, for example, performing an atomic decrement operation on the readable times in the target storage address.

[0080] In some embodiments, when the synchronization value in the target storage address is different from the target synchronization value, a synchronization failure message is returned to the first processing core.

[0081] Specifically, if the data distribution unit determines that the synchronization value in the target storage address is different from the target synchronization value, it indicates that there are second processing cores that have not completed the data write operation in the storage unit, therefore, the data distribution unit returns a synchronization failure message to the first processing core.

[0082] In the embodiments of the present application, after the first processing core sends the synchronization signal reading request with the prompt flag, the data distribution unit can determine the synchronization signal reading request as a synchronization operation according to the prompt flag, so as to directly determine whether the target storage address exists in the storage address, and confirm whether the synchronization is successful through the synchronization signal in the target storage address, instead of confirming whether the synchronization is successful through the synchronization signal in the storage unit, which greatly reduces the time spent for the synchronization signal reading, that is, time can be saved, and the delay is reduced, and the processing efficiency of the processing core is improved.

[0083] Moreover, multiple accesses to the data scheduling unit and the storage unit can be avoided as much as possible, so that the bandwidth of the data scheduling unit and the storage unit is saved, the bandwidth waste is avoided, and the working efficiency of the whole system is improved.

[0084] In some embodiments, when the readable times are adjusted to 0, the target storage address is adjusted to an invalid state.

[0085] Specifically, when the data distribution unit determines that the readable times in the storage address are 0, it indicates that all the first processing cores of the to-be-read synchronization signals have completed the synchronization signal reading operation, that is, all the synchronization signals are successfully synchronized, and then the data distribution unit automatically adjusts the target storage address to an invalid state, that is, adjusts the value of the valid bit in the target storage address to 0, and automatically releases the target storage address for subsequent storage operations.

[0086] In some embodiments, a clear instruction of the target program segment identifier is received, and it is determined whether there is a target storage address matching the target program segment identifier in the storage address in the valid state, and if so, the target storage address is adjusted to an invalid state.

[0087] Specifically, the processor sends a clear instruction of the target program segment identifier to the data distribution unit; the data distribution unit receives the clear instruction of the target program segment identifier, and according to the clear instruction of the target program segment identifier, it is determined whether there is a target storage address matching the target program segment identifier in the storage address in the valid state, and if so, the target storage address is adjusted to an invalid state. In this way, it can be ensured that after the execution of a certain program segment is completed and the synchronization is successful, some errors do not occur in the data distribution unit to automatically release the target storage address, so the processor can issue a clear instruction of the target program segment identifier, so that the data distribution unit can release the target storage address, and the accuracy of the state of the storage address in the data distribution unit is further ensured.

[0088] In some embodiments, as shown in Figure 6 the method further includes:

[0089] S500, receiving the synchronization signal write request with the prompt flag sent by the second processing core;

[0090] Specifically, the second processing core first processes the synchronization signal write request, sets the prompt flag on the synchronization signal write request, and then sends the synchronization signal write request carrying the program segment identifier, the synchronization address identifier, the synchronization value, and the readable number of times;

[0091] Specifically, the synchronization value can be implemented by setting the synchronization value or atomic addition operation, for example, when there is one second processing core, the synchronization value can be implemented by setting the synchronization value in the storage address, that is, directly writing the value of the synchronization value as 1; for example, when there are three second processing cores, the first second processing core can write data in the storage unit, and then perform atomic addition operation in the synchronization signal buffer to increase the value of the synchronization value from 0 to 1; the second second processing core can write data in the storage unit, and then perform atomic addition operation in the synchronization signal buffer to increase the value of the synchronization value from 1 to 2; the third second processing core can write data in the storage unit, and then perform atomic addition operation in the synchronization signal buffer to increase the value of the synchronization value from 2 to 3.

[0092] S600, according to the prompt flag, confirming that the synchronization signal write request is a synchronization operation, assigning an invalid state storage address to the synchronization signal write request, writing the program segment identifier, the synchronization address identifier, the synchronization value, and the readable number of times in the synchronization signal write request into the storage address, and adjusting the storage address from the invalid state to the valid state;

[0093] Specifically, the data distribution unit receives the synchronization signal write request and detects that the synchronization signal write request has the prompt flag, so as to determine that the synchronization signal write request sent by the second processing core is a synchronization operation. Then, the data distribution unit first searches for whether there is an invalid state storage address in the multiple rows of storage addresses in the synchronization signal buffer module, if there is an invalid state storage address, the data distribution unit randomly assigns an invalid state storage address to the synchronization signal write request, writes the program segment identifier, the synchronization address identifier, the synchronization value, and the readable number of times in the synchronization signal write request into the storage address, and adjusts the storage address from the invalid state to the valid state, that is, adjusts the value of the valid bit of the storage address to 1.

[0094] Specifically, if there is no valid storage address, the data distribution unit cannot allocate an invalid storage address for the synchronization signal write request. In this case, the data distribution unit sends the synchronization signal write request to the data scheduling unit, which then distributes the synchronization signal write request to the storage unit, thereby storing the synchronization signal write request in the storage unit. This ensures that the synchronization signal write request will not be discarded when there is no invalid storage address, thus avoiding synchronization failure.

[0095] In some embodiments, a synchronization signal write request is simultaneously distributed to a data scheduling unit, and the synchronization signal write request is distributed to a storage unit through the data scheduling unit.

[0096] Specifically, while the data distribution unit assigns the synchronization signal to the storage address in the invalid state, it also needs to distribute the synchronization signal to the data scheduling unit. The synchronization signal to the storage unit is then distributed to the storage unit through the data scheduling unit. This configuration allows the synchronization signal to be executed in the storage unit, avoiding the situation where storage fails at the storage address, and thus preventing some synchronization operations from being missing.

[0097] For example, such as Figure 7 As shown, the GPGPU configuration includes: a first processing core 101, a first processing core 102, a second processing core 103, a second processing core 104, a data distribution unit 20, a data scheduling unit 30, and a storage unit 40.

[0098] First, when neither the second processing core 103 nor the second processing core 104 has completed writing the target data into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, the multiple storage addresses 2010 in the synchronization signal cache module 201 are not the target storage addresses; both the first processing core 101 and the first processing core 102 set a prompt flag for the synchronization signal read request, and the first processing core 101 and the first processing core 102 send the synchronization signal read request carrying the target program segment identifier, the target synchronization address identifier, and the target synchronization value to the data distribution unit 20, where the target synchronization value is 2; if the data distribution unit 20 does not find the target storage address, it routes the synchronization signal read request to the data scheduling unit 30, and the data scheduling unit 30 then routes the synchronization signal read request to the storage unit 40. If there is no synchronization signal in the storage unit 40, it returns a synchronization failure message to the first processing core 101 and the first processing core 102;

[0099] Second, when the second processing core 103 has completed writing target data into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, and the second processing core 104 has not completed writing target data into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, the second processing core 103 sets a prompt flag on the synchronization signal write request, and sends the synchronization signal write request carrying the program segment identifier, the synchronization address identifier, the synchronization value, and the number of readable times to the data distribution unit 20; the data distribution unit 20 randomly allocates the invalid state storage address 2010-1 in the synchronization signal cache module 201 to the synchronization signal write request, at this time the value of the valid bit in the storage address 2010-1 is 0, after allocation, writes the synchronization signal write request sent by the second processing core 103 into the storage address 2010-1, and adjusts the storage address 2010-1 to the valid state, that is, sets the value of the valid bit in the storage address 2010-1 to 1, wherein the storage address 2010-1 is the target storage address, and writes the synchronization signal write request sent by the second processing core 103 into the storage address 2010-1; at this time, the valid bit in the storage address 2010-1 is 1, the synchronization value is adjusted to 1 through the atomic addition operation, and the number of readable times is 2;

[0100] The first processing core 101 and the first processing core 102 both set a prompt flag on the synchronization signal read request, and send the synchronization signal read request carrying the target program segment identifier, the target synchronization address identifier, and the target synchronization value to the data distribution unit 20, wherein the target synchronization value is 2; the data distribution unit 20 determines that the storage address 2010-1 is the target storage address by matching the target program segment identifier and the target synchronization address identifier, and determines that the synchronization value 1 in the storage address 2010-1 is not the same as the target synchronization value 2 in the synchronization signal read request, then the data distribution unit 20 returns a synchronization failure message to the first processing core 101 and the first processing core 102;

[0101] Finally, when the second processing core 103 and the second processing core 104 have both completed writing the target data into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, the second processing core 104 sets a prompt flag on the synchronization signal write request, and the second processing core 104 sends the synchronization signal write request carrying the program segment identifier, the synchronization address identifier, the synchronization value, and the readable times to the data distribution unit 20; the data distribution unit 20 finds the same program segment identifier and synchronization address identifier in the storage address 2010-1 in the synchronization signal cache module 201 according to the program segment identifier and the synchronization address identifier in the synchronization signal write request sent by the second processing core 104, and then writes the synchronization signal write request sent by the second processing core 104 into the storage address 2010-1; at this time, the valid bit in the storage address 2010-1 is 1, the synchronization value is adjusted from 1 to 2 through an atomic addition operation, and the readable times is 2;

[0102] The first processing core 101 sets a prompt flag on the synchronization signal read request first, and the first processing core 101 sends the synchronization signal read request carrying the target program segment identifier, the target synchronization address identifier, and the target synchronization value to the data distribution unit 20, where the target synchronization value is 2; the data distribution unit 20 determines that the storage address 2010-1 is the target storage address by matching the target program segment identifier and the target synchronization address identifier, and determines that the synchronization value 2 in the storage address 2010-1 is the same as the target synchronization value 2 in the synchronization signal read request, so the data distribution unit 20 returns a synchronization success message to the first processing core 101, and reduces the readable times 2 in the storage address 2010-1 by 1, so the readable times in the storage address 2010-1 is 1; and the first processing core 101 can perform subsequent operations, such as reading the data written into the storage unit 40 by the second processing core 103 and the second processing core 104 through the data distribution unit 20 and the data scheduling unit 30, after receiving the synchronization success message;

[0103] The first processing core 102 first sets a prompt flag on the synchronization signal reading request. The first processing core 102 sends the synchronization signal reading request carrying a target program segment identifier, a target synchronization address identifier, and a target synchronization value to the data distribution unit 20, where the target synchronization value is 2. The data distribution unit 20 determines that the storage address 2010-1 is the target storage address by matching the target program segment identifier and the target synchronization address identifier, and determines that the synchronization value 2 in the storage address 2010-1 is the same as the target synchronization value 2 in the synchronization signal reading request. The data distribution unit 20 returns a synchronization success message to the first processing core 102, decrements the readable times 1 in the storage address 2010-1 by 1, so that the readable times in the storage address 2010-1 are 0, and adjusts the storage address 2010-1 to an invalid state, that is, adjusts the valid bit in the storage address 2010-1 from 1 to 0. After receiving the synchronization success message, the first processing core 102 can perform subsequent operations, such as reading the data written by the second processing core 103 and the second processing core 104 into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30.

[0104] When it is determined that the first processing core 101 and the first processing core 102 have completed reading the data written by the second processing core 103 and the second processing core 104 into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, the processor 50 sends an emptying instruction of the target program segment identifier to the data distribution unit 20. The data distribution unit 20 receives the emptying instruction of the target program segment identifier, and determines whether there is a target storage address (for example, the storage address 2010-1 has not been adjusted to an invalid state) matching the target program segment identifier from the storage address 2010 in the valid state according to the emptying instruction of the target program segment identifier. If there is, the data distribution unit 20 adjusts the target storage address (for example, the storage address 2010-1) to an invalid state.

[0105] In the embodiment of the present application, after the first processing core sends the synchronization signal reading request with the prompt flag, the data distribution unit can determine that the synchronization signal reading request is a synchronization operation according to the prompt flag, so as to directly determine whether there is a target storage address in the storage address, and confirm whether the synchronization is successful through the synchronization signal in the target storage address, instead of confirming whether the synchronization is successful through the synchronization signal in the storage unit, which greatly reduces the time spent for the synchronization signal reading, that is, time can be saved, and the delay is reduced, and the processing efficiency of the processing core is improved.

[0106] Moreover, multiple accesses to the data scheduling unit and the storage unit can be avoided as much as possible, so as to save the bandwidth of the data scheduling unit and the storage unit, avoid bandwidth waste, and further improve the working efficiency of the entire system.

[0107] Based on the same technical concept, the embodiment of the present application provides a computer device, which comprises at least one artificial intelligence chip 100 and a memory 200 connected with the at least one artificial intelligence chip 100. Figure 8 As shown in the figure, the computer device comprises at least one artificial intelligence chip 100 and a memory 200 connected with the at least one artificial intelligence chip 100. Figure 8 In the embodiment of the present application, the artificial intelligence chip 100 and the memory 200 are connected through a bus. The bus can be divided into an address bus, a data bus, a control bus and the like.

[0108] In the embodiment of the present application, the memory 200 stores instructions executable by the at least one artificial intelligence chip 100, and the at least one artificial intelligence chip 100 can execute the steps of the instruction synchronization method by executing the instructions stored in the memory 200.

[0109] The artificial intelligence chip 100 is the control center of the computer device, can connect various parts of the computer device through various interfaces and lines, and can realize instruction synchronization by running or executing instructions stored in the memory 200 and calling data stored in the memory 200.

[0110] Optionally, the artificial intelligence chip 100 can comprise one or more processing units, and the artificial intelligence chip 100 can integrate an application processor and a modem processor. The application processor mainly processes an operating system, a user interface and an application program, and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 200 can be realized on the same chip, and in some embodiments, they can also be realized on independent chips respectively.

[0111] The artificial intelligence chip 100 can be a general processor, such as an image processor (GPU), a general image processor (GPGPU), a digital signal processor, an application specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can realize or execute the methods, steps and logic block diagrams disclosed in the embodiment of the present application. The general processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiment of the present application can be directly embodied as execution completed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0112] The memory 200, as a non-volatile computer readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 200 can include at least one type of storage medium, for example, can include flash memory, hard disk, multimedia card, card type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. The memory 200 is any other medium capable of carrying or storing desired program codes in the form of instructions or data structures and capable of being accessed by a computer device, but is not limited thereto. The memory 200 in the embodiments of the present application can also be a circuit or any other device capable of realizing a storage function, used to store program instructions and / or data.

[0113] Based on the same application concept, the embodiments of the present application provide a computer readable storage medium, which stores a computer program executable by a computer device, and when the computer program runs on the computer device, causes the computer device to execute the steps of the above instruction synchronization method.

[0114] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) containing computer-usable program code.

[0115] The present application is described with reference to flowcharts and / or block diagrams according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer device or other programmable data processing apparatus produce a machine that implements the functions specified in the flowcharts and / or block diagrams. Figure 1one or more processes and / or blocks Figure 1 an apparatus for performing the functions specified in the flowchart

[0116] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the flowchart Figure 1 one or more processes and / or blocks Figure 1 an apparatus for performing the functions specified in the flowchart

[0117] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions that are executed on the computer or other programmable apparatus provide steps for implementing the flowchart Figure 1 one or more processes and / or blocks Figure 1 an apparatus for performing the functions specified in the flowchart

[0118] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such additional variations and modifications as fall within the scope of the application.

[0119] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A method of processing a synchronization signal, characterized by, The application is applied to a data distribution unit, comprising: receiving a synchronization signal reading request with a prompt flag sent by a first processing core, the synchronization signal reading request carrying a target program segment identifier, a target synchronization address identifier and a target synchronization value; confirming that the synchronization signal reading request is a synchronization operation according to the prompt flag; confirming that there is a storage address in an active state in a storage address of the data distribution unit, and determining whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier from the storage address in the active state; if there is the target storage address, returning a synchronization success message to the first processing core when the synchronization value in the target storage address is the same as the target synchronization value, and performing an atomic decrement operation on the readable times in the target storage address; wherein the synchronization value represents the number of second processing cores that have completed data writing, and the readable times are the readable times of the synchronization value.

2. The method of claim 1, wherein, when the readable times are adjusted to 0, the target storage address is adjusted to an invalid state.

3. The method of claim 1, wherein, when the synchronization value in the target storage address is different from the target synchronization value, a synchronization failure message is returned to the first processing core.

4. The method according to any one of claims 1 to 3, characterized in that, further comprising: if there is no target storage address, distributing the synchronization signal reading request to a data scheduling unit, and the synchronization signal reading request is distributed to a storage unit through the data scheduling unit.

5. The method of claim 4, wherein, further comprising: receiving a synchronization signal writing request with a prompt flag sent by a second processing core, the synchronization signal writing request carrying a program segment identifier, a synchronization address identifier, the synchronization value and the readable times; confirming that the synchronization signal writing request is a synchronization operation according to the prompt flag, allocating an invalid storage address to the synchronization signal writing request, writing the program segment identifier, the synchronization address identifier, the synchronization value and the readable times in the synchronization signal writing request into the storage address, and adjusting the storage address from the invalid state to the active state.

6. The method of claim 5, wherein, further comprising: distributing the synchronization signal writing request to the data scheduling unit at the same time, and the synchronization signal writing request is distributed to the storage unit through the data scheduling unit.

7. The method according to any one of claims 1 to 3, wherein the method is performed in a single step. further comprising: receiving a clear instruction of the target program segment identifier, determining whether there is a target storage address matching the target program segment identifier from the storage address in the active state, and adjusting the target storage address to an invalid state if there is.

8. An artificial intelligence chip, characterized by, comprising: a plurality of processing cores, a data distribution unit, a data scheduling unit and a storage unit; the plurality of processing cores comprise a first processing core; the first processing core is configured to read target data from the storage unit through the data distribution unit and the data scheduling unit, and send a synchronization signal reading request with a prompt flag before reading the target data; wherein the synchronization signal reading request carries a target program segment identifier, a target synchronization address identifier and a target synchronization value; The data distribution unit is configured to confirm, according to the prompt flag, that the synchronization signal reading request is a synchronization operation, and that there is a storage address in an active state, and determine whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier in the storage address in the active state. The data distribution unit is further configured to confirm that there is the target storage address, determine that the synchronization value in the target storage address is the same as the target synchronization value, return a synchronization success message to the first processing core, and adjust the number of readable times in the target storage address.

9. The artificial intelligence chip of claim 8, wherein, The data distribution unit is further configured to confirm that the number of readable times is adjusted to 0, and adjust the target storage address to an invalid state.

10. The artificial intelligence chip of claim 8, wherein, The data distribution unit is further configured to confirm that the synchronization value in the target storage address is different from the target synchronization value, and return a synchronization failure message to the first processing core.

11. The artificial intelligence chip of any one of claims 8-10, wherein, The plurality of processing cores further include a second processing core, and the second processing core is configured to write the target data into the storage unit through the data distribution unit and the data scheduling unit, and send a synchronization signal writing request with a prompt flag after confirming that the target data is written. The data distribution unit includes a synchronization signal cache module, and the synchronization signal cache module includes a plurality of storage addresses, which are configured to store the synchronization signal writing request. The data distribution unit is further configured to confirm, according to the prompt flag, that the synchronization signal writing request is a synchronization operation, assign an invalid storage address to the synchronization signal writing request, write the program segment identifier, the synchronization address identifier, the synchronization value and the number of readable times in the synchronization signal writing request into the storage address, and adjust the storage address from the invalid state to the active state.

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