A data scheduling and control method based on motherboard memory pass-through

Abstract

The application discloses a data scheduling and control method based on motherboard memory pass-through, and relates to the technical field of computer hardware.The method preallocates a pass-through memory region for a mounting device in a firmware initialization stage, establishes a mapping relationship between a device identifier and a dedicated memory segment physical address, and enables the device to bypass a system cache level and access the dedicated memory segment in a direct memory access mode through address conversion and access control rules of the firmware layer.A firmware scheduling table is constructed based on the mapping relationship to manage access requests of all devices, and transmission delay is monitored in real time, and priority weight and bandwidth allocation in the scheduling table are dynamically adjusted according to the monitoring result; and the scheduling table is updated to sort the requests, thereby scheduling and controlling the memory access behavior of the device.The application effectively solves the delay bottleneck caused by multi-level copying and firmware scheduling lag in motherboard data forwarding.

Description

Technical Field

[0001] This application relates to the field of computer hardware technology, specifically a data scheduling and control method based on motherboard memory pass-through. Background Technology

[0002] With the increasing demand for high-performance computing, cloud servers, and real-time data analytics, data transfer rates and latency bottlenecks on motherboards are becoming increasingly prominent. In existing motherboard architectures, data transfer between the Central Processing Unit (CPU), memory, and high-speed buses, such as the Peripheral Component Interconnect Express (PCIe) standard, typically requires multiple copies, such as sequentially from the application layer, operating system kernel buffer, driver buffer, Direct Memory Access (DMA) controller, to the device. This process generates multiple levels of data buffering and context switching. To reduce latency, some systems introduce DMA technology, allowing devices to bypass the CPU and directly read and write to memory; another type of optimization is interrupt merging and queuing to reduce the overhead of frequent interrupt calls.

[0003] While DMA can reduce CPU overhead, it still requires scheduling and address mapping at the operating system / driver level, preventing further latency compression. This is especially true in high-frequency, small-packet data scenarios (such as financial transactions, online games, and real-time monitoring). The jitter caused by this scheduling and multiple memory copies significantly reduces system throughput and real-time performance. Therefore, existing technologies have failed to effectively address the latency bottleneck caused by multi-level copying and firmware scheduling lag in motherboard data forwarding. Summary of the Invention

[0004] The purpose of this application is to provide a data scheduling and control method based on motherboard memory pass-through, so as to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, this application provides the following technical solution: During the firmware initialization phase, a pass-through memory region is pre-allocated for multiple devices mounted on the motherboard, a dedicated memory segment is allocated for each device, and a mapping relationship is established between the device identifier and the physical address of the dedicated memory segment; by establishing address translation and access control rules at the firmware layer, devices bypass the system cache level and access the allocated dedicated memory segment through direct memory access; based on the mapping relationship between the device identifier and the physical address of the dedicated memory segment, a firmware scheduling table is established in the firmware, which is used to manage all direct memory access requests from devices to the pass-through memory region; the data transmission latency of each device is monitored in real time, and the priority weight and bandwidth allocation in the firmware scheduling table are dynamically adjusted based on the latency monitoring results of the direct memory access requests; priority is assigned to each direct memory access request according to the firmware scheduling table and sorted; based on the sorting results of each direct memory access request, the scheduling and control of device memory access behavior are completed.

[0006] Preferably, during the firmware initialization phase, passthrough memory regions are pre-allocated for multiple devices mounted on the motherboard, including: allocating a predetermined proportion of the total system physical memory as passthrough memory regions; calculating the total capacity of the passthrough memory regions using the total system physical memory and the predetermined allocation proportion; employing a high-address-to-low-address allocation strategy, allocating from the high address end of the system physical memory and aligning addresses according to the memory page size specified by the processor architecture; and configuring protection attributes for the passthrough memory regions, including read / write permissions, direct memory access compatibility settings, and cache coherency strategies.

[0007] Preferably, a dedicated memory segment is allocated to each device, and a mapping relationship is established between the device identifier and the physical address of the dedicated memory segment. This includes: normalizing the traffic weight of each device based on the total capacity of the determined pass-through memory region; determining the standardized weight allocation ratio of each device by calculating the sum of the weights of all devices; calculating and determining the allocation size of the dedicated memory segment for each device according to the total capacity of the pass-through memory region and the standardized weight allocation ratio of each device, and down-aligning the dedicated memory segment size according to the predefined memory page size; determining the starting physical address of the dedicated memory segment for each device sequentially using a cumulative allocation method; creating a complete address mapping entry for each device identifier, the mapping entry including the device's unique identifier, the starting physical address of the corresponding dedicated memory segment, the memory segment allocation size, the device type identifier, and access permission configuration, and constructing a device address mapping table to establish the correspondence between the device identifier and the physical address of the dedicated memory segment.

[0008] Preferably, by establishing address translation and access control rules at the firmware layer, devices can bypass the system cache layer and access allocated dedicated memory segments via direct memory access. This includes: registering access permission tables for each device at the firmware layer to specify the physical address range corresponding to the dedicated memory segments accessible to each device; configuring read and write permissions for each device and enabling direct memory access mode, and configuring the security level of each device to hardware enforcement; allocating a dedicated hardware channel for each device in the direct memory access controller, limiting the transmission address range to the dedicated memory segment, and setting the transmission mode to direct memory access to bypass the system cache layer; and creating address translation entries for each device in the system memory management unit to map the dedicated virtual address space of each device to the dedicated physical memory address, and configuring cache consistency mode.

[0009] Preferably, based on the mapping relationship between device identifiers and the physical addresses of dedicated memory segments, a firmware scheduling table is established through the firmware. This includes: creating corresponding scheduling entries for each device in the firmware scheduling table based on the device identifiers in each device address mapping table, using the device identifier as the first dimension index of the firmware scheduling table; extracting the starting physical address and size information of each device's dedicated memory segment from the device address mapping table, and configuring the starting physical address as the direct memory access address parameter in the firmware scheduling table; the firmware scheduling table adopts a three-dimensional structure, with the first dimension being the device identifier, the second dimension being the data flow type, and the third dimension being the set of scheduling parameters; each firmware scheduling table entry includes priority weight, queue depth limit, bandwidth allocation weight, direct memory access address, and access permission.

[0010] Preferably, each direct memory access request is prioritized and sorted according to the firmware scheduling table, including: querying and extracting the corresponding priority weight and queue depth limit parameters from the firmware scheduling table based on the device identifier and data stream type of the direct memory access request; calculating the arbitration weight of each device under different data stream types based on the extracted priority weight and the current queue depth status, wherein the arbitration weight is calculated by combining the priority weight with the queue depth adjustment factor, and the queue depth adjustment factor is used to characterize the load status of the current device's request queue; using the arbitration weight as the basis for priority allocation to determine the scheduling order; and sorting all waiting direct memory access requests according to the scheduling order.

[0011] Preferably, the system monitors the data transmission latency of each device in real time and dynamically adjusts the priority weights and bandwidth allocation in the firmware scheduling table based on the latency monitoring results of direct memory access requests. This includes: recording the complete time span from the initiation of a direct memory access request to the completion of data transmission as a single transmission latency; using an exponentially weighted moving average algorithm, the system calculates a smoothed latency value by weighting the current transmission latency monitoring results and historical smoothed latency values ​​according to a preset weight ratio; dynamically adjusting the priority weights of the corresponding devices in the firmware scheduling table based on the comparison results between the smoothed latency value and a preset target latency benchmark, increasing the priority weight when the smoothed latency value exceeds the target latency benchmark and decreasing the priority weight when the smoothed latency value is lower than the target latency benchmark; calculating a latency deviation normalization factor using the target latency benchmark and the smoothed latency value; and dynamically adjusting the bandwidth allocation weights in the firmware scheduling table based on the latency deviation normalization factor.

[0012] Preferably, the scheduling and control of device memory access behavior is completed based on the sorting results of each direct memory access request, including: processing each direct memory access request sequentially according to the priority sorting results in the ordered scheduling execution queue, wherein the direct memory access request with higher priority is given priority scheduling execution rights; allocating hardware resources according to the sorting results, prioritizing the allocation of available direct memory access channels and bandwidth resources to high-priority direct memory access requests; establishing anomaly detection based on latency monitoring results, and determining the classification criteria for mild, moderate, and severe anomalies based on the comparison results of latency monitoring results and baseline values; dynamically calculating and adjusting latency control thresholds and queue depth thresholds in combination with the current system load status and queue depth information in the sorting results; when the transmission latency or queue depth of the current device is detected to exceed the corresponding threshold, the scheduling decision is re-executed based on the updated firmware scheduling table, and the direct memory access request of the current device is promoted to a higher priority queue position to complete adaptive flow control.

[0013] Compared with the prior art, the beneficial effects of this application are: 1. This application establishes a hardware pass-through data channel by pre-allocating a dedicated memory region during the firmware initialization phase, enabling the device to bypass the traditional multi-layered buffer structure and directly access the target memory segment. This direct memory access method eliminates the multi-level copying process of data between the application layer, operating system kernel buffer, and driver buffer in the traditional architecture, and can significantly improve the real-time performance of the system, especially in high-frequency small packet data transmission scenarios.

[0014] 2. This application monitors transmission delay in real time and dynamically adjusts the bandwidth allocation weight and priority parameters of each device. The system can adaptively optimize scheduling according to the current load conditions, effectively solving the problem that the existing firmware scheduling granularity is too coarse and cannot quickly respond to high-frequency burst traffic. It ensures that high-priority data streams can be processed in a timely manner, and avoids the phenomenon of excessive concentration of system resources and delay accumulation through load balancing. Attached Figure Description

[0015] Figure 1 A flowchart illustrating a data scheduling and control method based on motherboard memory pass-through provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the process of pre-allocating pass-through memory regions to multiple devices mounted on the motherboard during the firmware initialization phase, as provided in an embodiment of this application. Figure 3 This is a schematic diagram illustrating a process for allocating dedicated memory segments to each device and establishing a mapping relationship between device identifiers and the physical addresses of dedicated memory segments, as provided in an embodiment of this application. Figure 4 This is a schematic diagram illustrating a process for allocating dedicated memory segments to each device and establishing a mapping relationship between device identifiers and the physical addresses of dedicated memory segments, as provided in an embodiment of this application. Figure 5 This is a schematic diagram illustrating the process of establishing a firmware scheduling table through firmware based on the mapping relationship between device identifier and physical address of dedicated memory segment provided in one embodiment of this application. Figure 6 This is a schematic diagram illustrating the process of establishing a firmware scheduling table through firmware based on the mapping relationship between device identifier and physical address of dedicated memory segment provided in one embodiment of this application. Figure 7 This is a schematic diagram illustrating a process for real-time monitoring of data transmission latency of each device and dynamic adjustment of priority weights and bandwidth allocation in the firmware scheduling table based on the latency monitoring results of direct memory access requests, according to an embodiment of this application. Figure 8 This is a schematic diagram illustrating the process of scheduling and controlling device memory access behavior based on the sorting results of each direct memory access request, as provided in one embodiment of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] Figure 1 This is a schematic diagram of a data scheduling and control method based on motherboard memory pass-through provided in an embodiment of this application. Figure 1 As shown, the data scheduling and control method based on motherboard memory pass-through provided in this application includes the following steps: Step 100: During the firmware initialization phase, passthrough memory regions are pre-allocated for multiple devices mounted on the motherboard, dedicated memory segments are allocated for each device, and a mapping relationship is established between the device identifier and the physical address of the dedicated memory segment.

[0018] Specifically, a memory passthrough infrastructure is established at the firmware level. By pre-allocating dedicated memory regions and establishing device-to-memory mappings, the foundation for direct memory access is laid. This eliminates the need for multi-level buffer copying in traditional architectures, enabling devices to bypass the operating system kernel and directly access designated physical memory segments. This significantly reduces data transmission latency and improves overall system performance. Through systematic memory region partitioning, device weight allocation, and address mapping table construction, the rational allocation of memory resources and the security of access control in multi-device environments are ensured.

[0019] Step 101: By establishing address translation and access control rules at the firmware layer, the device can bypass the system cache level and access the allocated dedicated memory segment through direct memory access.

[0020] Specifically, at the firmware layer, access permission tables are registered for each device, specifying the physical address range corresponding to the dedicated memory segments accessible to each device. The access permission tables define the range of memory addresses accessible to each device, configure read and write permissions for each device, enable direct memory access mode, and configure the security level of each device to be enforced by hardware, ensuring the reliability of access control. In the direct memory access controller, a dedicated hardware channel is allocated to each device, limiting the transmission address range to the dedicated memory segment. The transmission mode is set to direct memory access to bypass the system cache layer.

[0021] Step 102: Based on the mapping relationship between device identifier and physical address of dedicated memory segment, a firmware scheduling table is established through the firmware. The firmware scheduling table is used to manage all direct memory access requests from devices to the pass-through memory region.

[0022] Specifically, based on the pre-established mapping relationship between the device identifier and the physical address of the dedicated memory segment allocated to it, the underlying firmware of the system builds and maintains a dedicated firmware scheduling table. This scheduling table serves as the core hub for hardware resource access, recording and managing the legal access permissions, address ranges, and operation attributes of all Direct Memory Access (DMA) devices to their pass-through memory regions, ensuring that only authorized devices are allowed to directly access the specified memory space through physical address mapping, thereby achieving secure and controllable DMA transfer scheduling and isolation protection at the hardware level.

[0023] Step 103: Monitor the data transmission latency of each device in real time, and dynamically adjust the priority weight and bandwidth allocation in the firmware scheduling table based on the latency monitoring results of direct memory access requests.

[0024] Specifically, the system monitors and collects the actual latency data of each device transmitting data through the direct memory access channel in real time, and dynamically analyzes its performance status based on the latency monitoring results. Through the built-in scheduling algorithm, the system automatically adjusts the access priority weight and bandwidth allocation strategy of the corresponding device in the firmware scheduling table, so as to prioritize the transmission efficiency of low-latency devices in the bus resource contention scenario, realize dynamic load balancing and real-time performance optimization, and ensure that the real-time data transmission requirements of critical devices are met.

[0025] Step 104: Assign priority to each direct memory access request and sort them according to the firmware scheduling table.

[0026] Specifically, priority values ​​are dynamically assigned to each direct memory access request according to the firmware scheduling table, and the request queue is sorted and scheduled based on the priority. Priority arbitration is performed through the hardware scheduler to ensure that requests from high-priority devices (such as peripherals with high real-time requirements) are given priority access to bus access and memory bandwidth allocation, thereby optimizing the overall data transmission efficiency of the system and meeting the service quality requirements of different devices.

[0027] Step 105: Based on the sorting results of each direct memory access request, complete the scheduling and control of the device's memory access behavior.

[0028] Specifically, based on the priority ranking of direct memory access requests, the system uses a hardware scheduler to arbitrate and schedule the request queue in real time, dynamically allocating memory bandwidth and bus access permissions. Through control strategies such as forcing low-priority requests to wait or inserting them into idle periods for transmission, allocating contiguous memory blocks for high-priority requests, and prefetching resources, the system achieves fine-grained control over device memory access behavior. Ultimately, while ensuring the transmission efficiency of high-real-time devices, the system optimizes overall memory resource utilization and system concurrency performance.

[0029] The beneficial effects of this application's embodiments are as follows: By establishing the allocation and mapping of pass-through memory regions during the firmware initialization phase, and combining traffic weight normalization and address alignment strategies, fair allocation and efficient management of dedicated memory segments for each device are achieved, ensuring the rationality of system resource utilization and access compatibility. Through firmware-level access control, DMA dedicated channel configuration, and address translation, a precise access control and cache consistency strategy is established in a multi-device environment, ensuring the security, isolation, and consistency of data transmission. Through real-time latency monitoring, dynamic priority and bandwidth adjustment, arbitration sorting, and adaptive traffic control, a complete closed-loop scheduling optimization is formed, ensuring high-priority request response while achieving performance balance and stable operation of the system under different load conditions.

[0030] Figure 2 This is a schematic diagram illustrating a process for pre-allocating pass-through memory regions to multiple devices mounted on the motherboard during the firmware initialization phase, as provided in one embodiment of this application. Figure 2 As shown in the embodiments of this application, the data scheduling and control method based on motherboard memory passthrough provides that, during the firmware initialization phase, pre-allocates passthrough memory regions for multiple devices mounted on the motherboard, including the following steps: Step 200: Allocate a predetermined proportion of the total physical memory of the system to a pass-through memory region.

[0031] Specifically, in the first stage of firmware initialization, the system needs to determine the allocation range of the passthrough memory region within the overall memory architecture. The total physical memory of the system serves as the basis for calculation, measured in bytes. The number of devices supporting passthrough determines the complexity of memory allocation. These devices mainly include high-performance computing components such as high-speed network interface cards, storage controllers, and graphics processing units. The predetermined allocation ratio needs to comprehensively consider the overall system performance balance and the actual needs of the passthrough function. According to technical specifications, the direct memory access allocation ratio should be set between 10% and 30%. The lower limit of this ratio range ensures sufficient memory space is reserved for the passthrough function to support basic high-speed data transmission needs, while the upper limit avoids significant impact on normal system operation. In the specific process of determining the predetermined allocation ratio, the system evaluates the type and number of currently mounted devices and the expected workload intensity. For high-frequency small packet data transmission scenarios, such as financial trading systems or real-time monitoring applications, the predetermined allocation ratio tends to be set at the upper limit. For general performance computing applications, a medium-level configuration can be adopted, set at around 20%.

[0032] Step 201: Calculate the total capacity of the through memory region by using the total physical memory of the system and the predetermined allocation ratio.

[0033] Specifically, based on the predetermined allocation ratio determined in step 200, the system calculates the total capacity of the pass-through memory region. The calculation process uses the product of the total system physical memory and the predetermined allocation ratio to ensure the accuracy and consistency of the numerical calculation. The total capacity of the pass-through memory region is determined by the following calculation: the total capacity of the pass-through memory region equals the total system physical memory multiplied by the predetermined allocation ratio. This calculation ensures that the system reserves sufficient memory space for the pass-through function while avoiding impact on normal system operation. Numerical verification is required during the calculation process to confirm that the calculation results meet the system hardware constraints. The system checks whether the total capacity of the pass-through memory region exceeds the maximum addressing capability of the physical memory management unit and verifies whether this capacity meets the basic memory requirements of all expected pass-through devices. If the calculation results do not meet hardware constraints or device requirements, the system will re-evaluate the predetermined allocation ratio and re-execute the calculation process. After the calculation is completed, the system records the numerical result of the total capacity of the pass-through memory region, providing basic parameters for address allocation and memory segment partitioning. This value will serve as the input parameter for the memory allocation algorithm, directly affecting the size allocation of dedicated memory segments for each device.

[0034] Step 202: An allocation strategy from high address to low address is adopted, starting from the high address end of the system physical memory and aligning the addresses according to the memory page size specified by the processor architecture.

[0035] Specifically, the system employs a high-to-low address allocation strategy, allocating pass-through memory regions starting from the high address end of the system's physical memory. This allocation strategy is chosen based on memory management efficiency and system compatibility considerations, avoiding conflicts with the memory regions of the operating system kernel and system components. The base address of the pass-through memory region uses a strategy of allocating from the end of physical memory forward. Specifically, the initial value of the base address is obtained by subtracting the total capacity of the pass-through memory region from the end address of physical memory. This calculation method ensures that the pass-through memory region is located in the high address segment of physical memory, maintaining compatibility with traditional system memory allocation modes. Address alignment is a crucial step in ensuring hardware access efficiency. The system performs address alignment according to the memory page size specified by the processor architecture, with a standard configuration of four thousand bytes. During the alignment process, the calculated base address needs to be down-aligned according to the memory page size to ensure hardware access efficiency and compatibility.

[0036] The specific alignment algorithm is implemented as follows: The system calculates the modulo operation result between the base address and the memory page size. If the result is not zero, the base address is subtracted from the modulo operation result to make the base address an integer multiple of the memory page size. Alignment ensures that the starting address of each through-memory region meets the basic requirements of hardware access, avoiding performance loss or access errors caused by address misalignment.

[0037] Step 203: Configure protection attributes for the pass-through memory region. Protection attributes include read / write permissions, direct memory access compatibility settings, and cache consistency policies.

[0038] Specifically, to ensure that the pass-through memory region can be accessed securely and efficiently by relevant devices, the system needs to configure complete protection attributes for this region. The protection attribute configuration includes three components: read / write permissions, direct memory access compatibility settings, and cache consistency policies. Read / write permission configuration determines the basic access mode of the pass-through memory region. The system sets read / write permissions for the pass-through memory region, allowing authorized devices to perform data read and write operations on this region. Permission settings adopt a hardware enforcement mode, implementing permission verification through access control of the memory management unit. Unauthorized access attempts will be directly rejected at the hardware level, ensuring the security of memory access. Direct memory access compatibility settings establish a coordination interface between the pass-through memory region and the direct memory access controller. This setting ensures that the direct memory access controller can recognize and correctly process data transfer requests for the pass-through memory region. Compatibility configuration includes address space identification, transfer mode support, and interrupt handling, providing a hardware foundation for devices to bypass the central processing unit and directly access memory. Cache consistency policy configuration addresses the data consistency problem during concurrent access by multiple devices. The system establishes cache consistency guarantees for the pass-through memory region, ensuring that access operations by different devices to the same memory location maintain data consistency and correctness. This strategy is implemented through a hardware cache controller and includes operations such as cache refresh, cache invalidation, and cache synchronization to prevent data errors or system anomalies caused by cache inconsistency.

[0039] After the protection attributes are configured, the system establishes a coordination interface with the system memory management unit to ensure compatibility between the passthrough memory region and existing virtual memory management. This interface is responsible for address translation, permission verification, and exception handling, providing a complete configuration foundation for device address mapping and access control. The output of the configuration process includes the base address of the passthrough memory region, the total capacity of the passthrough memory region, the memory region protection configuration, and the system memory management coordination interface. These outputs will serve as input parameters for device-specific memory segment allocation and address mapping establishment, ensuring the technical consistency and implementation integrity of the entire memory passthrough process.

[0040] The beneficial effects of this application's embodiments are as follows: By pre-determined allocation ratios and capacity calculations, a reasonable proportion of the pass-through memory region in the system's physical memory is ensured, providing a balance between high-performance data transmission and system stability. The use of a high-to-low address allocation strategy and strict address alignment ensures that memory access meets processor architecture requirements, improving access efficiency and system reliability. Comprehensive protection attributes, including read / write permissions, DMA compatibility, and cache coherency strategies, achieve a balance between efficient access and secure isolation for the pass-through memory region.

[0041] Figure 3 This is a schematic diagram illustrating a process for allocating dedicated memory segments to each device and establishing a mapping relationship between device identifiers and the physical addresses of dedicated memory segments, as provided in one embodiment of this application. Figure 3 As shown in the embodiments of this application, the data scheduling and control method based on motherboard memory pass-through allocates dedicated memory segments to each device and establishes a mapping relationship between device identifiers and the physical addresses of dedicated memory segments, including the following steps: Step 300: Based on the total capacity of the determined pass-through memory region, normalize the traffic weights of each device.

[0042] Specifically, based on the basic address and total capacity of the pass-through memory region output in step 203, the system begins to perform traffic weight normalization processing for each device. This process converts the original traffic weights of different devices into unified standardized values, providing a comparable weight basis for memory allocation calculations. The system first collects traffic weight information for all devices requiring pass-through functionality. The estimated traffic weight of each device reflects the relative size of the memory bandwidth requirements of different devices, and this weight is determined based on device type, expected workload, and historical performance data. High-speed network interface cards typically have higher traffic weights, the weight of the storage controller is set according to its processing capacity and expected data throughput, and the weight of the graphics processing unit is determined based on the memory access patterns of its compute-intensive applications. The normalization process uses a standard weight normalization algorithm. The system calculates the cumulative sum of the original traffic weights of all devices, and then divides the original traffic weight of each device by this cumulative sum to obtain a normalized weight ranging from zero to one. This normalization process ensures the fairness and rationality of memory allocation, avoiding allocation deviations caused by differences in weight value ranges. After the normalization calculation is completed, the system verifies whether the sum of the normalized weights of all devices equals one to confirm the accuracy of the calculation process. If a numerical deviation is found, the system will re-execute the normalization calculation and adjust the precision to ensure the mathematical accuracy of the weight allocation and the stability of the system.

[0043] Step 301: Determine the standardized weight allocation ratio of each device by calculating the sum of the weights of all devices.

[0044] Specifically, based on the normalized weights completed in step 300, the system determines the standardized weight allocation ratio for each device by calculating the sum of the weights of all devices. This establishes the relative allocation weights of each device within the passthrough memory region, providing a basis for memory segment size calculation. The calculation of the standardized weight allocation ratio uses a direct proportional allocation method. Since weight normalization has been completed in step 300, the sum of the normalized weights of all devices equals one; therefore, the standardized weight allocation ratio for each device is directly equal to its normalized weight value. This ratio represents the percentage share that a specific device should be allocated in the total capacity of the passthrough memory region. The system verifies the rationality of the standardized weight allocation ratio. The verification process includes checking for excessive weight concentration, i.e., whether the allocation ratio of a single device exceeds 50% of the total capacity. If excessive weight concentration is detected, the system will trigger a weight balancing adjustment, appropriately reducing the proportion of high-weight devices and redistributing them to other devices to ensure a reasonable distribution of memory resources. After the allocation ratio is determined, the system generates a standardized weight allocation ratio table, recording the allocation ratio value corresponding to each device identifier. This ratio table will serve as a parameter for calculating the memory segment size, directly affecting the final allocation result of the dedicated memory segment for each device.

[0045] Step 302: Calculate and determine the allocation size of the dedicated memory segment for each device based on the total capacity of the pass-through memory region and the standardized weight allocation ratio of each device, and perform downward alignment of the dedicated memory segment size according to the predefined memory page size.

[0046] Specifically, the calculation process employs numerical computation to ensure that each device receives a memory space allocation commensurate with its weight ratio. The size of a single device's dedicated memory segment allocation is calculated by multiplying the total capacity of the through-memory region by the device's standardized weight allocation ratio. The device's dedicated memory segment allocation size equals the total capacity of the through-memory region multiplied by the device's standardized weight allocation ratio. This calculation method ensures the correspondence between memory allocation and device weight. To ensure hardware access efficiency and compatibility, the system performs down-alignment processing on the dedicated memory segment allocation size based on a predefined memory page size. The memory page size parameter is used to ensure address alignment, with a standard configuration typically of four thousand bytes. The alignment algorithm calculates the modulo operation result of each device's dedicated memory segment allocation size and the memory page size. If the result is not zero, the allocation size is subtracted from the modulo operation result to ensure the final allocation size is an integer multiple of the memory page size. After alignment, the system verifies whether the sum of the aligned sizes of all device dedicated memory segments exceeds the total capacity of the through-memory region. If a capacity limit is found, the system initiates capacity adjustment, proportionally reducing the size of each device's dedicated memory segment to ensure the total allocation is controlled within the total capacity of the through-memory region. The adjustment process maintains the relative weight ratios of each device to ensure fair allocation.

[0047] Step 303: The starting physical address of the dedicated memory segment for each device is determined sequentially using a cumulative allocation method.

[0048] Specifically, the allocation method calculates the physical address location of each device within the pass-through memory region by sequentially accumulating the memory segment sizes of each device. The cumulative allocation algorithm starts execution from the base address of the pass-through memory region. The starting physical address of the first device's dedicated memory segment is directly set to the base address of the pass-through memory region. For subsequent devices, the starting physical address of their dedicated memory segment is calculated by adding the starting physical address of the previous device to the size of its dedicated memory segment. This cumulative calculation process ensures the continuous distribution of each device's dedicated memory segment in the physical address space. During the allocation process, the system maintains a cumulative address counter to track the boundary positions of the allocated address space in real time. After each device's address allocation is completed, the system updates the value of the cumulative address counter, providing a starting reference point for the address calculation of the next device. This ensures the continuity and consistency of address allocation. The system performs a boundary check on the starting physical address of each device to verify whether the calculated address is within the valid range of the pass-through memory region. The boundary check includes confirming that the starting physical address is not lower than the base address of the pass-through memory region, and that the starting physical address plus the size of the dedicated memory segment does not exceed the end address of the pass-through memory region. If an address out-of-bounds situation is detected, the system will trigger error handling and re-execute the allocation calculation.

[0049] Step 304: Create a complete address mapping entry for each device identifier. The mapping entry includes the device's unique identifier, the starting physical address of the corresponding dedicated memory segment, the memory segment allocation size, the device type identifier, and the access permission configuration. Construct a device address mapping table to establish the correspondence between the device identifier and the physical address of the dedicated memory segment.

[0050] Specifically, a complete address mapping entry is created for each device identifier, and a device address mapping table is constructed to establish the correspondence between device identifiers and the physical addresses of dedicated memory segments. This mapping table is the core data structure of the entire memory passthrough, providing basic information for address translation and access control. The process of constructing address mapping entries involves creating a complete record structure for each device identifier. Each mapping entry includes five data fields: a unique device identifier, the starting physical address of the corresponding dedicated memory segment, the memory segment allocation size, the device type identifier, and access permission configuration. The unique device identifier ensures the uniqueness and traceability of the mapping relationship, while the starting physical address and memory segment allocation size define the range of physical memory accessible to the device. The device type identifier field records the specific classification information of the device, such as high-speed network interface cards, storage controllers, and graphics processing units, providing differentiated access strategies and performance optimization configurations for different types of devices. The access permission configuration field inherits the protection attribute settings established in step 203, ensuring the consistency of access permissions and memory protection configurations for each device.

[0051] The device address mapping table employs an efficient index structure design, supporting fast lookup and access based on device identifiers. The mapping table uses a hash index with the device identifier as the index key, achieving constant-time lookup performance. This index provides efficient data access capabilities for firmware scheduling and address translation. After the mapping table is built, the system performs integrity verification to confirm that all expected devices have successfully created corresponding mapping entries, and that the address ranges in the mapping entries do not overlap or exceed limits. The verification process also includes checking the integrity of the mapping table's data structure and the correctness of the index. Once verification is successful, the device address mapping table officially takes effect, providing a complete configuration foundation for firmware-level address translation and access control.

[0052] The beneficial effects of this application's embodiments are as follows: By normalizing traffic weights and allocating proportionally, fair allocation of resources among different devices in the pass-through memory region is achieved, avoiding excessive resource concentration and ensuring the accuracy and balance of allocation calculations. The use of memory segment size calculation and alignment processing, as well as cumulative allocation address determination, ensures that the memory allocation results meet hardware access efficiency requirements and achieves continuity and boundary security in the physical address space. The construction of a device address mapping table combined with efficient indexes enables unified management and rapid lookup of device unique identifiers, addresses, and permission information, improving system access security and maintainability.

[0053] Figure 4 This is a schematic diagram illustrating a process for allocating dedicated memory segments to each device and establishing a mapping relationship between device identifiers and the physical addresses of dedicated memory segments, as provided in one embodiment of this application. Figure 4 As shown in the embodiments of this application, the data scheduling and control method based on motherboard memory pass-through enables the device to bypass the system cache level and access the allocated dedicated memory segment through direct memory access by establishing address translation and access control rules at the firmware layer. The method includes the following steps: Step 400: Register an access permission table for each device at the firmware layer to specify the physical address range corresponding to the exclusive memory segment that each device can access.

[0054] Specifically, based on the device address mapping table constructed in step 304, detailed access control entries are established for each device to ensure that the device can only access its allocated dedicated memory segment region. The registration process of the access permission table establishes detailed access control entries for each device. These entries define the range of memory addresses that the device can access, specifically including the complete interval from the starting physical address of the device's dedicated memory segment to the starting physical address plus the allocated memory segment size. The system extracts the starting physical address and memory segment allocation size information for each device from the device address mapping table and calculates the access address boundary range for each device. The structure design of the permission table entries includes fields such as a unique device identifier, the allowed starting physical address, the allowed ending physical address, the access type identifier, and the permission level configuration. The starting physical address directly references the starting physical address of the device's dedicated memory segment, and the ending physical address is calculated by adding one to the starting physical address and the allocated memory segment size, ensuring the definition of the address range.

[0055] The system establishes access permission verification at the firmware layer. When a device initiates a memory access request, the firmware first queries the access permission table to verify whether the target address of the request is within the range of physical addresses allowed by the device. If the access address exceeds the authorized range, the firmware will immediately reject the access request and record the violation event, ensuring the security and isolation of memory access. The access permission table is implemented using an efficient lookup structure, supporting fast permission verification based on device identifiers. The system establishes an index for the permission table, using the device's unique identifier as the lookup key, achieving constant-time performance for permission queries. This ensures that permission verification does not significantly impact the overall system performance.

[0056] Step 401: Configure read and write permissions for each device and enable direct memory access mode, and configure the security level of each device to hardware enforcement.

[0057] Specifically, based on the access permission table established in step 400, the operation permissions and security control policies of the devices are further refined. The read / write permission configuration process determines the specific operational capabilities of each device for its dedicated memory segment. The system sets read / write permissions for each device, allowing authorized devices to perform data read and write operations on their dedicated memory segments. Permission configuration is determined based on device type and expected operating mode. High-speed network interface cards typically require full read / write permissions to support bidirectional data transmission, and the storage controller configures corresponding access permissions according to its functional characteristics.

[0058] The system sets a direct memory access mode flag in the device permission configuration, indicating that the device can bypass the traditional operating system kernel buffer and driver buffer to directly access the target memory segment. This mode configuration eliminates the data copying process between multi-level buffers in traditional architectures, significantly improving data transmission efficiency. The security level is configured to hardware enforcement mode to ensure the reliability and unbypassability of access control. Hardware enforcement means that permission verification and access control are directly implemented by the hardware-level memory management unit, without relying on software-level permission checks. This configuration uses hardware-level access control logic to perform real-time permission verification when the device attempts to access memory; unauthorized access attempts will be directly rejected by the hardware. The system assigns a security token to each device, which is embedded in the device's memory access request as the basis for hardware permission verification. When the memory management unit receives a memory access request, it first verifies the legality of the security token, and then checks whether the access address is within the authorized range of the device, ensuring that the access operation complies with the preset security policy.

[0059] Step 402: Allocate a dedicated hardware channel for each device in the direct memory access controller, limit the range of transmission addresses to a dedicated memory segment, and set the transmission mode to direct memory access to bypass the system cache level.

[0060] Specifically, a hardware-level pass-through connection is established between the device and its dedicated memory segment. The allocation process for the dedicated hardware channel involves creating an independent data transfer channel for each device within the direct memory access controller. Based on the device information in the device address mapping table, the system assigns a unique hardware channel identifier to each device. This channel configuration defines the source and destination address ranges for data transfer, both pointing to the dedicated memory segment allocated to the device, ensuring that data transfer is strictly confined to the authorized memory area.

[0061] The transfer address range is limited through hardware register configuration. The system sets the address boundary parameters for each device-specific channel in the corresponding registers of the Direct Memory Access Controller (DMI), including the minimum and maximum allowed physical addresses. During data transfer, the DMI automatically verifies whether the transfer address is within the preset address range; transfer requests outside this range are directly blocked by the hardware. The transfer mode is configured as Direct Memory Access, bypassing CPU intervention and system cache levels. This mode configuration allows devices to directly exchange data with the target memory segment, avoiding the multi-level buffering and context switching overhead of traditional data transfer paths. The system sets the transfer mode register in the DMI to instruct data transfer to be performed using hardware pass-through.

[0062] The system assigns a unique interrupt vector to each device to ensure timely notification to relevant components upon completion of data transmission. Interrupt vector configuration includes interrupt number assignment, interrupt priority setting, and interrupt handler binding. When a device completes a data transmission operation, the Direct Memory Access Controller (DMI) sends a completion notification to the system via the pre-configured interrupt vector, triggering the data processing flow. Concurrency control ensures data consistency during concurrent access by multiple devices through hardware-level mutexes. The system establishes channel coordination within the DMI; when multiple devices simultaneously access adjacent or overlapping memory regions, the hardware automatically performs access serialization to avoid data races or consistency issues caused by concurrent access.

[0063] Step 403: Create address translation entries for each device in the system memory management unit, map the virtual address space of each device to its own physical memory address, and configure cache consistency mode.

[0064] Specifically, a virtual-to-physical address translation mechanism is established to provide a unified virtual address access interface for each device. The creation of address translation entries involves establishing a dedicated address mapping record for each device within the memory management unit. The virtual address base is set to a device-specific virtual address space, which provides an independent address access view for each device, shielding it from the complexity of the underlying physical addresses. The physical address base points to the starting physical address of the dedicated memory segment allocated to the device, establishing a direct mapping relationship between virtual and physical addresses.

[0065] The address mapping mode employs a controlled one-to-one mapping strategy, ensuring that each address in the device's virtual address space has a unique corresponding physical address. The system calculates the size of the virtual address space to be equal to the allocated size of the device's dedicated memory segment, maintaining a complete correspondence between the virtual address range and the physical address range. This mapping mode guarantees both access efficiency and system security. The cache consistency mode configuration addresses cache synchronization issues in multi-device environments. The system sets a cache consistency policy for each device's address translation entry, ensuring that the device's access operations to its dedicated memory segment maintain data consistency with the system cache. Cache consistency configuration includes elements such as cache refresh policies, cache invalidation, and cache synchronization protocols to prevent data errors caused by cache inconsistency. The protection flag configuration inherits access permission settings from the device's address mapping table, maintaining system security and access control consistency. The system embeds the read / write permissions and security level information configured in step 401 into the protection flag field of the address translation entry, ensuring that permission verification during the address translation process is consistent with the overall security policy. After the address translation entry is established, the system performs translation verification to confirm that the virtual address to physical address translation can be executed correctly. The verification process includes address translation accuracy testing, permission verification function testing, and cache consistency testing to ensure that address translation entries can provide reliable address translation services for data transmission.

[0066] The beneficial effects of this application's embodiments are as follows: By using firmware-level access permission tables and real-time verification, precise access control of dedicated memory segments by the device is achieved, ensuring access security and non-bypassability. The use of independent DMA channel configuration and concurrent access control ensures efficient and consistent data transmission in multi-device environments, improving system reliability. Establishing address translation and cache consistency in the memory management unit enables secure mapping between virtual and physical addresses, further enhancing the overall security and stability of the system.

[0067] Figure 5 This is a schematic diagram illustrating the process of establishing a firmware scheduling table through firmware, based on the mapping relationship between device identifiers and the physical addresses of dedicated memory segments, as provided in one embodiment of this application. Figure 5 As shown in the embodiments of this application, the data scheduling and control method based on motherboard memory pass-through establishes a firmware scheduling table based on the mapping relationship between device identifiers and the physical addresses of dedicated memory segments, including the following steps: Step 500: Based on the device identifier in each device address mapping table, create a corresponding scheduling entry for each device in the firmware scheduling table, and use the device identifier as the first dimension index of the firmware scheduling table.

[0068] Specifically, the basic data structure of the firmware scheduling table is established to provide a framework for configuring multi-dimensional scheduling parameters. The scheduling entry creation process extracts device identification information one by one from the device address mapping table. The system traverses each valid entry in the device address mapping table, reading the device's unique identifier as the basic data for the firmware scheduling table index. After the device identifier is extracted, the system allocates dedicated storage space for each device identifier in the firmware scheduling table, establishing a one-to-one mapping relationship between the device identifier and the scheduling entry.

[0069] The firmware scheduling table uses device identifiers as the first-dimensional index, ensuring the scheduling system can quickly locate corresponding scheduling parameters based on device identifiers. The system creates a unique index value for each device identifier, maintaining a strict correspondence with the unique device identifier in the device address mapping table, thus preserving data structure consistency and lookup efficiency. The initialization process of scheduling entries pre-allocates storage structures for scheduling parameters for each device. Although the specific parameter values ​​are configured in subsequent steps, this pre-allocation of storage space ensures the integrity of the scheduling table structure and access performance. The system simultaneously builds indexes during scheduling entry creation, supporting constant-time lookup operations based on device identifiers. After scheduling entries are created, the system performs integrity verification, confirming that the number of scheduling entries in the firmware scheduling table perfectly matches the number of valid devices in the device address mapping table, and verifying that each scheduling entry is correctly associated with its corresponding device identifier, ensuring the accuracy and integrity of the scheduling table structure.

[0070] Step 501: Extract the starting physical address and size information of each device's dedicated memory segment from the device address mapping table, and configure the starting physical address as the direct memory access address parameter in the firmware scheduling table.

[0071] Specifically, a direct association is established between the firmware scheduling table and physical memory addresses, providing an address basis for hardware-level memory access. The address information extraction process is based on the scheduling entries established in step 500. For each device identifier, the system queries and extracts the corresponding dedicated memory segment's starting physical address and memory segment allocation size information from the device address mapping table. The extraction process ensures the accuracy and completeness of the address information; the system verifies that the address information for each device has been successfully extracted and that the values ​​are valid.

[0072] The configuration process for the starting physical address involves directly writing the extracted address information into the direct memory access address field of the corresponding scheduling entry in the firmware scheduling table. This address parameter serves as the target address reference when the device performs direct memory access, directly pointing to the starting position of the dedicated memory segment allocated to the device, ensuring that the device can accurately access its authorized memory region. The memory segment size information is also configured in the scheduling table as the basis for address boundary verification. The system stores the memory segment allocation size information in the corresponding field of the scheduling entry. This information, together with the starting physical address, defines the complete range of memory addresses accessible by the device, providing a parameter basis for address boundary checks and access control. After the address parameters are configured, the system performs address validity verification to confirm that all configured starting physical addresses are within the valid physical memory range, verify that address alignment meets hardware access requirements, and check that the memory address ranges of different devices do not overlap or conflict, ensuring the security and correctness of memory access.

[0073] Step 502: The firmware scheduling table adopts a three-dimensional structure. The first dimension is the device identifier, the second dimension is the data stream type, and the third dimension is the set of scheduling parameters.

[0074] Specifically, the three-dimensional structural design supports multi-dimensional priority management, providing fine-grained scheduling control capabilities for different data stream types from different devices. The first dimension, device identification, is based on the scheduling entries established in step 500, allocating an independent index space for each device in the scheduling table. This device identification dimension ensures the scheduling system can distinguish the scheduling needs of different devices, providing each device with independent scheduling parameter configuration and management capabilities. The second dimension, data stream type, is designed according to a predefined set of data stream types, including three basic types: real-time stream, batch stream, and interactive stream. Real-time streams are suitable for latency-sensitive applications, such as financial transactions and real-time monitoring systems, and have the highest scheduling priority. Batch streams are suitable for large-volume data transmission scenarios, such as data backup and batch processing tasks, focusing on throughput optimization. Interactive streams are suitable for user interaction applications, balancing latency and throughput requirements. The third dimension, the scheduling parameter set, contains the complete scheduling control parameters required for each device's stream type combination. This dimension supports multi-parameter collaborative scheduling, enabling the system to achieve fine-grained performance control and resource allocation based on different combinations of scheduling parameters.

[0075] The three-dimensional index adopts the access pattern of the firmware scheduling table FST[Device Identifier][Data Stream Type][Scheduling Parameter Set]. This index design supports efficient parameter lookup and update operations, enabling the scheduling system to quickly locate the required scheduling parameters based on the device identifier and data stream type, thus achieving real-time scheduling decisions. After the structural design is completed, the system allocates complete storage space for the three-dimensional scheduling table and establishes a multi-dimensional index to ensure that the scheduling table can support all expected combinations of device numbers and data stream types, providing a stable data structure foundation for scheduling parameter configuration and scheduling algorithm execution.

[0076] Step 503: Each firmware scheduling entry includes priority weight, queue depth limit, bandwidth allocation weight, direct memory access address, and access permissions.

[0077] Specifically, complete scheduling control parameters are configured for each three-dimensional index position in the firmware scheduling table to achieve fine-grained scheduling management capabilities. Priority weight parameters are used to determine the relative importance of the device flow type combination during arbitration. Based on a predefined basic priority configuration matrix, the system assigns initial priority weight values ​​to combinations of different device types and data flow types. Real-time flows typically receive higher priority weights to ensure that low-latency requirements are met first. Batch flows receive medium priority weights to balance processing efficiency and resource consumption. Interactive flows receive appropriate weight configurations based on specific application requirements. Queue depth limit parameters are used to prevent a single device from consuming excessive buffer resources, ensuring the overall fairness and stability of the system. The system sets queue depth limits based on device type and expected workload; high-performance devices typically receive larger queue depth limits to support burst traffic processing, while general-performance devices receive moderate limits to avoid excessive resource consumption.

[0078] The bandwidth allocation weight parameter represents the weight share of the device's flow type in the total bandwidth. The system calculates the bandwidth allocation weight based on the device's traffic weight and data flow type characteristics to ensure reasonable allocation of bandwidth resources. To ensure the consistency of the scheduling table, the system uses normalization processing, controlling the sum of the bandwidth allocation weights of all devices to within 85% of the total system bandwidth capacity, reserving a 15% buffer space to cope with load bursts and system overhead. The direct memory access address parameter directly references the physical address mapping result configured in step 501, ensuring that the scheduling parameters are consistent with the actual memory allocation. This parameter provides the scheduling system with the target address information for device memory access, supporting hardware-level direct memory access operations. The access permission parameter inherits the permission configuration established in step 401, ensuring that scheduling operations comply with security policies and access control requirements. This parameter includes read / write permission settings, security level configuration, and hardware enforcement flags, maintaining security and permission consistency during the scheduling process. After the parameter configuration is completed, the system establishes a fast index for the scheduling table and a concurrent access control lock to ensure the access security and performance efficiency of the scheduling table in a multi-threaded environment. The system also generates an initial bandwidth weight allocation scheme, providing basic configuration parameters for the real-time arbitration algorithm and ensuring that the firmware scheduling table can support efficient real-time scheduling decisions and dynamic parameter adjustments.

[0079] The beneficial effects of this application's embodiments are as follows: A firmware scheduling table structure with device identifier as the core index is established, realizing a direct association between scheduling and physical memory allocation, thereby improving the location efficiency and management accuracy of device scheduling. Through three-dimensional scheduling table design and multi-parameter configuration, differentiated scheduling strategies for different data stream types are supported, achieving a balance between flexibility and security in bandwidth allocation, priority management, and access control.

[0080] Figure 6 This is a schematic diagram illustrating the process of establishing a firmware scheduling table through firmware, based on the mapping relationship between device identifiers and the physical addresses of dedicated memory segments, as provided in one embodiment of this application. Figure 6 As shown in the embodiments of this application, the data scheduling and control method based on motherboard memory passthrough allocates priority to each direct memory access request and sorts them according to the firmware scheduling table, including the following steps: Step 600: Based on the device identifier and data stream type of the direct memory access request, query and extract the corresponding priority weight and queue depth limit parameters from the firmware scheduling table.

[0081] Specifically, a correlation is established between direct memory access requests and scheduling parameters to provide the foundational data for arbitration weight calculation. The parameter query process first parses the device identification information for each direct memory access request. The system extracts two parameters from the direct memory access request: device identifier and data stream type. The device identifier is used to determine the specific device from which the request originates, and the data stream type is used to identify the processing characteristics and priority requirements of the request. The system verifies the correctness and validity of the extracted identification information format to ensure the accuracy of subsequent query operations.

[0082] The firmware scheduling table query operation utilizes the three-dimensional index structure established in step 502. The system quickly locates the target scheduling parameter through the access mode of the firmware scheduling table FST[Device Identifier][Data Stream Type][Scheduling Parameter Set]. The query process leverages the index established in step 500 to achieve parameter retrieval with constant time complexity, ensuring the real-time response performance of the scheduling system. The priority weight parameter extraction process reads the Priority_Weight value from the corresponding entry in the firmware scheduling table. This value reflects the relative importance of a specific device and data stream type combination in scheduling arbitration. The system also extracts the queue depth limit parameter Queue_Depth_Limit, which defines the maximum queue capacity allowed for the corresponding device under the current data stream type, preventing a single device from excessively consuming system buffer resources. After parameter extraction, the system performs data integrity verification to confirm that all extracted parameter values ​​are within the expected range and meet system configuration requirements. If parameter anomalies or missing parameters are found, the system will trigger exception handling, using default scheduling parameters to ensure stable system operation, and recording the exception event for subsequent analysis and correction.

[0083] Step 601: Based on the extracted priority weights and combined with the current queue depth status, calculate the arbitration weights of each device under different data flow types. The arbitration weights are calculated by combining the priority weights with the queue depth adjustment factor, which is used to characterize the load status of the current device's request queue.

[0084] Specifically, the arbitration weight is calculated using a priority weight and a queue depth adjustment factor, which characterizes the load status of the current device's request queue. The current queue depth status monitoring process acquires the request queue occupancy status of each device in real time. The system maintains a current queue depth counter for each device. This counter records the number of direct memory access requests currently awaiting processing on a specific device. Queue depth monitoring uses atomic operations for updates, ensuring the accuracy and consistency of the counter value in a multi-threaded environment.

[0085] The queue depth adjustment factor is calculated using an improved load balancing algorithm, specifically: ; in, For equipment queue depth adjustment factor The adjustment coefficient is affected by queue depth. , For equipment Queue depth limit, For equipment The current queue depth.

[0086] This improved formula uses a max function to ensure that the adjustment factor does not decrease excessively, avoiding the numerical stability problem of weight values ​​approaching zero. Current queue depth. The closer to the queue depth limit When the queue depth is low, the adjustment factor is appropriately reduced to achieve load balancing. When the queue depth is low, the adjustment factor is kept at a high value to ensure that the device can obtain the corresponding scheduling resources. The final calculation of the arbitration weight is obtained by calculating the priority weight and the queue depth adjustment factor: ; in, For equipment Arbitration weight, For devices in the Firmware Scheduler (FST) The priority weights correspond to the flow type. This calculation method comprehensively considers the device's basic priority and current load status, achieving an effective combination of priority scheduling and load balancing.

[0087] Step 602: Use the arbitration weight as the basis for priority allocation to determine the scheduling order.

[0088] Specifically, based on the arbitration weights calculated in step 601, a scheduling priority sequence for all pending direct memory access requests is established. The scheduling order determination algorithm uses weighted sorting, and the system arranges all direct memory access requests in descending order according to their corresponding arbitration weights. Requests with higher arbitration weights receive higher scheduling priorities and will be processed more quickly during the scheduling process. The sorting algorithm uses efficient quicksort or heapsort to ensure that the time complexity of the sorting operation is kept within an acceptable range.

[0089] The priority allocation process assigns a unique priority number to each direct memory access request, with numbers increasing sequentially from the beginning; smaller numbers indicate higher priority. The system handles requests with equal arbitration weights simultaneously, using a first-in, first-out (FIFO) principle to determine the scheduling order of requests with the same weight, ensuring fairness and determinism in the scheduling decision. Scheduling latency estimation, considering current system load and hardware processing capabilities, calculates the expected scheduling latency for each request. The estimation method considers factors such as the expected processing time of preceding requests, current system resource usage, and hardware concurrency capabilities, providing a basis for subsequent dynamic bandwidth allocation and performance optimization. After the scheduling order is determined, the system generates a complete priority allocation result table, recording the final priority number, corresponding arbitration weight value, and estimated scheduling latency for each direct memory access request. This result table serves as input data for the sorting operation in step 603, ensuring the accuracy and efficiency of the sorting process.

[0090] Step 603: Sort all waiting direct memory access requests according to the scheduling order.

[0091] Specifically, the scheduling order determined in step 602 is transformed into a specific request processing sequence, establishing a scheduling queue for actual system execution. The request sorting operation is based on the priority allocation result generated in step 602; the system reorganizes all pending direct memory access requests according to their priority numbers. The sorting process employs a stable sorting algorithm to ensure that requests with the same priority maintain their original relative order, guaranteeing the consistency and predictability of scheduling decisions.

[0092] The sorted request queue is managed using a priority queue data structure, supporting dynamic insertion of high-priority requests and deferred processing of low-priority requests. The system establishes multi-level priority queues, allocating requests to different levels of queues based on the range of arbitration weights, achieving finer-grained scheduling control and higher processing efficiency. Request queue maintenance includes queue status monitoring, queue capacity management, and queue fairness assurance. The system monitors the occupancy of each priority queue in real time to prevent excessive occupancy of high-priority queues from causing low-priority requests to wait for extended periods. Queue capacity management ensures that the total size of the system's request queue is kept within a reasonable range, avoiding excessive memory resource consumption. After sorting, the system generates the final scheduling execution queue, which contains all pending direct memory access requests in descending priority order. The scheduling execution queue supports real-time updates; when new direct memory access requests arrive or the priority of existing requests changes, the system can dynamically adjust the queue contents to ensure that scheduling decisions are always based on the latest system state and priority configuration.

[0093] The beneficial effects of this application's embodiments are as follows: By employing a three-dimensional index structure and efficient querying, constant-time complexity retrieval of scheduling parameters is achieved, ensuring the system's real-time response capability. An arbitration weight calculation algorithm based on comprehensive load status dynamically combines device priority and queue depth, achieving a unified approach to priority scheduling and load balancing. Arbitration weight-based sorting and multi-level queue management ensure the consistency and predictability of scheduling decisions and support real-time updates to adapt to dynamic system changes.

[0094] Figure 7 This is a schematic diagram illustrating a process for real-time monitoring of data transmission latency of each device, and dynamic adjustment of priority weights and bandwidth allocation in the firmware scheduling table based on the latency monitoring results of direct memory access requests, according to one embodiment of this application. Figure 7 As shown in the embodiments of this application, the data scheduling and control method based on motherboard memory passthrough monitors the data transmission latency of each device in real time, and dynamically adjusts the priority weights and bandwidth allocation in the firmware scheduling table based on the latency monitoring results of direct memory access requests, including the following steps: Step 700: Record the complete time span from the initiation of the direct memory access request to the completion of the data transfer as the single transfer delay.

[0095] Specifically, latency measurement is established to provide accurate foundational data for latency analysis and dynamic adjustments. A complete timestamp recording system is established at the firmware level for transmission latency measurement. When a device initiates a memory pass-through access request, the firmware records a start timestamp the instant the request is received. This timestamp marks the precise moment the direct memory access request enters the system scheduling queue. The system uses a high-precision clock counter to acquire timestamp data, ensuring the accuracy and consistency of time measurements.

[0096] Data transmission completion is detected via a completion interrupt signal from the Direct Memory Access Controller (DMI). When a device completes a data transmission operation to a dedicated memory segment, the DMI sends a transmission completion notification to the firmware, which records an end timestamp upon receiving the notification. This ensures that transmission latency measurement covers the entire time span from request initiation to actual data transmission completion. The calculation of single transmission latency uses time difference arithmetic: the system calculates the difference between the end timestamp and the start timestamp, then divides it by the system clock frequency to obtain the latency value in microseconds. This calculation method eliminates the influence of system clock frequency differences on the measurement results, ensuring the standardization and comparability of latency data. Latency data storage and management employ a circular buffer structure, with the system maintaining an independent latency data recording queue for each device. The buffer design supports real-time data updates and historical data retention, providing a complete data foundation for smooth latency calculations and trend analysis. The system also establishes anomaly latency filtering, automatically identifying and processing latency data that significantly exceeds the normal range, avoiding interference from outliers in the overall analysis results.

[0097] Step 701: The exponentially weighted moving average algorithm is used to obtain the smoothed delay value by weighting the current transmission delay monitoring result and the historical smoothed delay value according to a preset weight ratio.

[0098] Specifically, this eliminates instantaneous fluctuations in transmission delay and establishes a stable and reliable delay assessment benchmark. The implementation of the exponentially weighted moving average algorithm uses a recursive calculation method: ; in, This is the smoothed delay value at the current moment. This is the monitoring result of a single transmission delay at the current moment. This is the smoothed delay value from the previous moment. This is a smoothing factor.

[0099] The recursive property of this algorithm can be expressed as: ; The weighting coefficients decay over time, satisfying the following: ; when At that time, the initial smoothing delay value was used for start-up learning. ; in, The number of samples during the initialization phase is set to 5-10.

[0100] This recursive calculation method allows the smoothed delay value to gradually adapt to the trend of delay changes, while maintaining the memory effect of historical delay data and avoiding evaluation bias caused by a single abnormal delay.

[0101] The initialization of the smoothed delay value employs a startup learning approach. When the device first runs, the system uses the simple average of the previous few actual delay measurements as the initial smoothed delay value. This ensures that the smoothed delay value quickly converges to a reasonable range, avoiding the impact of data deviations during the initialization phase on subsequent calculations. The system maintains independent smoothed delay values ​​for each device and data stream type combination, ensuring that delay characteristics under different application scenarios are accurately reflected. Updates to the smoothed delay value are implemented using atomic operations, guaranteeing data consistency and accuracy in a multi-threaded environment and providing reliable input parameters for dynamically adjusting the algorithm.

[0102] Step 702: Based on the comparison result between the smoothed delay value and the preset target delay benchmark, dynamically adjust the priority weight of the corresponding device in the firmware scheduling table. When the smoothed delay value exceeds the target delay benchmark, increase the priority weight; when the smoothed delay value is lower than the target delay benchmark, decrease the priority weight.

[0103] Specifically, the target latency baseline is set based on the actual needs of the application scenario and system performance metrics. Real-time streaming typically has a lower target latency baseline to ensure fast response times for latency-sensitive applications. Batch streaming has a more lenient target latency baseline, focusing on overall throughput optimization. Interactive streaming has a target latency baseline that falls between the two, balancing response speed and processing efficiency.

[0104] The priority weight adjustment algorithm employs a proportional control strategy, with the adjustment magnitude directly proportional to the degree of latency deviation. When the smoothed latency value exceeds the target latency benchmark, the system calculates the excess latency percentage and accordingly increases the priority weight of the corresponding data stream type for that device. The weight increase is controlled by a preset adjustment factor to ensure the stability and controllability of the adjustment process. The specific implementation of weight adjustment involves modifying the Priority_Weight parameter of the corresponding entry in the firmware scheduling table. The system calculates the new priority weight value and updates the corresponding data in the firmware scheduling table through atomic operations. Version control is used for the update operation to ensure the consistency of the scheduling table and the security of concurrent access. The adjustment process includes boundary checks to prevent priority weights from exceeding a preset reasonable range. The system sets upper and lower limits for weight adjustment; when the calculation result exceeds the boundaries, the weight value is automatically limited to the effective range. This prevents adverse effects of weight adjustment on system stability in extreme cases.

[0105] Step 703: Calculate the delay deviation normalization factor using the target delay benchmark and the smoothed delay value.

[0106] Specifically, a standardized latency deviation quantification is established to provide a unified calculation benchmark for the dynamic adjustment of bandwidth allocation weights. The latency deviation normalization factor is calculated as follows: the latency deviation normalization factor equals the difference between the target latency benchmark and the smoothed latency value, divided by the target latency benchmark. This formula converts the absolute latency difference into a relative proportion, eliminating the impact of differences in target latency benchmarks between different devices on the adjustment results and ensuring the fairness and consistency of the adjustment algorithm. The numerical range and meaning of the normalization factor have clear physical significance. When the smoothed latency value equals the target latency benchmark, the normalization factor is zero, indicating that the latency performance meets the expected requirements. When the smoothed latency value is lower than the target latency benchmark, the normalization factor is positive, indicating that the latency performance is better than expected, and resource allocation can be appropriately reduced. When the smoothed latency value exceeds the target latency benchmark, the normalization factor is negative, indicating that the latency performance does not meet the standard, and resource allocation needs to be increased. The calculation process includes numerical stability protection. When the target latency benchmark is close to zero, the system uses the minimum threshold as a substitute to avoid numerical anomalies caused by division by zero. At the same time, an effective range limit for the normalization factor is established to prevent the calculation results from exceeding the reasonable range under extreme latency conditions. The system independently calculates the latency deviation normalization factor for each device and data stream type combination, ensuring that adjustment decisions accurately reflect their respective latency conditions. The calculation results are stored as high-precision floating-point numbers to guarantee the accuracy and reliability of subsequent bandwidth adjustment calculations.

[0107] Step 704: Dynamically adjust the bandwidth allocation weight in the firmware scheduling table based on the delay deviation normalization factor.

[0108] Specifically, by reallocating bandwidth resources, the overall system transmission performance is optimized and latency accumulation is prevented. The bandwidth allocation weight adjustment algorithm is based on the latency feedback control principle, determining the adjustment direction and magnitude of bandwidth allocation through a latency deviation normalization factor. The adjustment formula is: the new bandwidth allocation weight equals the current bandwidth allocation weight plus the bandwidth adjustment step parameter multiplied by the latency deviation normalization factor. The bandwidth adjustment step parameter controls the sensitivity and stability of the adjustment and is optimized through system configuration.

[0109] When the latency deviation normalization factor is negative, it indicates that the device latency exceeds the target baseline. The system increases the bandwidth allocation weight of this device, providing more transmission resources to improve latency performance. When the latency deviation normalization factor is positive, it indicates that the device latency is better than the target baseline. The system can appropriately reduce the bandwidth allocation weight of this device, releasing resources to other devices that need them. The bandwidth weight adjustment process includes system capacity constraint checks to ensure that the sum of the new bandwidth allocation weights for all devices does not exceed 85% of the total available bandwidth capacity of the system, maintaining a 15% safety buffer. When the adjustment results in the total weight exceeding the limit, the system uses a proportional scaling method to adjust the weight allocation of all devices proportionally, maintaining the relative allocation ratio unchanged. The application of the adjustment results is achieved by updating the corresponding Bandwidth_Weight parameter in the firmware scheduling table. The system uses transactional updates to ensure the atomicity and consistency of the bandwidth weight adjustment. After the update is completed, the new bandwidth allocation weight takes effect immediately, affecting the resource allocation decisions of subsequent scheduling cycles, forming a closed-loop control of latency monitoring, weight adjustment, and performance optimization.

[0110] The beneficial effects of this application's embodiments are as follows: By recording delays and performing smooth calculations, a stable and reliable delay evaluation benchmark is obtained, avoiding the impact of instantaneous fluctuations and providing an accurate reference for dynamic optimization. Establishing a dynamic adjustment of priority and bandwidth based on delay feedback enables adaptive allocation of scheduling resources, ensuring the performance requirements of delay-sensitive devices and maintaining overall system stability. A closed-loop control system of delay monitoring, weight adjustment, and bandwidth allocation is formed, ensuring the real-time performance, rationality, and scalability of the scheduling process.

[0111] Figure 8 This is a schematic diagram illustrating a process for scheduling and controlling device memory access behavior based on the sorting results of each direct memory access request, as provided in one embodiment of this application. Figure 8 As shown in the embodiments of this application, the data scheduling and control method based on motherboard memory passthrough completes the scheduling and control of device memory access behavior based on the sorting results of each direct memory access request, including the following steps: Step 800: According to the priority sorting result in the ordered scheduling execution queue, each direct memory access request is processed in turn, and the direct memory access request with higher priority is given priority scheduling execution rights.

[0112] Specifically, the scheduling execution queue generated in step 603 is transformed into actual hardware scheduling operations to ensure that high-priority requests are processed in a timely manner. Scheduling execution is based on the multi-level priority queue structure established in step 603. The system processes direct memory access requests sequentially according to their priority numbers, from smallest to largest. The scheduler employs a preemptive scheduling strategy; when a higher-priority request arrives, the system can interrupt the currently processing low-priority request and prioritize urgent requests, ensuring that real-time requirements are met.

[0113] The specific execution process of request processing is coordinated by the firmware scheduler across various hardware components. The system first extracts the highest-priority direct memory access request from the head of the scheduling execution queue. Then, based on the device identifier and target memory address information in the request, it configures the corresponding hardware transmission channel. The configuration process includes setting parameters such as the source address, destination address, data transfer size, and transmission mode. Execution permission allocation ensures that only authorized requests can occupy specific hardware resources at any given time. The system maintains a hardware resource occupancy status table, recording the current usage of each direct memory access channel. When a request begins execution, the system marks the corresponding hardware resource as occupied; when the request completes, it releases the relevant resources for subsequent requests. The scheduling execution process includes complete status tracking, with the system monitoring the processing progress of each executing direct memory access request in real time. When a request successfully completes, the system updates the request status and triggers a completion notification. When an exception occurs during request execution, the system records the error information and initiates an exception handling process to ensure system stability and reliability.

[0114] Step 801: Allocate hardware resources according to the sorting results, giving priority to allocating available direct memory access channels and bandwidth resources to high-priority direct memory access requests.

[0115] Specifically, resource allocation priorities are established to ensure that requests receive sufficient hardware support. The hardware resource allocation algorithm is based on the sorting results of step 603 and the current availability of hardware resources. The system maintains a resource pool for direct memory access channels, including the number of available channels, the processing capacity of each channel, and its current load. The allocation algorithm prioritizes allocating the best-performing hardware channel to the highest-priority direct memory access request, ensuring that high-priority requests receive optimal processing resources. Bandwidth resource allocation is based on the bandwidth allocation weight parameters dynamically adjusted in step 704. The system calculates the bandwidth share that each device should receive in the current scheduling cycle based on the updated Bandwidth_Weight value in the firmware scheduling table. Bandwidth allocation uses a weighted fair queue algorithm to ensure that each device receives corresponding transmission bandwidth according to its weight ratio, while guaranteeing the advantageous position of high-priority requests in bandwidth contention.

[0116] The dynamic adjustment of resource allocation optimizes resource utilization efficiency based on the real-time system load. When some hardware channels are detected to be idle, the system dynamically allocates these resources to high-priority requests waiting to be processed, improving resource utilization. When the overall system load is high, the resource allocation algorithm employs stricter priority control to ensure that requests are not affected. The allocation process includes resource conflict detection and resolution. When multiple high-priority requests simultaneously compete for limited hardware resources, the system arbitrates based on the specific priority value and timestamp information of the requests, employing a strategy that combines highest priority first and first-come, first-served to ensure the fairness and efficiency of resource allocation.

[0117] Step 802: Establish anomaly detection based on delay monitoring results, and determine the grading criteria for mild, moderate and severe anomalies based on the comparison results between delay monitoring results and benchmark values.

[0118] Specifically, a complete performance anomaly identification system is established to provide a basis for adaptive adjustments. Anomaly detection utilizes the smoothed latency value calculated in step 701 as the primary judgment criterion. The system compares the smoothed latency value of each device with the corresponding historical baseline latency. The historical baseline latency is calculated using long-term statistical data and reflects the typical latency level of the device under normal operating conditions. The grading standards are set based on the severity of latency exceeding the standard. The criterion for mild anomaly is that the smoothed latency value exceeds 1.2 times but does not reach 1.5 times the historical baseline latency. This level indicates a slight deterioration in latency performance, requiring attention but not immediate intervention. The criterion for moderate anomaly is that the latency exceeds 1.5 times but does not reach 2.0 times the baseline, indicating a more significant latency problem requiring adjustment measures. The criterion for severe anomaly is that the latency exceeds 2.0 times the baseline, indicating a severe deterioration in latency performance requiring urgent handling. The anomaly detection algorithm uses a sliding window to avoid misjudgments caused by single latency fluctuations. The system continuously monitors the latency status within a preset time window. Only when the abnormal conditions are continuously met within the window period is the corresponding level of anomaly flag triggered. This improves the accuracy and stability of anomaly detection. The processing of detection results adopts a graded response strategy. Minor anomalies trigger monitoring alarms, and the system records the abnormal event but does not immediately adjust scheduling parameters. Moderate anomalies initiate minor priority adjustments, moderately increasing the scheduling priority of the corresponding device. Severe anomalies trigger emergency scheduling mode, significantly increasing the device priority and allocating additional system resources.

[0119] Step 803: Combine the current system load status and queue depth information in the sorting results to dynamically calculate and adjust the delay control threshold and queue depth threshold.

[0120] Specifically, an adaptive threshold management system is established, enabling the system to optimize performance control standards based on actual operating conditions. The dynamic adjustment of the latency control threshold is calculated based on the deviation between the current system load factor and the optimal load factor. The system load factor is defined as the ratio of the number of currently active transmission requests to the system's maximum concurrency capacity. The optimal load factor is determined through historical performance data statistics and is typically set between 0.7 and 0.8.

[0121] The delay threshold is calculated as follows: the new delay control threshold equals the system target delay upper limit multiplied by an adjustment factor. The adjustment factor AC is: ; in, For load adjustment factor, The current load factor is... Optimal load factor.

[0122] This algorithm enables the latency threshold to adaptively change according to system load conditions, appropriately relaxing the threshold standard under high load and tightening the control requirements under low load. The dynamic adjustment of the queue depth threshold is calculated based on the latency variance. The latency variance reflects the stability of the system transmission delay; a larger variance indicates more severe system jitter, requiring more stringent queue depth control. The new queue depth threshold is: ; ; ; in, The new queue depth threshold, Based on the basic queue depth threshold, This is the variance adjustment factor. Delayed variance adjustment factor To normalize the delayed variance, The current delay variance, This represents the historical baseline variance. When system latency fluctuates significantly, the threshold is appropriately lowered to improve control accuracy; conversely, when the system is running stably, the threshold is correspondingly increased to enhance processing efficiency.

[0123] Step 804: When the transmission delay or queue depth of the current device is detected to exceed the corresponding threshold, the scheduling decision is re-executed based on the updated firmware scheduling table, and the direct memory access request of the current device is promoted to a higher priority queue position to complete adaptive flow control.

[0124] Specifically, the flow control trigger condition is based on the anomaly detection result in step 802 and the dynamic threshold comparison in step 803. When the transmission delay of a device exceeds its corresponding delay control threshold, in real-time streaming application scenarios, the basic target delay is 50-100 microseconds, the delay control threshold is 60-120 microseconds (1.2 times the basic target), and the emergency handling threshold is 100-200 microseconds (2.0 times the basic target); in interactive streaming application scenarios, the basic target delay is 200-500 microseconds, the delay control threshold is 240-600 microseconds, and the emergency handling threshold is 400-1000 microseconds; in batch streaming application scenarios, the basic target delay is 1-5 milliseconds, the delay control threshold is 1.2-6 milliseconds, and the emergency handling threshold is 2-10 milliseconds. The basic queue depth limit for high-speed network interface cards is 256-512 requests, with a queue depth control threshold of 205-410 requests (80% of the limit) and a severe anomaly threshold of 230-460 requests (90% of the limit). For storage controllers, the basic queue depth limit is 128-256 requests, with a queue depth control threshold of 102-205 requests and a severe anomaly threshold of 115-230 requests. For graphics processing units, the basic queue depth limit is 64-128 requests, with a queue depth control threshold of 51-102 requests and a severe anomaly threshold of 58-115 requests. When the queue depth simultaneously exceeds the queue depth control threshold, the system determines that the device requires flow control intervention and initiates corresponding adjustments.

[0125] Priority elevation is adjusted based on the severity of the anomaly. The new priority weight equals the original priority weight multiplied by a priority elevation factor, which is dynamically determined based on the degree of latency exceeding the limit. The elevation factor is set to 1.2 for mild exceeding the limit, 1.5 for moderate exceeding the limit, and 2.0 for severe exceeding the limit, ensuring the adjustment matches the severity of the problem. The scheduling decision re-execution process is based on the updated firmware scheduling table parameters. The system writes the adjusted priority weight back to the firmware scheduling table established in step 503, updating the Priority_Weight parameter for the corresponding device and data stream type. The update operation uses atomic writes to ensure the consistency and real-time nature of parameter modifications. Queue position adjustment elevates direct memory access requests from the affected device from their current position to a higher priority queue position. The system recalculates the arbitration weight of the device's request, executes the arbitration weight calculation algorithm in step 601 based on the new priority weight, and then re-determines the request's position in the scheduling queue based on the new weight value. Flow control recovery monitors the improvement in device performance. When the transmission delay of a device returns to the normal range, i.e., below half of the delay control threshold, the system performs a priority normalization operation, restoring the priority weight of the device to its original configuration value, releasing the temporarily allocated additional scheduling resources for use by other devices, ensuring the reasonable allocation of system resources and the optimized balance of overall performance.

[0126] The beneficial effects of this application's embodiments are as follows: By employing preemptive priority scheduling and hardware resource priority allocation, high-priority requests are ensured to receive timely responses, while also considering the fairness and efficiency of resource allocation. A latency anomaly detection and dynamic threshold adjustment system is established to achieve a tiered response from alarms to emergency scheduling, and adaptive performance optimization is achieved by combining load status and queue depth. An adaptive flow control and closed-loop scheduling system is constructed to dynamically adjust scheduling parameters during anomalies and recovery processes, ensuring the system's real-time performance, stability, and efficiency.

[0127] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A data scheduling and control method based on motherboard memory pass-through, characterized in that, include: During the firmware initialization phase, pass-through memory regions are pre-allocated for multiple devices mounted on the motherboard, a dedicated memory segment is allocated for each device, and a mapping relationship is established between the device identifier and the physical address of the dedicated memory segment. By establishing address translation and access control rules at the firmware layer, the device can bypass the system cache level and access the allocated dedicated memory segment through direct memory access. Based on the mapping relationship between the device identifier and the physical address of the dedicated memory segment, a firmware scheduling table is established through the firmware. The firmware scheduling table is used to manage all direct memory access requests from all devices to the pass-through memory region. Real-time monitoring of data transmission latency of each device, and dynamic adjustment of priority weights and bandwidth allocation in the firmware scheduling table based on the latency monitoring results of the direct memory access request; Each direct memory access request is assigned a priority and sorted according to the firmware scheduling table; Based on the sorting results of each direct memory access request, the scheduling and control of device memory access behavior are completed.

2. The data scheduling and control method based on motherboard memory pass-through according to claim 1, characterized in that, During the firmware initialization phase, pre-allocating pass-through memory regions for multiple devices mounted on the motherboard includes: The predetermined allocation ratio of the total physical memory of the system is set as a pass-through memory region; The total capacity of the pass-through memory region is calculated by using the total physical memory of the system and the predetermined allocation ratio. The allocation strategy is from high address to low address, starting from the high address end of the system physical memory and aligning the addresses according to the memory page size specified by the processor architecture. Configure protection attributes for the pass-through memory region, including read / write permissions, direct memory access compatibility settings, and cache consistency policies.

3. The data scheduling and control method based on motherboard memory pass-through according to claim 2, characterized in that, The process of allocating dedicated memory segments to each device and establishing a mapping relationship between device identifiers and the physical addresses of the dedicated memory segments includes: Based on the total capacity of the determined pass-through memory region, the traffic weights of each device are normalized. The standardized weight allocation ratio of each device is determined by calculating the sum of the weights of all devices; Based on the total capacity of the pass-through memory region and the standardized weight allocation ratio of each device, the allocation size of the dedicated memory segment for each device is calculated and determined, and the size of the dedicated memory segment is down-aligned according to the predefined memory page size. The starting physical address of each device's dedicated memory segment is determined sequentially using a cumulative allocation method; Create a complete address mapping entry for each device identifier. The mapping entry includes a unique device identifier, the starting physical address of the corresponding dedicated memory segment, the memory segment allocation size, the device type identifier, and the access permission configuration. Construct a device address mapping table to establish the correspondence between the device identifier and the physical address of the dedicated memory segment.

4. The data scheduling and control method based on motherboard memory pass-through according to claim 3, characterized in that, The step of establishing address translation and access control rules at the firmware layer to enable the device to bypass the system cache layer and access the allocated dedicated memory segment via direct memory access includes: In the firmware layer, an access permission table is registered for each device to specify the physical address range corresponding to the dedicated memory segment that each device can access; Configure read and write permissions for each device and enable direct memory access mode, and configure the security level of each device to hardware enforcement; In the direct memory access controller, a dedicated hardware channel is allocated to each device, the range of transmission addresses is limited to the dedicated memory segment, and the transmission mode is set to direct memory access to bypass the system cache level; In the system memory management unit, address translation entries are created for each device to map the virtual address space of each device to a dedicated physical memory address, and a cache consistency mode is configured.

5. The data scheduling and control method based on motherboard memory pass-through according to claim 3, characterized in that, The process of establishing a firmware scheduling table based on the mapping relationship between the device identifier and the physical address of the dedicated memory segment includes: Based on the device identifier in the device address mapping table, a corresponding scheduling entry is created for each device in the firmware scheduling table, and the device identifier is used as the first dimension index of the firmware scheduling table. Extract the starting physical address and size information of each device-specific memory segment from the device address mapping table, and configure the starting physical address as the direct memory access address parameter in the firmware scheduling table; The firmware scheduling table adopts a three-dimensional structure, with the first dimension being the device identifier, the second dimension being the data stream type, and the third dimension being the set of scheduling parameters. Each firmware scheduling entry includes priority weight, queue depth limit, bandwidth allocation weight, direct memory access address, and access permissions.

6. The data scheduling and control method based on motherboard memory pass-through according to claim 5, characterized in that, The step of assigning priority and sorting each direct memory access request according to the firmware scheduling table includes: Based on the device identifier and data stream type of the direct memory access request, query and extract the corresponding priority weight and queue depth limit parameters from the firmware scheduling table; Based on the extracted priority weights and combined with the current queue depth status, the arbitration weights of each device under different data stream types are calculated. The arbitration weights are calculated by combining the priority weights with the queue depth adjustment factor, which is used to characterize the load status of the current device's request queue. The arbitration weights are used as the basis for priority allocation to determine the scheduling order; All waiting direct memory access requests are sorted according to the scheduling order.

7. A data scheduling and control method based on motherboard memory pass-through according to claim 6, characterized in that, The real-time monitoring of data transmission latency of each device, and the dynamic adjustment of priority weights and bandwidth allocation in the firmware scheduling table based on the latency monitoring results of the direct memory access requests, including: Record the complete time span from the initiation of the direct memory access request to the completion of data transmission as the single transmission delay; The exponentially weighted moving average algorithm is used to obtain the smoothed delay value by weighting the current transmission delay monitoring results with the historical smoothed delay values ​​according to a preset weight ratio. Based on the comparison between the smoothed latency value and the preset target latency benchmark, the priority weight of the corresponding device in the firmware scheduling table is dynamically adjusted. When the smoothed latency value exceeds the target latency benchmark, the priority weight is increased; when the smoothed latency value is lower than the target latency benchmark, the priority weight is decreased. The delay deviation normalization factor is calculated by using the target delay benchmark and the smoothed delay value; Based on the latency deviation normalization factor, the bandwidth allocation weight in the firmware scheduling table is dynamically adjusted.

8. A data scheduling and control method based on motherboard memory pass-through according to claim 7, characterized in that, The scheduling and control of device memory access behavior based on the sorting results of each direct memory access request includes: According to the priority sorting result in the ordered scheduling execution queue, each direct memory access request is processed in sequence, wherein the direct memory access request with higher priority is given priority scheduling execution privilege. Hardware resources are allocated according to the sorting results, with priority given to allocating available direct memory access channels and bandwidth resources to high-priority direct memory access requests. Anomaly detection is established based on the delay monitoring results, and the grading standards for mild, moderate and severe anomalies are determined based on the comparison results between the delay monitoring results and the benchmark values. Based on the current system load status and the queue depth information in the sorting results, the delay control threshold and the queue depth threshold are dynamically calculated and adjusted. When the transmission delay or queue depth of the current device is detected to exceed the corresponding threshold, the scheduling decision is re-executed based on the updated firmware scheduling table, and the direct memory access request of the current device is promoted to a higher priority queue position to complete adaptive flow control.

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