Method for realizing IIC reading, electronic equipment and readable storage medium

Abstract

The invention discloses a method for realizing IIC reading, electronic equipment and a readable storage medium, and belongs to the field of communication. The method comprises the following steps: acquiring target data transmitted by a master device through a system management bus; in response to an inter-integrated circuit IIC reading command contained in the target data, obtaining to-be-returned data corresponding to the IIC reading command; storing the to-be-returned data into a memory, and switching an input / output interface, corresponding to the system management bus, on the slave equipment into a general input / output mode; and sending the to-be-returned data to the master device in the general input and output mode.

Description

Technical Field

[0001] This application belongs to the field of communications, and specifically relates to a method for implementing IIC reading, an electronic device, and a readable storage medium. Background Technology

[0002] The System Management Bus (SMBus) is a two-wire serial bus that is currently widely used in low-speed communication scenarios. On the SMBus bus, the SMBus master device can obtain relevant information from the SMBus slave device through inter-integrated circuit (IIC) reading.

[0003] However, in the process of implementing IIC reading, the relevant technologies usually require the device to support the IIC reading function in hardware, and it is impossible to implement the IIC reading function without hardware support. Summary of the Invention

[0004] This application provides a method, electronic device, and readable storage medium for implementing IIC reading, which can solve the problem that related technologies cannot implement IIC reading function without hardware support.

[0005] In a first aspect, embodiments of this application provide a method for implementing IIC reading, applied to a slave device, comprising: Acquire the target data transmitted by the master device through the system management bus; In response to the target data containing an IIC read command, the data to be returned corresponding to the IIC read command is obtained; The data to be returned is stored in the memory, and the input / output interface on the slave device corresponding to the system management bus is switched to general input / output mode; The data to be returned is sent to the master device in the general input / output mode.

[0006] In a second aspect, embodiments of this application provide an electronic device, including a processor and a memory, wherein the memory stores a program or instructions, which, when executed by the processor, implement the method described in the first aspect.

[0007] Thirdly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the method described in the first aspect.

[0008] Fourthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0009] In this embodiment, in response to the target data transmitted by the master device including an IIC read command, the slave device can store the data to be returned corresponding to the IIC read command into its memory and switch the I / O interface of the SMBus bus to GPIO mode. In GPIO mode, the slave device sends the data to be returned to the master device, enabling the master device to obtain relevant information from the slave device via IIC read. Thus, without requiring the slave device to support IIC read functionality in hardware, this embodiment can implement the entire process of the master device obtaining relevant information from the slave device via IIC read through software, solving the problem that related technologies cannot implement IIC read functionality without hardware support. Attached Figure Description

[0010] Figure 1 This is a flowchart illustrating a method for implementing IIC reading according to an embodiment of this application; Figure 2 This is a flowchart of another method for implementing IIC reading provided in the embodiments of this application; Figure 3 This is a flowchart of another method for implementing IIC reading provided in the embodiments of this application; Figure 4 This is a flowchart of another method for implementing IIC reading provided in the embodiments of this application; Figure 5 This is a schematic diagram of a mode switching method provided in an embodiment of this application; Figure 6 This is a flowchart illustrating a method for implementing IIC reading according to an embodiment of this application; Figure 7 This is a schematic diagram of a process for implementing IIC reading provided in an embodiment of this application; Figure 8 This is a structural block diagram of a slave device provided in an embodiment of this application; Figure 9 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0012] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0013] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0014] The method for implementing IIC reading provided in this application embodiment is applied to the communication technology of SMBus bus. Specifically, it can be applied to the process of a master device obtaining relevant information from a slave device through IIC reading. This application embodiment can switch the input / output (IO) interface corresponding to the SMBus bus to the general purpose input / output (GPIO) mode, so that the IIC reading process can be simulated through GPIO mode, thereby eliminating the need for the slave device to support the IIC reading function in hardware.

[0015] The method for implementing IIC reading provided in this application embodiment can be executed by a slave device, which is a slave device on the SMBus bus.

[0016] The method for implementing IIC reading provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0017] For reference Figure 1 , Figure 1 This is a flowchart illustrating a method for implementing IIC reading according to an embodiment of this application, which is applied to a slave device. Figure 1 As shown, the method includes the following steps: Step 110: Obtain the target data transmitted by the master device via the SMBus bus.

[0018] In this embodiment, the SMBus bus is a two-wire serial bus based on IIC, typically used for communication with system management components such as power management chips, batteries, and temperature sensors. On the SMBus bus, the SMBus master device (hereinafter referred to as the master device) initiates and controls communication, while the SMBus slave device (hereinafter referred to as the slave device) listens for requests from the master device and responds accordingly. For example, when a slave device detects that the master device has initiated an IIC read operation, it sends corresponding data to the master device. For instance, the master device can be a host computer, and the slave device can be a storage device connected to the host computer, such as a solid-state drive (SSD).

[0019] Step 120: In response to the target data containing an IIC read command, obtain the data to be returned corresponding to the IIC read command.

[0020] In this embodiment, after the slave device acquires the target data via the SMBus bus, the target data can be parsed to determine whether it contains an IIC read command, i.e., whether the master device obtains relevant information from the slave device via IIC read. If it is determined that the target data contains an IIC read command, the slave device can obtain the data to be returned corresponding to the IIC read command; this data to be returned is the data to be read corresponding to the read command. If the target data does not contain an IIC read command, the slave device can respond accordingly to the target data in SMBus mode.

[0021] Step 130: Store the data to be returned into the memory, and switch the IO interface on the slave device corresponding to the SMBus bus to GPIO mode.

[0022] In this embodiment, the memory is, for example, the buffer of the slave device, into which the data to be returned is stored. The slave device has two I / O interfaces connected to the SMBus bus. By switching these two interfaces to GPIO mode, GPIO communication can be simulated via the SMBus bus. Specifically, these two I / O interfaces are the I / O interface for the serial data (Serial DA, SDA) channel and the I / O interface for the serial clock (Serial CLock, SCL) channel, respectively. The I / O interfaces for the SDA and SCL channels can be switched to GPIO mode, and are designated GPIO_27 and GPIO_28, respectively. In other words, this embodiment can multiplex the I / O interfaces on the slave device corresponding to the SMBus bus into GPIO mode, thereby implementing the IIC read function in GPIO mode.

[0023] Step 140: Send the data to be returned to the master device in the GPIO mode.

[0024] In this embodiment, the slave device can send the data to be returned stored in the memory (buffer) to the SMBus bus via the IO interface in GPIO mode, and then transmit the data to the master device via the SMBus bus. After sending the data, the IO interface can switch from GPIO mode to SMBus mode to resume the original SMBus communication. However, it should be noted that the switch to SMBus mode can be selected as appropriate, and the IO interface can also continue to transmit data via GPIO mode.

[0025] In this embodiment, it is not necessary for the slave device to support the IIC reading function in hardware. This embodiment can realize the entire process of the master device obtaining relevant information from the slave device through IIC reading in software, which solves the problem that related technologies cannot realize the IIC reading function without hardware support.

[0026] In one embodiment of this application, the slave device includes a master control chip, such as a master control chip for a storage device, and the master control chip includes an SMBus Intellectual Property (IP) core. Step 110, obtaining the target data transmitted by the master device via the SMBus bus, includes: reading the target data transmitted by the master device via the SMBus bus from the SMBus bus IP core. In this way, during data transmission between the master and slave devices, the master device can store the target data in the SMBus bus IP core, and the slave device can read the target data from the SMBus bus IP core, reducing the burden on the master device in data transmission.

[0027] Specifically, the SMBus IP core is implemented in hardware within the slave device. The SMBus IP core can report an interrupt signal to the firmware (FW) within the slave device. After the FW enters the interrupt service function, it can confirm whether the master device has initiated an IIC read operation by reading the target data from the relevant registers of the SMBus IP core. Here, the FW is the device program within the slave device.

[0028] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating another method for implementing IIC reading according to an embodiment of this application, which is applied to a slave device. Figure 2 As shown, the method includes the following steps: Step 210: Obtain the target data transmitted by the master device via the SMBus bus.

[0029] Step 220: In response to the target data containing an IIC read command and the CPU operating frequency on the slave device being at its highest operating frequency, obtain the data to be returned corresponding to the IIC read command.

[0030] In this embodiment, the CPU may be an embedded CPU within the slave device. Taking an SSD as an example, the slave device may include the SSD's controller chip, and the CPU may be an embedded CPU within the controller chip. The slave device can acquire the data to be returned after confirming that the master device has initiated an IIC read command and that its own operating frequency is at its highest operating frequency. This allows the slave device to execute the subsequent data transmission process of the data to be returned at its highest operating frequency.

[0031] Step 230: Store the data to be returned into the memory, and switch the IO interface on the slave device corresponding to the SMBus bus to GPIO mode.

[0032] Step 240: Send the data to be returned to the master device in the GPIO mode.

[0033] In this embodiment of the application, since the target data is acquired when the CPU of the slave device is operating at its highest operating frequency, the slave device can perform subsequent data transmission processes at its highest operating frequency, thereby improving the data transmission rate of the slave device and the processing rate of the IIC read command.

[0034] In one embodiment of this application, before obtaining the data to be returned corresponding to the IIC read command in step 220, the method for implementing IIC reading includes, in addition to steps 210-240, steps 210-240: detecting whether the slave device is currently in a low-power state, wherein the low-power state is a state where the power consumption value is lower than a preset value; in response to the slave device being in the low-power state, switching the clock source of the CPU on the slave device to a phase-locked loop (PLL) clock source and adjusting the CPU's operating frequency to the highest operating frequency; in response to the slave device not being in the low-power state, recording the current operating frequency of the CPU; and if the current operating frequency is not the highest operating frequency, adjusting the current operating frequency of the CPU to the highest operating frequency. In this way, by switching the CPU's clock source on the slave device and adjusting the CPU's operating frequency, the computing power and response speed of the slave device can be improved, ensuring that the processing rate of the slave device keeps up with the communication rate of the SMBus bus as much as possible, and avoiding failure of subsequent data transmission due to excessive data latency.

[0035] In this embodiment, the low-power state can be used to indicate that the current operating frequency of the CPU on the slave device is the minimum operating frequency. The preset value can be the minimum operating frequency or slightly higher than the minimum operating frequency. Before detecting whether the slave device is currently in a low-power state, the internal firmware of the slave device can trigger clock stretching by not writing data to be transmitted to the SMBus IP core and not pulling the ready register. Clock stretching is a hardware flow control mechanism in the IIC bus communication protocol. It refers to the process during IIC communication where the slave device lengthens the clock cycle by keeping the SCL signal line low, forcing the master device to pause data transmission, thus ensuring that the slave device has enough time to process received data or prepare data to be transmitted. Simply put, clock stretching refers to the slave device controlling the bus clock signal when necessary to adapt to its data processing rate.

[0036] During the clock extension window, the internal firmware (FW) of the slave device can determine whether the slave device is currently in a low-power state. If the FW determines that the slave device is in a low-power state, it can switch the slave device's clock source from a resistor-capacitor (RC) clock source to a PLL clock source. An RC clock source is a clock source that uses the charging and discharging characteristics of a resistor (R) and capacitor (C) to generate an oscillation frequency, and is usually integrated internally. A PLL clock source is a clock source that generates a clock signal by multiplying the frequency of an external crystal oscillator. The external crystal oscillator provides a high-precision and stable low-frequency or high-frequency reference clock, thus obtaining a stable high-frequency clock. Compared to an RC clock source, a PLL clock source has higher precision and higher stability. This allows the CPU's clock source on the slave device to be switched from a low-power internal RC oscillator to a high-precision, high-speed external crystal oscillator. In addition to switching the clock source, the CPU's operating frequency on the slave device can also be adjusted to its maximum operating frequency.

[0037] If the internal firmware (FW) determines that the slave device is not currently in a low-power state, it can then determine whether the slave device's CPU operating frequency is at its highest level. If the slave device's operating frequency is at its highest, no adjustment is needed. If the slave device's operating frequency is not at its highest, its current operating frequency (cur_cpu_clk, hereinafter referred to as cur_cpu_clk) can be recorded, and the slave device's CPU operating frequency can be adjusted to its highest. This ensures that regardless of the slave device's CPU state, its operating frequency remains at its highest before retrieving the data to be returned by the IIC read command.

[0038] Please refer to Figure 3 , Figure 3 This is a flowchart illustrating another method for implementing IIC reading according to an embodiment of this application, which is applied to a slave device. Figure 3 As shown, the method includes the following steps: Step 310: Obtain the target data transmitted by the master device via the SMBus bus.

[0039] Step 320: In response to the target data containing an IIC read command, obtain the data to be returned corresponding to the IIC read command.

[0040] Step 330: Store the data to be returned into the memory, and switch the IO interface on the slave device corresponding to the SMBus bus to GPIO mode.

[0041] Step 340: Obtain first data from the memory, wherein the first data is one transmission unit of data in the data to be returned.

[0042] In this embodiment of the application, before retrieving the first data from the memory in step 340, the slave device may, in response to the master device's IIC read command, first reply to the master device with an acknowledgment message for the IIC read command, and detect whether the master device has received the acknowledgment message for the IIC read command. Retrieving the first data from the memory in step 340 includes: retrieving the first data from the memory in response to the slave device detecting that the master device has received the acknowledgment message for the IIC read command. Specifically, in GPIO mode, the I / O interfaces of the SCL and SDA channels on the SMBus bus are switched to GPIO mode, denoted as GPIO_27 and GPIO_28 respectively. The slave device can reply to the master device with a command acknowledgment (ACK) message via GPIO_28 to inform the master device that the slave device has received the master device's IIC read command. To distinguish between different acknowledgment messages, this acknowledgment message for the IIC read command is denoted as ACK0. After the slave device replies to the master device with ACK0 via GPIO_28, the slave device can query the status of GPIO_27 to determine whether the master device has received ACK0.

[0043] After the slave device confirms that the master device has received ACK0, the data transmission process of the data to be returned can begin. Additionally, after starting the data transmission process, the slave device can first determine whether the current data transmission has ended, i.e., whether to continue transmitting the data to be returned. Retrieving the first data from the memory includes: in response to the data to be returned not having finished transmitting, retrieving the first data from the memory.

[0044] Step 350: In the GPIO mode, send the first data to the master device through the IO interface and the SMBus bus.

[0045] In other words, if it is determined that the data to be returned has not been completely transmitted, the slave device can retrieve one unit of data from the buffer and send this unit of data to the SMBus bus via GPIO_27 and GPIO_28, thereby transmitting this unit of data to the master device via the SMBus bus. Here, one unit of data is, for example, one byte. However, it should be noted that it is not limited to one byte; other units, such as one bit, can also be used.

[0046] Step 360: In response to receiving the acknowledgment information sent by the master device, in the GPIO mode, send the second data to the master device through the IO interface and the SMBus bus, wherein the second data is the data of the next transmission unit of the first data.

[0047] In this embodiment, the confirmation information refers to confirmation information for the first data, used to indicate that the master device has received the first data. That is, when the slave device receives the confirmation information for the first data, the slave device knows that the master device has received the first data and can begin transmitting the next unit of data. The slave device can retrieve the next unit of data (i.e., the second data) from the memory and send the second data to the master device through the IO interface and the SMBus bus in GPIO mode. By repeating this process, the slave device can transmit all the data in the pending return data to the master device one unit at a time.

[0048] For example, the data to be returned contains three bytes, denoted as byte 1, byte 2, and byte 3. The slave device can first retrieve byte 1 from memory and send it to the master device in GPIO mode via the I / O interface and the SMBus bus. After receiving an acknowledgment (ACK1) from the master device for byte 1, the slave device can then retrieve byte 2 from memory and send it to the master device in GPIO mode via the I / O interface and the SMBus bus. After receiving an acknowledgment (ACK2) from the master device for byte 2, the slave device can then retrieve byte 3 from memory and send it to the master device in GPIO mode via the I / O interface and the SMBus bus. After receiving an acknowledgment (ACK3) from the master device for byte 3, the slave device can confirm that the master device has received the complete data of the data to be returned, determining that the data transmission of the data to be returned is complete, and there is no need to continue retrieving data from memory.

[0049] In practice, in addition to replying with the aforementioned confirmation information, the master device may also reply with a Not Acknowledge (NACK) message in response to the data sent by the slave device. In this embodiment, the NACK message can be used to indicate that the master device has received enough data and will no longer receive data. That is, if the slave device receives a NACK message from the master device for a specific transmission unit of data, it indicates that the master device has received enough data after receiving that transmission unit and will no longer receive data. At this time, the slave device can begin detecting the master device's end-of-transmission signal. After the slave device detects the master device's end-of-transmission signal, it terminates the data transmission process.

[0050] In this embodiment of the application, during the entire process of the slave device sending the data to be returned to the master device, one transmission unit of data is transmitted at a time, and the next transmission unit of data is only sent after it is clearly confirmed that the master device has received one transmission unit of data, thereby ensuring that the master device can accurately receive the complete data to be returned.

[0051] Please refer to Figure 4 , Figure 4 This is a flowchart illustrating another method for implementing IIC reading according to an embodiment of this application, which is applied to a slave device. Figure 4 As shown, the method includes the following steps: Step 410: Obtain the target data transmitted by the master device via the SMBus bus.

[0052] Step 420: In response to the target data containing an IIC read command, obtain the data to be returned corresponding to the IIC read command.

[0053] Step 430: Store the data to be returned into the memory, and switch the IO interface on the slave device corresponding to the SMBus bus to GPIO mode.

[0054] Step 440: Send the data to be returned to the master device in the GPIO mode.

[0055] Step 450: Detect the end transmission signal of the master device.

[0056] In this embodiment of the application, the end transmission signal is used to indicate the end of the data transmission process in which the slave device sends the data to be returned to the master device. For example, detecting the end transmission signal of the master device in step 450 includes: detecting the end transmission signal of the master device in response to the slave device receiving NACK information sent by the master device.

[0057] Step 460: In response to the end transmission signal, switch the IO interface from the GPIO mode to the SMBus mode.

[0058] In this embodiment, upon detecting the termination signal from the master device, the communication process between the master device and the slave device is confirmed to have ended. The IO interface corresponding to the SMBus bus on the slave device can then be switched back to its original SMBus mode, resuming the communication process between the slave device and the master device in SMBus mode. This allows the slave device to reuse and configure its IO interface corresponding to the SMBus bus as GPIO mode to implement IIC read functionality, while simultaneously reverting to SMBus mode to retain the original functionality of the IO interface. In other words, the slave device and the master device can still communicate via SMBus mode.

[0059] The entire process of achieving IIC reading through mode switching can be referred to Figure 5 , Figure 5 This is a schematic diagram illustrating a mode switching method provided in an embodiment of this application. For example... Figure 5As shown, the SMBus slave device can parse the data on the SMBus bus to confirm whether it contains an IIC read command, update the data to be returned in real time, and store the data to be returned in a memory (buffer). Then, the SMBus slave device can smoothly switch the I / O port associated with the SMBus bus to GPIO mode, and send the data in the memory to the SMBus bus through the GPIO port, while simultaneously monitoring the end-of-transmission signal of the SMBus master device. After detecting the end-of-transmission signal of the SMBus master device, the SMBus slave device can switch the GPIO port back to SMBus mode.

[0060] In one embodiment of this application, before switching the IO interface from GPIO mode to SMBus mode in step 460, the method for implementing IIC reading includes, in addition to steps 410-460 above, steps 410-460, the following: determining whether the slave device was previously in a low-power state, wherein the low-power state is a state where the power consumption is lower than a preset value; in response to the slave device being previously in the low-power state, switching the clock source of the CPU on the slave device to an RC clock source and adjusting the CPU's operating frequency to the lowest operating frequency; in response to the slave device not being previously in the low-power state, obtaining the CPU's operating frequency before the mode switch; and if the CPU's operating frequency before the mode switch is not the highest operating frequency, adjusting the CPU's current operating frequency to the CPU's operating frequency before the mode switch. In this way, by switching the CPU's clock source and operating frequency on the slave device to the state before the mode switch, it can be ensured that the state of the slave device before implementing IIC reading is consistent with the state after implementing IIC reading, avoiding situations where the slave device malfunctions due to inconsistent states.

[0061] In this embodiment, during the process of switching the I / O interface to the GPIO mode, the slave device may switch its clock source and adjust the operating frequency of its CPU. Before switching the I / O interface from the GPIO mode to the SMBus mode, the CPU on the slave device can first restore its original clock source, and the operating frequency of the CPU on the slave device can be adjusted to its original operating frequency, so that the slave device returns to its original operating state.

[0062] Specifically, before switching the I / O interface from GPIO mode to SMBus mode, it can be determined whether the slave device was previously in a low-power state. That is, it can be determined whether the slave device was in a low-power state before executing the entire IIC read process, to determine whether the slave device needs to switch to a low-power state next. Whether the slave device was previously in a low-power state can be determined based on the identification information configured in the slave device's firmware. For example, if the identification information is a first value, it is determined that the slave device was previously in a low-power state; if the identification information is a second value, it is determined that the slave device was not previously in a low-power state.

[0063] Alternatively, whether the slave device was in a low-power state can be determined based on its power consumption state when reading the target data. That is, if the slave device was in a low-power state when reading the target data, it can be determined that the slave device can switch to a low-power state, thus restoring it to the low-power state it was in when reading the target data. If the slave device was not in a low-power state when reading the target data, it indicates that the slave device did not switch its power consumption state previously, and therefore it can be determined that the slave device does not need to switch to a low-power state.

[0064] Since the slave device previously switched its clock source from the RC clock source to the PLL clock source and adjusted the CPU operating frequency of the slave device to the highest operating frequency when it was in a low-power state, after determining that the slave device was in a low-power state, the clock source of the CPU on the slave device can be switched from the PLL clock source back to the original RC clock source, and the CPU operating frequency can be adjusted to the lowest operating frequency, so that the clock source and operating frequency of the CPU on the slave device are restored to the state when reading the target data.

[0065] If the slave device was not previously in the low-power state, it indicates that the slave device did not switch its clock source when switching from SMBus mode to GPIO mode. Therefore, there is no need to switch the CPU's clock source on the slave device; only the CPU's operating frequency needs to be switched. Specifically, if the CPU's current operating frequency is its maximum operating frequency, and if the CPU's operating frequency before the mode switch was not its maximum, the CPU's current operating frequency can be adjusted from its maximum operating frequency to its operating frequency before the mode switch. If the CPU's operating frequency before the mode switch was its maximum operating frequency, since the CPU's operating frequency did not change during the mode switch, the CPU's current operating frequency does not need to be adjusted. Here, mode switching refers to the I / O interface switching from SMBus mode to GPIO mode, i.e., the first mode switch.

[0066] In this embodiment of the application, after restoring the state of the CPU on the slave device to the state when reading the target data, the IO interface can be switched from GPIO mode to SMBus mode for a second mode switch.

[0067] In one embodiment of this application, the slave device in any of the above embodiments may be a device whose hardware does not support IIC reading functionality. That is, the embodiments of this application can be applied to situations where a master device obtains relevant information from a slave device via IIC reading, but the slave device does not support IIC reading functionality in its hardware. The embodiments of this application can implement the IIC reading process in software, reducing the hardware requirements for the slave device. Furthermore, it should be noted that the embodiments of this application do not limit the slave device to a device whose hardware does not support IIC reading functionality. That is, even when the slave device's hardware supports IIC reading functionality, IIC reading can still be implemented using the methods provided in the embodiments of this application.

[0068] Please see Figure 6 , Figure 6 This is a flowchart illustrating a method for implementing IIC reading according to an embodiment of this application. The method is applied to a slave device, which is a device whose hardware does not support IIC reading functionality. The slave device includes a master control chip, and the master control chip includes an SMBus IP core. Figure 6 As shown, the method includes the following steps: Step 610: Read the target data transmitted by the master device through the SMBus bus from the SMBus IP core.

[0069] Step 615: In response to the target data containing an IIC read command, detect whether the slave device is currently in a low-power state.

[0070] The low-power state is defined as a state where the power consumption is lower than a preset value. In step 615, if the slave device is detected to be in the low-power state, step 620 can be executed; if the slave device is detected not to be in the low-power state, step 625 can be executed.

[0071] Step 620: Switch the clock source of the CPU on the slave device to the PLL clock source, and adjust the CPU's operating frequency to the highest operating frequency.

[0072] Step 625: Record the current operating frequency of the CPU; if the current operating frequency is not the highest operating frequency, adjust the current operating frequency of the CPU to the highest operating frequency.

[0073] Step 630: In response to the CPU operating frequency of the slave device being at its highest operating frequency, obtain the data to be returned corresponding to the IIC read command.

[0074] Step 635: Store the data to be returned into the memory, and switch the IO interface on the slave device corresponding to the SMBus bus to GPIO mode.

[0075] Step 640: Send the data to be returned to the master device in the GPIO mode.

[0076] In this embodiment of the application, step 640, sending the data to be returned to the master device in the GPIO mode, includes: retrieving first data from the memory, the first data being one transmission unit of data in the data to be returned; sending the first data to the master device in the GPIO mode via the IO interface and the SMBus bus; and in response to receiving an acknowledgment message from the master device, sending second data to the master device in the GPIO mode via the IO interface and the SMBus bus, the second data being the next transmission unit of data in the first data.

[0077] Step 645: Detect the end transmission signal of the master device.

[0078] Step 650: In response to the termination transmission signal, determine whether the slave device was in a low-power state.

[0079] In step 650, if it is determined that the slave device was previously in the low-power state, step 655 may be performed; if it is determined that the slave device was not previously in the low-power state, step 660 may be performed.

[0080] Step 655: Switch the clock source of the CPU on the slave device to an RC clock source, and adjust the operating frequency of the CPU to the lowest operating frequency.

[0081] Step 660: Obtain the CPU's operating frequency before the mode switch; if the CPU's operating frequency before the mode switch is not the highest operating frequency, adjust the CPU's current operating frequency to the CPU's operating frequency before the mode switch.

[0082] Step 665: Switch the IO interface from GPIO mode to SMBus mode.

[0083] In this embodiment, it is not necessary for the device to support IIC reading in hardware. This embodiment can realize the entire process of the master device obtaining relevant information from the slave device through IIC reading in software, which solves the problem that related technologies cannot realize IIC reading function without hardware support.

[0084] For ease of understanding, the following is combined with Figure 7 The entire process of implementing IIC reading is described in detail. Figure 7 This is a schematic diagram of a process for implementing IIC reading provided in an embodiment of this application.

[0085] like Figure 7 As shown, firstly, the slave device (e.g., SSD) receives the IIC read command via the SMBus bus. Specifically, after the slave device powers on, the FW initializes two IO interfaces (denoted as GPIO_27 and GPIO_28 respectively) to SMBus mode. After the FW receives the interrupt signal from the SMBus IP core, it reads the relevant registers to confirm whether the master device has initiated the IIC read command.

[0086] Secondly, the FW triggers clock extension on the SMBus slave device. Within the clock extension window, the FW first determines whether the slave device is currently in a low-power state. If the slave device is currently in a low-power state, it first switches the CPU's current clock source from the RC clock source to the PLL clock source and increases the CPU's current operating frequency to the highest level. If the slave device is not currently in a low-power state, it records the CPU's current operating frequency (denoted as cur_cpu_clk) and determines whether the CPU's current operating frequency is the highest level. If the CPU's current operating frequency is not the highest level, it increases the CPU's current operating frequency to the highest level. In response to the IIC read command and the fact that the CPU's current operating frequency is the highest level, the data to be returned can be updated and stored in the memory (buffer). The SCL and SDA channels of the SMBus bus are smoothly switched to GPIO mode, namely GPIO_27 and GPIO_28. The slave device replies to the master device with an ACK for the master device's IIC read command via GPIO_28, and confirms whether the master device has received the ACK by querying the status of GPIO_27.

[0087] Next, based on the SMBus timing, the slave device sends the data to be returned stored in memory to the master device using GPIO mode. The slave device first determines whether the data in memory has been completely transmitted. If the data transmission in memory is complete, it can query the master device's end-transmission signal to determine whether the data to be returned has finished transmitting. If the data in memory has not been completely transmitted, it can retrieve one byte of data from the memory and send this byte of data to the SMBus bus via GPIO_27 and GPIO_28, waiting for the master device to reply with an ACK or NACK for this byte of data. If the slave device receives an ACK from the master device for this byte of data, it again determines whether the data transmission in memory is complete. If the data in memory has not been completely transmitted, it can retrieve the next byte of data from the memory and send the next byte. If the slave device receives a NACK from the master device for this byte of data, it can further query the master device's end-transmission signal to determine whether the data to be returned has finished transmitting.

[0088] After the transmission of the data to be returned ends, the master device has received the data to be returned for the IIC read command, thus completing the IIC read command. At this point, the IO interface can be switched back to SMBus mode, and the state of the IO interface and the slave device can be restored to the state before the IIC read command was executed. Specifically, the firmware can first determine whether the slave device has entered a low-power state. If the slave device has entered a low-power state, the current clock source of the CPU on the slave device can be switched from the PLL clock source to the RC clock source, and the current operating frequency of the CPU can be reduced to the lowest level, i.e., the lowest operating frequency, to match the low-power state. If the slave device has not entered a low-power state, it can be determined whether the CPU's operating frequency before the mode switch was the highest operating frequency. If the CPU's operating frequency before the mode switch was the highest operating frequency, there is no need to adjust the current operating frequency of the CPU. If the CPU's operating frequency before the mode switch was not the highest operating frequency, the current operating frequency of the CPU can be adjusted to the operating frequency of the CPU before the mode switch. After completing the clock source switching and operating frequency adjustment, the GPIO_27 and GPIO_28 I / O interfaces can be switched back to SMBus mode to complete the entire IIC reading process.

[0089] It should be noted that the descriptions of the same or corresponding steps in the above embodiments can be referred to each other, for example... Figure 1 The description of step 110 in the text is applicable to Figure 2 Step 210 in the process will not be repeated here.

[0090] Meanwhile, it should be understood that the method for implementing IIC reading provided in this application embodiment multiplexes and configures the IO interfaces associated with the SMBus bus into GPIO mode, thereby enabling IIC reading functionality in GPIO mode. Furthermore, the method for implementing IIC reading provided in this application embodiment has the following beneficial effects: First, this application embodiment can implement IIC reading functionality through software when the SMBus slave device does not support IIC reading functionality in hardware. Second, this application embodiment can reuse the IO interfaces associated with the SMBus bus, eliminating the need for adding new IO interfaces and simplifying hardware circuit design.

[0091] Please see Figure 8 , Figure 8 This is a structural block diagram of a slave device provided in an embodiment of this application. For example... Figure 8 As shown, this application embodiment provides a slave device 800, which includes: a first acquisition module 810, a second acquisition module 820, a switching module 830, and a sending module 840.

[0092] The first acquisition module 810 is used to acquire target data transmitted by the master device through the system management bus; The second acquisition module 820 is used to acquire the data to be returned corresponding to the IIC read command in response to the target data containing the IIC read command; The switching module 830 is used to store the data to be returned into a memory and switch the input / output interface of the slave device corresponding to the system management bus to a general input / output mode. The sending module 840 is used to send the data to be returned to the master device in the general input / output mode.

[0093] In this embodiment, it is not necessary for the device to support IIC reading in hardware. This embodiment can realize the entire process of the master device obtaining relevant information from the slave device through IIC reading in software, which solves the problem that related technologies cannot realize IIC reading function without hardware support.

[0094] The slave device provided in this application embodiment can implement the various processes implemented in the above method embodiments, and will not be repeated here to avoid repetition.

[0095] like Figure 9As shown in the illustration, this application also provides an electronic device 900. The electronic device 900 includes a processor 910 and a memory 920. The memory 920 stores programs or instructions, which, when executed by the processor 910, implement the steps of any of the methods described above. For example, when the program is executed by the processor 910, it performs the following process: acquiring target data transmitted by the master device through the system management bus; in response to the target data containing an inter-integrated circuit (IIC) read command, acquiring the data to be returned corresponding to the IIC read command; storing the data to be returned in the memory; switching the input / output interface of the slave device corresponding to the system management bus to a general input / output mode; and sending the data to be returned to the master device in the general input / output mode. Thus, without requiring the slave device to support the IIC read function in hardware, this application embodiment can implement the entire process of the master device obtaining relevant information from the slave device through IIC read via software, solving the problem that related technologies cannot implement the IIC read function without hardware support.

[0096] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the steps of various embodiments of the method for implementing IIC reading and achieve the same technical effect. To avoid repetition, these steps will not be repeated here.

[0097] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0098] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0099] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, further details are omitted here.

[0100] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0101] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0102] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method of implementing IIC read, the method comprising: The application is applied to a slave device, comprising: acquiring target data transmitted by a master device through a system management bus; in response to the target data containing an inter-integrated circuit (IIC) read command, acquiring data to be returned corresponding to the IIC read command; storing the data to be returned in a memory and switching an input / output interface corresponding to the system management bus on the slave device to a general input / output mode; sending the data to be returned to the master device in the general input / output mode.

2. The method of claim 1, wherein, After sending the data to be returned to the master device in the general input / output mode, the method further comprises: detecting an end transmission signal of the master device; in response to the end transmission signal, switching the input / output interface from the general input / output mode to a system management bus mode.

3. The method of claim 1, wherein, The response to the target data containing an IIC read command and acquiring the data to be returned corresponding to the IIC read command comprises: in response to the target data containing an IIC read command and the working frequency of a CPU on the slave device being a highest working frequency, acquiring the data to be returned corresponding to the IIC read command.

4. The method of claim 3, wherein, Before acquiring the data to be returned corresponding to the IIC read command, the method further comprises: detecting whether the slave device is currently in a low-power consumption state, the low-power consumption state being a state in which the power consumption value is lower than a preset value; in response to the slave device being currently in the low-power consumption state, switching a clock source of a CPU on the slave device to a phase-locked loop clock source and adjusting the working frequency of the CPU to a highest working frequency; in response to the slave device not being currently in the low-power consumption state, recording the current working frequency of the CPU; and in the case that the current working frequency is not the highest working frequency, adjusting the current working frequency of the CPU to the highest working frequency.

5. The method of claim 1, wherein, The sending of the data to be returned to the master device in the general input / output mode comprises: acquiring first data from the memory, the first data being data of a transmission unit in the data to be returned; sending the first data to the master device through the input / output interface and the system management bus in the general input / output mode; in response to receiving acknowledgement information sent by the master device, sending second data to the master device through the input / output interface and the system management bus in the general input / output mode, the second data being data of a next transmission unit of the first data.

6. The method of claim 2, wherein, Before switching the input / output interface from the general input / output mode to the system management bus mode, the method further comprises: determining whether the slave device has ever been in a low-power consumption state, the low-power consumption state being a state in which the power consumption value is lower than a preset value; in response to the slave device having ever been in the low-power consumption state, switching a clock source of a CPU on the slave device to a resistor-capacitor clock source and adjusting the working frequency of the CPU to a lowest working frequency; In response to the slave device not being in the low-power state, obtaining a working frequency of the CPU before mode switching; and in a case where the working frequency of the CPU before mode switching is not a highest working frequency, adjusting a current working frequency of the CPU to the working frequency of the CPU before mode switching.

7. The method of claim 1, wherein, The slave device comprises a master control chip, and the master control chip comprises a system management bus intellectual property core; The target data transmitted by the master device through the system management bus comprises: The target data transmitted by the master device through the system management bus is read from the system management bus intellectual property core.

8. The method according to any one of claims 1 to 7, characterized in that, The slave device is a device that does not support IIC reading function on hardware.

9. An electronic device, comprising: The device comprises a processor and a memory, and the memory stores a program or instruction, and the program or instruction is executed by the processor to implement the method in any one of claims 1 to 8.

10. A readable storage medium, characterized by, The program or instruction is stored on the readable storage medium, and the program or instruction is executed by the processor to implement the method in any one of claims 1 to 8.

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