Image-based circuit board electronic component positioning method and system

Abstract

The invention belongs to the technical field of electronic component positioning, and particularly relates to a circuit board electronic component positioning method and system based on images, and the method comprises the steps: obtaining circuit board image data, circuit board topological structure data, electronic component three-dimensional model data, historical positioning error data and component library labeling data; the method comprises the following steps: constructing an image adaptation model and a dynamic anchor point matching model, extracting geometric and electrical connection and multi-modal texture features of an element in combination with a texture segmentation algorithm, matching a topological adjacency relation and analyzing position coordinates, performing coarse positioning in combination with real-time image data, generating a precise positioning coordinate set and a dynamic calibration instruction by utilizing a real-time error correction algorithm, and performing dynamic calibration on the precise positioning coordinate set and the dynamic calibration instruction. And extracting positioning deviation data, combining a positioning error mean value, feature matching accuracy, a topological relation analysis success rate and calibration instruction execution validity, generating a positioning precision evaluation table, synchronously positioning an abnormal area, and forming an electronic component positioning evaluation report. Therefore, the problems of poor positioning capability, poor analysis capability and the like in the prior art are solved.

Description

Technical Field

[0001] This invention belongs to the field of electronic component positioning technology, specifically relating to an image-based method and system for positioning electronic components on circuit boards. Background Technology

[0002] With the upgrading of electronic manufacturing towards intelligence and precision, and the increasing demand for smart factory testing, the market urgently needs high precision, high real-time performance, and strong anti-interference capabilities for the positioning of electronic components on circuit boards. This requires deep fusion of multi-source data, dynamic deviation compensation, and quantitative evaluation of positioning results. However, existing technologies lack cross-domain linkage between image data and topology, 3D models, and historical positioning error data. They also lack a multimodal feature collaborative reasoning framework and a dynamic positioning error quantification mechanism, making it difficult to support accurate positioning in scenarios with high-density components, complex topological layouts, and environmental interference. This presents a significant gap between these technologies and the technical requirements for constructing multi-dimensional component perception maps and optimizing positioning parameters in real time.

[0003] However, traditional electronic component positioning technologies suffer from key drawbacks: they often employ single image template matching or simple geometric feature recognition modes, resulting in insufficient response accuracy to component miniaturization, surface texture differences, and lighting fluctuations; they are also susceptible to interference from circuit board topology complexity and component assembly deviations. Furthermore, the models lack dynamic adjustment mechanisms driven by multi-source data, leading to significant discrepancies in feature matching weights and positioning parameters across different component models and high-density layouts. The data dimension is limited to single two-dimensional image acquisition or coarse coordinate recording, lacking cross-dimensional attention mechanisms for the collaborative processing of component geometric features, electrical connections, and historical positioning error data, resulting in a disconnect between component dynamic features and positioning control parameters. With the mass application of high-density circuit boards and miniaturized electronic components, and the increasing demands for inspection efficiency in smart factories, the market's need for highly accurate, stable, and efficient electronic component positioning technologies is becoming increasingly urgent. However, existing technologies, due to poor positioning capabilities, weak analytical capabilities, and incomplete evaluation, struggle to support efficient and accurate positioning applications in complex production and inspection scenarios. Summary of the Invention

[0004] This application provides an image-based method and system for locating electronic components on circuit boards, in order to solve the problems of poor positioning capability and poor resolution capability in the prior art.

[0005] The first aspect of this application provides an image-based method for locating electronic components on a circuit board, comprising the following steps: acquiring circuit board image data, circuit board topology data, electronic component 3D model data, historical positioning error data, and component library annotation data; constructing a topology-aware image adaptation model based on the circuit board topology data and the historical positioning error data; constructing a dynamic anchor point matching model based on the electronic component 3D model data, the circuit board image data, and the component library annotation data; combining the topology-aware image adaptation model and using a texture segmentation algorithm to extract the geometric features, electrical connection features, and multimodal texture features of the components, matching topological adjacency relationships, and resolving the 3D spatial coordinates of the components; performing coarse positioning of the components using real-time updated circuit board image data to obtain coarse positioning results; optimizing the coarse positioning results using a real-time error correction algorithm to generate a precise positioning coordinate set and dynamic calibration instructions for the components; extracting deviation data between the positioning points and theoretical coordinates based on the precise positioning coordinate set and dynamic calibration instructions; generating a positioning accuracy evaluation table by combining the mean positioning error, feature matching accuracy, topology relationship resolution success rate, and calibration instruction execution effectiveness indicators; synchronously marking component areas with positioning anomalies; and forming an electronic component positioning evaluation report.

[0006] Preferably, a topology-aware image adaptation model is constructed based on the circuit board topology data and the historical positioning error data, including: acquiring circuit board topology data and historical positioning error data; constructing a topology feature extraction network based on the circuit board topology data and historical positioning error data, and separating topology node correlation and wiring density gradient features through a multilayer perceptron, wherein the topology node correlation characterizes the tightness of electrical connections between components, and the wiring density gradient reflects the trend of changes in the density of wiring in the region; based on the topology feature extraction network, selecting image samples of frequently used circuit board types, labeling the samples according to positioning deviation type and image distortion level, and constructing a topology-aware image adaptation model by combining the separated topology features and optimizing the model through backpropagation.

[0007] Preferably, a dynamic anchor point matching model is constructed based on the 3D model data of the electronic components, the circuit board image data, and the component library annotation data, including: acquiring the 3D model data of the electronic components, the circuit board image data, and the component library annotation data; extracting core features of component geometry, pin layout, and package type based on the 3D model data of the electronic components and the component library annotation data, constructing an electronic component knowledge graph, and annotating feature attributes and topological association rules; processing the circuit board image data, combining it with the 3D contour features in the 3D model data of the electronic components, associating it with the electronic component knowledge graph, and fusing the enhanced topological features of the topology-aware image adaptation model to construct a dynamic anchor point matching model.

[0008] Preferably, the formula for the topology-aware image adaptation model is: ; ; ; ; ; ; ; ; ; ; in, Input features into the fused model; For feature splicing operations; Pixel features of circuit board image data; For linear embedding layers; A set of circuit board topology data; For line H The real space of the column; The height dimension of the image features; Image feature dimension; The embedding dimension of the topology parameters; The set of topological features after separation; For topological feature extraction networks; Extract network model parameters based on topological features; The correlation characteristics of the separated topological nodes; The separated wiring density gradient features; The topological clustering features of the separated pads; These are the features after the convolution operation; This is a two-dimensional convolution operation; These are the model parameters for a two-dimensional convolutional layer; For line H The real space of column k channels; This represents the number of convolutional kernels; For attention pooling operations; The attention mask corresponding to the topological node associativity; This is the attention mask corresponding to the wiring density gradient; For line H The real space of the column; The dimension of a single-class topological feature; For the attention mask corresponding to the topological clustering of pads; The feature vector for the circuit board scene label; This is a one-hot encoding operation; Labels for positioning deviation types; This is a normalization operation; Image sharpness label; Image distortion level labels; 1 row The real space of the column; The total dimension of the label features; Features are the result of multi-feature fusion; This is a vector repetition operation; For line H The real space of the column; Enhanced image features; For the adapted topology encoder; These are the encoder's model parameters; This is the total loss function of the model; , , For loss weights; This is the mean square error loss; Features of a standard clear image; Cross-entropy loss; The probability distribution of image distortion levels predicted by the model; Labels for the distortion level of real images; This is the average absolute error loss; The image sharpness score predicted by the model.

[0009] Preferably, the extraction of component geometric features, electrical connection features, and multimodal texture features, matching topological adjacency relationships, and parsing the 3D spatial coordinates of the components includes: constructing a multimodal feature fusion model; based on the feature extraction layer of the multimodal feature fusion model, parsing the circuit board image data, extracting component geometric features, electrical connection features, and multimodal texture features, verifying the features using a dynamic anchor point matching model, excluding invalid features that are not electrically connected to topological nodes, and obtaining valid features after verification; inputting the valid features after verification into the topology matching layer, matching them with the topological adjacency relationships output by the topology-aware image adaptation model, and parsing the 3D spatial coordinates and rotation angles of the components using triangulation and texture segmentation algorithms to generate positioning information containing coordinate accuracy level and topology matching degree.

[0010] Preferably, generating a positioning accuracy evaluation table includes: constructing a positioning accuracy evaluation model; based on the positioning accuracy evaluation model, inputting the deviation data between the positioning point and the theoretical coordinates, the feature matching accuracy rate, the success rate of topological relationship resolution, and the effectiveness index of calibration command execution, and calculating a comprehensive positioning reliability score; generating positioning accuracy levels and summarizing them into a positioning accuracy evaluation table according to the comprehensive positioning reliability score and the threshold values ​​of each index, and simultaneously marking the component areas with confidence scores below the threshold values ​​as positioning anomalies.

[0011] A second aspect of this application provides an image-based circuit board electronic component positioning system, comprising: an acquisition module for acquiring circuit board image data, circuit board topology data, electronic component 3D model data, historical positioning error data, and component library annotation data; a construction module for constructing a topology-aware image adaptation model based on the circuit board topology data and the historical positioning error data; and a parsing module for constructing a dynamic anchor point matching model based on the electronic component 3D model data, the circuit board image data, and the component library annotation data, and combining the topology-aware image adaptation model with a texture segmentation algorithm to extract the geometric features and electrical connection characteristics of the components. The system incorporates multimodal texture features, matches topological adjacency relationships, and resolves the 3D spatial coordinates of components. It then performs coarse positioning of components using real-time updated circuit board image data, obtaining a coarse positioning result. A real-time error correction algorithm iteratively optimizes this result, generating a precise positioning coordinate set and dynamic calibration instructions. A generation module extracts the deviation data between the positioning point and the theoretical coordinates based on the precise positioning coordinate set and dynamic calibration instructions. Combining the mean positioning error, feature matching accuracy, topological relationship resolution success rate, and calibration instruction execution effectiveness indicators, it generates a positioning accuracy evaluation table, simultaneously marking abnormally positioned component areas, and forming an electronic component positioning evaluation report.

[0012] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor executes the program to implement an image-based circuit board electronic component positioning method as described in the above embodiments.

[0013] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which is executed by a processor to implement an image-based circuit board electronic component positioning method as described in the above embodiments.

[0014] A fifth aspect of this application provides a computer program product, including a computer program or instructions, for implementing an image-based circuit board electronic component positioning method as described in the above embodiments.

[0015] Therefore, this application has the following beneficial effects: The embodiments of this application integrate multi-source data including circuit board images, topology, 3D models of electronic components, historical positioning errors, and component library annotations. Utilizing a topology-aware image adaptation model and a dynamic anchor point matching model, combined with a texture segmentation algorithm, multi-dimensional features are accurately extracted and topological relationships are matched. Through coarse positioning and real-time error correction, precise coordinates and calibration instructions are generated. This solves the problems of poor response to complex topologies and environmental interference, and large positioning parameter deviations in traditional single-feature or template matching, breaking down the disconnect between component dynamic features and positioning data. Simultaneously, by training and optimizing model parameter weights using deviation data and evaluation indicators, an evaluation table is generated and abnormal areas are marked. This significantly improves positioning accuracy and stability while ensuring positioning reliability, effectively filling the gap in deep multi-source data linkage and dynamic error correction in existing technologies, and minimizing positioning deviations. Thus, it solves the problems of poor positioning and resolution capabilities in existing technologies.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 This is a flowchart of an image-based method for locating electronic components on a circuit board according to an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of an electronic component positioning scenario on a high-density integrated circuit board according to an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of a component location scenario for mobile phone motherboard repair according to an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of an image-based method for locating electronic components on a circuit board according to an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of an image-based circuit board electronic component positioning system according to an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Detailed Implementation

[0024] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0025] The following description, with reference to the accompanying drawings, illustrates an image-based method and system for locating electronic components on a circuit board. Addressing the poor positioning capabilities mentioned in the background section, this application provides an image-based method for locating electronic components on a circuit board. This method integrates multi-source data, including circuit board images, topology, 3D models of electronic components, historical positioning errors, and component library annotations. It utilizes a topology-aware image adaptation model and a dynamic anchor point matching model, combined with a texture segmentation algorithm to accurately extract multi-dimensional features and match topological relationships. Through coarse positioning and real-time error correction, precise coordinates and calibration instructions are generated. This solves the problems of poor response to complex topologies and environmental interference, and large positioning parameter deviations in traditional single-feature or template matching methods, breaking down the disconnect between component dynamic features and positioning data. Simultaneously, by training and optimizing model parameter weights using deviation data and evaluation indicators, an evaluation table is generated and abnormal areas are marked. This significantly improves positioning accuracy and stability while ensuring positioning reliability, effectively filling the gap in deep multi-source data linkage and dynamic error correction in existing technologies, and minimizing positioning deviations. Thus, it solves the problems of poor positioning and resolution capabilities in existing technologies.

[0026] Specifically, Figure 1 This is a schematic flowchart illustrating an image-based method for locating electronic components on a circuit board, as provided in an embodiment of this application.

[0027] like Figure 1 As shown, this image-based method for locating electronic components on a circuit board includes the following steps:

[0028] In step S101, circuit board image data, circuit board topology data, electronic component 3D model data, historical positioning error data, and component library annotation data are acquired.

[0029] Among them, circuit board topology data is the core data that describes the layout of electronic components on the circuit board, the routing of lines between components, and the connection relationships between nodes.

[0030] It is understood that the embodiments of this application, by acquiring circuit board topology data and linking it with circuit board images, 3D models of electronic components, historical positioning errors, and component library annotation data, provide a structural reference for the topology-aware image adaptation model to mine the adaptation rules of component features and topological relationships. This avoids the subjectivity of setting model topology analysis parameters, improves the accuracy of component topology adjacency matching and position analysis, and provides a structural basis for the reasonable allocation of feature matching weights in positioning parameter settings, reducing positioning errors caused by topology analysis deviations. At the same time, it can also serve as benchmark data for training and evaluating the positioning model. By comparing the differences between the positioning results and the topology data, the improvement effect of positioning accuracy can be clearly quantified, and the model parameter weights can be dynamically updated. This provides key data support for the fine positioning of electronic components, the improvement of positioning accuracy, and the adaptation to complex circuit board scenarios.

[0031] In step S102, a topology-aware image adaptation model is constructed based on the circuit board topology data and historical positioning error data.

[0032] Among them, the topology-aware image adaptation model refers to a model tool built based on circuit board topology data and historical positioning error data, which can capture circuit board topology features, adapt to image distortion and positioning error patterns, optimize image feature extraction effects, and improve the positioning accuracy of subsequent components.

[0033] It is understood that the embodiments of this application, by combining the electrical connection relationships and wiring distribution patterns between components contained in the circuit board topology data with the positioning deviation features captured by historical positioning error data, provide technical support for feature extraction and adaptation optimization of circuit board images that combines topological correlation and error avoidance. This can effectively compensate for the positioning deviation problem caused by the traditional image matching model ignoring the topology, and avoid feature mis-extraction caused by uneven wiring density and complex component layout. It can also provide high-quality image feature input for dynamic anchor point matching models after topology adaptation and error correction, support accurate verification of multimodal features and efficient analysis of component 3D spatial coordinates, and enable the dual-model fusion process to dynamically adjust the strategy according to the topological characteristics and positioning error patterns of different circuit boards, improve the topology adaptability and error controllability of electronic component positioning, and synergistically improve positioning accuracy and efficiency.

[0034] In this embodiment, a topology-aware image adaptation model is constructed based on circuit board topology data and historical positioning error data. This includes: acquiring circuit board topology data and historical positioning error data; constructing a topology feature extraction network based on the circuit board topology data and historical positioning error data; separating topology node correlation and wiring density gradient features using a multilayer perceptron, where topology node correlation characterizes the tightness of electrical connections between components, and wiring density gradient reflects the trend of varying wiring density in a region; based on the topology feature extraction network, selecting image samples of frequently used circuit board types, labeling samples according to positioning deviation type and image distortion level, and combining the separated topology features with a backpropagation optimization model to construct a topology-aware image adaptation model.

[0035] Among them, the topology feature extraction network refers to an algorithm architecture based on deep learning that automatically separates core topology features such as topology node correlation and wiring density gradient from circuit board topology data and historical positioning error data, providing topology-level feature support for image adaptation and component positioning.

[0036] It is understood that the embodiments of this application deeply integrate the topological association attributes in the circuit board topology data with the error patterns in the historical positioning error data. By utilizing a topological feature extraction network, core topological features are accurately separated and the correlation patterns between positioning errors and topological features are efficiently captured. This breaks through the limitations of insufficient positioning adaptation caused by the lack of targeted topological feature extraction in traditional image processing. At the same time, it outputs standardized topological features and scene-specific image sample label data. This avoids the one-sidedness of feature extraction caused by relying solely on image features or coarse topological data, and improves the accuracy of topological feature extraction and the targeting of positioning scene adaptation. It also provides high-quality feature input for the subsequent construction of topology-aware image adaptation models. The adaptation strategy can be dynamically adjusted based on clear topological features and error patterns. This prevents positioning deviations caused by unclear topology resolution and reduces feature extraction errors caused by image distortion, thus synergistically improving the image adaptation effect and the accuracy of subsequent component positioning.

[0037] It should be noted that the formula for topological feature extraction networks is as follows: ; ; ; ; in, Original topology fusion features; This is for fully connected layer operations; For data embedding functions; This refers to the circuit board topology data. These are the weights for the fully connected layer. Bias for fully connected layers; This is a topology-error attention mechanism; This is historical positioning error data; The correlation characteristics of the separated topological nodes; For activation functions; This is a one-dimensional convolution operation; The convolution weights are the node correlation features; The convolution bias is applied to the node correlation feature; The separated wiring density gradient features; For activation functions; The convolution weights are the wiring density gradient features; The bias is used for the convolution of wiring density gradient features; This is the final output topological feature vector; For feature splicing operations; for OK The real space of the column; The feature height dimension; It represents the dimension of a single-class topological feature.

[0038] For example, such as Figure 2 As shown, taking the electronic component positioning scenario of a high-density integrated circuit board as an example, when positioning a circuit board containing hundreds of micro-components, the topology feature extraction network first receives the topology data of the circuit board (including component pin connection relationships and wiring routing) and historical positioning error data (such as deviation records caused by dense wiring in past positioning). The two types of data are converted into high-dimensional embedding vectors through the Embed function, and then fused with a fully connected layer and attention mechanism to obtain the original topology features. Subsequently, Conv1d is used to extract the correlation degree of topology nodes (such as the tightness of connection between the core chip and surrounding resistors) and wiring density gradient (such as the difference in wiring density between the edge and center areas of the circuit board). After these separated topology features are input into the topology-aware image adaptation model, the model can quickly adapt to high-density wiring scenarios, accurately distinguish the image features of adjacent components, filter out interference caused by overlapping wiring, and output optimized image features. This provides accurate support for the subsequent dynamic anchor point matching model to analyze the 3D spatial coordinates of components, effectively improving the positioning accuracy of high-density circuit boards.

[0039] In this embodiment, the formula for the topology-aware image adaptation model is: [Formula for the topology-aware image adaptation model is missing from the original text.] ; ; ; ; ; ; ; ; ; ; in, Input features into the fused model; For feature splicing operations; Pixel features of circuit board image data; For linear embedding layers; A set of circuit board topology data; For line H The real space of the column; The height dimension of the image features; Image feature dimension; The embedding dimension of the topology parameters; The set of topological features after separation; For topological feature extraction networks; Extract network model parameters based on topological features; The correlation characteristics of the separated topological nodes; The separated wiring density gradient features; The topological clustering features of the separated pads; These are the features after the convolution operation; This is a two-dimensional convolution operation; These are the model parameters for a two-dimensional convolutional layer; For line H The real space of column k channels; This represents the number of convolutional kernels; For attention pooling operations; The attention mask corresponding to the topological node associativity; This is the attention mask corresponding to the wiring density gradient; For line H The real space of the column; The dimension of a single-class topological feature; For the attention mask corresponding to the topological clustering of pads; The feature vector for the circuit board scene label; This is a one-hot encoding operation; Labels for positioning deviation types; This is a normalization operation; Image sharpness label; Image distortion level labels; 1 row The real space of the column; The total dimension of the label features; Features are the result of multi-feature fusion; This is a vector repetition operation; For line H The real space of the column; Enhanced image features; For the adapted topology encoder; These are the encoder's model parameters; This is the total loss function of the model; , , For loss weights; This is the mean square error loss; Features of a standard clear image; Cross-entropy loss; The probability distribution of image distortion levels predicted by the model; Labels for the distortion level of real images; This is the average absolute error loss; The image sharpness score predicted by the model.

[0040] It is understood that the embodiments of this application integrate the topological correlation characteristics in the circuit board topology data and the error patterns in the historical positioning error data through the topology-aware image adaptation model. When processing circuit board image data, it can specifically adapt to the topology, offset the influence of image distortion, and correct positioning deviations. This can effectively make up for the shortcomings of general image models in terms of positioning accuracy when adapting to complex circuit boards, and avoid feature extraction errors caused by unclear topology resolution or image quality issues. It can also provide high-quality image input for the dynamic anchor point matching model after topology adaptation and error correction, helping to accurately extract multimodal features of components and resolve 3D spatial coordinates, ensuring the topological correlation and error controllability of component positioning. At the same time, it can also continuously iterate by combining the subsequently collected positioning accuracy data to further improve the stability and accuracy of electronic component positioning.

[0041] For example, taking the positioning of electronic components on an automotive electronic control unit (ECU) circuit board as an example, when locating components such as microcontrollers, capacitors, and resistors on the circuit board, the topology-aware image adaptation model first calls the topology data of the circuit board (such as the pin connection relationship between the microcontroller and surrounding components, and the distribution of wiring density). Combining this with the pattern in historical positioning error data that "positioning deviation is prone to occur around the microcontroller due to dense wiring," the model quickly adapts to the topology characteristics of the ECU circuit board. Subsequently, the acquired circuit board image data is processed. Through convolution operations and attention pooling in the model, key features such as microcontroller pins and capacitor pads are enhanced, and interference caused by image distortion (such as reflection and slight blur) is filtered out. Finally, the optimized enhanced image features are output, providing support for the dynamic anchor point matching model to accurately extract the geometric features of components and resolve 3D spatial coordinates. This keeps the positioning error of the microcontroller within ±0.01mm, which is significantly better than traditional positioning methods. At the same time, the model records the error data of this adaptation and continuously updates the parameters based on subsequent feedback, further improving the positioning accuracy of similar circuit boards.

[0042] In step S103, a dynamic anchor point matching model is constructed based on the 3D model data of electronic components, the image data of the circuit board, and the annotation data of the component library. Combined with the topology-aware image adaptation model and the texture segmentation algorithm, the geometric features, electrical connection features, and multimodal texture features of the components are extracted. The topological adjacency relationship is matched and the 3D spatial position coordinates of the components are resolved. The components are coarsely located by combining the real-time updated circuit board image data to obtain the coarse location result. The coarse location result is optimized by the real-time error correction algorithm to generate the precise location coordinate set of the components and the dynamic calibration command.

[0043] Among them, the dynamic anchor point matching model refers to an image adaptation model that is built based on the 3D model of electronic components, circuit board images and component library annotation data, and integrates topology-awareness. It is used to extract multimodal features of components, match topological relationships and support the analysis and positioning optimization of 3D spatial coordinates of components.

[0044] It is understood that the embodiments of this application integrate 3D structural information from the 3D model data of electronic components, visual features from the circuit board image data, and attributes and topological rules from the component library annotation data. The dynamic anchor point matching model fuses the optimized image features of the topology-aware image adaptation model. This can accurately extract the geometric, electrical connection, and multimodal texture features of components, effectively compensating for the positioning deviation caused by the insufficient consideration of the 3D structure and topological association of components in traditional models, and avoiding feature confusion caused by differences in component packaging or dense layout. Furthermore, it can efficiently resolve the 3D spatial coordinates of components through texture segmentation algorithms and topological adjacency matching, and complete coarse positioning and iterative error correction in combination with real-time image data, ensuring the accuracy and stability of the positioning coordinates. At the same time, it can continuously iterate through the subsequently collected positioning evaluation data, continuously strengthening the multi-feature fusion and error correction capabilities, further improving the efficiency and accuracy of electronic component positioning, and meeting the positioning needs of complex circuit boards.

[0045] It should be noted that when performing coarse component localization using real-time updated circuit board image data, the process first relies on the geometric features, electrical connection features, and multimodal texture features extracted by the dynamic anchor point matching model and the topology-aware image adaptation model, as well as the matched topological adjacency relationships and the initially resolved 3D spatial coordinates. These pre-generated feature information are then rapidly compared and correlated with the real-time updated circuit board image data in multiple dimensions. The real-time updated circuit board image data reflects the actual operating conditions of the circuit board, including the real-time placement of components and any possible slight displacements or orientation changes, avoiding localization errors caused by relying on static data. During localization, topological adjacency relationships are used as constraints to clarify the relative positional relationships of each component on the circuit board (e.g., the connection layout relationship between a component and surrounding resistors and capacitors). Geometric features (component shape and size) and multimodal texture features (surface texture and color distribution) are used as the core matching criteria. Combined with the initial 3D spatial coordinates, the search range is narrowed. Without requiring fine calculations, regions in the image that highly match the features of the target component are quickly selected, initially locking the approximate location range of each component in the circuit board image (e.g., the boundary of the region marked by a rectangle). The focus of this process is to quickly eliminate irrelevant areas and determine the approximate distribution of components. It does not pursue the ultimate positioning accuracy. The core purpose is to provide a clear positioning basis for subsequent precise optimization steps, and finally form a coarse positioning result containing the approximate position information of all target components.

[0046] When optimizing the coarse positioning results using a real-time error correction algorithm, the algorithm first comprehensively analyzes potential error sources in the coarse positioning results by combining 3D model data of electronic components, component library annotation data, and real-time updated circuit board image data. These sources include image noise interference, feature matching deviations, subtle changes in component posture, and positioning offsets caused by slight deformation of the circuit board. The algorithm uses previously extracted component geometric features, electrical connection features, multimodal texture features, and topological adjacency relationships as core constraints. It performs multi-dimensional comparisons between the approximate component position range obtained from coarse positioning and the standard parameters of the 3D model and the annotation benchmarks of the component library to accurately calculate the position deviation value (covering multiple types of deviations such as translation, rotation, and scaling). Subsequently, an iterative optimization strategy is adopted to dynamically adjust the positioning coordinates based on real-time acquired circuit board image frames: the matching accuracy of component edges and surface texture features is further refined through texture segmentation algorithms, and topological adjacency relationships are used to ensure that the corrected position of a single component and its relative connection relationship with surrounding components conform to the circuit design logic, avoiding positional conflicts between components. Meanwhile, the algorithm monitors the deviation trend in real time. For persistent deviations (such as component installation errors or minor displacements during equipment operation), it generates dynamic calibration instructions based on the error accumulation pattern. These instructions guide parameter adjustments or real-time corrections of related equipment in subsequent positioning processes. After multiple rounds of dynamic comparison and iterative optimization, the algorithm finally outputs the precise 3D spatial coordinates of each component, forming a precise positioning coordinate set for the component. This ensures that the positioning accuracy meets the high-precision requirements of electronic component assembly and testing scenarios. At the same time, the dynamic calibration instructions guarantee the stability and accuracy of subsequent positioning processes.

[0047] Real-time error correction algorithm formula: ; ; ; in, This is the combined error vector; Geometric feature error weights; Geometric feature deviation; Weights for electrical connection characteristic errors; For electrical connection characteristic deviations; For texture feature error weights; This is due to multimodal texture feature deviation; These are the topological constraint coefficients; For topology compatibility constraints; These are the optimized positioning coordinates after the (k+1)th iteration; The coordinates are the results of the coarse positioning. Let k be the iteration step size. This is the error normalization function; This is the comprehensive error vector (same as above); For real-time feedback coefficients; This is a real-time image feedback function; For real-time updated circuit board image data; The optimized positioning coordinates are those obtained after the k-th iteration. For dynamic calibration command parameters; Weighted by the rate of change of error; This represents the comprehensive error amplitude for the (k+1)th round. This represents the comprehensive error amplitude for the k-th round. The time interval between two iterations; Cumulative weighting for deviations; This represents the cumulative amount of historical deviation.

[0048] For example, such as Figure 3 As shown, taking the component location scenario in mobile phone motherboard repair as an example, when performing component testing on a faulty motherboard of a certain model of mobile phone, the system first imports the 3D model data of the electronic components of the motherboard, the real-time acquired motherboard image data, and the annotation data of surface-mount capacitors and micro resistors in the component library. Using a dynamic anchor point matching model, combined with a topology-aware image adaptation model and texture segmentation algorithm, the system extracts the square geometric features of the target surface-mount capacitor, its pin electrical connection features with surrounding chips, and the multimodal texture features of its surface markings. Simultaneously, it matches the topological adjacency relationship between the capacitor and adjacent resistors and chips and resolves the initial 3D spatial coordinates. Then, combined with the real-time updated motherboard image data, it quickly correlates and compares topological relationships as constraints and feature information as the basis to roughly locate the approximate area of ​​the surface-mount capacitor in the motherboard image. Finally, a real-time error correction algorithm optimizes the coarse location result, generating a precise 3D positioning coordinate set and dynamic calibration instructions for the capacitor. This assists automated repair equipment in accurately picking up the faulty capacitor and replacing it, effectively improving the efficiency and accuracy of motherboard component location.

[0049] In this embodiment, a dynamic anchor point matching model is constructed based on 3D model data of electronic components, circuit board image data, and component library annotation data. This includes: acquiring 3D model data of electronic components, circuit board image data, and component library annotation data; extracting core features of component geometry, pin layout, and package type based on the 3D model data and component library annotation data, constructing an electronic component knowledge graph, and annotating feature attributes and topological association rules; processing the circuit board image data, combining it with the 3D contour features in the 3D model data of the electronic components, associating it with the electronic component knowledge graph, and fusing the enhanced topological features of the topology-aware image adaptation model to construct a dynamic anchor point matching model.

[0050] Among them, the electronic component knowledge graph refers to a structured knowledge system built on the three-dimensional model data of electronic components and the component library annotation data. It includes core features such as component geometry and pin layout, annotation feature attributes and topological association rules, and is used to support component feature verification and topological relationship matching.

[0051] It is understood that the embodiments of this application utilize an electronic component knowledge graph to integrate the core features of components with topological association rules, providing structured knowledge support for the dynamic anchor point matching model. This avoids feature matching chaos caused by scattered data and enables rapid verification of the consistency between circuit board image data and 3D model data through the association rules of the knowledge graph. At the same time, it integrates the enhanced topological features of the topology-aware image adaptation model, further strengthening the model's ability to adapt to the circuit board topology, enabling the model to accurately extract multimodal features of components and efficiently match topological relationships. This effectively reduces positioning errors caused by similar component features or complex topological associations, and improves the accuracy and efficiency of component 3D spatial coordinate analysis.

[0052] It should be noted that, based on the 3D model data of electronic components and the labeled data of the component library, the core features of component geometry, pin layout, and package type are extracted to construct an electronic component knowledge graph. Feature attributes and topological association rules are labeled. First, the 3D model data of electronic components is processed. 3D model parsing tools (such as MeshLab) are used to extract the core features of component geometry (length, width, height, pin spacing), pin layout (pin number, arrangement, pin length), and package type (SMT, DIP, QFP, etc.). The labeled data of the component library is then cleaned and structured, supplementing information such as component electrical parameters and topological connection compatibility. Subsequently, the core framework of the knowledge graph is constructed using an entity-relationship-attribute triplet pattern, where entities include "electronic components". The system includes attributes such as "component," "package type," and "topology connection point," with relationships including "having geometric dimensions," "using package type," and "can be topologically connected to XX component." Attributes include specific numerical values ​​for geometric dimensions, standard parameters for the package type, and adaptation conditions for topology connections. For example, the entity "0805 type surface mount resistor" has attributes of "length 2.0mm, width 1.25mm, pin pitch 0.5mm, package type SMT," and the relationship is "can be topologically connected to 0603 type capacitor." Finally, the knowledge graph data is stored in the Neo4j graph database, establishing feature indexes and related query interfaces to support the model's rapid retrieval of component features and topology rules. Simultaneously, through manual verification and machine iterative optimization, feature annotation errors and topology relationship deviations are corrected to ensure the accuracy and completeness of the knowledge graph.

[0053] The circuit board image data is processed and combined with the 3D contour features from the 3D model data of electronic components. This is then linked to the electronic component knowledge graph and fused with enhanced topological features from a topology-aware image adaptation model. First, the circuit board image data is preprocessed (e.g., noise reduction, image enhancement, distortion correction). Then, 2D contour features of the components are extracted using edge detection algorithms (e.g., the Canny algorithm). Next, the 2D contour features are matched with the 3D contour features from the 3D model data of the electronic components to initially screen candidate component types. The core features and topological association rules of the candidate components are queried through the electronic component knowledge graph to verify the consistency between the 2D and 3D contour features, eliminating invalid candidates with mismatched features. Finally, enhanced topological features output by the topology-aware image adaptation model (e.g., the correlation between the component and surrounding topological nodes, wiring density gradient) are fused to further optimize the matching accuracy of the candidate components, providing accurate preliminary support for the dynamic anchor point matching model to extract multimodal features of components and resolve 3D spatial coordinates.

[0054] Dynamic anchor point matching model formula: ; ; ; in, This is a multi-source feature fusion vector; Image feature fusion weights; 2D features extracted from circuit board images; Weights for feature fusion in 3D models; 3D contour features for three-dimensional models of electronic components; Weights for knowledge graph feature fusion; The feature vector of the electronic component knowledge graph; To enhance the weighting of topological feature fusion; Enhanced topological features output by the topology-aware image adaptation model; For the generated dynamic anchor points; The K-means clustering algorithm is used. This refers to the number of anchor points; The resolved 3D spatial coordinates of the component; This is a triangulation algorithm; This is 3D model data for electronic components.

[0055] In this embodiment, the extraction of component geometric features, electrical connection features, and multimodal texture features, matching topological adjacency relationships, and parsing the 3D spatial coordinates of the components includes: constructing a multimodal feature fusion model; based on the feature extraction layer of the multimodal feature fusion model, parsing the circuit board image data, extracting component geometric features, electrical connection features, and multimodal texture features, verifying the features using a dynamic anchor point matching model, excluding invalid features that are not electrically connected to topological nodes, and obtaining valid features after verification; inputting the valid features after verification into the topology matching layer, matching them with the topological adjacency relationships output by the topology-aware image adaptation model, and parsing the 3D spatial coordinates and rotation angles of the components using triangulation and texture segmentation algorithms to generate positioning information containing coordinate accuracy level and topology matching degree.

[0056] Among them, the multimodal feature fusion model refers to a model tool built based on deep learning, used to extract multi-dimensional features such as component geometry, electrical connections, and multimodal textures from circuit board image data, and to fuse and verify them.

[0057] It is understood that the embodiments of this application extract multi-dimensional features of components through a multimodal feature fusion model, which not only comprehensively captures the core attributes of the components, but also verifies and eliminates invalid features through a dynamic anchor point matching model, avoiding positioning deviations caused by feature redundancy or invalidity; by matching with topological adjacency relationships, the topological correlation of features is strengthened, and by combining triangulation and texture segmentation algorithms, the 3D spatial coordinates and rotation angles of the components are accurately analyzed, generating positioning information that includes accuracy level and topological matching degree. This not only ensures the accuracy of coordinate analysis, but also provides a quantitative basis for subsequent coarse positioning and error correction, effectively improving the comprehensiveness and reliability of electronic component positioning.

[0058] It should be noted that the formula for the multimodal feature fusion model is as follows: ; ; ; ; ; in, The extracted geometric features of the components; This is a two-dimensional convolution operation; This refers to the preprocessed circuit board image data; Geometric feature convolution weights; Bias for convolution of geometric features; for OK List The real space of the channel; Image height; Image width; Geometric feature dimension; For extracted electrical connection features; For graph neural networks; Electrical connection diagram structure data for circuit board images; Electrical characteristic weights; For electrical characteristic bias; for OK List The real space of the channel; For electrical characteristics; For the extracted multimodal texture features; This is a multi-scale convolution operation; Convolution weights for texture features; Apply a bias to the convolution of texture features; for OK List The real space of the channel; For texture feature dimensions; This is the result of multimodal feature fusion; For feature splicing operations; for OK List The real space of the channel; These are the valid features after verification; For feature masking operations; The feature verification results are for the dynamic anchor point matching model.

[0059] The validated valid features are input into the topology matching layer and matched with the topological adjacency relationships output by the topology-aware image adaptation model. Using triangulation and texture segmentation algorithms, the 3D spatial coordinates and rotation angles of the components are analyzed to generate positioning information containing coordinate accuracy levels and topology matching degrees. First, the similarity between the valid features and the topological adjacency relationships is calculated to match the corresponding topological nodes and associated components, determining the component's position within the circuit board topology. Then, a texture segmentation algorithm (such as Mask R-CNN) is used to segment the independent texture regions of the components, combining this with the texture features of the electronic component's 3D model. The system optimizes feature matching accuracy. Using triangulation, it calculates the 3D spatial coordinates (X, Y, Z axis coordinates) and rotation angles (rotation angles around the X, Y, Z axes) of components based on circuit board image data from different perspectives and topology node coordinates. Finally, it quantifies the coordinate accuracy level (e.g., Level 1: error ≤ 0.01mm, Level 2: 0.01mm < error ≤ 0.05mm) based on feature matching accuracy and topology relationship resolution success rate, calculates the topology matching degree (number of effective topology associations / total number of topology associations), and generates structured positioning information containing coordinate values, rotation angles, accuracy level, and topology matching degree.

[0060] Triangulation formula: ; ; in, Here are the homogeneous pixel coordinates of the element in image 1; Let be the projection matrix of camera 1; The homogeneous 3D spatial coordinates of the component; It is a zero vector; Here are the homogeneous pixel coordinates of the element in image 2; Let be the projection matrix of camera 2; The rotation angle of the component; It is the inverse cosine function; This is the normal vector of the circuit board plane; for The modulus length; for The length of the module.

[0061] Texture segmentation algorithm formula: ; in, Texture segmentation mask for components; It is the sigmoid activation function; This is a two-dimensional convolution operation; For the extracted multimodal texture features; Convolution weights for texture segmentation; Convolution bias for texture segmentation.

[0062] In step S104, based on the precise positioning coordinate set of the component and the dynamic calibration command, the deviation data between the positioning point and the theoretical coordinate is extracted. Combined with the average positioning error, feature matching accuracy, topology relationship resolution success rate and calibration command execution effectiveness index, a positioning accuracy evaluation table is generated, and component areas with positioning anomalies are marked simultaneously to form an electronic component positioning evaluation report.

[0063] Among them, the electronic component positioning evaluation report refers to a structured report generated based on the positioning results of electronic components, using core indicators such as positioning deviation data and feature matching accuracy, combined with accuracy level and anomaly markers, to evaluate the positioning effect and guide model optimization.

[0064] It is understood that the embodiments of this application, by extracting positioning deviation data and combining it with multi-dimensional evaluation indicators to generate positioning accuracy evaluation tables and reports, can not only comprehensively quantify the positioning effect and clearly present the positioning accuracy level and abnormal situations of each component, but also provide a clear direction for model optimization. For example, for positioning anomalies caused by low success rate of topology relationship parsing, the topology feature extraction network can be optimized; at the same time, the abnormal area marking can quickly locate the components and areas where positioning has failed, providing a basis for manual review and secondary positioning, effectively improving the closed-loop management capability of electronic component positioning, and continuously optimizing positioning accuracy and reliability.

[0065] For example, taking a smartphone motherboard mass production line of a consumer electronics manufacturer as an example, when evaluating the positioning results of electronic components on a batch of 500 motherboards, the generated electronic component positioning evaluation report clearly presented the 3D coordinate deviation value, topology matching degree, and accuracy level of each component. Among them, it was found that the chip resistor of model 0402 had a batch positioning deviation exceeding the standard by 12% (exceeding the accuracy threshold of ±0.05mm). The report also indicated that the root cause of the deviation was insufficient feature extraction of small-sized components by the texture segmentation algorithm. Based on the report's conclusions, the production line technical team specifically optimized the small feature channel weights of multi-scale convolution, re-run the positioning process, and generated another evaluation report. The positioning deviation of the chip resistor was reduced to within ±0.03mm, and the topology matching degree was improved to 98%. Ultimately, this not only improved the detection efficiency of motherboard component positioning by 20%, but also increased the production yield caused by component positioning deviation from 92% to 98.5%, effectively ensuring the stable and efficient operation of the production line.

[0066] In this embodiment of the application, generating a positioning accuracy evaluation table includes: constructing a positioning accuracy evaluation model; based on the positioning accuracy evaluation model, inputting the deviation data between the positioning point and the theoretical coordinates, the feature matching accuracy rate, the success rate of topological relationship resolution, and the effectiveness index of calibration command execution, and calculating the comprehensive positioning reliability score; generating positioning accuracy levels and summarizing them into a positioning accuracy evaluation table according to the comprehensive positioning reliability score and the threshold values ​​of each index, and simultaneously marking the component areas with confidence scores below the threshold as positioning anomalies.

[0067] Among them, the positioning accuracy assessment model refers to a model tool built based on positioning deviation data, feature matching accuracy, and other multi-dimensional indicators, used to calculate the comprehensive positioning reliability score, classify accuracy levels, and mark positioning anomalies.

[0068] It is understood that the embodiments of this application integrate multi-dimensional evaluation indicators through a positioning accuracy evaluation model, and quantitatively calculate the comprehensive positioning reliability score. This not only avoids the one-sidedness of single indicator evaluation, but also classifies accuracy levels and marks positioning anomalies through clear threshold standards, making the positioning effect evaluation more objective and accurate. At the same time, the output positioning accuracy evaluation table can clearly present the positioning status of each component, providing structured data support for subsequent model optimization and manual review, effectively improving the quality control capability of electronic component positioning, and ensuring the reliability and usability of positioning results.

[0069] It should be noted that the formula for the positioning accuracy evaluation model is as follows: ; ; in, To synthesize the location reliability score; , , , The indicator weights (summing up to 1); This represents the deviation between the location point and the theoretical coordinates. This is the maximum permissible deviation value; For feature matching accuracy; For the success rate of topological relationship resolution; To verify the validity of the calibration instruction execution (0-1 range); This refers to the positioning accuracy level.

[0070] Based on the comprehensive positioning reliability score and various indicator thresholds, positioning accuracy levels are generated and summarized into a positioning accuracy evaluation table. Simultaneously, component areas with confidence scores below the threshold are marked as positioning anomalies. A comprehensive quantitative score is calculated by integrating multiple dimensions of positioning indicators such as component 3D coordinate deviation, topology matching degree, and texture feature matching rate, along with pre-set acceptable thresholds (such as coordinate deviation thresholds and confidence thresholds) based on accuracy requirements in scenarios such as circuit board component assembly. Then, the comprehensive positioning reliability score of each component is compared with preset level classification standards (e.g., confidence ≥ 0.95 corresponds to "Level 1 accuracy," 0.85-0.95 corresponds to "Level 2 accuracy") to determine the positioning accuracy level of each component. Next, the component numbers, comprehensive confidence scores, positioning accuracy levels, and various sub-indicators (such as coordinate deviation values) are uniformly organized to form a clear and intuitive positioning accuracy evaluation table. At the same time, components with comprehensive positioning reliability scores below the preset threshold are selected, and the corresponding circuit board areas of these components are labeled "Positioning Anomaly" in the evaluation table, clearly identifying the positioning areas that do not meet the acceptable standards, providing clear guidance for subsequent repositioning or optimization of the positioning process.

[0071] For example, taking the mass production testing of automotive electronic control unit (ECU) circuit boards as a scenario, when an automotive electronics manufacturer verifies the component positioning results of a batch of 200 ECU circuit boards, it uses a positioning accuracy evaluation model: First, the positioning information such as the 3D spatial positioning coordinates and topology matching degree of each component is imported into the model along with the standard reference coordinates in the circuit board design file. The model generates a comprehensive positioning confidence score by calculating indicators such as coordinate deviation value and topology matching error. Then, combined with a preset accuracy level threshold (e.g., confidence level ≥ 0.95 is "Level 1 accuracy"), it outputs a positioning accuracy evaluation table. The system identified abnormal areas where the positioning reliability (0.82) of eight circuit boards in a certain model of main control chip was lower than the threshold (0.9), and determined that the root cause of the deviation was insufficient extraction of the surface texture features of the chip. Based on the evaluation results output by the model, the technical team optimized the texture feature channel weights of the multi-scale convolution. After rerunning the positioning process and evaluating the model again, the positioning reliability of the main control chip was improved to 0.97, and the accuracy level reached "Level 1". Ultimately, the pass rate of the ECU circuit board component positioning was increased from 91% to 99%, effectively avoiding circuit assembly failures caused by positioning deviations.

[0072] This application proposes an image-based method for locating electronic components on circuit boards. By integrating multi-source data including circuit board images, topology, 3D models of electronic components, historical positioning errors, and component library annotations, and utilizing a topology-aware image adaptation model and a dynamic anchor point matching model, combined with a texture segmentation algorithm, multi-dimensional features are accurately extracted and topological relationships are matched. After coarse positioning and real-time error correction, precise coordinates and calibration instructions are generated. This solves the problems of poor response to complex topologies and environmental interference, and large positioning parameter deviations in traditional single-feature or template matching methods, breaking down the disconnect between component dynamic features and positioning data. Simultaneously, by training and optimizing model parameter weights using deviation data and evaluation indicators, an evaluation table is generated and abnormal areas are marked. This significantly improves positioning accuracy and stability while ensuring positioning reliability, effectively filling the gap in deep multi-source data linkage and dynamic error correction in existing technologies, and minimizing positioning deviations. Therefore, it solves the problems of poor positioning and resolution capabilities in existing technologies.

[0073] The following will illustrate an image-based method for locating electronic components on a circuit board through a specific embodiment, such as... Figure 4 As shown, it includes:

[0074] Taking a consumer electronics manufacturer's smartphone motherboard SMT (Surface Mount Technology) production line as an example, this is a fully automated flexible production line with an annual capacity of 10 million smartphone motherboards, focusing on the mass production of the X10 Pro flagship motherboard. The motherboard measures 140mm × 70mm, adopts a 10-layer PCB (Printed Circuit Board) design, and integrates more than 230 electronic components, including 0201 / 0402 specification surface mount resistors and capacitors (accounting for 65%), a BGA packaged main control chip (1 chip, size 12mm × 12mm), LGA packaged RF chips (3 chips), connector interfaces (8), and miniature sensors (5), etc. The smallest component size is only 0.6mm × 0.3mm, requiring extremely high positioning accuracy (the positioning error of core components must be ≤ ±0.02mm, and that of ordinary components ≤ ±0.05mm). The production line is equipped with 6 placement lines, each containing one solder paste printer, one high-speed pick-and-place machine, one reflow oven, and one AOI (Automated Optical Inspection) machine, along with 3 offline inspection stations and 1 data monitoring center, producing an average of 30,000 motherboards per day. The core requirement is to use high-precision image positioning technology to achieve pre-placement positioning calibration, post-placement accuracy inspection, and faulty component location during rework, solving the problem of cold solder joints and incorrect soldering caused by positioning deviations of small-sized components, and improving production line yield and inspection efficiency. The data acquisition and processing equipment system is built around "image acquisition - topology analysis - 3D modeling". The specific configuration is as follows: the image acquisition equipment uses 8 Hikvision MV-CA050-10GM industrial cameras (resolution 2592×1944, frame rate 30fps, pixel size 2.2μm, equipped with a 5-megapixel industrial lens and a ring LED light source), arranged in a "binocular + multi-view" layout—one set of binocular cameras (15cm spacing, vertically shooting the motherboard, covering the entire board) is deployed at each assembly line's mounting station; two side-view cameras (tilted 4...) are deployed at the AOI inspection station. The offline inspection station is equipped with a 5° angle for capturing the component's side mounting height. It also features a high-magnification camera (200× magnification for detailed imaging of minute components). The topology data processing equipment consists of three Dell PowerEdge R750 servers (two Intel Xeon Gold 6430 CPUs, 256GB RAM, and 50TB storage) responsible for topology data analysis and model training. The 3D modeling equipment uses a Keyence LK-G80 laser profilometer (measurement accuracy ±0.1μm, scanning speed 1000 points / second) to acquire component 3D morphology data. All equipment is connected to the production line's MES (Manufacturing Execution System) via industrial Ethernet, supporting real-time data transmission and collaborative equipment control, meeting the data support requirements for the entire image positioning process.

[0075] To achieve end-to-end data input for the positioning method, a comprehensive data acquisition system was constructed, comprising five categories: circuit board image data, circuit board topology data, electronic component 3D model data, historical positioning error data, and component library annotation data. Each data acquisition scheme was designed in accordance with the characteristics of the industrial scenario and hardware adaptability: Circuit board image data acquisition adopted a "multi-view shooting + precise preprocessing" scheme. A binocular camera simultaneously captured the front view and local detail images of the motherboard, a side-view camera captured the height contour after component mounting, and a high-magnification camera captured the texture details of tiny components such as 0201 specification. Image preprocessing was implemented using OpenCV 4.8.0, sequentially performing grayscale conversion (using weighted averaging to improve contrast), noise reduction (Gaussian filter kernel size 3×3), distortion correction (radial distortion correction based on camera intrinsic parameter matrix), and image alignment (based on the positioning holes on the edge of the motherboard, with an error ≤ ±0.01mm). The final output was standardized image data (resolution 2048×1024, pixel accuracy 0.007mm / pixel). The circuit board topology data was extracted from the motherboard CAD design file (Altium Designer format). A CAD-to-graphics tool was used to parse the component layout coordinates, pad positions, wire connections, and network topology. NetworkX was used to construct a topology diagram (nodes representing components / pads, edges representing electrical connections), annotating parameters such as line width and spacing for each connection to form a structured topology data file. The 3D model data of electronic components was generated using a combination of laser scanning and parametric modeling: standard components (such as resistors and capacitors) were imported from the manufacturer's 3D model library (IPC standard format), while non-standard components (such as custom connectors) were scanned using a laser profilometer to obtain point cloud data. After denoising and reconstruction using MeshLab software, an STL format 3D model was generated, annotating geometric parameters such as length, width, height, and pin positions. Historical positioning error data was extracted from nearly 12 months of production logs from the production line MES system, covering 1.5 million component positioning records. These records include component model, positioning coordinates, actual placement coordinates, error values, fault types (such as offset, rotation, and missing placement), and rework records. The data was categorized and organized by "component type - placement station - production period" to form a historical error feature library. The component library annotation data integrates multiple resources, including over 200 datasheets provided by component manufacturers, IPC component standard manuals, and a self-built annotation library (containing 50,000 component image annotations). The annotation content covers component model, geometric dimensions, color, surface texture (such as silkscreen markings and pin arrangement), electrical parameters, and pad matching specifications, and is stored in a structured XML format.Data transmission and storage adopt an "edge computing + cloud backup" architecture: five Huawei Atlas200DK edge computing modules (8 TOPS computing power, supporting real-time image processing) are deployed at the edge to handle camera image acquisition and preprocessing, with a processing latency of ≤50ms; the cloud uses the Alibaba Cloud Industrial Internet Platform, configured with 100TB of storage space to store historical data, model parameters and positioning records, supporting data traceability by "production batch - motherboard serial number", and setting up a triple backup mechanism (real-time incremental backup, daily full backup, and off-site disaster recovery backup) to ensure the security and compliance of production data.

[0076] Based on the Python 3.9 programming language and the PyTorch 2.0 deep learning framework, a topology-aware image adaptation model is constructed, which achieves accurate matching between the circuit board topology and image data. The model input features include two core dimensions: topology features (relative positions of components, pad connection relationships, and network topology density extracted from the circuit board topology data, encoded as a 16-dimensional vector) and historical error features (average historical positioning errors of similar components, error fluctuation coefficient, and mounting station adaptation coefficient, encoded as an 8-dimensional vector). The two types of features are concatenated into a 24-dimensional input vector after Min-Max standardization (mapped to the [0,1] interval). The model structure adopts a fusion architecture of "CNN+GNN": the input layer receives a 24-dimensional feature vector, which is mapped to a 32-dimensional feature space through a fully connected layer; the feature extraction layer is divided into a parallel image feature branch and a topology feature branch—the image feature branch uses two layers of Conv2d convolution (3×3 / 5×5 kernels, 32 / 64 output channels, ReLU activation function) to extract the global layout features of the circuit board image, and the topology feature branch uses GAT (Graph Attention Network) to extract the adjacency relationship features between components (4 attention heads, 64 hidden layer dimensions); the fusion layer uses an attention mechanism to weight and fuse the two types of features (adaptive learning of weights), outputting a 48-dimensional fused feature; the output layer is mapped to a 6-dimensional vector through a fully connected layer, corresponding to adaptation parameters such as image scaling factor, rotation angle, and translation offset. The model training dataset consists of 800,000 labeled data points from the past 6 months (divided into a 7:2:1 ratio: 560,000 training data points, 160,000 validation data points, and 80,000 test data points). The AdamW optimizer (learning rate 0.0008, weight decay 1e-6) was used, with a mixed loss function of mean squared error and cross-entropy. Training was conducted for 40 epochs, with an early stopping strategy (stopping if the validation set loss does not decrease for 5 consecutive epochs). Model testing results show that the topology-image adaptation accuracy is ≥99.2%, and the positional deviation between the adapted image and the topology is ≤±0.005mm. This effectively eliminates the positioning reference deviation caused by the image shooting angle and the motherboard placement posture, providing a unified coordinate reference for subsequent feature extraction.

[0077] Based on 3D model data of electronic components, circuit board image data, and component library annotation data, a dynamic anchor point matching model is constructed, which is mainly divided into three stages: feature extraction, coarse localization, and error correction. In the feature extraction stage, combined with the unified coordinate benchmark output by the topology-aware image adaptation model, three types of core features are extracted collaboratively using multiple algorithms: geometric features are extracted through Conv2d convolution and contour detection algorithms, including the outer rectangle size of the component, the radius of the corners, the number of pins, and the spacing of the arrangement (such as the ball grid array spacing of BGA chips), encoded into a 24-dimensional geometric feature vector; electrical connection features are processed by the GNN model to process the circuit board topology map, extracting the relationship features such as the number of connections between component pads and surrounding wires, and the direction of the wires, combined with the gray value distribution of the pads (reflecting the solder paste coverage state), to generate a 16-dimensional electrical connection feature vector; multimodal texture features are extracted through a texture segmentation algorithm improved by U-Net, with differentiated processing for the texture characteristics of different components—the silkscreen numbers of the chip resistors are recognized by OCR and encoded as texture features, the surface markings of the chips are extracted using SIFT feature point matching, and the metal contacts of the connectors are extracted using gray-level histogram features, finally generating a 32-dimensional texture feature vector. The coarse localization stage is based on the feature set generated by the dynamic anchor point matching model, combined with real-time updated circuit board image data (updated 1 frame every 0.5 seconds), and constrained by topological adjacency relationships (such as the fixed relative positions of the main control chip and the RF chip). A feature matching dictionary is constructed (the key is the feature vector, and the value is the historical positioning coordinates). The KNN algorithm is used to quickly match similar features and initially lock the approximate position range of the component in the image (marked with a rectangular box, the range is 20% larger than the actual component). The coarse localization result is output (positioning error of ordinary components ≤ ±0.1mm, core chip ≤ ±0.05mm). The error correction stage employs a real-time iterative optimization algorithm. Using the 3D model data of electronic components as the standard, it calculates the geometric and texture matching deviations between the coarse positioning results and the standard model. Combined with the disparity data from a binocular camera (depth information calculated via triangulation), an error correction function is constructed. Each iteration adjusts the positioning coordinates using gradient descent, iterating 3-5 times until the deviation is less than the accuracy threshold (≤ ±0.02mm for core components, ≤ ±0.05mm for ordinary components). Simultaneously, dynamic calibration instructions are generated (including adjustments to the pick-and-place machine nozzle position and camera angle correction values). To verify the positioning effect, a one-week test was conducted on the production line: positioning over 230 types of components on 50,000 motherboards. The core chip positioning accuracy was 100%, the 0201 specification component positioning accuracy was 99.5%, and the overall average positioning error was 0.018mm, fully meeting the accuracy requirements of the SMT production line. The dynamic calibration instruction execution response time was ≤0.3 seconds, adapting to the high-speed placement rhythm of the pick-and-place machine.

[0078] Based on the precise positioning coordinate set of components and dynamic calibration commands, a positioning accuracy evaluation system is constructed to achieve quantitative evaluation of positioning performance and anomaly tracing. The evaluation index system covers four core indicators: positioning deviation index (the difference between precise positioning coordinates and theoretical design coordinates, statistically analyzed along the X / Y / Z axes), feature matching index (the matching accuracy of geometric / electrical / texture features), topological relationship index (the success rate of topological adjacency relationship resolution), and calibration effectiveness index (the error reduction rate after the execution of dynamic calibration commands). Preset thresholds are set for these indicators (e.g., positioning deviation threshold ±0.02mm / ±0.05mm, feature matching accuracy threshold 95%, topological resolution success rate threshold 99%, and calibration effectiveness threshold 80%). The evaluation model is constructed using a random forest algorithm. The input is the quantitative data of the four types of indicators, and the output is a comprehensive positioning reliability score (0-1 point, the higher the score, the more reliable the positioning). The score is used to classify three accuracy levels: 0.9-1.0 points are "Level 1 Accuracy" (standard for core components), 0.8-0.9 points are "Level 2 Accuracy" (standard for ordinary components), and below 0.8 points are "Unqualified". Based on the evaluation model output, a positioning accuracy evaluation table is generated, which includes the motherboard serial number, component model, precise positioning coordinates, confidence score, accuracy level, and values ​​of various sub-indicators, and is summarized and stored by production batch. At the same time, components with a confidence score below 0.8 are automatically filtered and marked as "positioning anomaly" in the evaluation table. The causes of the anomaly are preliminarily analyzed (e.g., low feature matching accuracy corresponds to texture contamination, topology resolution failure corresponds to PCB wire oxidation), and the abnormal areas are marked in the circuit board image (highlighted with red boxes).

[0079] Based on the positioning accuracy evaluation table and anomaly marking results, the production line technical team carried out targeted optimizations: During the testing period, it was found that 3.2% of the 0201 specification chip resistors had positioning anomalies (confidence level 0.75-0.79). The reason was traced back to the fact that the texture features of this type of component are simple (only silkscreen numbers), and the feature extraction is unstable due to changes in lighting. The technical team added a brightness adjustment module for the ring light source (supporting 10 levels of brightness adaptation), optimized the threshold parameters of the texture segmentation algorithm, and retrained the texture feature extraction branch of the dynamic anchor point matching model. After optimization and retesting, the positioning anomaly rate of this type of component dropped to 0.3%, the average confidence level increased to 0.92, and the accuracy level reached "Level 2". A daily electronic component positioning evaluation report is generated, covering three main modules: batch positioning performance summary (e.g., overall positioning pass rate of 99.2% for 30,000 motherboards on the day, with 68% achieving Level 1 accuracy and 31.2% achieving Level 2 accuracy), anomaly analysis (abnormal component types, percentages, and cause classifications, e.g., among 126 anomalies on the day, texture contamination accounted for 62%, PCB deformation for 28%, and equipment vibration for 10%), and optimization suggestions (e.g., suggesting replacing the vibration damping pads on a certain production line to reduce the impact of equipment vibration). Based on the evaluation report, the parameters of the topology-aware image adaptation model and the dynamic anchor point matching model are iterated monthly, updating the feature extraction weights and error correction function coefficients to adapt the model to component batch differences and equipment aging characteristics. After implementing this positioning method, the production line achieved significant results: the motherboard mounting yield increased from 92% to 99.2%, the missoldering rate of 0201 specification components decreased from 1.5% to 0.08%; AOI inspection efficiency increased by 40% (single board inspection time was reduced from 8 seconds to 4.8 seconds); the fault component positioning time at the rework station was reduced from 5 minutes / piece to 30 seconds / piece, significantly reducing labor costs.

[0080] In summary, this invention constructs a comprehensive data acquisition system covering multiple data types, including circuit board images, topology structures, and 3D models of electronic components. Combined with a storage architecture integrating edge computing for real-time processing and cloud backup, it provides compliant and efficient data support for subsequent positioning model construction and precise positioning. A topology-aware image adaptation model based on a CNN+GNN architecture eliminates positioning benchmark deviations. Coupled with a multi-feature collaborative extraction and iterative error correction algorithm using a dynamic anchor point matching model, it achieves high-precision positioning of core and ordinary components, effectively solving the problems of cold solder joints and incorrect soldering caused by positioning deviations of small-sized components. Based on precise positioning coordinates and dynamic calibration commands, an evaluation system of multiple core indicators is constructed, generating a positioning accuracy evaluation table. It also marks abnormal areas to assist the technical team in optimizing the extraction of small components, significantly improving motherboard placement yield and reducing the missoldering rate of small-sized components; dynamic calibration commands respond quickly to adapt to the high-speed placement rhythm, replacing manual inspection with automated positioning, shortening AOI single-board inspection time and faulty component positioning time at rework stations, greatly reducing labor costs and improving production line operating efficiency; through daily positioning evaluation reports to analyze the causes of anomalies and regularly iterate model parameters, a closed-loop management of data collection-modeling-positioning-evaluation-optimization is formed to ensure that the model adapts to changes in production scenarios, continuously improves positioning accuracy and production stability, and achieves long-term optimization and efficient operation of the entire SMT production line process of placement, inspection, and rework.

[0081] Next, referring to the accompanying drawings, an image-based circuit board electronic component positioning system according to an embodiment of this application is described.

[0082] Figure 5 This is a schematic diagram of the structure of an image-based circuit board electronic component positioning system according to an embodiment of this application.

[0083] like Figure 5 As shown, the image-based circuit board electronic component positioning system 10 includes: an acquisition module 100, a construction module 200, a parsing module 300, and a generation module 400.

[0084] The module 100 acquires circuit board image data, circuit board topology data, electronic component 3D model data, historical positioning error data, and component library annotation data. The module 200 constructs a topology-aware image adaptation model based on the circuit board topology data and historical positioning error data. The module 300 constructs a dynamic anchor point matching model based on the electronic component 3D model data, circuit board image data, and component library annotation data. It then combines the topology-aware image adaptation model with a texture segmentation algorithm to extract the geometric features, electrical connection features, and multimodal texture features of the components, matches topological adjacency relationships, and parses the 3D spatial coordinates of the components. It then performs coarse positioning of the components using real-time updated circuit board image data to obtain coarse positioning results. A real-time error correction algorithm is used to iteratively optimize the coarse positioning results, generating a precise positioning coordinate set and dynamic calibration instructions for the components. The module 400 extracts the deviation data between the positioning points and theoretical coordinates based on the precise positioning coordinate set and dynamic calibration instructions. It then combines the mean positioning error, feature matching accuracy, topology relationship parsing success rate, and calibration instruction execution effectiveness indicators to generate a positioning accuracy evaluation table, simultaneously marking component areas with positioning anomalies, and forming an electronic component positioning evaluation report.

[0085] It should be noted that the foregoing explanation of an embodiment of an image-based circuit board electronic component positioning method also applies to an image-based circuit board electronic component positioning system of this embodiment, and will not be repeated here.

[0086] According to the embodiments of this application, an image-based circuit board electronic component positioning system integrates multi-source data including circuit board images, topology, 3D models of electronic components, historical positioning errors, and component library annotations. Utilizing a topology-aware image adaptation model and a dynamic anchor point matching model, combined with a texture segmentation algorithm, it accurately extracts multi-dimensional features and matches topological relationships. Through coarse positioning and real-time error correction, it generates precise coordinates and calibration instructions. This solves the problems of poor response to complex topologies and environmental interference, and large positioning parameter deviations in traditional single-feature or template matching systems, breaking down the disconnect between component dynamic features and positioning data. Simultaneously, it trains and optimizes model parameter weights using deviation data and evaluation indicators, generating an evaluation table and marking abnormal areas. While ensuring positioning reliability, it significantly improves positioning accuracy and stability, effectively filling the gap in deep multi-source data linkage and dynamic error correction in existing technologies, and minimizing positioning deviations. Thus, it solves the problems of poor positioning and resolution capabilities in existing technologies.

[0087] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include:

[0088] The memory 601, the processor 602, and the computer program stored on the memory 601 and capable of running on the processor 602.

[0089] When the processor 602 executes the program, it implements the image-based circuit board electronic component positioning method provided in the above embodiments.

[0090] Furthermore, electronic devices also include:

[0091] Communication interface 603 is used for communication between memory 601 and processor 602.

[0092] The memory 601 is used to store computer programs that can run on the processor 602.

[0093] The memory 601 may include high-speed RAM (Random Access Memory) and may also include non-volatile memory, such as at least one disk storage device.

[0094] If the memory 601, processor 602, and communication interface 603 are implemented independently, then the communication interface 603, memory 601, and processor 602 can be interconnected via a bus to complete communication between them. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0095] Optionally, in a specific implementation, if the memory 601, processor 602, and communication interface 603 are integrated on a single chip, then the memory 601, processor 602, and communication interface 603 can communicate with each other through an internal interface.

[0096] The processor 602 may be a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of this application.

[0097] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described image-based circuit board electronic component positioning method.

[0098] Furthermore, embodiments of this application also provide a computer program product, including a computer program or instructions, which, when executed, implement the above-described image-based circuit board electronic component positioning method.

[0099] In the description of this specification, the references to "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0100] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0101] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0102] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any of the following techniques known in the art, or a combination thereof: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0103] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium. When executed, the program includes one or a combination of the steps of the method embodiments.

[0104] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An image-based method of locating electronic components on a circuit board, the method comprising: The method comprises the following steps: acquiring circuit board image data, circuit board topology data, electronic component three-dimensional model data, historical positioning error data, and component library annotation data; constructing a topology-aware image adaptation model according to the circuit board topology data and the historical positioning error data; based on the electronic component three-dimensional model data, the circuit board image data, and the component library annotation data, constructing a dynamic anchor point matching model, combining the topology-aware image adaptation model, and using a texture segmentation algorithm to extract geometric features, electrical connection features, and multi-modal texture features of the components, match the topology adjacency relationship, and analyze the 3D spatial position coordinates of the components, combine the real-time updated circuit board image data to coarsely position the components, obtain a coarse positioning result, optimize the coarse positioning result by using a real-time error correction algorithm, and generate a component accurate positioning coordinate set and a dynamic calibration instruction; according to the component accurate positioning coordinate set and the dynamic calibration instruction, extracting deviation data of the positioning points and the theoretical coordinates, combining positioning error mean, feature matching accuracy, topology relationship analysis success rate, and calibration instruction execution effectiveness index to generate a positioning accuracy evaluation table, synchronously marking the component area with positioning abnormalities, and forming an electronic component positioning evaluation report.

2. The image-based electronic component positioning method of claim 1, wherein, According to the circuit board topology data and the historical positioning error data, a topology-aware image adaptation model is constructed, which comprises the following steps: acquiring circuit board topology data and historical positioning error data; according to the circuit board topology data and the historical positioning error data, constructing a topology feature extraction network, separating topology node correlation and wiring density gradient features through a multi-layer perception machine, wherein the topology node correlation represents the closeness of electrical connection between components, and the wiring density gradient reflects the change trend of the region wiring density; based on the topology feature extraction network, filtering image samples of frequently used circuit board types according to positioning deviation types and image distortion levels, labeling sample labels, combining separated topology features, optimizing the model through back propagation, and constructing a topology-aware image adaptation model.

3. The image-based electronic component positioning method of claim 1, wherein, Based on the electronic component three-dimensional model data, the circuit board image data, and the component library annotation data, a dynamic anchor point matching model is constructed, which comprises the following steps: acquiring electronic component three-dimensional model data, circuit board image data, and component library annotation data; based on the electronic component three-dimensional model data and the component library annotation data, extracting core features such as component geometric dimensions, pin layout, and packaging type, constructing an electronic component knowledge graph, and labeling feature attributes and topology correlation rules; processing the circuit board image data, combining the 3D contour features in the electronic component three-dimensional model data, associating the electronic component knowledge graph, fusing the enhanced topology features of the topology-aware image adaptation model, and constructing a dynamic anchor point matching model.

4. The image-based electronic component positioning method of claim 1, wherein, The formula of the topology-aware image adaptation model is: ； ； ； ； ； ； ； ； ； ； wherein, is the input feature of the fused model; is the feature concatenation operation; is the pixel feature of the circuit board image data; is the linear embedding layer; is the circuit board topology data set; is the real number space of H rows columns; is the height dimension of the image feature; is the image feature dimension; is the embedding dimension of the topology parameter; is the separated topology feature set; is the topology feature extraction network; is the model parameter of the topology feature extraction network; is the separated topology node correlation degree feature; is the separated wiring density gradient feature; is the separated pad topology clustering feature; is the feature after convolution operation; is the two-dimensional convolution operation; is the model parameter of the two-dimensional convolution layer; is the real number space of H rows columns k channels; is the number of convolution kernels; is the attention pooling operation; is the attention mask corresponding to the topology node correlation degree; is the attention mask corresponding to the wiring density gradient; is the real number space of H rows columns; is the dimension of the single-class topology feature; is the attention mask corresponding to the pad topology clustering; is the feature vector of the circuit board scene label; is the one-hot encoding operation; is the positioning bias type label; is the normalization operation; is the image sharpness label; is the image distortion level label; is the real number space of 1 row columns; is the total dimension of the label feature; is the feature after multi-feature fusion; is the vector repetition operation; is the real number space of H rows columns; is the enhanced image feature; encoder for an adapted topology; model parameters of the encoder; total loss function of the model; 、 、 loss weight; mean squared error loss; features of the standard sharp image; cross-entropy loss; image distortion level probability distribution predicted by the model; true image distortion level label; mean absolute error loss; image sharpness score predicted by the model.

5. The image-based electronic component positioning method of claim 1, wherein, extracting geometric features, electrical connection features, and multi-modal texture features of components, matching topology adjacency relationships, and analyzing 3D spatial position coordinates of components, comprising: constructing a multi-modal feature fusion model; Based on the feature extraction layer of the multi-modal feature fusion model, the circuit board image data is parsed to extract element geometric features, electrical connection features and multi-modal texture features, the features are verified by combining a dynamic anchor point matching model, invalid features without electrical connection with the topological nodes are excluded, and valid features after verification are obtained; The valid features after verification are input into a topological matching layer, and are matched with topological adjacency relationships output by a topological-aware image adaptation model, the 3D spatial position coordinates and rotation angles of the elements are analyzed by triangulation method and texture segmentation algorithm, and positioning information containing coordinate accuracy level and topological matching degree is generated.

6. The image-based electronic component positioning method of claim 1, wherein, A positioning accuracy evaluation table is generated, including: a positioning accuracy evaluation model is constructed; based on the positioning accuracy evaluation model, deviation data of positioning points and theoretical coordinates, feature matching accuracy, topological relationship analysis success rate and calibration instruction execution effectiveness indicators are input, and a comprehensive positioning confidence score is calculated; according to the comprehensive positioning confidence score and the threshold values of each indicator, a positioning accuracy level is generated and summarized into a positioning accuracy evaluation table, and element regions with confidence lower than the threshold value are marked as positioning abnormalities.

7. An image-based circuit board electronic component positioning system, characterized by, including: an acquisition module for acquiring circuit board image data, circuit board topological structure data, electronic element three-dimensional model data, historical positioning error data and component library annotation data; a construction module for constructing a topological-aware image adaptation model according to the circuit board topological structure data and the historical positioning error data; an analysis module for constructing a dynamic anchor point matching model based on the electronic element three-dimensional model data, the circuit board image data and the component library annotation data, extracting geometric features, electrical connection features and multi-modal texture features of the elements by combining the topological-aware image adaptation model and using a texture segmentation algorithm, matching topological adjacency relationships and analyzing 3D spatial position coordinates of the elements; combining real-time updated circuit board image data to perform coarse positioning on the elements to obtain coarse positioning results, and using a real-time error correction algorithm to iteratively optimize the coarse positioning results to generate accurate positioning coordinate sets of the elements and dynamic calibration instructions; a generation module for extracting deviation data of positioning points and theoretical coordinates based on the accurate positioning coordinate sets of the elements and the dynamic calibration instructions, generating a positioning accuracy evaluation table by combining positioning error mean value, feature matching accuracy, topological relationship analysis success rate and calibration instruction execution effectiveness indicators, synchronously marking element regions with positioning abnormalities, and forming an electronic element positioning evaluation report.

8. An electronic device, comprising: A computer program or instructions are executed to implement the image-based circuit board electronic element positioning method of any one of claims 1-6.

9. A computer readable storage medium having stored thereon a computer program or instructions, characterized in that, A computer program or instructions are executed to implement the image-based circuit board electronic element positioning method of any one of claims 1-6.

10. A computer program product comprising computer programs or instructions, characterized in that, A computer program or instructions are executed to implement the image-based circuit board electronic element positioning method of any one of claims 1-6.

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