Memory management method and storage device

Abstract

The application provides a memory management method and a storage device. The method comprises: obtaining slow-varying metadata and fast-varying metadata of a target page before performing a complete data read operation in response to a read instruction of the target page; obtaining a first voltage adjustment parameter according to the slow-varying metadata; obtaining a second voltage adjustment parameter according to the fast-varying metadata; adjusting a read voltage of the target page from a preset read voltage to a target read voltage according to the first voltage adjustment parameter and the second voltage adjustment parameter; and performing the complete data read operation on the target page according to the target read voltage, wherein the complete data read operation is performed without a historical read failure occurring for the target page. Thus, the data read efficiency of the storage device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a memory management method and a storage device. BACKGROUND

[0002] As a kind of high-density, low-power non-volatile memory, NAND Flash has been widely used in consumer electronics, data centers and industrial control fields. In recent years, with the rapid development of intelligent networked vehicles and advanced driver assistance systems (ADAS), the role of NAND Flash in vehicle-mounted storage systems is becoming more and more critical - not only for recording driving logs and sensor data, but also directly supporting real-time data access required for automatic driving decision-making. However, the delay and reliability of data read and write in the vehicle-mounted environment have put forward much more stringent requirements than consumer-grade products.

[0003] In the automatic driving scenario, the vehicle generates several GB level of multi-source heterogeneous data per second, which puts forward very high requirements on integrity, timeliness and reliability. Any data loss or processing lag caused by reading errors or delays of the storage medium may affect the stability of the perception-decision-control closed loop, and thus endanger driving safety. Therefore, the vehicle-mounted storage system must still guarantee the high reliable read and write capability of data under extreme temperature, vibration, power fluctuation and other harsh working conditions.

[0004] The traditional storage system usually adopts a read retry mechanism of "reading first, decoding later, and retrying if failed", which significantly increases the I / O delay because the data transmission and decoding process need to be executed completely each time of retry. In applications such as automatic driving that are sensitive to response time, this delay may exceed the system tolerance threshold, causing critical data processing to timeout, and even triggering functional safety risks.

[0005] In addition, although relying on high complexity ECC hardware to improve error correction capability can improve reliability, it will significantly increase chip area and power consumption, which does not meet the stringent constraints of cost, energy efficiency and certification period of vehicle-grade chips.

[0006] Therefore, it is urgent to develop a read retry method that takes into account both read efficiency and data reliability, which can effectively improve data read efficiency and system performance without relying on high-cost decoding hardware, and realize a high safety level of vehicle-mounted storage system, which is one of the research topics that the technical personnel in the field are committed to. SUMMARY

[0007] The present application provides a memory management method and a storage device, which aims to solve the technical problems of high read delay and low resource utilization caused by passive response and rough voltage correction of the traditional read retry mechanism, and is particularly suitable for automatic driving systems that require high reliability and fast response.

[0008] To achieve the above object, the technical solution adopted by the present application is as follows:

[0009] The embodiment of the present application provides a memory management method for a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of blocks, each block comprises a plurality of pages, and the memory management method comprises: obtaining slow-varying metadata and fast-varying metadata of a target page before performing a complete data read operation in response to a read instruction of the target page; obtaining a first voltage adjustment parameter by querying a multi-dimensional lookup table and performing interpolation calculation based on a plurality of parameters in the slow-varying metadata according to the slow-varying metadata; obtaining a second voltage adjustment parameter by comparing a fast-varying metadata value with a threshold dynamically calculated based on a program / erase number of a block to which the target page belongs according to the fast-varying metadata; adjusting a read voltage of the target page from a preset read voltage to a target read voltage according to the first voltage adjustment parameter and the second voltage adjustment parameter; and performing the complete data read operation on the page according to the target read voltage, wherein the complete data read operation is performed without a historical read failure occurring for the target page. Thus, a large number of unnecessary re-reading operations are fundamentally avoided, the average read delay and the tail delay are significantly reduced, and the data read efficiency is improved.

[0010] The embodiment of the present application further provides a storage device, which comprises a connection interface electrically connected to a host system, a memory module comprising a plurality of blocks, each block comprising a plurality of pages, and a memory controller comprising an error checking and correction circuit, a buffer memory, and a memory control circuit, the memory control circuit being configured to: obtain slow-varying metadata and fast-varying metadata of a target page before performing a complete data read operation in response to a read instruction of the target page; obtain a first voltage adjustment parameter by querying a multi-dimensional lookup table and performing interpolation calculation based on a plurality of parameters in the slow-varying metadata according to the slow-varying metadata; obtain a second voltage adjustment parameter by comparing a fast-varying metadata value with a threshold dynamically calculated based on a program / erase number of a block to which the target page belongs according to the fast-varying metadata; adjust a read voltage of the target page from a preset read voltage to a target read voltage according to the first voltage adjustment parameter and the second voltage adjustment parameter; and perform the complete data read operation on the page according to the target read voltage, wherein the complete data read operation is performed without a historical read failure occurring for the target page.

[0011] By the above-mentioned "voltage pre-correction" mechanism, the threshold voltage drift caused by long-term slow-changing factors and read fast-changing factors is actively and cooperatively compensated before the complete data read operation is performed, so as to strive for the first read to be successful, thereby avoiding entering the high-delay re-read process. Compared with the traditional method, the present application can significantly reduce the average read delay and tail delay, improve the first read success rate of data, and reduce unnecessary re-reading operation and system overhead.

[0012] This improvement is particularly suitable for the field of automotive electronics and autonomous driving, and can effectively guarantee the integrity, timeliness and reliability of data, while reducing system delay and meeting functional safety requirements.

[0013] In order to make the above-mentioned purposes, technical solutions and beneficial effects of the present application more obvious and easy to understand, the following embodiments are described in detail below, and the accompanying drawings are described as follows. The technical features and terms used in all embodiments are consistent with the claims. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present application;

[0015] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present application;

[0016] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present application;

[0017] Figure 4 is a schematic diagram of a memory module zone block according to an embodiment of the present application;

[0018] Figure 5 is a schematic diagram of multiple write voltage levels and multiple critical voltages in a page according to an embodiment of the present application;

[0019] Figure 6 is a flowchart of a memory management method according to an embodiment of the present application;

[0020] Figure 7 is a flowchart of querying a multi-dimensional lookup table and combining an interpolation algorithm to obtain ΔV_slow according to an embodiment of the present application;

[0021] Figure 8 is a dynamic compensation flowchart based on metadata threshold according to an embodiment of the present application;

[0022] Figure 9 is a voltage adjustment template schematic diagram of applying voltage adjustment parameters to multiple read voltage levels according to an embodiment of the present application;

[0023] Figure 10 is a flowchart illustrating an optimized re-read procedure according to an embodiment of the present application;

[0024] Figure 11 is a flowchart illustrating a delay optimization method according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0026] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present application. Please refer to Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 is connectable to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (e.g., a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0027] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Thus, the storage device 12 can communicate (e.g., exchange signals, instructions, and / or data) with the host system 11 via the connection interface 121.

[0028] The memory module 122 is used to store data. For example, the memory module 122 can include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module can include one or more arrays of memory cells. A memory cell in an array of memory cells stores data in the form of a voltage, also referred to as a threshold voltage. For example, the memory module 122 can include a Single Level Cell (SLC) NAND-type flash memory module, a Multi Level Cell (MLC) NAND-type flash memory module, a Triple Level Cell (TLC) NAND-type flash memory module, a Quad Level Cell (QLC) NAND-type flash memory module, and / or other memory modules having the same or similar characteristics.

[0029] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered as a control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 can include a Central Processing Unit (CPU), or other programmable general purpose or special purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), or other similar devices, or a combination of such devices. In an embodiment, the memory controller 123 can include a flash memory controller.

[0030] The memory controller 123 can send a sequence of instructions to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a sequence of write instructions to the memory module 122 to instruct the memory module 122 to store data into specific memory cells. For example, the memory controller 123 can send a sequence of read instructions to the memory module 122 to instruct the memory module 122 to read data from specific memory cells. For example, the memory controller 123 can send a sequence of erase instructions to the memory module 122 to instruct the memory module 122 to erase data stored in specific memory cells. In addition, the memory controller 123 can send other types of sequences of instructions to the memory module 122 to instruct the memory module 122 to perform other types of operations, without limitation. The memory module 122 can receive the sequences of instructions from the memory controller 123 and access the memory cells within the memory module 122 according to the sequences of instructions.

[0031] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present application. Referring to FIG. 1, a memory controller 123 is shown. The memory controller 123 can be used to control or manage the operation of a memory module 122. For example, the memory controller 123 can communicate with a host system 11 through a connection interface 121 and access the memory module 122 through a memory interface 122. Figure 1 Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0032] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0033] In an embodiment, the memory controller 123 can further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to buffer data. For example, the buffer memory 24 can be used to buffer instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0034] ​In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited in this application.

[0035] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply to the storage device 10.

[0036] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of this application. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0037] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, an entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0038] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited thereto.

[0039] In one embodiment, a physical program unit is a minimum unit of data that is written synchronously in the memory module 122. For example, when a program operation (also referred to as a write operation) is performed on a physical program unit to write data to the physical program unit, multiple memory cells in the physical program unit can be programmed synchronously to store corresponding data. For example, when a physical program unit is programmed, a write voltage can be applied to the physical program unit to change threshold voltages of at least some memory cells in the physical program unit. For example, a threshold voltage of a memory cell can reflect a bit of data stored in the memory cell.

[0040] In one embodiment, a physical erase unit can include multiple physical program units. In one embodiment, a physical erase unit can be considered as a physical block.

[0041] In one embodiment, multiple physical program units in a physical erase unit can be programmed synchronously. For example, when a program operation is performed on a physical erase unit, a program voltage can be applied to multiple physical program units in the physical erase unit to change threshold voltages of at least some memory cells in the physical program units. By performing a program operation on a physical erase unit, data stored in the physical erase unit can be erased.

[0042] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the free area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the free area 32 all do not store data (e.g., valid data).

[0043] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated to the free area 32. In addition, a physical unit in the free area 32 can be erased to clear data in the physical unit. In one embodiment, a physical unit in the free area 32 is also referred to as a free physical unit. In one embodiment, the free area 32 is also referred to as a free pool.

[0044] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0045] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1) to 302(C) to map physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0046] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0047] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-physical mapping table).

[0048] Figure 4 This is a schematic diagram of a physical unit (block) 400 in a memory module 122 according to an embodiment of this application, wherein the memory module 122 is a three-dimensional NAND flash memory. Figure 4 As shown, the physical cell 400 includes multiple memory cells (such as the floating gate transistor 402 shown or other charge trap elements), which form a three-dimensional NAND memory architecture through multiple bit lines (only BL1 to BL3 are shown in the figure) and multiple word lines (such as WL0 to WL2, WL4 to WL6 shown in the figure). Figure 4For example, in the uppermost plane, all the floating gates on the word line WL0 form at least one data page, all the floating gates on the word line WL1 form another at least one data page, and all the floating gates on the word line WL2 form yet another at least one data page, and so on. In addition, the definition of the word line WL0 and the data page (logical data page) can be different depending on the writing mode of the memory module 122. In detail, when writing in a single-level cell (SLC) mode, all the floating gates on the word line WL0 correspond to a single data page; when writing in a multi-level cell (MLC) mode, all the floating gates on the word line WL0 correspond to two data pages; when writing in a triple-level cell (TLC) mode, all the floating gates on the word line WL0 correspond to three data pages; and when writing in a quad-level cell (QLC) mode, all the floating gates on the word line WL0 correspond to four data pages.

[0049] Figure 5 A diagram of multiple writing voltage levels L1-L8 and multiple reading voltages Vt1-Vt7 using a triple-level storage block as the block 400, where the reading voltages Vt1-Vt7 can also be referred to as threshold voltages. As shown in FIG. 4, the writing voltage levels L1-L8 are applied to the word line WL0, and the reading voltages Vt1-Vt7 are applied to the word line WL1. Figure 5As shown, each floating gate transistor 402 can be programmed to have a voltage level LI (i.e., (MSB, CSB, LSB) = (1, 1, 1)), a voltage level L2 (i.e., (MSB, CSB, LSB) = (1, 1, 0)), a voltage level L3 (i.e., (MSB, CSB, LSB) = (1, 0, 0)), a voltage level L4 (i.e., (MSB, CSB, LSB) = (0, 0, 0)), a voltage level L5 (i.e., (MSB, CSB, LSB) = (0, 1, 0)), a voltage level L6 (i.e., (MSB, CSB, LSB) = (0, 1, 1)), a voltage level L7 (i.e., (MSB, CSB, LSB) = (0, 0, 1)), or a voltage level L8 (i.e., (MSB, CSB, LSB) = (1, 0, 1)). When the memory control circuit 23 needs to read the least significant bit (LSB) in the floating gate transistor 402, the memory control circuit 23 uses the read voltage Vtl, Vt5 to read the floating gate transistor 402 and generates a "1" or a "0" according to the on / off state (whether current is generated) of the floating gate transistor 402. Similarly, when the memory control circuit 23 needs to read the middle significant bit (CSB) in the floating gate transistor 402, the memory control circuit 23 uses the read voltage Vt2, Vt4 and Vt6 to read the floating gate transistor 402 and generates a "1" or a "0" according to the on / off state (whether current is generated) of the floating gate transistor 402 for decoding by the error checking and correction circuit 25. Similarly, when the memory control circuit 23 needs to read the most significant bit (MSB) in the floating gate transistor 402, the memory control circuit 23 uses the read voltage Vt3 and Vt7 to read the floating gate transistor 402 and judges whether the most significant bit is a "1" or a "0" according to the on / off state (whether current is generated) of the floating gate transistor 402 for decoding by the error checking and correction circuit 25. In this embodiment, the floating gate transistor 402 having the voltage level LI can be referred to as having an erase state, and the floating gate transistor 402 having any one of the voltage levels L2-L8 can be referred to as having a program state.

[0050] It is noted that, Figure 5 The example shown is only used to illustrate the process of reading the floating gate transistor 402 by the memory control circuit 23, and the implementation is not limited to the present application. Specifically, the above-mentioned least significant bit, middle significant bit and most significant bit can have different encoding manners, and the memory control circuit 23 can additionally use additional auxiliary voltages to read the floating gate transistor 402 to provide more information to the error checking and correction circuit 25 for decoding.

[0051] Because the memory module 122 can cause the write voltage levels L1~L8 to drift due to data retention, write state, environmental factors, and the like, and the original read voltages Vt1~Vt7 cannot correctly read the flash memory module 122, the manufacturer of the memory module 122 usually provides multiple read retry tables, each of which records at least one read voltage, and any two read voltages are not the same. The memory control circuit 23 can load the read retry table into the buffer memory 24 at startup to control the flash memory module 122 to use different read voltages Vt1~Vt7 to read the flash memory module 122 to obtain data that is better in quality and can be successfully decoded. However, this kind of re-reading mechanism belongs to a passive retry method.

[0052] The re-reading process of the passive retry method needs to go back and forth to the memory interface 22 multiple times, and each retry involves a complete command-address-data transmission cycle, which will lengthen the read delay in the worst case, affect the user experience (such as application startup lag, I / O response jitter, etc.), that is, there is a high tail latency. In addition, each retry occupies the channel bandwidth of the memory module 122 and repeatedly consumes hardware resources such as error checking and correction circuit 25, which reduces the overall I / O throughput, especially exacerbates system bottlenecks under high load, that is, causes bandwidth and resource waste. In addition to this, the existing read table is usually a static, discrete voltage offset set, which cannot dynamically distinguish the causes of threshold voltage drift (such as long-term aging VS. short-term noise), and also lacks judgment of the current page, resulting in insufficient or excessive correction, that is, the correction granularity is rough.

[0053] To solve the above problems, the present application provides a read voltage pre-correction mechanism, the core of which is to change the retry logic from “after-response” to “before-prediction”. This mechanism actively acquires and comprehensively analyzes slow-varying metadata reflecting the long-term health of the storage and fast-varying metadata reflecting instantaneous interference, and calculates the optimal or nearly optimal target read voltage before performing the first complete data read operation, striving for first-time read success, thereby avoiding or significantly reducing passive re-reading operations with high delay and high overhead.

[0054] To implement the above voltage pre-correction, the present application provides a specific embodiment, the core process of which is as shown in Figure 6 Figure 6 ​is a flowchart of a memory management method according to embodiments of the present application. Upon receiving a read command for a data storage page (target page), instead of performing a full first read immediately, the memory control circuit 23 enters a pre-correction procedure. The read command can be initiated by the host system 11 or automatically generated by data management and / or data migration operations (e.g. garbage collection, wear leveling) performed internally by the storage device 12. Also, the read command is used to indicate that the data belonging to a specific logical unit (also referred to as a first logical unit) is to be read. The first logical unit is mapped to a first physical unit (target page) by a logical-to-physical address mapping table.

[0055] Step 601: Before performing a full data read operation in response to the read command for the target page, the memory control circuit 23 first performs a pre-correction gating decision to determine whether a refined voltage pre-correction is needed. In an embodiment, a low-overhead quick evaluation procedure is introduced as a means to implement the gating decision to avoid performing full pre-correction calculation for all pages, thereby optimizing the average read latency.

[0056] Specifically, the quick evaluation procedure includes performing a pre-read operation on the target page using a default read voltage Vread, which reads only a small portion of data (e.g. the first Cache Line, 512 bytes or 1 KB in size) of the target page instead of the full page. Subsequently, the error checking and correction circuit 25 performs a quick quality evaluation on the pre-read portion of data. The quality evaluation includes calculating and comparing the weight of the ECC syndrome (i.e. the number of "1"s in the syndrome) of the portion of data. When the syndrome weight is less than a pre-determined enable threshold, it indicates that the data quality read using the default read voltage is already good enough, and the full read success rate is expected to be high. If the quality evaluation result is better than the enable threshold, it is determined that the target page is in good health, and the subsequent metadata acquisition and voltage calculation steps (steps 602-604) are skipped, and the full data read operation is performed using the default read voltage Vread directly in step 605. By this gating mechanism, pages in good health can be quickly filtered out, and their read requests can be completed with lower latency, which helps to reduce the overall average read latency and calculation overhead of the storage device.

[0057] If the quick quality evaluation result is worse than the enable threshold, it is determined that the voltage pre-correction operation needs to be enabled, and the flow enters the phase of acquiring the slow and fast variable metadata of the target page and performing voltage calculation based on the slow and fast variable metadata.

[0058] Step S602: Acquire the first voltage adjustment parameter (AV_slow) based on the slow variable metadata. In a specific embodiment, the first voltage adjustment parameter is obtained by querying a multi-dimensional lookup table and performing interpolation calculation based on multiple parameters in the slow variable metadata.Figure 10 .

[0059] Step S603: Obtain a second voltage adjustment parameter (ΔV_fast) according to the fast-varying metadata. In one embodiment, ΔV_fast is obtained by comparing the value of the fast-varying metadata with a threshold dynamically calculated based on the number of program / erase cycles of the block to which the target page belongs.

[0060] In one embodiment, to minimize latency, a parallel processing method is adopted, i.e., steps S602 and 603 are executed in parallel. The purpose is to hide the calculation processes of ΔV_slow and ΔV_fast within the inherent access latency required for reading partial data of the target page (for gated judgment and fast evaluation of S601) or preparing to read full-page data from the memory module 122, which ensures that the pre-correction mechanism does not increase the read latency.

[0061] Step 604: The memory control circuit 23 adjusts the read voltage of the target page from a preset read voltage (Vread) to a target read voltage (Vread') according to the obtained ΔV_slow and ΔV_fast.

[0062] In one embodiment, the synthesis can be linear superposition: Vread' = Vread + ΔV_slow + ΔV_fast, Equation 1.

[0063] In one embodiment, to improve correction accuracy, especially when both ΔV_slow and ΔV_fast are large and there may be nonlinear coupling, the following nonlinear synthesis formula can be used:

[0064] Vread' = Vread + ΔV_slow + ΔV_fast + γ × ΔV_slow × ΔV_fast, Equation 2;

[0065] where γ is a coupling coefficient (first coupling coefficient or parameter coupling coefficient), which is a scalar parameter obtained through offline testing or online learning, used to represent the nonlinear interaction strength between the first voltage adjustment parameter and the second voltage adjustment parameter. Through this synthesis, an optimized read voltage that integrates long-term trends and instantaneous disturbances is obtained.

[0066] Step 605: Memory control circuit 23 performs a full data read operation on the target page using the target read voltage Vread’ obtained from the above-mentioned pre-correction, reads and transfers the full page data to buffer memory 24, and then decodes it by error checking and correction circuit 25. The core of this step is that this full data read operation is actively and proactively performed using the optimized voltage before any read failure occurs for the target page, thereby fundamentally avoiding the high tail latency problem caused by the traditional "first read - failure - re-read" process.

[0067] Step 606: In response to the completion of the read operation, whether the read is successful or not, memory control circuit 23 updates the relevant metadata. For example, the read disturbance count corresponding to the page in buffer memory 24 is incremented by one. If the read is successful, the process ends; if the read fails, the optimized re-read process (see the description of the following Figure 7 ) is entered.

[0068] Further, in an embodiment, the above-mentioned pre-correction gating judgment (S601) can also be simplified based directly on the metadata state. For example, if the program / erase count in the slow-varying metadata is below a preset health threshold (indicating that the block is very new), and the read disturbance count parameter in the fast-varying metadata is zero, it can be directly determined that the state of the target page is excellent, the pre-correction calculation of steps 602-604 is skipped, and the preset read voltage is directly used for reading. This fast gating based on metadata can further save resources, and is especially suitable for brand new or lightly used storage devices.

[0069] Thus, through the synergistic effect of the above-mentioned baseline correction based on slow-varying metadata and dynamic fine-tuning based on fast-varying metadata, and by setting gating at the entrance of the process, the voltage pre-correction mechanism of the present application realizes "double predictive correction" of the read voltage. This mechanism can not only cope with the progressive aging of the storage unit, but also respond agilely to changes in the real-time operating environment, thereby significantly improving the first read success rate, reducing the average latency and tail latency, and improving the overall performance of the storage device.

[0070] In an embodiment, to implement the above-mentioned voltage pre-correction, a scheme for managing and utilizing metadata (Meta-Data) is proposed to build the data basis of the pre-correction scheme. Specifically, memory control circuit 23 is configured to manage and maintain metadata corresponding to each physical unit (including blocks, word lines, and pages) in memory module 122, and to manage them by explicitly distinguishing them into slow-varying metadata and fast-varying metadata. This differentiated management mechanism provides a data basis for subsequent differentiated voltage compensation for long-term drift and instantaneous disturbance.

[0071] In an embodiment, slow-varying metadata: changes slowly, reflecting long-term health and intrinsic characteristics of the storage cell, typically changing significantly over hours, days, or even longer periods. It can include at least one of: program / erase count (P / E cycle), data retention, cell type, process variation parameters, word line position sensitive parameters, and historical average bit error rate (HBER). Such data is suitable as a long-term, stable basis for read voltage adjustment.

[0072] wherein, cell type: SLC / MLC / TLC / QLC / PLC. Process variation parameters: differences in electrical characteristics between dies at different locations on the same wafer due to minor process variations. Word line position sensitive parameters: in 3D NAND, due to the vertical stacking of the manufacturing process, word lines at different physical heights have systematic differences in electrical characteristics. Historical average bit error rate: average bit error rate (HBER, Historical Bit Error Rate) obtained statistically over a longer period of time or after a large number of P / E.

[0073] In an embodiment, fast-varying metadata: changes rapidly, reflecting instantaneous state and disturbances caused by current or recent operations, possibly changing significantly in a single intensive read or write operation. It includes at least one of: read disturb count, write disturb count, real-time temperature, temperature history, recent error rate, error distribution map, number of decoding iterations, and read interval statistics. Such data is suitable as an instantaneous basis for real-time, dynamic fine-tuning of the base voltage.

[0074] wherein, read disturb count (RDC, Read Disturb Count), reflecting the number of times the page's belonging block has been read. Write disturb count: reflecting the cumulative disturbance caused by programming operations on neighboring cells. Real-time temperature: current temperature of the memory module obtained through temperature sensors. Temperature history: reflecting temperature data (such as average temperature, peak temperature, high temperature duration) experienced by the memory module during operation or storage. Recent error rate: instantaneous bit error rate obtained statistically in the last few read operations. Error distribution map: recording the physical location distribution of error bits within the page, word line, or block in a read operation; analyzing whether the errors are randomly distributed or concentrated in a specific area (e.g., a certain word line). Number of decoding iterations: the number of data exchanges required for successful decoding when the error checking and correction circuit 25 performs error correction. The more decoding iterations, the more serious the data error, and the higher the decompression delay and power consumption. Read interval statistics: statistics of the time interval between two read operations on the same page data.

[0075] The core purpose of such classification management is to avoid under-correction or over-correction caused by a single metadata source. For example, relying solely on slow-varying metadata (such as P / E Cycle) can fail to capture voltage shifts caused by consecutive reads in a short period of time (fast-varying factor); conversely, relying solely on fast-varying metadata (such as RDC) can ignore reference voltage drifts caused by long-term aging (slow-varying factor). Only through joint analysis and compensation of both can accurate voltage compensation and pre-correction covering the entire life cycle of the storage device be achieved.

[0076] In an embodiment, the first copy of the slow-varying metadata and the fast-varying metadata is maintained in the buffer memory 24 and is updated periodically (e.g., by a background patrol task every 24 hours) or based on certain events (such as the number of program / erase reaching a certain threshold). The second copy is stored in the memory module 122. In order to ensure the timeliness of the metadata while minimizing the write operations to the memory module (to reduce write amplification), a lazy update method is also used to manage the consistency of the first copy and the second copy of the metadata.

[0077] The lazy update method includes copy storage, update triggering, and consistency and reliability maintenance.

[0078] Specifically, the first copy (hot data) of the slow-varying metadata and the fast-varying metadata is maintained in the buffer memory 24 to ensure high-speed access. The second copy (cold data) is stored in the system area or the spare area of the corresponding page of the memory module 122 in a more reliable mode (e.g., SLC mode).

[0079] Regarding the update triggering, a "dirty bit" flag is associated with each metadata item. When the metadata in the buffer memory 24 (especially the fast-varying metadata such as RDC, which is frequently updated) is modified, the corresponding dirty bit is set. In detail, the triggering conditions of the lazy update method include but are not limited to: the cumulative increment of the fast-varying metadata (e.g., read disturbance count) of a certain block (page) reaching a preset threshold (e.g., cumulative increase of 1000 times); or the storage device 12 entering an idle state; or the storage device 12 performing a background management task (e.g., background garbage collection, patrol task start).

[0080] Regarding consistency and reliability, in response to the above triggering conditions, the memory control circuit 23 only writes back the first copy of the metadata marked "dirty" to the memory module 122 in batches, updating the corresponding second copy. At the same time, version numbers or CRC checks can be used to ensure the consistency of the data during the write-back process. This method significantly reduces unnecessary write operations, reduces write amplification, prolongs the life of the storage device, while ensuring the safety and access efficiency of critical metadata, and is suitable for storage devices of UFS and SSD with strict write life requirements.

[0081] In one embodiment, the memory control circuit 23 executes a pre-correction scheme based on the aforementioned metadata management scheme. This scheme is implemented through a hierarchical model consisting of two serial, two-stage correction operations: a slow correction operation and a fast correction operation. The slow correction operation is executed first, using slowly changing metadata to determine a relatively stable base voltage offset; the fast correction operation is executed subsequently, using rapidly changing metadata to perform fine-grained dynamic compensation on this basis. Finally, a high-precision target read voltage is synthesized.

[0082] In one embodiment, the slow correction operation is designed to compensate for the drift in the center of the threshold voltage distribution caused by long-term, gradual factors such as programming / erasing wear and data storage duration, and its output is a first voltage adjustment parameter (ΔV_slow). This parameter serves as a long-term, stable reference for voltage adjustment.

[0083] like Figure 7 As shown, Figure 8 This is a flowchart illustrating a Multi-Dimensional Look-Up Table (MD-LUT) and its query mechanism as an example.

[0084] To balance storage overhead and query accuracy, this multi-dimensional lookup table employs a hierarchical compressed table structure. The table's data structure includes: Base Table: Stores base voltage bias values ​​at the block level, representing a typical combination of slowly varying metadata for that block (e.g., a specific P / E cycle range and average retention). This table is relatively small. Delta Table: Stores the difference (DeltaValue) of each word line relative to the base value of its corresponding block, at the word line level. This compensates for systematic electrical differences in word lines of different physical heights caused by manufacturing processes within the 3D memory module. Special Table: Sparsely stores correction values ​​for individual pages requiring special adjustments, such as those used to mark and compensate for known weak pages discovered through testing or online learning.

[0085] When ΔV_slow needs to be calculated, the memory control circuit 23 constructs a query vector from the slow-changing metadata of the current target page (e.g., containing an index of programming / erase counts, a data storage duration index, a word line position index, etc.). The query and calculation process includes:

[0086] Step S701: Based on the block number and the approximate metadata range, find the corresponding reference voltage bias value in the base table.

[0087] Step S702: Obtain the voltage offset specific to the word line from the delta table according to the word line position.

[0088] Step S703: Query the correction table to check if there is a special correction value for the page.

[0089] Step S704: Since the actual metadata parameter value combination is a continuous value, and the lookup table index is discrete, interpolation calculation is needed. For example, the Trilinear Interpolation algorithm is used. According to the examples of the template query vector and multiple adjacent grid points in the MD-LUT in each dimension, a set of interpolation weights is calculated, and then the multiple adjacent voltage values obtained in steps S701-S703 are weighted and summed to obtain the final ΔV_slow. This process is used to explain the "interpolation calculation based on multiple parameters".

[0090] For example, the first voltage adjustment parameter can be calculated by the following schematic formula:

[0091] Formula three;

[0092] Where w_i is the distance-based trilinear interpolation weight, LUT(P_i) is the voltage offset value stored by the lookup table at grid point P_i, β is the real-time temperature compensation coefficient, T_current is the real-time temperature, and T_ref is the reference temperature. It can be understood that the above formula is only an exemplary implementation, and other interpolation algorithms or calculation models can also be used.

[0093] In an embodiment, to reduce the calculation overhead, formula three can be simplified as:

[0094] Formula four;

[0095] In an embodiment, the above MD-LUT itself can also be dynamically updated by an online learning process (to be described later) to adapt to individual differences of the memory and characteristic drifts in the life cycle. When updating, the Copy-on-Write and atomic switching techniques are used to ensure that the performance of the foreground reading operation is not affected by the background update activity.

[0096] In an embodiment, the fast correction operation aims to compensate for the rapid voltage disturbance caused by transient operation interference and environmental changes, and its output is the second voltage adjustment parameter (ΔV_fast). The present application provides multiple optional implementation methods, including a dynamic threshold-based comparison method, a heuristic read and quality evaluation-based method, and a confidence weighting-based fusion method.

[0097] In one embodiment, a dynamic threshold based comparison method for obtaining AV_fast from fast-varying metadata is proposed. It includes: dynamically calculating a read disturb threshold according to the program / erase (P / E) cycle in slow-varying metadata; comparing the read disturb count in fast-varying metadata with the read disturb threshold; and in response to the read disturb count being greater than the read disturb threshold, calculating AV_fast according to the difference between the read disturb count and the read disturb threshold. And the step of calculating AV_fast according to the difference further includes: multiplying the difference by a read disturb sensitivity coefficient to obtain AV_fast, wherein the numerical value or sign of the read disturb sensitivity coefficient depends on the cell type in the slow-varying metadata.

[0098] Specifically, the dynamic threshold based comparison method is shown as Figure 8 Figure 9 A dynamic compensation flowchart based on metadata threshold is shown in one embodiment. The core of this method is to dynamically adjust the compensation trigger threshold of fast-varying factors (such as RDC) using slow-varying metadata (such as P / E Cycle), realizing the cross coordination of slow-varying and fast-varying factors. Specifically, it includes:

[0099] Step S801: Real-time calculation of read disturb threshold (Threshold_RD) according to the P / E Cycle value of the block to which the target page belongs in the slow-varying metadata. For example:

[0100] Threshold_RD = Base_Threshold + a * P / E Cycle, formula five. Wherein, Base_Threshold is a basic threshold (for example, 3000 times), and a is a negative coefficient, meaning that as the P / E Cycle increases, the RDC threshold triggering compensation decreases, reflecting the characteristics of aging cells being more sensitive to read disturb, so the RDC threshold triggering compensation needs to be lowered to adjust the voltage earlier.

[0101] Step S802: Read the read disturb count (RDC) in the fast-varying metadata and compare it with Threshold_RD.

[0102] Step S803: If RDC > Threshold_RD, calculate the difference Delta.

[0103] ​Delta = RDC - Threshold_RD. Further, AV_fast = K x Delta is calculated. Where K is a read disturb sensitivity coefficient, the value and sign of K depends on the cell type in the slow varying metadata. For example, for more sensitive QLC / PLC cells, K can be a larger negative value (e.g. -0.01 mV / instance) indicating that the read voltage needs to be lowered; for SLC cells, K can be a smaller negative value or zero. K can be fitted from off-line post-silicon characterization.

[0104] In an embodiment, a heuristic read and quality assessment based method for obtaining AV_fast from fast varying metadata is proposed. It includes: reading a first portion of data of a target page using a pre-set read voltage and at least one heuristic read voltage; performing quality assessment on the first portion of data read using different read voltages; and determining AV_fast based on the quality assessment results. The quality assessment includes calculating and comparing the syndrome weights of the read data corresponding to the pre-set read voltage and the heuristic read voltage respectively.

[0105] Specifically, the heuristic read and quality assessment based method does not rely on historical metadata prediction, but directly "measures" the optimal voltage offset through a fast hardware heuristic once, belonging to a real-time feedback mechanism.

[0106] Step 901: Memory control circuit 23 sends a special probe read command sequence to memory module 122. The command instructs the memory module to first read a first portion of data (e.g. the first Cache Line, size 512 bytes or 1 KB) of a target page using a pre-set read voltage Vread and return; then immediately read the same portion of data again using a heuristic voltage Vread + AV_test (e.g. AV_test = +50 mV) and return.

[0107] Step 902: After receiving the two portions of data, error check and correction circuit 25 performs fast quality assessment. For example, the syndrome weights of the two portions of data are calculated and compared. The smaller the syndrome weight, the smaller the data error, and the more optimal the corresponding read voltage.

[0108] Step 903: If the data syndrome weight corresponding to the heuristic voltage is smaller, then AV_fast = AV_test; otherwise, AV_fast = 0. This method is direct and accurate, and is particularly suitable for scenarios where metadata has not yet been established or sudden environmental changes (such as sudden temperature changes) have occurred.

[0109] In an embodiment, a confidence-weighted fusion method for obtaining ΔV_fast is proposed, which includes: performing at least two methods for obtaining ΔV_fast in parallel to obtain at least two preliminary voltage adjustment parameters; assigning a confidence to each preliminary voltage adjustment parameter; and performing weighted fusion on the at least two preliminary voltage adjustment parameters to obtain ΔV_fast, wherein the weight is the corresponding confidence.

[0110] Specifically, the confidence-weighted fusion method is used to improve the robustness of fast correction by performing the above two or more fast correction methods in parallel and performing weighted fusion on the results. Specifically, the calculation process based on the dynamic threshold and the process based on the trial reading are started at the same time to obtain at least two preliminary voltage adjustment parameters (such as ΔV_fast_threshold and ΔV_fast_read). A confidence (Confidence) is assigned to each preliminary voltage adjustment parameter. For example, the confidence based on the threshold can be determined according to the difference size of RDC-Threshold_RD and the historical accuracy rate; the confidence based on the trial reading can be determined according to the difference size of the weight of the two read check codes. The final ΔV_fast=W1×ΔV_fast_threshold+W2×ΔV_fast_read, wherein W1 and W2 are normalized confidence weights (W1+W2=1). This fusion method combines the prediction advantage of historical statistics and the accuracy advantage of real-time measurement, and can effectively cope with complex and variable actual working scenarios. It can avoid the potential blind area or error of a single method, and can improve the reliability of the fast correction result.

[0111] In an embodiment, a dynamic granularity decision mechanism is used to balance the calculation overhead and accuracy. It dynamically selects the metadata granularity level and the calculation complexity according to the real-time working load characteristics, the block health status and the storage device resource situation.

[0112] The decision is based on the comprehensive criticality score (Criticality_Score):

[0113] C_S==0.4RBER_Norm+0.3ReadDisturb_Norm +0.2×Data_Importance + 0.1×Temp_Norm, Equation Six;

[0114] When the score is lower than 1.5, the block-level granularity is used; when it is between 1.5 and 3.0, the word line-level granularity is used, and when it is higher than 3.0, the page-level granularity is used. In the ultra-high IOPS scenario (such as >100K IOPS) or when the IOPS exceeds the threshold, it is automatically reduced to the block-level granularity to control the calculation delay.

[0115] For MLC / TLC / QLC and other multi-level memory cells, the threshold voltage distribution contains multiple states (State) and there is coupling between adjacent states. Simply applying the same offset to all read reference voltages can not be accurate enough. To this end, in an embodiment, it is also proposed to select a target voltage adjustment template from a plurality of voltage adjustment templates according to the slow and fast variable metadata, wherein each voltage adjustment template defines how to apply voltage adjustment parameters to a plurality of read voltage levels; and adjust the plurality of read voltage levels of the target page according to the target voltage adjustment template, ΔV_slow and ΔV_fast.

[0116] Specifically, the memory control circuit selects a target template from a plurality of predefined voltage adjustment templates according to the dominant failure mechanism inferred from the slow and fast variable metadata. As shown in Figure 9 Figure 5 The voltage adjustment template shown in an embodiment for applying voltage adjustment parameters to a plurality of read voltage levels. By identifying the potential dominant physical mechanism that causes threshold voltage drift, different voltage adjustment templates are selected to achieve accurate compensation of the entire threshold voltage distribution pattern.

[0117] Specifically, the first adjustment template (overall offset template): when the data storage time is long and the read disturbance count is low, it is determined that the dominant factor is charge leakage, and the same positive offset is applied to all read voltage levels.

[0118] Specifically, the second adjustment template (disturbance supplement template): when the read disturbance count is very high, a same negative voltage offset is applied to all read voltages.

[0119] Specifically, the third adjustment template (distribution widening template): when the number of programming / erasing is very large, it indicates that the cell is severely aged, and an asymmetric adjustment is adopted to apply different direction and size of offset to different levels to compensate for the distribution widening and distortion. For example, it can increase the voltage difference between V1 and V3 while keeping V2 unchanged, or apply different size or direction of offset to different voltage levels.

[0120] In an embodiment, when the target template is applied and the target page is a multi-level memory cell, adjusting the plurality of read voltage levels of the target page according to the target voltage adjustment template, ΔV_slow and ΔV_fast includes: obtaining an inter-level coupling coefficient between the plurality of read voltage levels; generating a set of coordinated adjustment parameters for the plurality of read voltage levels according to the inter-level coupling coefficient, ΔV_slow and ΔV_fast; and synchronously adjusting the plurality of read voltage levels according to the set of coordinated adjustment parameters.

[0121] ​In particular, a matrix of inter-gear coupling coefficients is obtained. This matrix describes the amount of compensation needed for the jth read voltage to maintain the optimal BER when adjusting the ith read voltage. This matrix is obtained through off-line testing or on-line learning. Then, based on the preliminary calculated AV_slow and AV_fast (or the base offset vector specified by the template), a set of coordinated adjustment parameters {AV1, AV2,... AVn} for all read voltage gears is generated through a matrix operation or a look-up table, in combination with the aforementioned coupling coefficient matrix. According to this parameter set, all relevant read reference voltages applied to the memory module 122 are adjusted synchronously. For example, as shown in FIG. 3A, the 7 read voltages (Vr1-Vr7) of a TLC page are adjusted in a coordinated and consistent manner. This ensures that when compensating for a state drift, the BER of adjacent states is not worsened, achieving global optimality. Figure 10

[0122] In an embodiment, if a full data read operation based on the target read voltage fails, an optimized re-read procedure is entered, the core of which is to use the information obtained by the pre-correction process to narrow down and guide the search range of the re-read voltage, i.e. to construct a re-read voltage search window centered on the target read voltage, thereby speeding up data read / recovery. The optimized re-read procedure is shown in FIG. 3B, Figure 10 Figure 11 is a flowchart of the optimized re-read procedure according to an embodiment of the present application. The procedure includes the following steps:

[0123] Step 1001: When the first read based on the pre-correction voltage fails, instead of blindly searching for a retry in a wide default voltage range as in the conventional re-read procedure, the present embodiment constructs a search window (also referred to as a narrow-band search window, e.g. Vread' - δ, Vread' + δ) centered on the target voltage Vread' obtained by pre-correction, which is much smaller than the conventional range. The window offset δ can be dynamically calculated based on the absolute value of AV_fast and the confidence of the pre-correction process (the window is slightly larger when the confidence is low). When constructing the search window, if the historical information indicates a multi-peak distribution, the search window is expanded to Vread' - δ', Vread' + δ', where δ' = δ + AV_fast. In this way, the search window is expanded to the left and right of the target voltage Vread' by the absolute value of AV_fast. This takes advantage of the prior information on the voltage position provided by the pre-correction result, fundamentally avoiding invalid searches in the full voltage range and reducing the number of voltage points that need to be tried.

[0124] ​​​​​​​​Step 1002; to improve search efficiency, further combine the soft information (such as the distribution of log-likelihood ratio LLR) of LDPC decoding when the first reading fails. Analyze the overall drift trend of the threshold voltage distribution, and preferentially search in this direction. For example, if the LLR distribution indicates that the voltage distribution is shifted to the left, then preferentially attempt to search for voltage points lower than Vread' in the search window; otherwise, preferentially attempt to search for higher voltage points. This directional guidance based on real-time decoding feedback avoids trial and error in the wrong direction, further reducing the number of retry iterations.

[0125] Step 1003: After reading with a candidate voltage each time, instead of immediately performing full data volume LDPC decoding, first quickly calculate the syndrome weight of the read data. When the syndrome weight is significantly lower than a certain threshold (indicating that the data quality has improved substantially), trigger the full decoding process. Skipping redundant decoding of poor voltage points speeds up the process of locating the optimal read voltage.

[0126] Based on the above optimization, even if the re-reading process is entered, the delay is much lower than that of the traditional blind retry scheme, effectively improving the tail delay in the worst case.

[0127] To overcome the additional calculation and access delay that the pre-correction mechanism may introduce, the present application introduces a delay optimization method as shown in Figure 11 Figures 6 to 11 is a flowchart of the delay optimization method according to the embodiment of the present application. The purpose is to "hide" the pre-correction overhead within the inherent memory access delay through parallel processing, prefetching, and approximate calculation, etc., so as to minimize its impact on the overall read performance. This delay optimization method includes: after converting the logical address of the read instruction into the physical address of the target page, prefetching the slow and fast variable metadata in parallel; after sending the read command to the memory module, performing the calculation of ΔV_slow and ΔV_fast in parallel during the delay time of accessing the data within the memory module and transmitting the data to the memory controller; dynamically selecting different precision calculation modes for the calculation of ΔV_slow and ΔV_fast according to the real-time load of the storage device and the criticality of the target page data.

[0128] Step 1101: While performing logical to physical address conversion, trigger the prefetching operation of the slow and fast variable metadata related to the target page immediately. This converts the serial operation on the metadata access path into a parallel operation with the address conversion, ensuring that the required metadata is ready when the voltage calculation is performed, avoiding the stall caused by waiting for the metadata.

[0129] ​Step 1102: After sending the read command to the memory module 122, the calculation of ΔV_slow and ΔV_fast is performed in parallel with the data access and the inherent hardware delay time of transferring data to the memory controller 123 through the channel. When the data transfer is completed, the voltage adjustment parameters are also calculated, achieving a near "zero additional delay" pre-correction. Through this "calculation-transmission overlap" method, the calculation of the voltage adjustment parameters does not occupy additional critical path time, so that the pre-correction mechanism is realized in a "zero delay" manner. That is, the original waiting time is fully utilized to realize the overlap of calculation and transmission.

[0130] Step 1103: According to the real-time load (IOPS) of the storage device and the criticality of the data stored in the target page (such as system page / user data page storing metadata), different precision calculation modes are dynamically selected. For example, for low load or critical data, high-precision calculation (such as 32-bit floating point, full interpolation) is used, and for non-critical data or high-load scenarios, low-precision calculation (such as 8-bit table lookup and simple interpolation operation) is used. This flexible calculation method enables the storage device to allocate computing resources, control computing delay, and adapt to complex actual application scenarios while ensuring correction effect. This is particularly important for maintaining the overall performance stability of the storage device when the storage device is a UFS / SSD and needs to cope with sudden high-throughput loads.

[0131] Step 1104: For parameters that need to access sensors such as real-time temperature, under non-extreme conditions, a sliding evaluation prediction value based on historical temperature can be used, or the most recent sampling value can be directly applied, avoiding waiting for sensor response every time the data is read. This avoids the uncertainty delay introduced by frequent access to sensors, further improving the timeliness and certainty of the pre-correction process.

[0132] To make the pre-correction mechanism applicable to individual differences of memory modules and continuous changes in the life cycle, in an embodiment, a prior learning process is also proposed. It records the metadata, voltage adjustment parameters and read results in the historical pre-correction operation, and uses these data to periodically obtain the rules or models used when calculating ΔV_slow and / or ΔV_fast.

[0133] Specifically, the history pre-correction quad-tuple information is recorded continuously: slow / fast metadata input, calculated AV_slow / AV_fast, actual applied read voltage, read result (success / failure i.e. error bit count / soft information characteristic). The learning process is initiated by a background task periodically (e.g. daily) or after accumulating enough data. With the collected data, the values in MD-LUT, the coefficients (e.g. a) in dynamic threshold calculation formula, the read disturb sensitive coefficient K, the coupling coefficient g, etc. are fine-tuned and optimized by light-weight machine learning algorithms (e.g. linear regression, decision tree) or statistical methods. The updated parameters or table entries replace the old version in an atomic operation manner, ensuring no impact on the foreground business.

[0134] In addition to the above-mentioned "periodic" online learning method of accumulating a batch of historical data to update the model, in an embodiment, an "event-based" online learning method is also proposed, which evaluates the effect of each successful read operation and provides feedback. In this way, the convergence speed of the model is accelerated and the environmental adaptability is improved. The above-mentioned online learning process also includes instant fine-tuning based on a single read operation:

[0135] After successfully completing the complete data read operation on the target page according to the target read voltage, the actual decoding soft information or the final error bit count of this operation is obtained; the actual decoding soft information or the final error bit count is compared with the expected quality range; if the comparison result is out of the expected quality range, a fine-tuning amount is generated based on the comparison difference; the fine-tuning amount is used to update the specific parameters corresponding to the current read scene in the rules or models used to obtain the first voltage adjustment parameter and / or the second voltage adjustment parameter, for subsequent read voltage pre-correction of the same or similar type of page.

[0136] Specifically, in the read operation, the actual decoding soft information (such as the distribution statistics of LLR values) or the final corrected error bit count (BER) of this read is obtained from the error checking and correction circuit 25. The above-mentioned feedback signal is compared with the expected quality range (for example, the ideal BER should be close to but slightly lower than half of the error correction capability of the error checking and correction circuit 25). If the feedback signal indicates that the data quality BER is extremely low or the BER is close to the error correction limit, it means that there is still room for optimization of the current pre-correction voltage. Based on the comparison difference, a small voltage adjustment amount (fine-tuning amount) is generated. Using this fine-tuning amount, the specific parameters corresponding to the current read scene (specific programming / erase times range, specific word line position, etc.) in the rules or models used to obtain AV_slow or AV_fast are directly updated. For example, the value of a certain grid point in the MD-LUT is fine-tuned. This enables the storage device to continuously and finely calibrate itself for each unique memory module / block / page and each specific usage mode, and to maintain optimal read performance throughout the entire storage device life cycle.

[0137] When adjustment suggestions from slow-varying and fast-varying data conflict or are of different dimensions, how to safely and effectively synthesize them. Direct and simple addition can lead to over-adjustment or under-adjustment. For example, at very high real-time temperature, the weight of fast-varying metadata can be adjusted higher, because the immediate effect of temperature on threshold voltage is huge, so priority arbitration is needed. And dynamic range constraints, that is, for a block with a high number of program / erase times and a long data storage time, its threshold voltage distribution has widened, and the allowed adjustment range must be narrowed accordingly to prevent voltage adjustment to adjacent states, causing uncorrectable errors.

[0138] In an embodiment, after obtaining the first voltage adjustment parameter and the second voltage adjustment parameter, further comprising: determining a priority weight of the first voltage adjustment parameter and the second voltage adjustment parameter based on the cell type in the slow-varying metadata and the real-time temperature in the fast-varying metadata; weighting and fusing the first voltage adjustment parameter and the second voltage adjustment parameter according to the priority weight to obtain a target voltage adjustment amount; and constraining the target voltage adjustment amount within a dynamic voltage adjustment range, wherein the dynamic voltage adjustment range is determined based on the number of program / erase times and the data storage time of the block to which the target page belongs.

[0139] In such multi-level cells as TLC / QLC, adjusting a read reference voltage, for example, Vra used to distinguish Er state and A state, will directly affect the error rate of adjacent states, for example, Vrb used to distinguish A state and B state. Therefore, when adjusting the read voltage of the target page to the target read voltage, "coordinated adjustment" is needed to avoid the problem of "pushing down the gourd to float the dipper", that is, through one calculation, all related read voltages are adjusted together to ensure the lowest overall error rate, which is crucial for high-density storage media.

[0140] In an embodiment, the storage type of the target page is determined according to the cell type in the slow-varying metadata; if the storage type of the target page is single-layer storage cell, the first adjustment method is adopted. Wherein, in calculating the target read voltage, the weight of the second voltage adjustment parameter is set to zero or a very small value, and the calculation of the first voltage adjustment parameter is simplified. If the storage type of the target page is multi-layer storage cell, the second adjustment method is adopted. Wherein, the second adjustment method applies the first voltage adjustment parameter and the second voltage adjustment parameter comprehensively. This embodiment introduces scene-adaptive optimization, which adopts different complexity of read voltage adjustment methods for storage cells with different reliability and performance requirements, thereby achieving the best balance between performance and power consumption / delay.

[0141] Specifically, SLC itself is very reliable and insensitive to read disturbance, etc. Therefore, the impact of most fast-varying metadata can be ignored (the weight is set to 0), and the erase and calculation of slow-varying metadata are simplified (for example, only using the number of programming / erasing for one-dimensional lookup table), thereby greatly reducing the overhead and read delay. For MLC / TLC / QLC / PLC, which are more fragile storage units compared with SLC, a full set of complex adjustment methods are enabled.

[0142] However, Figures 6 to 11 The steps in the method have been described in detail above, and will not be repeated here. It is worth noting that, Figures 6 to 11 The steps in the method can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, ​ The method can be used in combination with the above example embodiments, or can be used alone, and the present application is not limited thereto.

[0143] In summary, the memory management method and storage device proposed in the embodiments of the present application actively and cooperatively compensate for the threshold voltage drift caused by long-term slow-varying factors and short-term fast-varying factors before the first read, thereby achieving accurate pre-correction of the read voltage. This fundamentally avoids a large number of unnecessary re-reading operations, significantly reduces the average read delay and the tail delay in the worst case, and thus comprehensively improves the data read efficiency and user experience of the storage device. Compared with the traditional passive retry mechanism, the present application is particularly suitable for application scenarios with strict requirements on delay and reliability, such as UFS / SSD storage devices using TLC / QLC / PLC high-density NAND Flash as the memory module, without significantly increasing the hardware cost. The present application provides key storage performance guarantees for the fields of automotive electronics, data centers, and high-end mobile devices.

[0144] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent replacements for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory control method, characterized in that, For a storage device, wherein the storage device includes a memory module, the memory module includes multiple blocks, each block includes multiple pages, and the memory control method includes: Before performing a full data read operation in response to a read command for the target page, obtain the slow-changing metadata and fast-changing metadata of the target page; Based on the slow-varying metadata, the first voltage adjustment parameter is obtained by querying a multi-dimensional lookup table and performing interpolation calculations based on multiple parameters in the slow-varying metadata. The second voltage adjustment parameter is obtained by comparing the value of the fast-changing metadata with a threshold dynamically calculated based on the number of programming / erasing operations of the block to which the target page belongs. The slow-varying metadata includes at least one of the following: programming / erasing count, data storage duration, cell type, process variation parameters, word line position sensitive parameters, and historical average bit error rate; The rapidly changing metadata includes at least one of the following: read interference count, write interference count, real-time temperature, temperature history, recent error rate, error distribution map, decoding iteration count, and read interval statistics. Based on the first voltage adjustment parameter and the second voltage adjustment parameter, the read voltage of the target page is adjusted from the preset read voltage to the target read voltage; The complete data read operation is performed on the target page according to the target read voltage, wherein the complete data read operation is performed without any historical read failures for the target page.

2. The memory control method according to claim 1, characterized in that, The first copy of the slow-changing metadata and the fast-changing metadata are maintained in the buffer memory of the storage device, and the second copy is stored in the memory module; as well as The method further includes: using a lazy update method to manage the consistency between the first replica and the second replica, wherein the lazy update method is triggered in response to at least one of the following conditions: the cumulative increment of the fast-changing metadata reaches a preset threshold, the storage device enters an idle state, or the storage device executes a background management task.

3. The memory control method according to claim 1, characterized in that, The multi-dimensional lookup table includes a hierarchical compressed storage structure, which includes: The base table stores the base voltage bias values ​​in blocks. An incremental table stores the differences relative to the base table at word-level granularity. The correction table stores the correction values ​​for pages that require special adjustments in a sparse manner. The interpolation calculation includes a step of weighted summation of multiple neighboring voltage values ​​obtained from the base table, incremental table, and correction table based on a query vector composed of the slow-varying metadata.

4. The memory control method according to claim 1, characterized in that, The step of obtaining the second voltage adjustment parameter based on the fast-changing data includes: The read interference threshold is dynamically calculated based on the number of programming / erasing operations in the slowly changing metadata. Compare the read interference count in the rapidly changing metadata with the read interference threshold; and In response to the read interference count being greater than the read interference threshold, the second voltage adjustment parameter is calculated based on the difference between the read interference count and the read interference threshold.

5. The memory control method according to claim 4, characterized in that, The step of calculating the second voltage adjustment parameter based on the difference includes: The difference is multiplied by a read interference sensitivity coefficient to obtain the second voltage adjustment parameter, wherein the magnitude or sign of the read interference sensitivity coefficient depends on the cell type in the slow-varying metadata.

6. The memory control method according to claim 1, characterized in that, The step of obtaining the second voltage adjustment parameter based on the fast-changing data includes: The first portion of the data in the target page is read using a preset read voltage and at least one trial read voltage, respectively. A quality assessment is performed on the first portion of data read using different read voltages; and The second voltage adjustment parameter is determined based on the quality assessment results; The amount of data in the first part is less than the total amount of data in the target page.

7. The memory control method according to claim 6, characterized in that, The quality assessment includes calculating and comparing the checksum weights of the read data corresponding to the preset read voltage and the trial read voltage, respectively.

8. The memory control method according to claim 1, characterized in that, The step of obtaining the second voltage adjustment parameter based on the fast-changing metadata includes: At least two methods for obtaining the second voltage adjustment parameter are executed in parallel to obtain at least two preliminary voltage adjustment parameters; Assign a confidence level to each of the aforementioned preliminary voltage adjustment parameters; and The at least two preliminary voltage adjustment parameters are weighted and fused to obtain the second voltage adjustment parameter, wherein the weight is the corresponding confidence level.

9. The memory control method according to claim 1, characterized in that, The step of adjusting the reading voltage to the target reading voltage based on the first voltage adjustment parameter and the second voltage adjustment parameter is calculated using the following nonlinear synthesis formula: Vread' = Vread +ΔV_slow +ΔV_fast +γ×ΔV_slow×ΔV_fast; Where Vread' is the target read voltage of the target page, Vread is the preset read voltage, ΔV_slow is the first voltage adjustment parameter, ΔV_fast is the second voltage adjustment parameter, and γ is the coupling coefficient.

10. The memory control method according to claim 1, characterized in that, Also includes: Based on the slow-changing metadata and the fast-changing metadata, a target voltage adjustment template is selected from multiple voltage adjustment templates, wherein each voltage adjustment template defines how to apply voltage adjustment parameters to multiple reading voltage levels; as well as The plurality of read voltage levels of the target page are adjusted according to the target voltage adjustment template, the first voltage adjustment parameter and the second voltage adjustment parameter.

11. The memory control method according to claim 10, characterized in that, When the target page is a multi-level storage unit, adjusting the multiple read voltage levels of the target page according to the target voltage adjustment template, the first voltage adjustment parameter, and the second voltage adjustment parameter includes: Obtain the inter-voltage coupling coefficient between the multiple reading voltage levels; Based on the coupling coefficient between the gear positions, the first voltage adjustment parameter, and the second voltage adjustment parameter, a set of coordinated adjustment parameters for the multiple reading voltage gear positions is generated; Based on the aforementioned coordinated adjustment parameter set, the multiple reading voltage levels are adjusted synchronously.

12. The memory control method according to claim 6, characterized in that, Before obtaining the slow-changing metadata and the fast-changing metadata, the following is also included: The target page is pre-read using the preset read voltage to obtain partial data and to perform a quality assessment on the partial data. If the quality assessment result is better than an activation threshold, then skip the steps of obtaining slow-changing metadata and fast-changing metadata and subsequent steps, and directly use the preset reading voltage to perform the complete data reading operation; If the quality assessment result is worse than the activation threshold, then the steps of obtaining slow-changing metadata and fast-changing metadata and subsequent steps are performed.

13. The memory control method according to claim 12, characterized in that, It also includes a latency optimization step: After converting the logical address of the read instruction into the physical address of the target page, the slow-changing metadata and fast-changing metadata are obtained in parallel. After sending a read command to the memory module, during the delay time between accessing data within the memory module and transmitting data to the memory controller, the calculation of the first voltage adjustment parameter and the second voltage adjustment parameter are performed in parallel. Based on the real-time load of the storage device and the criticality of the target page data, different precision calculation modes are dynamically selected for calculating the first voltage adjustment parameter and the second voltage adjustment parameter.

14. The memory control method according to claim 1, characterized in that, In response to the failure of the complete data read operation based on the target read voltage and the entry into the reread process, a reread voltage search window is constructed with the target read voltage as the center.

15. The memory control method according to claim 1, characterized in that, It also includes the online learning process: Record metadata, voltage adjustment parameters, and reading results from historical pre-calibration operations; The rules or models used to obtain the first voltage adjustment parameters and / or the second voltage adjustment parameters are periodically updated using these recorded data.

16. The memory control method according to claim 15, characterized in that, The online learning process also includes real-time fine-tuning based on a single read operation: After successfully completing the full data reading operation of the target page according to the target reading voltage, obtain the actual decoding soft information or the final number of error bits for this operation; Compare the actual decoded soft information or the final number of error bits with the expected quality range; If the comparison result exceeds the expected quality range, a fine-tuning amount is generated based on the comparison difference; The fine-tuning amount is used to update the specific parameters in the rule or model used to obtain the first voltage adjustment parameter and / or the second voltage adjustment parameter, corresponding to the current reading scenario.

17. The memory control method according to claim 1, characterized in that, After obtaining the first voltage adjustment parameter and the second voltage adjustment parameter, the method further includes: Based on the cell type in the slow-changing metadata and the real-time temperature in the fast-changing metadata, the priority weights of the first voltage adjustment parameter and the second voltage adjustment parameter are determined. The first voltage adjustment parameter and the second voltage adjustment parameter are weighted and fused according to the priority weight to obtain a target voltage adjustment amount; The target voltage adjustment amount is constrained within a dynamic voltage adjustment range, wherein the dynamic voltage adjustment range is determined based on the number of programming / erasing operations and the data storage duration of the block to which the target page belongs.

18. The memory control method according to claim 1, characterized in that, Also includes: The storage type of the target page is determined based on the unit type in the slow-changing metadata. If the target page is a single-level storage cell, the first adjustment method is adopted, wherein when calculating the target read voltage, the weight of the second voltage adjustment parameter is set to zero or a minimum value; If the target page is a multi-level storage cell, a second adjustment method is adopted, wherein the first voltage adjustment parameter and the second voltage adjustment parameter are fully applied.

19. A storage device, characterized in that, include: A connection interface for electrically connecting to the host system; The memory module comprises multiple blocks, and each block comprises multiple pages; as well as The memory controller is electrically connected to the connection interface and the memory module. The memory controller is configured to perform the memory control method of any one of claims 1 to 18.

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