A test circuit and memory

Abstract

This disclosure provides a test circuit and a memory. The test circuit includes an error recording circuit and a test core circuit. The error recording circuit is located in the physical interface area of ​​the memory, while the test core circuit is located in other areas of the memory. The test core circuit is used to store at least one address signal under test. The test core circuit is also used to receive an error address indication signal and output the corresponding address signal under test. The address signal under test corresponding to the error address indication signal is the error address signal. The error recording circuit is used to record the error address indication signal and also to send the error address indication signal to the test core circuit. This disclosure saves the area of ​​the physical interface area and reduces the design difficulty of the physical interface area.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a test circuit and a memory. Background Technology

[0002] High Bandwidth Memory (HBM) is a dynamic random access memory (DRAM) technology based on 3D stacking process. It provides extremely high bandwidth and energy efficiency by vertically stacking multiple DRAM chips and using through silicon via (TSV) technology to achieve high-speed interconnection.

[0003] Memory Built-in Self Test (MBIST) is a technique used to verify whether the read and write functions of memory are working properly. Its core principle is to automatically generate test vectors through embedded test logic, completing the test without the need for external devices.

[0004] Due to the large number of ubump input / output interfaces (ubump IO interfaces) on HBM, traditional high-speed testing methods are unsuitable for HBM products. Currently, programmable MBISTs are an important means of mass production testing for HBM.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] This disclosure provides a test circuit and a memory.

[0007] In a first aspect, embodiments of this disclosure provide a test circuit, including an error recording circuit and a test core circuit; the error recording circuit is located in the physical interface area of ​​the memory, and the test core circuit is located in other areas of the memory;

[0008] The core test circuit is used to store at least one address signal under test;

[0009] The core test circuit is also used to receive an error address indication signal and output the test address signal corresponding to the error address indication signal; the test address signal corresponding to the error address indication signal is an error address signal.

[0010] The error recording circuit is used to record the error address indication signal;

[0011] The error recording circuit is also used to send the error address indication signal to the test core circuit.

[0012] In some embodiments, the test core circuit is configured to receive at least one command signal and a corresponding address signal under test in sequence, generate an indication signal when the command signal is received, and store the corresponding address signal under test based on the indication signal. The indication signal is used to indicate the storage location of the address signal under test in the test core circuit.

[0013] The indication signal corresponding to the error address signal and the error address indication signal corresponding to the error address signal indicate the same storage location in the test core circuit. In some embodiments, the command signal includes a first command signal and a second command signal, the address signal under test includes at least a row address signal and a column address signal, and the test core circuit includes a first storage circuit, an indication signal generation circuit, and a second storage circuit;

[0014] The first storage circuit is configured to receive the first command signal and the corresponding row address signal, and store the row address signal;

[0015] The first storage circuit is further configured to receive the second command signal, read the stored row address signal based on the second command signal, and transmit it to the second storage circuit;

[0016] The indicator signal generation circuit is used to receive the second command signal and process the second command signal into the indicator signal according to a preset rule; the indicator signal is specifically used to indicate the storage location of the measured address signal in the second storage circuit.

[0017] The second storage circuit is configured to receive the column address signal corresponding to the second command signal, the indication signal, and the row address signal transmitted by the first storage circuit; and to store the column address signal and the row address signal at the storage location indicated by the indication signal.

[0018] In some embodiments, the preset rule is: the indicator signal is generated based on the order in which the address signal under test is stored in the test core circuit; the indicator signal generation circuit is a counter;

[0019] The counter is used to receive the second command signal, count the second command signal, and obtain the indication signal.

[0020] In some embodiments, the counting range of the counter is N, and the number of the measured address signals that the second storage circuit can store is M, where N and M are both positive integers, and N is greater than or equal to M;

[0021] The second storage circuit is further configured to receive control signals, and based on the control signals, use M consecutive values ​​from N as indication signals corresponding to the M storage units in the second storage circuit.

[0022] In some embodiments, the address signal under test further includes a first address signal; the first address signal serves as the address signal of a storage cell in the first storage circuit.

[0023] The first storage circuit is further configured to receive a first address signal corresponding to the first command signal and store the row address signal into the storage unit corresponding to the first address signal;

[0024] The first storage circuit is further configured to receive a first address signal corresponding to the second command signal and read the row address signal from the storage unit corresponding to the first address signal;

[0025] The second storage circuit is further configured to store the first address signal into the storage unit corresponding to the indication signal.

[0026] In some embodiments, the first address signal is a repository address signal.

[0027] In some embodiments, both the first storage circuit and the second storage circuit include: a write address terminal, a write data terminal, a write command terminal, a read address terminal, a read data terminal, and a read command terminal;

[0028] Both the first storage circuit and the second storage circuit are used to write the signal received by the write data terminal into the storage unit corresponding to the address signal received by the write address terminal when the write command terminal receives the corresponding command signal.

[0029] Both the first storage circuit and the second storage circuit are used to output the signal stored in the storage unit corresponding to the address signal received by the read address terminal from the read data terminal when the read command terminal receives the corresponding command signal.

[0030] In some embodiments, in the first storage circuit, the write address terminal is used to receive the first address signal corresponding to the first command signal, the write data terminal is used to receive the row address signal, the write command terminal is used to receive the first command signal, the read address terminal is used to receive the first address signal corresponding to the second command signal, the read data terminal is used to output the stored row address signal, and the read command terminal is used to receive the second command signal.

[0031] And / or, in the second storage circuit, the write address terminal is used to receive the indication signal, the write data terminal is used to receive the tested address signal, the write command terminal is used to receive the second command signal, the read address terminal is used to receive the error address indication signal, the read data terminal is used to output the stored tested address signal, and the read command terminal is used to receive the error address capture signal.

[0032] In some embodiments, the test circuit further includes a control circuit;

[0033] The control circuit is used to send the error address capture signal to the second storage circuit;

[0034] And / or, the control circuit is further configured to receive the error address signal output by the second storage circuit;

[0035] And / or, the control circuit is further configured to send an error address read command to the error recording circuit; correspondingly, the error recording circuit is configured to send the error address indication signal to the test core circuit when it receives the error address read command.

[0036] In some embodiments, the error recording circuit is further configured to record the corresponding error address indication signal according to the indication signal when the measured address signal corresponding to the indication signal is an error address signal.

[0037] In a second aspect, embodiments of this disclosure provide a memory including a test circuit as described in any of the first aspects.

[0038] In some embodiments, the memory is a high-bandwidth memory; the address signal under test includes a row address signal, a first address signal, and a column address signal, wherein the first address signal includes: chip identification number, virtual channel address, and repository address; the core test circuit includes a first storage circuit, an indicator signal generation circuit, and a second storage circuit;

[0039] The first storage circuit is configured to receive a first command signal and the corresponding row address signal, and store the row address signal;

[0040] The first storage circuit is further configured to receive a second command signal, read the stored row address signal based on the second command signal, and transmit it to the second storage circuit;

[0041] The indicator signal generation circuit is used to receive the second command signal and process the second command signal into the indicator signal according to a preset rule; the indicator signal is specifically used to indicate the storage location of the measured address signal in the second storage circuit.

[0042] The second storage circuit is configured to receive the column address signal corresponding to the second command signal, the indication signal, and the row address signal transmitted by the first storage circuit; and to store the column address signal and the row address signal at the storage location indicated by the indication signal.

[0043] This disclosure provides a test circuit and a memory. The test circuit includes an error recording circuit and a test core circuit. The error recording circuit is located in the physical interface area of ​​the memory, and the test core circuit is located in other areas of the memory. The test core circuit is used to store at least one address signal under test. The test core circuit is also used to receive an error address indication signal and output the address signal under test corresponding to the error address indication signal. The address signal under test corresponding to the error address indication signal is an error address signal. The error recording circuit is used to record the error address indication signal and also to send the error address indication signal to the test core circuit.

[0044] In this way, the core test circuit is placed in a region other than the physical interface area. The core test circuit is introduced into the memory to assist in the analysis of error addresses. The random access memory (RAM) and first-in-first-out (FIFO) circuit used to store the address signal under test in the physical interface area are removed, thereby saving valuable area in the physical interface area and reducing the design difficulty of the physical interface area. Attached Figure Description

[0045] Figure 1 A schematic diagram of a built-in self-test circuit provided in an embodiment of this disclosure;

[0046] Figure 2 A schematic diagram of a test circuit provided in an embodiment of this disclosure. Figure 1 ;

[0047] Figure 3 A schematic diagram of a test circuit provided in an embodiment of this disclosure. Figure 2 ;

[0048] Figure 4 A schematic diagram of a test core circuit provided in an embodiment of this disclosure;

[0049] Figure 5 A schematic diagram of a test circuit provided in an embodiment of this disclosure. Figure 3 . Detailed Implementation

[0050] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0052] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0053] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0054] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows:

[0055] High-bandwidth memory (HBM);

[0056] Dynamic Random Access Memory (DRAM);

[0057] Memory Built-in Self Test (MBIST);

[0058] Micro-bump input / output interface (ubump Input / Output, ubump IO interface);

[0059] Random Access Memory (RAM);

[0060] First-In-First-Out (FIFO)

[0061] MBIST core;

[0062] MBIST channel;

[0063] Base die;

[0064] Physical interface area (PHY area);

[0065] Command decoder;

[0066] Error correct memory (ECM);

[0067] Joint Electron Device Engineering Council (JEDEC)

[0068] Chip identity document (SID);

[0069] Pseudo Channel (PC);

[0070] Repository (bank);

[0071] row;

[0072] row address (ra);

[0073] The repository address (rba) where the row is located;

[0074] Column address (ca);

[0075] Microcontroller Unit (MCU);

[0076] Read with Auto-Precharge (RDA);

[0077] Write with Auto-Precharge (WRA);

[0078] D-type flip-flop (DFF);

[0079] Embedded Core Integrated Circuit Test Methodology Standard (IEEE 1500).

[0080] Due to the large number of ubump I / O interfaces in HBM (such as the third-generation HBM: HBM3), traditional high-speed testing methods are not suitable for HBM3 products. Currently, programmable MBIST is an important means of mass production testing for HBM3. It consists of two parts, the MBIST core and the MBIST channel, integrated into the HBM base chip.

[0081] like Figure 1 As shown, the MBIST channel is located in the physical interface area (PHY area), which includes a command decoder, RAM, logic circuits, FIFO circuits, data topology generation circuits, comparator circuits, and ECM.

[0082] The MIBST core can send JEDEC-compliant command signals at the highest speed that HBM3 can operate at, such as active, write, read, and precharge commands. Figure 1 As shown in path ①, the signal is transmitted to ubump (not shown in the figure) via the MBIST channel. Bist_C[7:0] and Bist_R[9:0] represent the command signals before decoding.

[0083] When the activation command `act` is sent, the MBIST channel records the row address in RAM (e.g., ...). Figure 1 As shown in path ②, the activation command `act` is passed from the write enable terminal `wenc` of RAM, enabling RAM to write to these addresses. The addresses to be written are input from the write data terminal `wdata` of RAM. The RAM itself that stores these addresses is the write address `act_rba` received by the write address terminal `waddr`. The write address `act_rba` represents the address carried by the activation command, specifically the address of the repository where the row is located, which can be composed of the SID, PC address, and bank address.

[0084] When a write command or a read command is issued, the address information is read out and placed into the FIFO circuit along with the column address ca, such as... Figure 1As shown in path ③, the write command or read command is passed from the read enable terminal renc of RAM, enabling RAM to read the stored address. The address of RAM itself, which is addressed in RAM, is the read address rd_rba received by the read address terminal raddr (taking the read command as an example). Here, rd_rba represents the address carried by the read command, which is specifically the address of the repository where the row is located. It can be composed of SID, PC address and bank address.

[0085] When WL-2 or RL-2 is used, all addresses are read together to generate the data pattern to be written or the expected data pattern to be read, such as... Figure 1 As shown in path ④, WL-2 refers to a write operation triggered by a write command, meaning the write operation is performed within a write latency minus 2 (both units are clock cycles). RL-2 refers to a read operation triggered by a read command, meaning the read operation is performed within a read latency minus 2 (both units are clock cycles). Specifically: the logic circuit generates a write operation signal (not shown in the diagram) based on the write command to trigger the write operation; the data topology generation circuit generates the data to be written and writes it to the corresponding address in the memory array; the logic circuit generates a read operation signal RD_RL_2 based on the read command, which serves as a pointer to the address read from the FIFO.

[0086] The comparator circuit compares the written data with the data read from the memory array. If they differ, an error has occurred. When an error occurs, the MBIST channel records the error address in the error recording memory (ECM). Figure 1 The path is shown in ⑤. Test engineers can obtain this information by reading the ECM for subsequent storage array repair.

[0087] This solution has at least the following problems: the PHY area is very limited; it includes a 64-bit RAM for storing address information and a 4-bit FIFO for address retrieval via RL-2. These modules consume a lot of area resources, complicating the design and timing.

[0088] Based on this, the present disclosure provides a test circuit that sets the core test circuit in other areas outside the physical interface area, introduces the core test circuit into the memory to assist in analyzing error addresses, and removes the RAM and FIFO circuits used to store the address signal under test in the physical interface area, thereby saving valuable area in the physical interface area and reducing the design difficulty of the physical interface area.

[0089] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0090] In one embodiment of this disclosure, see [link to embodiment]. Figure 2This illustrates a schematic diagram of a test circuit provided in an embodiment of the present disclosure. Figure 2 As shown, the test circuit 20 includes an error recording circuit 202 and a test core circuit 201; wherein:

[0091] The core test circuit 201 is used to store at least one address signal under test.

[0092] The core test circuit 201 is also used to receive the error address indication signal and output the test address signal corresponding to the error address indication signal; the test address signal corresponding to the error address indication signal is the error address signal.

[0093] Error recording circuit 202 is used to record error address indication signals;

[0094] The error recording circuit 202 is also used to send the error address indication signal to the test core circuit 201.

[0095] It should be noted that the test circuit 20 can specifically be an MBIST circuit applied to the memory to perform built-in self-tests. The core test circuit 201 is equivalent to the MBIST core, which can be considered a microcontroller unit (MCU). The memory can be HBM or other types of memory; taking HBM as an example, the test circuit 20 can be located in the HBM base die. Specifically, the error logging circuit 202 is located in the physical interface area (PHY area) of the HBM base die, and the core test circuit 201 is located in other areas of the HBM base die. Here, "other areas" refers to areas outside the PHY area of ​​the base die.

[0096] It should also be noted that during the built-in self-test of the memory, the address signal corresponding to each address under test in the memory array is recorded as the address signal under test. For each address tested, the test core circuit 201 records the corresponding address signal under test. If the address under test is an error address, the error recording circuit 202 records the error address indication signal corresponding to the error address. This error address indication signal can be considered an index or address, used to locate the stored error address signal in the test core circuit 201.

[0097] When it is necessary to read out the error address signal, the error recording circuit 202 sends the recorded error address indication signal to the test core circuit 201. The test core circuit 201 searches based on the error address indication signal and outputs the found test address signal (i.e., the error address signal), thereby realizing the recording and query output of the error address.

[0098] Thus, this embodiment utilizes the test core circuit 201 (MBIST core) to store the address signal under test (specifically, a RAM or other storage circuit can be set in the test core circuit 201 to store the address signal under test), instead of setting RAM and FIFO circuits in the PHY area of ​​the memory to store the address signal under test. Since the area of ​​the MBIST core is relatively ample, it will not cause a shortage of circuit area; by not setting RAM and FIFO circuits in the PHY area to store the address signal under test, the valuable area of ​​the PHY area is significantly saved. At the same time, the error recording circuit 202 only needs to record a small number of error address indication signals indicating error addresses, without occupying a large area, and even if it is set in the PHY area, it will not affect the area occupied by the PHY area.

[0099] In some embodiments, such as Figure 3 As shown, the test core circuit 201 is used to receive at least one command signal and a corresponding address signal under test in sequence. When the command signal is received, an indication signal is generated, and the corresponding address signal under test is stored based on the indication signal. The indication signal is used to indicate the storage location of the address signal under test in the test core circuit.

[0100] Among them, the indication signal corresponding to the error address signal and the error address indication signal corresponding to the error address indicate the same storage location in the test core circuit 201.

[0101] It should be noted that the command signal represents the operation performed on the address under test. Each time a command signal and its corresponding address under test are received, it indicates that a test is currently being performed on the address corresponding to that address. Therefore, each time the core test circuit 201 receives a command signal and its corresponding address under test, it stores the corresponding address under test. The storage method involves generating an indicator signal as an index or address of the storage location of the address under test, and then writing the address under test into the corresponding storage location based on the indicator signal.

[0102] It should also be noted that if the address signal under test is an error address signal, the indicator signal corresponding to the storage location of the error address signal needs to be recorded so that the error address signal can be read from the test core circuit 201 based on the indicator signal when the error address is read later.

[0103] In other words, for a certain error address signal a, assuming it is stored in storage unit A of the test core circuit 201, the indication signal generated by the test core circuit 201 for the error address signal a is indication signal 1, and the error address indication signal corresponding to the error address signal a stored in the error recording circuit 202 is error address indication signal A, then the storage location indicated by indication signal 1 and error address indication signal A in the test core circuit 201 is storage unit A.

[0104] In this embodiment of the disclosure, the indication signal corresponding to the error address signal can be directly stored as the error address signal, or the indication signal corresponding to the error address signal can be processed and then stored as the error address signal. That is, the error address indication signal A and the indication signal 1 can be the same signal, or the error address indication signal A can be a related signal generated based on the indication signal 1.

[0105] In this way, the present embodiment generates an indication signal based on the command signal and stores the address signal under test in the test core circuit 201 instead of storing it in the PHY area, thereby avoiding a large occupation of the PHY area and saving the limited area of ​​the PHY area.

[0106] In some embodiments, the error recording circuit 202 is further configured to record the corresponding error address indication signal according to the indication signal when the measured address signal corresponding to the indication signal is an error address signal.

[0107] It should be noted that during the testing process, the error recording circuit 202 or other related circuits (which can be referred to as error monitoring circuits) will monitor whether the address under test is an error address. For example, the testing method is as follows: write data to the address under test and read data from the address under test, compare whether the written data and the read data are the same. If they are the same, it indicates that the read and write function of the address under test is normal; if they are different, it indicates that the address under test is an error address. Therefore, in this embodiment of the disclosure, the command signal can be a read command signal, a write command signal, or other command signals carrying address signals, etc. When the address under test is an error address, the error recording circuit 202 stores the corresponding indication signal, i.e., the error address indication signal; or, the indication signal is first processed to obtain the error address indication signal; for example, the indication signal is encoded to reduce its number of bits, further reducing the area occupied by the PHY region.

[0108] It should also be noted that, in this embodiment, the error recording circuit 202 can receive each indication signal and directly store or process the indication signal corresponding to the error address to generate an error address indication signal for storage; alternatively, the error monitoring circuit receives the indication signal and determines whether the measured address is an error address. If it is an error address, it sends the indication signal to the error recording circuit 202 for processing and storage, or the error monitoring circuit processes the indication signal into an error address indication signal before sending it to the error recording circuit 202 for storage. Alternatively, this embodiment can also adopt any other feasible method for error monitoring and generating error address indication signals. The error monitoring circuit can be located in other areas outside the PHY area to save the area of ​​the PHY area.

[0109] It should also be noted that the indicator signal is used to indicate the storage location of the address signal under test in the test core circuit 201, and its essence can be considered as an index or address signal. For example, suppose the test core circuit 201 contains M storage units for storing the address signals under test, where M is a positive integer, and each storage unit can store one address signal under test. If the address signal under test is multi-bit, then each storage unit is also multi-bit, thus storing multi-bit data of the address signal under test. Each storage unit corresponds to its own index or address. For example, the indicator signals corresponding to the first to the Mth storage units are indicator signal 1, indicator signal 2, indicator signal 3, ..., indicator signal M, respectively. Following a certain order, each time a new command signal and the corresponding address signal under test are received, the address signal under test is stored in the storage unit corresponding to the current indicator signal. For example, upon receiving the first command signal and the corresponding address signal under test, indicator signal 1 is generated, and the first address signal under test is stored in the storage unit 1 corresponding to indicator signal 1; upon receiving the second command signal and the corresponding address signal under test, indicator signal 2 is generated, and the second address signal under test is stored in the corresponding storage unit 2; ...; upon receiving the Mth command signal and the corresponding address signal under test, indicator signal M is generated, and the Mth address signal under test is stored in the storage unit M corresponding to indicator signal M, thereby realizing the storage of the address signal under test.

[0110] Since the number of memory cells in the test core circuit 201 is much smaller than the number of memory cells in the memory array under test, the number of addresses of the memory cells in the test core circuit 201 is much smaller than the number of addresses of the memory cells in the memory array. Therefore, the error recording circuit 202 only records a small number of error address indication signals indicating error addresses, without occupying a large area, which can reduce the area occupied by the PHY region.

[0111] In some embodiments, such as Figure 4As shown, the command signal includes a first command signal and a second command signal, the address signal under test includes at least a row address signal and a column address signal, and the test core circuit 201 includes a first storage circuit 2011, an indicator signal generation circuit 2013 and a second storage circuit 2012.

[0112] The first storage circuit 2011 is used to receive the first command signal and the corresponding row address signal, and to store the row address signal;

[0113] The first storage circuit 2011 is also used to receive the second command signal, read the stored row address signal based on the second command signal, and transmit it to the second storage circuit 2012;

[0114] The indicator signal generation circuit 2013 is used to receive the second command signal and process the second command signal into an indicator signal according to a preset rule; the indicator signal is specifically used to indicate the storage location of the measured address signal in the second storage circuit 2012;

[0115] The second storage circuit 2012 is used to receive the column address signal, the indication signal, and the row address signal transmitted by the first storage circuit 2011 corresponding to the second command signal; and to store the column address signal and the row address signal in the storage location indicated by the indication signal.

[0116] It should be noted that reading and writing addresses in memory usually involves activating a specific row first and then selecting a specific column. Therefore, in this embodiment, the row address signal is temporarily stored in the first storage circuit 2011 and then stored together with the subsequent column address signal in the second storage circuit 2012, thereby avoiding the inability to capture the row address signal when the second command signal is received.

[0117] The first command signal can be, for example, an activation command signal, used to activate a specific row address. The first command signal corresponds to at least one row address signal, so the first storage circuit 2011 stores the corresponding row address signal upon receiving the first command signal. The second command signal can be a read command signal, a write command signal, or a command signal such as RDA or WRA. The second command signal corresponds to at least one column address signal, so the row address signal and column address signal can locate specific positions within the storage array. Upon receiving the second command signal, the first storage circuit 2011 reads the corresponding row address signal and sends it to the second storage circuit 2012. The second storage circuit 2012 combines the received row address signal and column address signal to form the measured address signal and stores it.

[0118] In this way, the row address signal is temporarily stored first, and then combined with the column address signal received later to form the address signal under test for storage. This ensures that the address signal under test is correctly stored while meeting the read and write addressing mode specified in the standard, and avoids the loss or incompleteness of the address signal under test.

[0119] It should also be noted that each received second command signal indicates the need to store a tested address signal. Therefore, an indication signal can be generated based on the second command signal. The preset rule for generating the indication signal based on the second command signal can be: generating the indication signal according to the order in which the tested address signals are stored in the test core circuit 201.

[0120] For example, taking the test core circuit 201, which includes M memory cells for storing the address signal under test, as an example, in Figure 4 In the example shown, the second storage circuit 2012 includes M storage cells (denoted as the second storage cell). If the sequence of the first second command signal is 1, then indicator signal 1 is generated, and the corresponding measured address signal is stored in the second storage cell 1, and so on.

[0121] In this way, the corresponding indicator signal is generated based on the sequence of the address signal being tested, without the need to set up complex logic to generate the indicator signal, making the circuit design and implementation relatively simple.

[0122] In some embodiments, the indication signal generation circuit 2013 can be a counter, used to receive the second command signal, count the second command signal, and obtain the indication signal.

[0123] It should be noted that the count value of the counter counting the second command signal can be directly used as the indicator signal. That is: the value of indicator signal 1 is 1, corresponding to the second storage unit 1; the value of indicator signal 2 is 2, corresponding to the second storage unit 2; ...; the value of indicator signal M is M, corresponding to the second storage unit M. In this way, the indicator signal can be generated using the existing counter circuit without the need for additional complex circuit design; and the number of bits of the counter's output signal is usually smaller than the number of bits of the measured address signal, which can be stored in a smaller storage space, further saving space.

[0124] In some embodiments, the counting range of the counter is N, and the number of measured address signals that the second storage circuit 2012 can store is M, where N and M are both positive integers, and N is greater than or equal to M.

[0125] The second storage circuit 2012 is also used to receive control signals and, based on the control signals, use M consecutive numbers from N as addresses corresponding to the M second storage units in the second storage circuit 2012.

[0126] It should be noted that the counting range of the counter may be greater than the storage limit of the second storage circuit 2012. In this case, the value range of the indicator signal corresponding to each second storage unit in the second storage circuit 2012 can be changed by the control signal. For example, assume N=256 and M=64. That is, the counter can count count values ​​from 1 to 256 (or 0 to 255), and the second storage circuit 2012 contains 64 second storage units. Based on the control signal, count values ​​1 to 64 (or count values ​​0 to 63) can be used as indicator signals corresponding to the 64 second storage units, or count values ​​65 to 128 (or count values ​​64 to 127) can be used as indicator signals corresponding to the 64 second storage units, or the remaining 64 consecutive count values ​​can be selected as indicator signals corresponding to the 64 second storage units. In this way, when the counting range of the counter is greater than the storage limit of the second storage circuit 2012, the embodiments of this disclosure can also be combined with actual settings to determine which count range of the tested address signal is stored, increasing the flexibility of the test.

[0127] In some embodiments, such as Figure 4 As shown, the address signal under test also includes a first address signal; the first address signal serves as the address signal of the storage unit (denoted as the first storage unit) in the first storage circuit 2011;

[0128] The first storage circuit 2011 is also used to receive the first address signal corresponding to the first command signal. Figure 4 (Not shown), the row address signal is stored in the first storage unit corresponding to the first address signal;

[0129] The first storage circuit 2011 is also used to receive the first address signal corresponding to the second command signal. Figure 4 (Not shown), read the row address signal from the first memory cell corresponding to the first address signal;

[0130] The second storage circuit 2012 is also used to store the first address signal into the second storage unit corresponding to the indication signal.

[0131] It should be noted that the first address signal is an address signal at a higher level than the row address and column address, such as a repository address signal. If the first storage circuit 2011 stores multiple row address signals from different repositories before receiving the second command signal, it is necessary to determine which one needs to be stored as the test address signal in the second storage circuit 2012. It is understood that multiple row addresses will not be activated simultaneously in the same repository; therefore, row address signals within the same repository will not conflict. Thus, the repository address can be used as the address of the first storage unit, eliminating the need for additional address design and ensuring the accuracy of the stored row address signal.

[0132] It should also be noted that, assuming the first storage circuit 2011 includes K first storage cells, each first storage cell is used to store a row address signal. In this embodiment, the first address signal is used as the address signal of the first storage cell in the first storage circuit 2011. For example, assuming the memory includes K storage cells, then the K first storage cells and K storage cell address signals correspond one-to-one. For example, when the first storage circuit 2011 receives a first command signal 1 and the corresponding storage cell address signal 1 and row address signal 1, it stores the row address signal 1 into the first storage cell 1 corresponding to the storage cell address signal 1; the first storage circuit 2011 also receives a first command signal 2 and the corresponding storage cell address signal 2 and row address signal 2, and stores the row address signal 2 into the first storage cell 2 corresponding to the storage cell address signal 2. When the second storage circuit 2012 receives the second command signal and the corresponding storage address signal, it searches in the first storage circuit 2011 based on the storage address signal. If the received storage address signal is storage address signal 1, the corresponding row address signal 1 is read from the corresponding first storage unit 1; if the received storage address signal is storage address signal 2, the corresponding row address signal 2 is read from the corresponding first storage unit 2.

[0133] It should also be noted that in some memories, the first address signal may also include the repository group address signal.

[0134] It should also be noted that in HBM, the first address signal can also include the chip ID. HBM consists of multiple stacked chips, and the chip ID is used to indicate a specific chip. In HBM, the first address signal can also include the PC address, where PC is a proprietary concept in HBM, representing an architectural design that further subdivides physical channels. For example, every 64-bit physical channel is divided into two 32-bit pseudo-channels (denoted as PC0 and PC1, respectively).

[0135] It should also be noted that, in this embodiment of the disclosure, the storage of the measured address signal can be implemented in, but is not limited to, the following two different ways:

[0136] Method 1: The first storage circuit 2011 receives the first command signal and the corresponding row address signal and first address signal, and stores the row address signal in the first storage unit corresponding to the first address signal. When the second command signal arrives, the first storage circuit 2012 receives the first address signal corresponding to the second command signal, performs addressing based on the received first address signal in the first storage circuit 2012, reads the row address signal from the corresponding first storage unit, and sends it to the second storage circuit 2012. The second storage circuit 2012 receives the first address signal and column address signal corresponding to the second command signal, as well as the row address signal sent by the first storage circuit 2011, and stores the row address signal, column address signal, and first address signal as the measured address signal in the second storage unit corresponding to the indicator signal.

[0137] Method 2: The first storage circuit 2011 receives the first command signal and the corresponding row address signal and first address signal, and stores the row address signal and first address signal into the first storage unit corresponding to the first address signal. When the second command signal arrives, the first storage circuit 2012 receives the first address signal corresponding to the second command signal, performs addressing based on the received first address signal in the first storage circuit 2012, reads the row address signal and first address signal from the corresponding first storage unit, and sends them to the second storage circuit 2012. The second storage circuit 2012 receives the column address signal corresponding to the second command signal, as well as the row address signal and first address signal sent by the first storage circuit 2011, and stores the row address signal, column address signal, and first address signal as the measured address signal into the second storage unit corresponding to the indicator signal.

[0138] In Method 1, the first storage circuit 2011 only needs to store the row address signal, thus occupying less storage space.

[0139] Further, see Figure 5 This illustration shows a detailed structural diagram of a test circuit provided in an embodiment of the present disclosure. Figure 5 As shown, both the first storage circuit 2011 and the second storage circuit 2012 include: a write address terminal waddr, a write data terminal wdata, a write command terminal fwrite, a read address terminal raddr, a read data terminal rdata, and a read command terminal fread;

[0140] The first storage circuit 2011 and the second storage circuit 2012 are both used to write the signal received by the write data terminal wdata into the storage unit corresponding to the address signal received by the write address terminal waddr when the write command terminal fwrite receives the corresponding command signal.

[0141] The first storage circuit 2011 and the second storage circuit 2012 are both used to read out the signal stored in the storage unit corresponding to the address signal received by the read address terminal raddr and output it from the read data terminal rdata when the read command terminal fread receives the corresponding command signal.

[0142] It should be noted that the first storage circuit 2011 and the second storage circuit 2012 may also include a write circuit and a read circuit, so as to realize the writing and reading of data when the corresponding signal is received at each end.

[0143] like Figure 5 As shown, specifically in the first storage circuit 2011, the write address terminal waddr is used to receive the first address signal corresponding to the first command signal, the write data terminal wdata is used to receive the row address signal (and can also receive the first address signal at the same time), the write command terminal fwrite is used to receive the first command signal, the read address terminal raddr is used to receive the first address signal corresponding to the second command signal, the read data terminal rdata is used to output the stored row address signal (if the first address signal is stored, it can also output the first address signal at the same time), and the read command terminal fread is used to receive the second command signal;

[0144] And / or, in the second storage circuit 2012, the write address terminal waddr is used to receive the indication signal, the write data terminal wdata is used to receive the measured address signal, the write command terminal fwrite is used to receive the second command signal, the read address terminal raddr is used to receive the error address indication signal, the read data terminal rdata is used to output the stored measured address signal, and the read command terminal fread is used to receive the error address capture signal.

[0145] In other words, for the first storage circuit 2011: the first command signal is used as a write command signal; the first address signal corresponding to the first command signal is used as a write address signal; the row address signal is used as write data, or the row address signal and the first address signal are used as write data; the second command signal is used as a read command signal; the first address signal corresponding to the second command signal is used as a read address signal; the row address signal is used as read data, or the row address signal and the first address signal are used as read data.

[0146] For the second storage circuit 2012: the second command signal serves as the write command signal; the indicator signal serves as the write address signal; the measured address signal (row address signal + column address signal + first address signal) serves as the write data, wherein the row address signal is stored in the first storage circuit 2011, the column address signal corresponds to the second command signal, and the first address signal corresponds to the second command signal or is stored in the first storage circuit 2011; the error address capture signal serves as the read command signal; the error address indicator signal serves as the read address signal; and the error address signal serves as the read data.

[0147] In this embodiment of the disclosure, both the first storage circuit 2011 and the second storage circuit 2012 can be RAM.

[0148] It should also be noted that, such as Figure 5 As shown, the test core circuit 201 may also include:

[0149] The timing circuit 2014 is used to receive the second command signal, adjust the timing of the second command signal so that the timing of the second command signal is the same as the timing of the indication signal, and send the timing-adjusted second command signal to the second storage circuit 2012.

[0150] The timing circuit 2014 can be, for example, a delay circuit, a DFF or multiple DFFs in series, etc., to delay the second command signal to match the delay caused by the counter (i.e. the indicator signal generation circuit 2013), to ensure the accuracy of the timing, and to avoid the inability to store the address signal under test normally.

[0151] In some embodiments, such as Figure 5 As shown, the test circuit 20 may further include a control circuit 2015. In some embodiments, the control circuit 2015 is disposed within the test core circuit 201; in other embodiments, the control circuit 2015 is disposed outside the test core circuit 201. The following description uses the example of the control circuit 2015 being disposed within the test core circuit 201, in which case the test core circuit 201 may further include the control circuit 2015.

[0152] Control circuit 2015 is used to send an error address capture signal (captureWR) to the second storage circuit 2012.

[0153] And / or, the control circuit 2015 is also used to receive the error address signal output by the second storage circuit 2012;

[0154] And / or, the control circuit 2015 is also used to send an error address read command to the error recording circuit 202; correspondingly, the error recording circuit 202 is also used to send an error address indication signal to the test core circuit 201 when it receives the error address read command, specifically to the second storage circuit 2012.

[0155] It should be noted that, in this embodiment of the disclosure, the control circuit 2015 can be an IEEE 1500 circuit. When it is necessary to read the error address signal, an error address read command is sent to the error recording circuit 202, an error address capture command is sent to the second storage circuit 2012, and the error address signal output by the second storage circuit 2012 is received.

[0156] In some embodiments, such as Figure 5 As shown, the first storage circuit 2011 and the second storage circuit 2012 also include a write clock terminal wclk and a read clock terminal rclk. The write clock terminal wclk and read clock terminal rclk of the first storage circuit 2011, as well as the write clock terminal of the second storage circuit 2012, all receive a system clock signal. The read clock terminal rclk of the second storage circuit 2012 receives a test clock signal wrclk, which matches the speed of the control circuit 2015. The first storage circuit 2011 and the second storage circuit 2012 perform data writing and reading based on their respective clock signals.

[0157] In some embodiments, such as Figure 5 As shown, the test core circuit 201 may also include:

[0158] The first decoding circuit 2016 is used to receive the first command address signal, decode the first command address signal, and obtain the first command signal and the corresponding first address signal and row address signal.

[0159] The second decoding circuit 2017 is used to receive the second command address signal, decode the second command address signal, and obtain the second command signal and the corresponding first address signal and column address signal.

[0160] It should be noted that, as Figure 5 As shown, the first decoding circuit 2016 and the second decoding circuit 2017 are decoding circuits used to decode the command address signal to obtain the command signal and the address signal. Both the first command address signal and the second command address signal can be multi-bit signals. Specifically, the first command address signal can include 4-bit signals: R0, F0, R1, and F1, and the second command address signal can include 4-bit signals: CR0, CF0, CR1, and CF1. They are decoded according to JEDEC specifications to obtain the corresponding command signal and address signal.

[0161] In some embodiments, the error address indication signal sent by the error recording circuit 202 is a serial signal (which can be denoted as WSO); for example Figure 5 As shown, the test circuit 20 may also include:

[0162] The serial-to-parallel conversion circuit 203 is used to process the error address indication signal from serial to parallel before sending it to the second storage circuit 2012.

[0163] It should be noted that within the core test circuit 201, signals can be transmitted in parallel. If the error recording circuit 202 transmits data serially, a serial-to-parallel converter 203 can be used for conversion. Furthermore, the test circuit 20 may also include a parallel-to-serial converter (not shown in the figure) to process the indication signal from parallel to serial. This parallel-to-serial converter is connected between the indication signal generation circuit 2013 and the error recording circuit 202, or integrated within the error recording circuit 202, or integrated within the aforementioned error monitoring circuit.

[0164] based on Figure 5 The circuit shown illustrates the procedure for testing the memory array as follows:

[0165] Programmable instructions are loaded into the MBIST core circuit 201. These instructions are parsed by the MBIST core (which also includes other circuits not mentioned above, such as circuits that parse these instructions) to generate commands that conform to the JEDEC standard.

[0166] Start MBIST core and make it run.

[0167] Waiting for the MBIST core to finish running.

[0168] An error address read command (such as an IEEE 1500 read command) is sent to the error recording circuit 202. The error recording circuit 202 records which read has an error (i.e., the error address indication signal). The error address indication signal is sent to the test core circuit 201. The error address indication circuit serves as the read address of the second storage circuit 2012, thereby enabling the stored error address to be read out. This error address signal is the complete storage array address.

[0169] It should also be noted that, in this embodiment of the disclosure, the error recording circuit 202 can be an ECM, which can store two error address indication signals to record two tested address signals that have erroneous. It can also store other numbers of error address indication signals, such as one, four, or more / fewer, without specific limitation.

[0170] In summary, since the MBIST core has ample area, this solution places the storage circuit (such as a 64-bit RAM) for storing the address signal under test within the MBIST core. When a read or write command signal arrives, the row address stored in the first storage circuit 2011 is read out and written into the second storage circuit 2012 along with the SID, PC address, bank address, and column address carried in the read or write command signal. Each read and write operation stores one address signal under test.

[0171] The error recording circuit 202 can record which read / write error occurred, for example, two errors. When the program finishes running and it is necessary to analyze which address the error occurred at, the error address indication signal recorded in the error recording circuit 202 is read into MBISTcore. MBISTcore uses the error address indication signal as the read address of the second storage circuit 2012 and outputs the corresponding error address signal.

[0172] Since no circuit for storing the address signal under test is set in the PHY region, the embodiments of this disclosure can greatly reduce the area of ​​the PHY region occupied by the test circuit, thereby simplifying the design of the PHY region and facilitating the timing convergence of the PHY region and the test circuit.

[0173] In another embodiment of this disclosure, a memory is also provided, which includes the test circuit 20 from any of the foregoing embodiments.

[0174] It should be noted that the memory also includes a memory array, which contains multiple memory cells (referred to as the third memory cell here to distinguish it from the first and second memory cells mentioned above). The test circuit 20 is used to test the third memory cell. The address indicated by the test address signal is the address of the third memory cell. During testing, the third memory cell is read from and written to determine whether it is an erroneous memory cell. In addition to the components of the test circuit 20 described above, the test circuit 20 also includes other necessary circuits for testing the memory array. These circuits can be proprietary to the test circuit 20 or reused with related circuits in the memory; they will not be described in detail here.

[0175] In some embodiments, the memory is an HBM memory, which is a high-bandwidth memory; the address signal under test includes a row address signal, a first address signal, and a column address signal, the first address signal including: chip identification number (SID), virtual channel (PC) address, and bank address; the test core circuit 201 includes a first storage circuit 2011, an indication signal generation circuit 2013, and a second storage circuit 2012;

[0176] The first storage circuit 2011 is used to receive the first command signal and the corresponding row address signal, and to store the row address signal.

[0177] The first storage circuit 2011 is also used to receive the second command signal, read the stored row address signal based on the second command signal, and transmit it to the second storage circuit 2012;

[0178] The indicator signal generation circuit 2013 is used to receive the second command signal and process the second command signal into an indicator signal according to a preset rule; the indicator signal is specifically used to indicate the storage location of the measured address signal in the second storage circuit 2012;

[0179] The second storage circuit 2012 is used to receive the column address signal, the indication signal, and the row address signal transmitted by the first storage circuit 2011 corresponding to the second command signal; and to store the column address signal and the row address signal in the storage location indicated by the indication signal.

[0180] The HBM memory comprises multiple stacked chips, including a base die and a core die. The test circuit 20 is located in the base die, and the memory array is located in the core die.

[0181] It should be noted that details not disclosed in the embodiments of this disclosure can be understood by referring to the description of the foregoing embodiments.

[0182] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0183] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0184] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0185] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0186] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0187] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0188] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A test circuit, characterized in that, It includes an error recording circuit and a test core circuit; the error recording circuit is located in the physical interface area of ​​the memory, and the test core circuit is located in other areas of the memory; The core test circuit is used to store at least one address signal under test; The core test circuit is also used to receive an error address indication signal and output the test address signal corresponding to the error address indication signal; the test address signal corresponding to the error address indication signal is an error address signal. The error recording circuit is used to record the error address indication signal; The error recording circuit is also used to send the error address indication signal to the test core circuit; Specifically, the test core circuit is used to sequentially receive at least one command signal and a corresponding address signal under test. When the command signal is received, an indication signal is generated, and the corresponding address signal under test is stored based on the indication signal. The indication signal is used to indicate the storage location of the address signal under test in the test core circuit. The indication signal corresponding to the error address signal and the error address indication signal corresponding to the error address signal indicate the same storage location in the test core circuit. The error recording circuit is further configured to record the corresponding error address indication signal according to the indication signal when the measured address signal corresponding to the indication signal is an error address signal.

2. The test circuit according to claim 1, characterized in that, The command signal includes a first command signal and a second command signal, the address signal under test includes at least a row address signal and a column address signal, and the core test circuit includes a first storage circuit, an indicator signal generation circuit, and a second storage circuit. The first storage circuit is configured to receive the first command signal and the corresponding row address signal, and store the row address signal; The first storage circuit is further configured to receive the second command signal, read the stored row address signal based on the second command signal, and transmit it to the second storage circuit; The indicator signal generation circuit is used to receive the second command signal and process the second command signal into the indicator signal according to a preset rule; the indicator signal is specifically used to indicate the storage location of the measured address signal in the second storage circuit. The second storage circuit is configured to receive the column address signal corresponding to the second command signal, the indication signal, and the row address signal transmitted by the first storage circuit; and to store the column address signal and the row address signal at the storage location indicated by the indication signal.

3. The test circuit according to claim 2, characterized in that, The preset rule is as follows: the indicator signal is generated based on the order in which the address signal under test is stored in the core test circuit; the indicator signal generation circuit is a counter. The counter is used to receive the second command signal, count the second command signal, and obtain the indication signal.

4. The test circuit according to claim 3, characterized in that, The counter has a counting range of N, and the second storage circuit can store M of the measured address signals, where N and M are both positive integers, and N is greater than or equal to M. The second storage circuit is further configured to receive control signals, and based on the control signals, use M consecutive values ​​from N as indication signals corresponding to the M storage units in the second storage circuit.

5. The test circuit according to claim 2, characterized in that, The address signal under test also includes a first address signal; the first address signal serves as the address signal of the storage cell in the first storage circuit; The first storage circuit is further configured to receive a first address signal corresponding to the first command signal and store the row address signal into the storage unit corresponding to the first address signal; The first storage circuit is further configured to receive a first address signal corresponding to the second command signal and read the row address signal from the storage unit corresponding to the first address signal; The second storage circuit is further configured to store the first address signal into the storage unit corresponding to the indication signal.

6. The test circuit according to claim 5, characterized in that, The first address signal is the repository address signal.

7. The test circuit according to claim 5, characterized in that, Both the first storage circuit and the second storage circuit include: a write address terminal, a write data terminal, a write command terminal, a read address terminal, a read data terminal, and a read command terminal; Both the first storage circuit and the second storage circuit are used to write the signal received by the write data terminal into the storage unit corresponding to the address signal received by the write address terminal when the write command terminal receives the corresponding command signal. Both the first storage circuit and the second storage circuit are used to output the signal stored in the storage unit corresponding to the address signal received by the read address terminal from the read data terminal when the read command terminal receives the corresponding command signal.

8. The test circuit according to claim 7, characterized in that, In the first storage circuit, the write address terminal is used to receive the first address signal corresponding to the first command signal, the write data terminal is used to receive the row address signal, the write command terminal is used to receive the first command signal, the read address terminal is used to receive the first address signal corresponding to the second command signal, the read data terminal is used to output the stored row address signal, and the read command terminal is used to receive the second command signal. And / or, in the second storage circuit, the write address terminal is used to receive the indication signal, the write data terminal is used to receive the tested address signal, the write command terminal is used to receive the second command signal, the read address terminal is used to receive the error address indication signal, the read data terminal is used to output the stored tested address signal, and the read command terminal is used to receive the error address capture signal.

9. The test circuit according to claim 8, characterized in that, The test circuit also includes a control circuit; The control circuit is used to send the error address capture signal to the second storage circuit; And / or, the control circuit is further configured to receive the error address signal output by the second storage circuit; And / or, the control circuit is further configured to send an error address read command to the error recording circuit; correspondingly, the error recording circuit is configured to send the error address indication signal to the test core circuit when it receives the error address read command.

10. A memory, characterized in that, Includes the test circuit as described in any one of claims 1-9.

11. The memory according to claim 10, characterized in that, The memory is a high-bandwidth memory; the address signal under test includes a row address signal, a first address signal, and a column address signal, wherein the first address signal includes: chip identification number, virtual channel address, and storage address; the core test circuit includes a first storage circuit, an indicator signal generation circuit, and a second storage circuit. The first storage circuit is configured to receive a first command signal and the corresponding row address signal, and store the row address signal; The first storage circuit is further configured to receive a second command signal, read the stored row address signal based on the second command signal, and transmit it to the second storage circuit; The indicator signal generation circuit is used to receive the second command signal and process the second command signal into the indicator signal according to a preset rule; the indicator signal is specifically used to indicate the storage location of the measured address signal in the second storage circuit. The second storage circuit is configured to receive the column address signal corresponding to the second command signal, the indication signal, and the row address signal transmitted by the first storage circuit; and to store the column address signal and the row address signal at the storage location indicated by the indication signal.

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