Multi-level converter wave-by-wave current limiting control method, system and device, and storage medium

Abstract

The application provides a multi-level converter wave-by-wave current limiting control method and system, equipment and a storage medium, and relates to the technical field of power electronics control. The method comprises the following steps: determining whether the inverter side current of the multi-level converter reaches a threshold value when wave-by-wave current limiting occurs; when the inverter side current reaches the threshold value, the duty cycle of positive and negative modulation waves and the time of seal driving when wave-by-wave current limiting occurs are calculated through the capacitor voltage, the positive and negative bus voltages and the switching period. In order to solve the problem that the multi-level converter is prone to triggering hardware overcurrent when wave-by-wave current limiting occurs, the duty cycle of positive and negative modulation waves and the time of seal driving are calculated according to the current inverter side current, the capacitor voltage, the positive and negative bus voltages and the switching period, so that the current during wave-by-wave current limiting is kept stable, and triggering of hardware overcurrent is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronic control, and particularly relates to a multi-level converter wave-by-wave current limiting control method and system, equipment and a storage medium. BACKGROUND

[0002] With the rapid development of power electronic technology, multi-level converters have been widely used in medium and high voltage and high power application fields. Compared with traditional two-level converters, multi-level converters have the advantages of low output voltage harmonic content, small switching device voltage stress and high efficiency.

[0003] When a multi-level converter operates off-grid, it usually needs to cope with impact loads such as asynchronous motors. When loaded, the current will become very large, which is easy to trigger hardware overcurrent and cause system shutdown. The wave-by-wave current limiting method is usually used to limit the current within a certain range, that is, when the current reaches the wave-by-wave current limiting threshold, the drive is closed, so that the current quickly drops, and after a certain time, the drive is restarted, and the current continues to rise, so as to control the current within a reasonable range and avoid triggering hardware overcurrent.

[0004] However, if the duty cycle is set according to the output of the control loop when the drive is restarted, the duty cycle may be large at this time. Considering the delay of the signal, it is still possible to trigger hardware overcurrent in this period of time. Therefore, other ways must be used to determine the duty cycle and the time of closing the drive to ensure that the current remains stable during wave-by-wave current limiting and avoid triggering hardware overcurrent. SUMMARY

[0005] In order to achieve the above-mentioned purposes and other advantages of the present application, the first object of the present application is to provide a multi-level converter wave-by-wave current limiting control method, comprising the following steps:

[0006] determining whether the inverter-side current of the multi-level converter reaches a threshold value when wave-by-wave current limiting occurs;

[0007] when the inverter-side current reaches the threshold value, calculating the duty cycle of the positive and negative modulation waves and the time of closing the drive during wave-by-wave current limiting through the capacitor voltage, the positive and negative bus voltages and the switching period.

[0008] Further, the step of determining whether the inverter-side current of the multi-level converter reaches a threshold value when wave-by-wave current limiting occurs comprises:

[0009] determining whether the inverter-side current of the multi-level converter is greater than a first threshold value when wave-by-wave current limiting occurs.

[0010] Further, the step of calculating the duty cycle of the positive and negative modulation waves and the time of closing the drive during wave-by-wave current limiting through the capacitor voltage, the positive and negative bus voltages and the switching period when the inverter-side current reaches the threshold value comprises:

[0011] When the inverter-side current is greater than the first threshold value, duty ratios of positive and negative modulation waves when the current is limited by each pulse are calculated by the capacitor voltage, the positive bus voltage, and the switching period.

[0012] Further, when the inverter-side current is greater than the first threshold value, the duty ratios of the positive and negative modulation waves and the time of the dead-time are calculated by the following formulas:

[0013] ;

[0014] wherein, and are duty ratios of the positive and negative modulation waves, is the time of the dead-time, , and are the capacitor voltage, the positive bus voltage and the negative bus voltage, is the switching period.

[0015] Further, the step of determining whether the inverter-side current reaches a threshold value when the current is limited by each pulse in the multi-level converter comprises:

[0016] determining whether the inverter-side current is less than a second threshold value when the current is limited by each pulse in the multi-level converter.

[0017] Further, the step of calculating the duty ratios of the positive and negative modulation waves and the time of the dead-time by the capacitor voltage, the positive and negative bus voltages and the switching period when the inverter-side current reaches a threshold value comprises:

[0018] When the inverter-side current is less than the second threshold value, duty ratios of positive and negative modulation waves when the current is limited by each pulse are calculated by the capacitor voltage, the negative bus voltage, and the switching period.

[0019] Further, when the inverter-side current is less than the second threshold value, the duty ratios of the positive and negative modulation waves and the time of the dead-time are calculated by the following formulas:

[0020] ;

[0021] wherein, and are duty ratios of the positive and negative modulation waves, is the time of the dead-time, , and are the capacitor voltage, the positive bus voltage and the negative bus voltage, is the switching period.

[0022] Further, the first threshold value is configured as 0, and the second threshold value is configured as 0.

[0023] A second object of the present application is to provide a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method when executing the computer program.

[0024] A third object of the present application is to provide a computer-readable storage medium having stored thereon a computer program, the computer program implementing the steps of the above method when executed by a processor.

[0025] A fourth object of the present application is to provide a multi-level converter wave-by-wave current limiting control system applying the above method, comprising an inverter-side current judging module and a duty cycle and dead-time calculation module.

[0026] The inverter-side current judging module is configured to determine whether the inverter-side current reaches a threshold value when the multi-level converter wave-by-wave current limiting occurs.

[0027] The duty cycle and dead-time calculation module is configured to calculate the duty cycle of the positive and negative modulation waves and the dead-time when the inverter-side current reaches the threshold value, by the capacitor voltage, the positive and negative bus voltages and the switching period.

[0028] Compared with the prior art, the present application has the following advantages:

[0029] The present application optimizes the multi-level converter wave-by-wave current limiting control method, calculates the duty cycle of the positive and negative modulation waves and the dead-time according to the current, the capacitor voltage, the positive and negative bus voltages and the switching period, so that the current during wave-by-wave current limiting is stable, and the hardware overcurrent is avoided.

[0030] The above description is only a summary of the technical solutions of the present application, in order to more clearly understand the technical means of the present application, and the content of the specification can be implemented. The following describes the preferred embodiments of the present application in detail with reference to the accompanying drawings. The specific embodiments of the present application are described in detail by the following examples and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0031] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0032] Figure 1 Flow chart of the multi-level converter wave-by-wave current limiting control method Figure 1 ;

[0033] Figure 2Input and output block diagram of the per-cycle current limiting control method for the multi-level converter

[0034] Figure 3 Flow of the per-cycle current limiting control method for the multi-level converter Figure 2 ;

[0035] Figure 4 Flow chart for calculating the duty ratio and the time of the gate drive

[0036] Figure 5 Topology diagram of the diode clamped three-level converter

[0037] Figure 6 Current waveform when the control method of the present application is not used in the per-cycle current limiting

[0038] Figure 7 Current waveform when the control method of the present application is used in the per-cycle current limiting

[0039] Figure 8 System block diagram of the per-cycle current limiting control method for the multi-level converter

[0040] Figure 9 Schematic diagram of the computer device

[0041] Figure 10 Schematic diagram of the computer readable storage medium DETAILED DESCRIPTION

[0042] Hereinafter, the present application will be further described with reference to the drawings and specific embodiments, obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. It should be noted that, without conflict, the following described embodiments or technical features can be combined to form new embodiments.

[0043] Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0044] The figure numbers in the present application are only used to distinguish each step in the scheme, and are not used to limit the execution order of each step, and the specific execution order is subject to the description in the specification.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application.

[0046] In the related art, the per-cycle current limiting technology of a multi-level converter (such as a diode midpoint clamping type or a cascade H-bridge type) maintains system stability while protecting power devices through real-time current monitoring and dynamic PWM control.

[0047] Specifically, the per-cycle current limiting protection realizes effective control of short-circuit and fault current in the multi-level converter through the combination of hardware circuit and software logic. When the output is short-circuited, the per-cycle current limiting protection mechanism limits the current size to prevent equipment damage; when the bridge arm is directly connected, the IGBT is protected from damage through fast detection and dead zone, interlocking and other measures. This protection mechanism is of great significance to improve the reliability and stability of the multi-level converter.

[0048] However, when the current reaches the per-cycle current limiting threshold and the drive is turned off, if the duty cycle is set according to the output of the control loop when the drive is turned on again, the duty cycle may be large at this time. Considering the delay of the signal, the hardware overcurrent may still be triggered during this period of time. Therefore, other ways must be used to determine the duty cycle and the time of sealing the drive to ensure that the current remains stable during per-cycle current limiting and to avoid triggering the hardware overcurrent.

[0049] To avoid triggering the hardware overcurrent during per-cycle current limiting of the multi-level converter, the present application proposes a per-cycle current limiting control method for a multi-level converter, which calculates the duty cycle of the positive and negative modulation waves and the time of sealing the drive according to the current on the inverter side, the capacitor voltage, the positive and negative bus voltages and the switching period.

[0050] The method can be executed by a master control unit of a per-cycle current limiting control system for the multi-level converter. The master control unit can be implemented in the form of software and / or hardware and is generally integrated on any electronic device with network communication function, which can be a mobile terminal, a PC terminal or a server, etc.

[0051] Embodiment 1

[0052] A per-cycle current limiting control method for a multi-level converter, as shown in Figure 1 , Figure 2 includes the following steps:

[0053] As a key protection technology for multi-level converters (such as diode clamping type, flying capacitor type and cascade H-bridge type), per-cycle current limiting ensures fast response of the system in overload or short circuit by monitoring and limiting the current peak value in each half switching cycle.

[0054] The inverter-side current i can be collected by a high-precision sensor (such as a Hall sensor) at a microsecond level frequency, compared with a preset wave-by-wave current limiting threshold, and a control logic is triggered. For example, the inverter-side current is directly measured by a current sensor installed at the output end. In a diode clamped type or flying capacitor type multi-level converter, due to the existence of multi-level voltage output, a current sensor with high precision and fast response characteristics needs to be used to ensure that the transient change at each level switching is captured.

[0055] When the inverter-side current i exceeds the set threshold, the control algorithm immediately controls the peak current to be suppressed by positive and negative modulation wave duty cycle correction.

[0056] Specifically, S100, determining whether the inverter-side current when the multi-level converter occurs wave-by-wave current limiting reaches a threshold value;

[0057] Since the wave-by-wave current limiting protection of the multi-level converter is realized by real-time monitoring of the current signal, when the current is over-limit, the PWM output is immediately blocked until the next cycle is detected again. If the current continues to be over-limit, it will continue to be blocked until it returns to normal. This control method needs to accurately adjust the duty cycle (i.e. the ratio of on-time to period) and the blocking time to realize dynamic current limiting.

[0058] By changing the ratio of on-time to period, the current change can be quickly responded. When the current anomaly is detected, reducing the duty cycle can immediately reduce the output power to avoid overcurrent damage to the equipment.

[0059] When the current exceeds the set threshold, the drive signal is blocked until the current returns to normal. This mechanism ensures that energy output is stopped during the fault period to prevent continuous overload.

[0060] Since the multi-level converter has a complex structure, fine adjustment of the duty cycle and blocking time is needed to balance the voltage and current waveforms to avoid harmonic interference and system oscillation.

[0061] Therefore, the dynamic adjustment of the duty cycle and the blocking time is the core control strategy of the wave-by-wave current limiting control method of the multi-level converter, which is directly related to the safety and stability of the system.

[0062] The embodiment sets a wave-by-wave current limiting threshold, and when the inverter-side current reaches the wave-by-wave current limiting threshold, the duty cycle and the time of blocking drive are dynamically adjusted according to the current polarity.

[0063] Specifically, S200, when the inverter-side current reaches the threshold value, the duty cycle of the positive and negative modulation waves and the time of blocking drive during wave-by-wave current limiting are calculated by the capacitor voltage, the positive and negative bus voltages, and the switching period.

[0064] By real-time acquisition of positive bus voltage, negative bus voltage and capacitor voltage, combined with switch cycle to determine duty ratio and time of drive blocking, the current is kept stable during current limiting by each wave, avoiding triggering hardware overcurrent.

[0065] When the inverter side current does not reach the threshold value, the control method program is not executed.

[0066] Optionally, the capacitor voltage is monitored in real time by a voltage sensor installed on the DC bus capacitor or flying capacitor. For example, in the diode clamping topology, the voltage balance state of each stage capacitor needs to be monitored, and in the flying capacitor topology, the voltage change of the suspended capacitor needs to be detected.

[0067] In the partial control system, the capacitor voltage can also be calculated by adjusting the parameters of the modulation strategy (such as SPWM), which is suitable for simulation scenarios with mathematical models.

[0068] Optionally, the positive and negative voltages of the DC bus are directly measured by a voltage sensor (such as a Hall voltage sensor or a resistance voltage divider network). When measuring the positive bus voltage, the positive terminal of the voltmeter is connected to the positive bus and the negative terminal is connected to ground; when measuring the negative bus voltage, the positive terminal of the voltmeter is connected to the negative bus and the negative terminal is connected to ground. If the voltage of one pole to ground is abnormal (such as non-zero value), it indicates that there is an insulation problem with the other pole.

[0069] In a three-level inverter, the bus voltage relationship can be derived from the switch function model. For example, in a T-type three-level topology, the positive and negative bus voltages are directly related to the switch state and DC side capacitor voltage. The mathematical model is usually based on Kirchhoff's law, and decoupling control is achieved through coordinate transformation.

[0070] Optionally, when the multi-level converter occurs current limiting by each wave, periodic detection is realized by high-precision timer or built-in timing function of PWM controller. When the current exceeds the set threshold value, the controller will immediately turn off the power switch and enter the protection state until the next switch cycle to try to restart. It should be noted that the sampling frequency needs to be synchronized with the PWM modulation frequency to ensure that each switch cycle can be monitored.

[0071] In this embodiment, the inverter side current i is used as the judgment condition, and the duty ratio of the positive and negative modulation waves and the time of drive blocking are calculated from the capacitor voltage , the positive bus voltage , the negative bus voltage and the switch cycle After triggering current limiting, the current is kept stable during current limiting by each wave, avoiding triggering hardware overcurrent.

[0072] In this embodiment, the modulation wave duty ratio and drive blocking time are dynamically adjusted according to the first threshold value, such as Figure 3As shown, the step of determining whether the inverter-side current when the multi-level converter occurs wave-by-wave current limiting reaches a threshold value comprises:

[0073] S110, determining whether the inverter-side current when the multi-level converter occurs wave-by-wave current limiting is greater than a first threshold value.

[0074] The step of calculating the duty cycle of the positive and negative modulation waves and the time of the dead zone drive when the inverter-side current reaches a threshold value through the capacitor voltage, the positive and negative bus voltages and the switching period comprises:

[0075] S210, when the inverter-side current is greater than the first threshold value, calculating the duty cycle of the positive and negative modulation waves through the capacitor voltage and the positive bus voltage, and calculating the time of the dead zone drive through the capacitor voltage, the positive and negative bus voltages and the switching period.

[0076] When the inverter-side current is greater than the first threshold value, the duty cycle of the positive modulation wave is determined by the capacitor voltage and the positive bus voltage, and the time of the dead zone drive is related to the capacitor voltage, the positive and negative bus voltages and the switching period. Specifically, when the inverter-side current is greater than the first threshold value, the calculation formula of the duty cycle of the positive and negative modulation waves and the time of the dead zone drive is:

[0077] (1) ;

[0078] Wherein, and are the duty cycles of the positive and negative modulation waves, is the time of the dead zone drive, , and are the capacitor voltage, the positive bus voltage and the negative bus voltage, is the switching period.

[0079] The dynamic adjustment range of the duty cycle of the positive modulation wave is 0-100%, and the duty cycle of the negative modulation wave is a fixed value 1, at this time the negative bus voltage directly determines the negative amplitude of the output level. This scheme ensures the stable operation of the multi-level converter under wave-by-wave current limiting through real-time matching of the duty cycle and the bus voltage.

[0080] In the calculation formula of the time of the dead zone drive, reflects the difference between the positive bus voltage and the capacitor voltage, and determines the energy transfer direction, embodies the superposition effect of the negative bus voltage and the capacitor voltage, and affects the equivalent impedance of the current loop, directly determines the control frequency, and a smaller The current limiting precision can be improved, but the switching loss is increased. The time of the blocking drive is adjusted through the above formula to meet the DC side ripple suppression requirement of the multi-level converter, and the overvoltage risk of the device caused by uneven voltage is avoided by accurately controlling the turn-off timing of the inner tube.

[0081] When the inverter-side current is not greater than the first threshold value, it can be determined whether the inverter-side current when the multi-level converter occurs wave-by-wave current limiting is less than a second threshold value.

[0082] The embodiment further adjusts the duty ratio of the modulation wave and the blocking time of the drive according to the second threshold value. The step of determining whether the inverter-side current when the multi-level converter occurs wave-by-wave current limiting reaches a threshold value comprises:

[0083] S120, determining whether the inverter-side current when the multi-level converter occurs wave-by-wave current limiting is less than a second threshold value.

[0084] When the inverter-side current reaches a threshold value, the duty ratio of the positive and negative modulation waves and the time of the blocking drive when wave-by-wave current limiting occurs are calculated through the capacitor voltage, the positive and negative bus voltages, and the switching period. The step comprises:

[0085] S220, when the inverter-side current is less than the second threshold value, the duty ratio of the positive and negative modulation waves when wave-by-wave current limiting occurs is calculated through the capacitor voltage and the negative bus voltage, and the time of the blocking drive is calculated through the capacitor voltage, the positive and negative bus voltages, and the switching period.

[0086] When the inverter-side current is less than the second threshold value, the duty ratio of the negative modulation wave is adjusted to be dominated by the capacitor voltage and the negative bus voltage, and the time of the blocking drive is related to the capacitor voltage, the positive and negative bus voltages, and the switching period. Specifically, when the inverter-side current is less than the second threshold value, the duty ratio of the positive and negative modulation waves and the time of the blocking drive are calculated by the following formula:

[0087] (2) ;

[0088] wherein, and are the duty ratios of the positive and negative modulation waves, is the time of the blocking drive, , and are the capacitor voltage, the positive bus voltage, and the negative bus voltage, is the switching period.

[0089] When the duty ratio of the positive modulation wave is 0, the phase bridge arm is completely turned off in the positive half cycle, and no positive level is output. The duty ratio of the negative modulation wave needs to compensate for the influence of the capacitor voltage on the negative bus voltage, and the conduction time is extended in the negative modulation wave period to offset the influence of the capacitor voltage fluctuation on the output level.

[0090] The multi-level converter limits the current peak by adjusting the duty cycle in real time when limiting current per wave. When the current is detected to exceed the threshold, the positive / negative modulation wave duty cycle is dynamically adjusted. The positive modulation wave duty cycle is reduced to 0 to cut off the positive current path, and the negative modulation wave duty cycle is increased to absorb the reverse energy. The capacitor voltage term in the calculation formula of the negative modulation wave duty cycle is used to compensate the reverse current.

[0091] The time calculation formula of the blocking drive reflects the influence of the difference between the negative bus voltage and the capacitor voltage on energy transfer. The greater the difference, the longer the time. The coupling effect of the positive and negative bus voltages determines the upper limit, avoiding long blocking drive time leading to current discontinuity.

[0092] When the inverter-side current is not less than the second threshold, the duty cycle and the time calculation program of the blocking drive are ended.

[0093] In order to ensure stable output level, it is preferred to dynamically switch the duty cycle of the positive and negative modulation waves and the time of the blocking drive according to the current direction. In a preferred embodiment, the modulation wave duty cycle and the drive time are dynamically adjusted according to the inverter-side current direction (i>0 or i<0). By monitoring the current direction in real time, the modulation waveform is dynamically optimized in combination with the circuit parameters, taking into account system efficiency and reliability.

[0094] Specifically, the first threshold is configured as 0, and the second threshold is configured as 0. As Figure 4 shown, if the current i>0 when limiting current per wave occurs, the duty cycle of the positive and negative modulation waves and the time of the blocking drive are calculated according to formula (1); if the current i<0 when limiting current per wave occurs, the duty cycle of the positive and negative modulation waves and the time of the blocking drive are calculated according to formula (2).

[0095] When the current i>0 when limiting current per wave occurs, the current flows from the DC side to the AC side, and energy needs to be transferred through the positive modulation wave. At this time, the calculation of the blocking drive time needs to consider the difference between the positive bus voltage and the capacitor voltage to limit the current rise rate. By prolonging the blocking drive time, the positive current overshoot is suppressed, and the device is prevented from being damaged by overcurrent.

[0096] When the current i<0 when limiting current per wave occurs, the current flows from the AC side to the DC side, and energy needs to be fed back through the negative modulation wave. At this time, the blocking drive time needs to compensate for the coupling effect of the negative bus voltage and the capacitor voltage. It prevents the negative current from causing the capacitor voltage to be unbalanced, while avoiding overloading the reverse freewheeling diode. The positive modulation wave duty cycle is set to 0 to completely shut off the positive current path, avoiding bridge arm short circuit, for example: in a T-type three-level inverter, the negative modulation wave duty cycle needs to be set to to compensate for the fluctuation of the capacitor voltage.

[0097] The coupling relationship between capacitor voltage and bus voltage differs under different current directions, requiring dynamic adjustment. It can balance the voltage stress of each device. The drive time needs to be designed in conjunction with the dead time to avoid bridge arm shoot-through due to current commutation delay.

[0098] This embodiment achieves bidirectional current limiting protection by dynamically adjusting the duty cycle and drive time, based on accurate measurement of capacitor voltage and bus voltage.

[0099] This embodiment uses the control method of wave-by-wave current limiting of a diode-clamped three-level converter as an example for illustration, and should not be construed as a limitation on the type of multi-level converter.

[0100] The topology of a diode-clamped three-level converter is as follows: Figure 5 As shown, the parameter settings are as follows: DC bus voltage is 830V, the effective value of the load voltage during normal operation is 230V, the frequency is 50Hz, the switching frequency is 16kHz, the wave-by-wave current limiting threshold is 380A, and the load is a single-phase 6.8kW×3 asynchronous motor.

[0101] The current waveform of a diode-clamped three-level converter without the control method of this invention during wave-by-wave current limiting is as follows: Figure 6 As shown. By Figure 6 As can be seen, when the driver is restarted, the duty cycle is relatively small in the first cycle, so the current does not reach the current limiting threshold. In the second cycle, the current will continue to rise, with a ripple amplitude of 200A and a maximum current of 400A, which can easily trigger hardware overcurrent.

[0102] The effect of using the control method of this invention when applying wave-by-wave current limiting to a diode-clamped three-level converter is as follows: Figure 7 As shown. By Figure 7 As can be seen, the current remains basically stable, the ripple amplitude decreases to 110A, and the maximum current decreases to 365A, effectively avoiding triggering hardware overcurrent.

[0103] It should be noted that the multilevel converter of the present invention is not limited to the specific embodiments described above, and can be implemented in various other ways, such as... Figure 5 The diode-clamped three-level topology in the text is replaced with a T-type three-level topology, etc.

[0104] To address the issue of hardware overcurrent being easily triggered during wave-by-wave current limiting in multilevel converters, this embodiment calculates the duty cycle of the positive and negative modulation waves and the drive time based on the current inverter-side current, capacitor voltage, positive and negative bus voltages, and switching cycle, thereby keeping the current stable during wave-by-wave current limiting and avoiding triggering hardware overcurrent.

[0105] Example 2

[0106] Based on the same concept, the application also provides a multi-level converter wave-by-wave current limiting control system, and the control method provided in Embodiment 1 is applied. For the detailed description of the control method provided in Embodiment 1, reference can be made to the corresponding description in the above method embodiments, which will not be repeated here.

[0107] It can be understood that, in order to implement the above functions, the multi-level converter wave-by-wave current limiting control system provided in the embodiment comprises a hardware structure and / or a software module corresponding to each function. In combination with the units and algorithm steps of each example disclosed in the embodiment, the embodiment can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is implemented in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the technical solution of the embodiment.

[0108] A multi-level converter wave-by-wave current limiting control system, as shown in Figure 8 The system 300 comprises an inverter-side current judgment module 310 and a duty ratio and dead-time calculation module 320. In the system 300,

[0109] The inverter-side current judgment module is configured to determine whether the inverter-side current when the multi-level converter occurs wave-by-wave current limiting reaches a threshold value.

[0110] The duty ratio and dead-time calculation module is configured to calculate the duty ratio of positive and negative modulation waves and the time of dead-time when the inverter-side current reaches the threshold value by using the capacitor voltage, the positive and negative bus voltages and the switching period.

[0111] In the technical solution of the above embodiment, optionally, the step of determining whether the inverter-side current when the multi-level converter occurs wave-by-wave current limiting reaches a threshold value comprises:

[0112] determining whether the inverter-side current when the multi-level converter occurs wave-by-wave current limiting is greater than a first threshold value.

[0113] In the technical solution of the above embodiment, optionally, the step of calculating the duty ratio of positive and negative modulation waves and the time of dead-time when the inverter-side current reaches the threshold value by using the capacitor voltage, the positive and negative bus voltages and the switching period comprises:

[0114] when the inverter-side current is greater than the first threshold value, calculating the duty ratio of positive and negative modulation waves by using the capacitor voltage and the positive bus voltage, and calculating the time of dead-time by using the capacitor voltage, the positive and negative bus voltages and the switching period.

[0115] On the basis of the technical solutions in the above-described embodiments, optionally, when the inverter-side current is greater than the first threshold value, the duty ratios of the positive and negative modulation waves and the time of the dead-time drive are calculated according to the following formulas:

[0116]

[0117] wherein, and are duty ratios of the positive and negative modulation waves respectively, is the time of the dead-time drive, , and are the capacitor voltage, the positive bus voltage and the negative bus voltage respectively, is the switching period.

[0118] On the basis of the technical solutions in the above-described embodiments, optionally, the step of determining whether the inverter-side current reaches a threshold value when the multilevel converter occurs the wave-by-wave current limiting comprises the following steps.

[0119] Determining whether the inverter-side current is less than a second threshold value when the multilevel converter occurs the wave-by-wave current limiting.

[0120] On the basis of the technical solutions in the above-described embodiments, optionally, the step of calculating the duty ratios of the positive and negative modulation waves and the time of the dead-time drive when the inverter-side current reaches a threshold value comprises the following steps.

[0121] When the inverter-side current is less than the second threshold value, the duty ratios of the positive and negative modulation waves are calculated according to the capacitor voltage and the negative bus voltage, and the time of the dead-time drive is calculated according to the capacitor voltage, the positive bus voltage and the switching period.

[0122] On the basis of the technical solutions in the above-described embodiments, optionally, when the inverter-side current is less than the second threshold value, the duty ratios of the positive and negative modulation waves and the time of the dead-time drive are calculated according to the following formulas:

[0123]

[0124] wherein, and are duty ratios of the positive and negative modulation waves respectively, is the time of the dead-time drive, , and are the capacitor voltage, the positive bus voltage and the negative bus voltage respectively, is the switching period.

[0125] On the basis of the technical solutions in the above-described embodiments, optionally, the first threshold value is configured as 0, and the second threshold value is configured as 0.

[0126] ​​In order to solve the problem that the multi-level converter is easy to trigger the hardware overcurrent when limiting the current wave by wave, the duty ratio of the positive and negative modulation waves and the time of the blocking drive are calculated according to the current of the inverter side, the capacitor voltage, the positive and negative bus voltages and the switching period, so that the current is stable when limiting the current wave by wave, and the hardware overcurrent is avoided.

[0127] Embodiment 3

[0128] A computer device 400, as shown in the figure, comprises a memory 410, a processor 420 and a computer program 430 stored in the memory and executable on the processor, and the processor implements the steps of the multi-level converter current limiting control method when executing the computer program. For detailed description of the method, please refer to the corresponding description in the above method embodiments, which will not be repeated here. Figure 9

[0129] Embodiment 4

[0130] A computer readable storage medium, as shown in the figure, stores a computer program, and the steps of the multi-level converter current limiting control method are implemented when the processor executes the computer program. For detailed description of the method, please refer to the corresponding description in the above method embodiments, which will not be repeated here. Figure 10

[0131] The number of devices and the processing scale described herein are used to simplify the description of the present application. The application, modification and change of the present application are obvious to those skilled in the art.

[0132] Although the embodiments of the present application have been disclosed as above, it is not limited to the application and implementation listed in the specification and embodiments, and it can be fully applied to various fields suitable for the present application, and additional modifications can be easily realized by those skilled in the art, therefore, the present application is not limited to specific details and the figures shown and described herein, without departing from the general concept defined by the claims and the equivalent scope.

[0133] The device, computer device, non-volatile computer storage medium and method provided by the embodiments of the present application are corresponding, therefore, the device, computer device, non-volatile computer storage medium also has similar beneficial technical effects as the corresponding method, since the beneficial technical effects of the method have been described in detail above, therefore, the beneficial technical effects of the corresponding device, computer device, non-volatile computer storage medium will not be repeated here.

[0134] ​​Those skilled in the art will also appreciate that, in addition to being implemented in purely computer readable program code means, the controller can be implemented using logical programming, to cause the controller to perform the same functions, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, and the like. The controller can thus be considered as a hardware component, and the means for performing the various functions comprised therein can be considered as structures within the hardware component. Alternatively, or even additionally, the means for performing the various functions can be considered as both software elements implementing the method and structures within the hardware component.

[0135] The system, device or unit illustrated in the above embodiments can be implemented by a computer chip or entity, or by a product with certain functions. For the convenience of description, the above device is described in various units according to functions. Of course, the functions of each unit can be implemented in one or more software and / or hardware when implementing one or more embodiments of the present specification.

[0136] Those skilled in the art will appreciate that the embodiments of the present specification can be provided as a method, a system, or a computer program product. Therefore, the embodiments of the present specification can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present specification can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) having computer-usable program code embodied therein.

[0137] The present specification is described with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present specification. It should be understood that each flow and / or block in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The means for performing the functions specified in one or more flows and / or blocks.

[0138] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including instruction means, which implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The means for performing the functions specified in one or more flows and / or blocks.

[0139] These computer program instructions can also be loaded into computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable devices to generate computer-implemented processes, thus the instructions executed on the computer or other programmable devices provide a process for implementing the functions specified in the flowcharts Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0140] It should also be noted that the terms "comprising", "comprises", "including", "includes" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article or apparatus. An element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article or apparatus that comprises the recited element.

[0141] The specification can be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. The specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules can be located in both local and remote computer storage media including memory storage devices.

[0142] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between each of the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0143] The above only describes the embodiments of the specification and does not limit one or more embodiments of the specification. One or more embodiments of the specification can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the specification shall be included in the scope of claims of one or more embodiments of the specification.

Claims

1. A wave-by-wave current limiting control method for a multilevel converter, characterized in that, Includes the following steps: Determine whether the inverter-side current reaches the threshold when wave-by-wave current limiting occurs in a multilevel converter. When the inverter-side current reaches the threshold, the duty cycle of the positive and negative modulation waves and the time of the sealing drive are calculated by the capacitor voltage, the positive and negative bus voltages and the switching cycle during wave-by-wave current limiting. The step of determining whether the inverter-side current reaches the threshold when wave-by-wave current limiting occurs in the multilevel converter includes: Determine whether the inverter-side current is greater than the first threshold when wave-by-wave current limiting occurs in a multilevel converter. The step of calculating the duty cycle of the positive and negative modulation waves and the timing of the drive during wave-by-wave current limiting when the inverter-side current reaches the threshold, based on the capacitor voltage, positive and negative bus voltages, and the switching cycle, includes: When the inverter-side current is greater than the first threshold, the duty cycle of the positive and negative modulation waves during wave-by-wave current limiting is calculated using the capacitor voltage and the positive bus voltage. The sealing drive time is calculated using the capacitor voltage, the positive and negative bus voltages, and the switching cycle. The formulas for calculating the duty cycle of the positive and negative modulation waves and the sealing drive time are as follows: in, and These represent the duty cycles of the positive and negative modulation waves, respectively. For the time of sealing the driver, , and These are the capacitor voltage, positive bus voltage, and negative bus voltage, respectively. The switching cycle.

2. The wave-by-wave current limiting control method for a multilevel converter as described in claim 1, characterized in that, The step of determining whether the inverter-side current reaches the threshold when wave-by-wave current limiting occurs in the multilevel converter includes: Determine whether the inverter-side current is less than the second threshold when the multilevel converter experiences wave-by-wave current limiting.

3. The wave-by-wave current limiting control method for a multilevel converter as described in claim 2, characterized in that, The step of calculating the duty cycle of the positive and negative modulation waves and the timing of the drive during wave-by-wave current limiting when the inverter-side current reaches the threshold, based on the capacitor voltage, positive and negative bus voltages, and the switching cycle, includes: When the inverter side current is less than the second threshold, the duty cycle of the positive and negative modulation waves during wave-by-wave current limiting is calculated using the capacitor voltage and the negative bus voltage, and the sealing drive time is calculated using the capacitor voltage, the positive and negative bus voltages, and the switching cycle.

4. The wave-by-wave current limiting control method for a multilevel converter as described in claim 3, characterized in that, When the inverter-side current is less than the second threshold, the calculation formulas for the duty cycle of the positive and negative modulation waves and the drive time are as follows: in, and These represent the duty cycles of the positive and negative modulation waves, respectively. For the time of sealing the driver, , and These are the capacitor voltage, positive bus voltage, and negative bus voltage, respectively. The switching cycle.

5. The wave-by-wave current limiting control method for a multilevel converter as described in claim 2, characterized in that: The first threshold is configured to 0, and the second threshold is configured to 0.

6. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 5.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 5.

8. A wave-by-wave current limiting control system for a multilevel converter, using the method described in any one of claims 1 to 5, characterized in that: This includes an inverter-side current determination module, a duty cycle and encapsulation drive time calculation module; among which, The inverter-side current judgment module is used to determine whether the inverter-side current reaches the threshold when the multilevel converter experiences wave-by-wave current limiting. The duty cycle and sealing drive time calculation module is used to calculate the duty cycle of the positive and negative modulation waves and the sealing drive time during wave-by-wave current limiting by using capacitor voltage, positive and negative bus voltage and switching cycle when the inverter side current reaches the threshold.

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