Primary and secondary fusion column circuit breaker and capacitor power supply parameter optimization method
By alternating the measurement time slot and power extraction time slot within the power frequency cycle and dynamically allocating resources, the impact of the capacitor power extraction device on voltage measurement is resolved, improving measurement accuracy and power extraction efficiency while avoiding increased hardware costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHEJIANG PUCHENG ELECTRIC CO LTD
- Filing Date
- 2026-06-26
- Publication Date
- 2026-07-24
AI Technical Summary
In the prior art, the capacitor power supply device and the voltage measurement function share the same voltage divider capacitor, which causes the power supply branch to pull down the voltage of the voltage divider node through the isolation transformer, affecting the measurement accuracy. In addition, the switching noise of the DC-DC converter is coupled to the measurement branch, which cannot completely eliminate the influence of the power supply load and increases the hardware cost.
By alternately configuring measurement time slots and power-taking time slots within each power frequency cycle, voltage measurement is performed by turning off the DC-DC converter during the measurement time slot, and power supply and charging are performed by enabling the DC-DC converter during the power-taking time slot. Resources are dynamically allocated to ensure measurement accuracy and power-taking efficiency.
Without increasing hardware costs, the accuracy of voltage measurement and power extraction efficiency have been improved, the impact of power extraction branches on measurement accuracy has been resolved, and the energy storage status has been taken into account, achieving adaptive resource allocation.
Smart Images
Figure CN122456743A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power distribution automation technology, and in particular relates to a method for optimizing the parameters of a primary and secondary integrated pole-mounted circuit breaker and its capacitor power supply. Background Technology
[0002] Primary and secondary integrated pole-mounted circuit breakers are widely used in 10kV distribution networks. Their built-in capacitor-based power extraction devices utilize high-voltage capacitors to directly obtain power from the line, supplying power to secondary equipment such as smart terminals, sensors, and communication modules. Simultaneously, the same group of voltage-dividing capacitors also serves as the signal source for electronic voltage transformers, providing voltage measurement signals.
[0003] In existing technologies, the capacitor-based power extraction device and the voltage measurement function share the same voltage divider capacitor. The power extraction branch draws current from the voltage divider node through an isolation transformer. Due to the low impedance of the isolation transformer, it significantly pulls down the voltage at the voltage divider node, resulting in a negative deviation in the voltage measurement. Simultaneously, the switching noise of the DC-DC converter in the power extraction branch is coupled to the measurement branch through the shared node, affecting measurement accuracy. To address these issues, existing solutions add a high-impedance buffer to the measurement branch to reduce the load effect. However, this method cannot completely eliminate the influence of the power extraction branch and increases hardware costs. Therefore, there is an urgent need for a method that fundamentally eliminates the impact of the power extraction load on measurement accuracy without increasing hardware costs. Summary of the Invention
[0004] This application provides a method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker, which can solve the problem that the existing technology cannot completely eliminate the influence of the power supply branch and increases hardware costs.
[0005] In a first aspect, embodiments of this application provide a method for optimizing the capacitor-driven power supply parameters of a primary and secondary integrated pole-mounted circuit breaker, applied to a primary and secondary integrated pole-mounted circuit breaker, wherein the circuit breaker includes at least: electronic equipment, a DC-DC converter connected to the electronic equipment, a capacitor voltage divider node connected to the input terminal of the DC-DC converter, and a load and energy storage unit connected to the output terminal of the DC-DC converter; the method includes: Obtain the current measurement accuracy requirement level and the state of charge of the energy storage unit; Based on the required measurement accuracy level and the state of charge, the allocation ratio of measurement time slots and power-taking time slots within one power frequency cycle is determined; wherein, the measurement time slot is used to perform voltage measurement, the power-taking time slot is used to perform power-taking operation, and the smallest unit of the measurement time slot and the power-taking time slot is collectively referred to as a microtime slot; According to the allocation ratio, the measurement time slot and the power take-up time slot are alternately configured in each power frequency cycle; During the measurement time slot, the DC-DC converter is turned off and the voltage measurement value of the capacitor voltage divider node is collected; during the power draw time slot, the DC-DC converter is enabled and supplies power to the load and charges the energy storage unit.
[0006] The technical solutions described in this application embodiment have at least the following technical effects: The method for optimizing the capacitor-fed power supply parameters of a primary and secondary integrated pole-mounted circuit breaker provided in this application firstly acquires the current measurement accuracy requirement level and the state of charge (SOC) of the energy storage unit. In this step, the electronic device reads two state variables, which solves the problem in traditional schemes where measurement and power extraction occur simultaneously, making it impossible to adjust resource allocation according to actual needs, and the lack of consideration for the SOC, which may lead to insufficient power extraction at low power levels or excessively low measurement density at high power levels. Secondly, based on the measurement accuracy requirement level and SOC, the allocation ratio of measurement time slots to power extraction time slots within a power frequency cycle is determined. In this step, the two acquired parameters are used to calculate the ratio of the number of measurement time slots to the number of power extraction time slots within a power frequency cycle. The smallest unit of both measurement and power extraction time slots is collectively referred to as a micro-time slot, which resolves the contradiction that a fixed allocation ratio cannot simultaneously satisfy high-precision measurement and rapid power replenishment at low power levels. Then, according to the allocation ratio, the measurement time slot and the power extraction time slot are alternately configured in each power frequency cycle. In this step, the measurement time slot and the power extraction time slot are sequentially arranged on the time axis of one power frequency cycle to form an alternating timing template. Through the alternating configuration, the power extraction path in the measurement time slot is cut off, and the voltage divider node is only connected to the high impedance measurement circuit, so the measurement value is more real and accurate. Finally, during the measurement time slot, the DC-DC converter is turned off and the voltage measurement value of the capacitor voltage divider node is acquired. During the power extraction time slot, the DC-DC converter is enabled and supplies power to the load and charges the energy storage unit. In this step, when entering the measurement time slot, the electronic device outputs a control signal to turn off the DC-DC converter, stopping it from drawing current from the voltage divider node. At the same time, the ADC is started to acquire the instantaneous voltage value of the capacitor voltage divider node and store it in the buffer. This temporary power extraction path can prevent the acquired voltage value from being affected by the voltage divider. When entering the power extraction time slot, the electronic device enables the DC-DC converter, allowing it to draw current from the voltage divider node. After conversion, it supplies power to the load and charges the energy storage unit to replenish the previously consumed power. This method can maximize the power extraction capacity while ensuring measurement accuracy. In this method, by dynamically allocating the ratio of measurement time slots to power extraction time slots, the power extraction efficiency is maximized while ensuring voltage measurement accuracy and taking into account the energy storage state. This solves the problem that existing technologies cannot completely eliminate the influence of the power extraction branch and increase hardware costs.
[0007] Secondly, embodiments of this application provide a capacitor power supply parameter optimization device for a primary and secondary integrated pole-mounted circuit breaker, applied to the primary and secondary integrated pole-mounted circuit breaker. The circuit breaker includes at least: electronic equipment, a DC-DC converter connected to the electronic equipment, a capacitor voltage divider node connected to the input terminal of the DC-DC converter, and a load and energy storage unit connected to the output terminal of the DC-DC converter; the device includes: The status acquisition module is used to acquire the current measurement accuracy requirement level and the state of charge of the energy storage unit. The ratio determination module is used to determine the allocation ratio of measurement time slots and power extraction time slots within one power frequency cycle based on the measurement accuracy requirement level and the state of charge; wherein, the measurement time slot is used to perform voltage measurement, the power extraction time slot is used to perform power extraction operation, and the smallest unit of the measurement time slot and the power extraction time slot is collectively referred to as a micro time slot; The time slot configuration module is used to alternately configure the measurement time slot and the power take-up time slot in each power frequency cycle according to the allocation ratio; The measurement control module is used to turn off the DC-DC converter and acquire the voltage measurement value of the capacitor voltage divider node during the measurement time slot. A power supply control module is used to enable the DC converter to supply power to the load and charge the energy storage unit during the power supply time slot.
[0008] Thirdly, embodiments of this application provide a primary and secondary integrated pole-mounted circuit breaker, including an electronic device, a DC-DC converter connected to the electronic device, a capacitor voltage divider node connected to the input terminal of the DC-DC converter, and a load and energy storage unit connected to the output terminal of the DC-DC converter. The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the method described in any of the first aspects above.
[0009] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in any of the first aspects above.
[0010] Fifthly, embodiments of this application provide a computer program product that, when run on an electronic device, causes the electronic device to execute the capacitor power supply parameter optimization method for a primary and secondary fusion pole-mounted circuit breaker as described in any of the first aspects above.
[0011] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a flowchart illustrating a method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker according to an embodiment of this application. Figure 2 This is a schematic diagram of the structure of the capacitor power supply parameter optimization device for the primary and secondary integrated pole-mounted circuit breaker provided in this application embodiment and its application environment; Figure 3 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation
[0014] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.
[0015] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.
[0016] In related technologies, integrated primary and secondary pole-mounted circuit breakers are widely used in 10kV distribution networks. Their built-in capacitor-based power extraction devices utilize high-voltage capacitors to directly obtain power from the line, supplying power to secondary equipment such as smart terminals, sensors, and communication modules. Simultaneously, the same capacitor bank also serves as the signal source for electronic voltage transformers, providing voltage measurement signals. In existing technologies, the capacitor-based power extraction device and voltage measurement function share the same capacitor bank. The power extraction branch draws current from the voltage divider node through an isolation transformer. Due to the low impedance of the isolation transformer, it significantly lowers the voltage at the voltage divider node, resulting in a negative deviation in the voltage measurement value. Furthermore, the switching noise of the DC-DC converter in the power extraction branch is coupled to the measurement branch through the shared node, affecting measurement accuracy. To address these issues, existing solutions reduce the load effect by adding a high-impedance buffer to the measurement branch. However, this method cannot completely eliminate the influence of the power extraction branch and increases hardware costs. Therefore, there is an urgent need for a method that fundamentally eliminates the impact of the power extraction load on measurement accuracy without increasing hardware costs.
[0017] To address the aforementioned issues, this application provides a method for optimizing the capacitor-based power supply parameters of a primary and secondary integrated pole-mounted circuit breaker. First, the method acquires the current measurement accuracy requirement level and the state of charge (SOC) of the energy storage unit. In this step, the electronic device reads two state variables, resolving the problem in traditional solutions where measurement and power extraction occur simultaneously, making it impossible to adjust resource allocation according to actual needs. It also addresses the lack of consideration for the SOC, which may lead to insufficient power extraction at low charge levels or excessively low measurement density at high charge levels. Second, based on the measurement accuracy requirement level and SOC, the allocation ratio of measurement time slots to power extraction time slots within a power frequency cycle is determined. In this step, the two acquired parameters are used to calculate the ratio of the number of measurement time slots to the number of power extraction time slots within a power frequency cycle. The smallest unit of both measurement and power extraction time slots is collectively referred to as a micro-time slot, resolving the contradiction that a fixed allocation ratio cannot simultaneously satisfy high-precision measurement and rapid power replenishment at low charge levels. Then, according to the allocation ratio, the measurement time slot and the power extraction time slot are alternately configured in each power frequency cycle. In this step, the measurement time slot and the power extraction time slot are sequentially arranged on the time axis of one power frequency cycle to form an alternating timing template. Through the alternating configuration, the power extraction path in the measurement time slot is cut off, and the voltage divider node is only connected to the high impedance measurement circuit, so the measurement value is more real and accurate. Finally, during the measurement time slot, the DC-DC converter is turned off and the voltage measurement value of the capacitor voltage divider node is acquired. During the power extraction time slot, the DC-DC converter is enabled and supplies power to the load and charges the energy storage unit. In this step, when entering the measurement time slot, the electronic device outputs a control signal to turn off the DC-DC converter, stopping it from drawing current from the voltage divider node. At the same time, the ADC is started to acquire the instantaneous voltage value of the capacitor voltage divider node and store it in the buffer. This temporary power extraction path can prevent the acquired voltage value from being affected by the voltage divider. When entering the power extraction time slot, the electronic device enables the DC-DC converter, allowing it to draw current from the voltage divider node. After conversion, it supplies power to the load and charges the energy storage unit to replenish the previously consumed power. This method can maximize the power extraction capacity while ensuring measurement accuracy. In this method, by dynamically allocating the ratio of measurement time slots to power extraction time slots, the power extraction efficiency is maximized while ensuring voltage measurement accuracy and taking into account the energy storage state. This solves the problem that existing technologies cannot completely eliminate the influence of the power extraction branch and increase hardware costs.
[0018] The method for optimizing the capacitor power supply parameters of the primary and secondary integrated pole-mounted circuit breaker provided in this application embodiment can be applied to electronic devices. In this case, the electronic device is the executing subject of the method for optimizing the capacitor power supply parameters of the primary and secondary integrated pole-mounted circuit breaker provided in this application embodiment. This application embodiment does not impose any restrictions on the specific type of electronic device.
[0019] For example, electronic devices can be microprocessors, single-chip microcomputers, computing devices, or other processing devices connected to a wireless modem.
[0020] To better understand the method for optimizing the capacitor power supply parameters of the primary and secondary integrated pole-mounted circuit breaker provided in this application embodiment, the specific implementation process of the method for optimizing the capacitor power supply parameters of the primary and secondary integrated pole-mounted circuit breaker provided in this application embodiment will be described in an exemplary manner below.
[0021] Figure 1 This illustration shows a schematic flowchart of a method for optimizing the capacitor-driven power supply parameters of a primary and secondary integrated pole-mounted circuit breaker according to an embodiment of this application. The method is applied to a primary and secondary integrated pole-mounted circuit breaker, which includes at least: electronic equipment, a DC-DC converter connected to the electronic equipment, a capacitor voltage divider node connected to the input terminal of the DC-DC converter, and a load and energy storage unit connected to the output terminal of the DC-DC converter. The method for optimizing the capacitor-driven power supply parameters of the primary and secondary integrated pole-mounted circuit breaker includes: S100: Obtain the current measurement accuracy requirement level and the state of charge of the energy storage unit.
[0022] This method is understood to be applied to a primary and secondary integrated pole-mounted circuit breaker. The hardware involved is explained below: Primary and Secondary Integrated Pole-Mounted Circuit Breaker: A power distribution automation device integrating a high-voltage switch body, electronic sensors, and intelligent terminals. Electronic Equipment: Refers to the microcontroller (MCU) or embedded processor inside the circuit breaker, used to execute the method steps. DC-DC Converter: A power electronic device that converts the AC voltage output from the capacitor voltage divider node into a stable DC voltage, which can be controlled to operate or shut down via the enable terminal (EN). Capacitor Voltage Divider Node: A voltage divider point formed by a high-voltage capacitor C1 and a low-voltage capacitor C2 connected in series. The voltage of this node is proportional to the line voltage, serving as both a signal source for voltage measurement and an input source for power supply. Load: Secondary equipment of the circuit breaker, such as intelligent terminals, communication modules, sensors, etc. Energy Storage Unit: A supercapacitor or battery used to store electrical energy and supply power to the load when the line voltage drops or power supply is insufficient.
[0023] In this step, the measurement accuracy requirement level is a discrete or continuous quantity, reflecting the urgency of the current voltage measurement task regarding sampling accuracy and density. It can be obtained from the circuit breaker's protection unit or fault detection module. For example, when abnormal fluctuations occur in the line voltage or protection is activated, the level is automatically increased. Specifically, the electronic equipment periodically reads the accuracy requirement flag bit from its internal register, which is written by the upper-level protection algorithm. The state of charge (SOC) of the energy storage unit represents the percentage of remaining charge in the energy storage unit.
[0024] S200 determines the allocation ratio of measurement time slots and power-taking time slots within one power frequency cycle based on the required measurement accuracy level and state of charge. The measurement time slot is used to perform voltage measurement, and the power-taking time slot is used to perform power-taking operations. The smallest unit of measurement time slots and power-taking time slots is collectively referred to as microtime slots.
[0025] It can be understood that the power frequency cycle refers to the frequency cycle of an AC power system. A measurement time slot is a tiny, pre-defined time period during which electronic equipment performs voltage measurement operations. A power extraction time slot is a tiny, equally long time period during which electronic equipment performs power extraction operations (enabling the DC-DC converter). A micro-time slot is a collective term for both measurement and power extraction time slots, each with the same fixed duration. The allocation ratio refers to the percentage of measurement time slots out of the total number of micro-time slots within a single power frequency cycle.
[0026] The electronic equipment calculates a reasonable ratio of measurement time slots to power-taking time slots within the current power frequency cycle based on the required measurement accuracy level and state of charge (SOC). Specifically, it can first preset a baseline number of measurement time slots, such as 40 micro-time slots, with 20% for measurement and 80% for power taking. Then, it determines a first weighting coefficient based on the required measurement accuracy level; for example, a coefficient of 1.0 for normal monitoring, 2.0 for fault detection window, and 3.0 for waveform recording mode. Next, it determines a second weighting coefficient based on SOC; for example, a coefficient of 0.5 for SOC > 80% (reducing measurement, prioritizing power taking), a coefficient of 1.5 for SOC < 30% (increasing measurement, ensuring accuracy), and a coefficient of 1.0 for the intermediate region. Finally, it calculates the number of measurement time slots for the current cycle as the baseline number × the first coefficient × the second coefficient, limiting it to a preset minimum and maximum value. The final allocation ratio is then calculated as the number of measurement time slots / the total number of micro-time slots.
[0027] The automatic determination rules for the required measurement accuracy level can be as follows: Normal monitoring: voltage change rate <5% or periodic and no protection activation; Fault detection window: voltage dips exceeding 10% or current surges exceeding 20%; Recording mode: recording is triggered by protection action or manual triggering.
[0028] In one possible implementation, in S200, the allocation ratio of measurement time slots to power-taking time slots within a power frequency cycle is determined based on the required measurement accuracy level and state of charge, including: S210, determine the first weighting coefficient according to the required measurement accuracy level, and determine the second weighting coefficient according to the state of charge.
[0029] It can be understood that the first weighting coefficient (α) is a multiplier factor positively correlated with the required measurement accuracy level, used to amplify or reduce the number of reference measurement time slots. That is, the higher the required measurement accuracy level, the larger α is, thus increasing the number of measurement time slots. The second weighting coefficient (β) is a multiplier factor positively correlated with the state of charge (SOC) of the energy storage unit. That is, the lower the SOC, the smaller β is, thus reducing the number of measurement time slots (i.e., reducing the proportion of measurement and prioritizing power extraction).
[0030] Optionally, the measurement accuracy requirement levels include at least normal monitoring level, fault detection window level, and waveform recording mode level; the electronic equipment is configured with different first weighting coefficients for different measurement accuracy requirement levels, wherein the first weighting coefficient for fault detection window level is greater than the first weighting coefficient for normal monitoring level, and the first weighting coefficient for waveform recording mode level is greater than the first weighting coefficient for fault detection window level.
[0031] It is understandable that measurement accuracy requirements are divided into three levels: Normal monitoring level: The line is operating stably with no signs of faults, and only conventional sampling rates and durations are needed to meet monitoring requirements. Fault detection window level: The line exhibits abnormal symptoms (such as voltage dips or current surges), requiring increased sampling density and duration to accurately capture fault characteristics. Waveform recording mode level: A fault has triggered waveform recording, requiring extremely high sampling density and duration to record the complete transient waveform. Therefore, when configuring different first weighting coefficients for different measurement accuracy requirement levels, the first weighting coefficient for the fault detection window level is greater than that for the normal monitoring level, and the first weighting coefficient for the waveform recording mode level is greater than that for the fault detection window level.
[0032] This configuration allows measurement resources to be allocated more towards high-priority tasks.
[0033] Optionally, the second weighting coefficient is determined based on the state of charge, including: S211, when the state of charge is greater than the first preset threshold, the second weighting coefficient is set to a first value greater than 1.
[0034] It is understandable that if the state of charge is greater than the first preset threshold (the first preset threshold can be 80%), it means that the energy storage device is not in a hurry to charge. Therefore, the second weighting coefficient is increased to increase the proportion of the measurement time slot, so that the second weighting coefficient is set to a first value greater than 1 (such as 1.2), thereby improving the measurement accuracy of the capacitor voltage divider node voltage.
[0035] S212, when the state of charge is less than the second preset threshold, the second weighting coefficient is set to a second value less than 1.
[0036] It is understandable that if the state of charge is less than the second preset threshold, it means that the energy storage device is short of power. Therefore, the second weighting coefficient is reduced to reduce the proportion of the measurement time slot, so that the second weighting coefficient is set to a second value less than 1 (such as 0.8), thereby improving the charging speed of the energy storage device.
[0037] S213, when the state of charge is between the second preset threshold and the first preset threshold, the second weighting coefficient is set to 1.
[0038] It is understandable that a state of charge between the second preset threshold and the first preset threshold means that the energy storage device is in a normal state between power shortage and power availability. Therefore, the second weighting coefficient is set to 1.
[0039] This configuration, with its three-segment interval management of the second weighting coefficient, can reflect the hysteresis characteristics of energy storage management and avoid frequent jumps in the SOC at the threshold boundary that could cause oscillations in the second weighting coefficient.
[0040] S220: Obtain the line voltage change rate of the road to be identified, and determine the third weighting coefficient based on the line voltage change rate.
[0041] The line voltage change rate refers to the magnitude of voltage change at the capacitor voltage divider node per unit time, usually expressed as a percentage or absolute value per millisecond. It reflects the severity of line voltage fluctuations and is calculated as: |V(t) - V(tT)| / (T × V_rated), where V(t) is the current voltage measurement, V(tT) is the voltage measurement after T, and V_rated is the system's nominal voltage (rated voltage). The third weighting coefficient (γ) is a multiplier factor positively correlated with the voltage change rate; that is, the larger the change rate, the larger γ, increasing the number of measurement time slots (because longer sampling time is needed to capture waveforms during severe voltage fluctuations). After determining the line voltage change rate, γ is determined based on a preset threshold, for example: γ = 1.0 when the change rate is <10% / cycle; γ = 1.2 when the change rate is between 10% and 30% / cycle; and γ = 1.5 when the change rate is >30% / cycle. The introduction of the third weighting coefficient (γ) allows the allocation ratio to respond to voltage surges, prioritizing measurement accuracy during fault conditions.
[0042] S230, based on the preset number of reference measurement time slots, the product of the first weighting coefficient, the second weighting coefficient and the third weighting coefficient, calculates the number of candidate measurement time slots for the current period.
[0043] It can be understood that the number of reference measurement time slots (M_base) is a preset fixed value, corresponding to the number of measurement time slots under the default working condition (normal monitoring, normal SOC, stable voltage). After that, multiply the number of reference measurement time slots, the first weighting coefficient, the second weighting coefficient, and the third weighting coefficient, and the obtained product is the number of candidate measurement time slots M_candidate for the current period.
[0044] S240, obtain the historical number of measurement time slots in the previous power frequency period, and perform weighted averaging on the candidate number of measurement time slots and the historical number of measurement time slots to obtain the number of measurement time slots for the current period; among them, the weight of the historical number of measurement time slots is less than the weight of the candidate number of measurement time slots.
[0045] It can be understood that the historical number of measurement time slots M_prev refers to the number of measurement time slots actually used in the previous power frequency period. Mix the candidate number of measurement time slots and the historical value in proportion. The formula is: M_current = (1 - k) × M_candidate + k × M_prev, where k is the historical weight and 0 < k < 0.5, to obtain the number of measurement time slots M_current for the current period. Introducing the historical number of measurement time slots can enhance the stability of the system and avoid the adverse effects brought by frequent switching of the scheduling mode.
[0046] S250, limit the number of measurement time slots for the current period between the preset minimum number of measurement time slots and the maximum number of measurement time slots.
[0047] It can be understood that in order to provide a safety margin to prevent the system from getting out of control due to extreme values of the algorithm, if M_current < the minimum number of measurement time slots M_min, it is forcibly set to M_min; if M_current > the maximum number of measurement time slots M_max, it is forcibly set to M_max.
[0048] S260, determine the allocation ratio according to the ratio of the number of measurement time slots for the current period to the total number of micro time slots.
[0049] It can be understood that dividing the number of measurement time slots for the current period by the total number of micro time slots, the obtained ratio is the allocation ratio.
[0050] With such settings, the measurement accuracy requirement level, the state of charge of the energy storage device, and the voltage stability are considered, the historical number of measurement time slots is introduced to enhance the stability of the system, and the minimum and maximum values are also set, making the obtained number of measurement time slots more reasonable.
[0051] S300, alternately configure measurement time slots and power-taking time slots in each power frequency period according to the allocation ratio.
[0052] As can be understood, alternating configuration refers to sequentially arranging measurement time slots and power-feeding time slots on the time axis. For example, the first M micro-time slots are measurement time slots, and the following NM are power-feeding time slots. This step is used to determine whether each micro-time slot is a measurement time slot or a power-feeding time slot within one power frequency cycle. The alternating configuration of measurement time slots and power-feeding time slots can be achieved through a timer.
[0053] S400, during the measurement time slot, shuts down the DC-DC converter and acquires the voltage measurement value of the capacitor divider node; during the power draw time slot, it enables the DC-DC converter and supplies power to the load and charges the energy storage unit.
[0054] It is understandable that during the measurement time slot, the electronic equipment first outputs a shutdown signal to stop the DC-DC converter from drawing power. At this time, the voltage divider node is only connected to the high-impedance measurement circuit (usually an operational amplifier buffer or ADC input), which can eliminate the pull-down effect of the power-drawing load on the voltage divider node. Then, the electronic equipment immediately starts ADC sampling to obtain an accurate line voltage measurement value. During the power-drawing time slot, the electronic equipment outputs an enable signal to start the DC-DC converter, drawing current from the voltage divider node. After voltage conversion by the DC-DC converter, it provides operating power to the load on one hand, and charges the energy storage unit on the other hand, replenishing the electrical energy consumed in the previous measurement time slot or storing energy for future opening and closing.
[0055] This setup achieves an adaptive balance between measurement accuracy and power extraction efficiency without increasing hardware costs, thus solving the problem that existing technologies cannot completely eliminate the influence of the power extraction branch and increase hardware costs.
[0056] Optionally, the method also includes: S510 monitors the buffer status of opening and closing operation signals and voltage measurement data in real time.
[0057] It can be understood that the circuit breaker opening / closing operation signal is a hardware interrupt signal issued by the circuit breaker operating mechanism or protection control unit, indicating that an opening or closing operation is about to be performed. Real-time detection is performed to check for circuit breaker opening / closing operation signals and voltage measurement data. For voltage measurement data, the buffer status is checked; the buffer status refers to the current fill level of the circular buffer (such as a DMA circular buffer) storing the voltage sampling data, for example, the percentage of used space.
[0058] When the S520 detects a circuit breaker operation signal, it forcibly enables the DC-DC converter with high priority and disables the alternating scheduling of the measurement time slot and the power supply time slot, continuously maintaining the preset emergency duration.
[0059] It is understandable that high priority means that the response priority of this event is higher than that of normal time slot scheduling, buffer overflow handling, and low-priority events, ensuring the fastest response. When a circuit breaker operation signal is detected, in order to ensure that the circuit breaker can be fully opened or closed, the DC-DC converter is forcibly enabled to provide power in the form of a highest priority interrupt, and a preset emergency duration is maintained. Because it is an interrupt, the alternation scheduling of measurement time slots and power supply time slots is blocked during the emergency duration to ensure that the circuit breaker can be fully opened or closed.
[0060] S530, when it detects that the cache status indicates that the storage space is about to be full, temporarily alternates scheduling during the power-on time slot with low priority to continuously execute multiple measurement time slots to read the voltage measurement data in the cache, and then resumes alternating scheduling.
[0061] Understandably, low priority refers to an event whose response priority is lower than high priority events, but higher than interrupt events in normal time slot scheduling and buffer overflow handling. Circuit breaker opening and closing are high priority events; therefore, while circuit breaker opening and closing processing is in progress, low priority events are suspended and wait. When a buffer status indicating that the storage space is about to be full is detected, low priority events are executed. In interrupt events, alternating scheduling is paused, and multiple measurement time slots are executed continuously to ensure sufficient time to read the voltage measurement data from the buffer.
[0062] This configuration clarifies the execution process of the two events: the opening and closing of the circuit breaker and the buffer state being about to reach its limit.
[0063] Optionally, the method also includes: S610 acquires voltage sample values and corresponding timestamps collected from multiple consecutive measurement time slots.
[0064] This can be understood as obtaining voltage sample values from multiple consecutive measurement time slots in the form of a discrete sequence, and then obtaining the timestamps corresponding to the voltage sample values in the same discrete sequence form. There must be at least four consecutive measurement time slots.
[0065] The S620 reconstructs the complete voltage waveform based on voltage sample values and timestamps using an interpolation algorithm; the interpolation algorithm is either cubic spline interpolation or Kalman filtering.
[0066] It can be understood that after obtaining the discrete sequence of voltage sample values and the corresponding discrete sequence of timestamps, an interpolation algorithm is used to fit the two discrete sequences into a continuous discrete function. The interpolation algorithm can be cubic spline interpolation or Kalman filtering. Cubic spline interpolation is a common method that fits discrete points using a piecewise cubic polynomial, essentially ensuring the continuity of the second derivative and a smooth waveform. Kalman filtering is another common recursive estimation algorithm, also used to estimate the voltage value at each moment of the voltage waveform.
[0067] Optionally, an interpolation algorithm is used to reconstruct the complete voltage waveform, including: S621, using the sampled values of at least four consecutive measurement time slots as interpolation nodes, constructs a cubic polynomial.
[0068] It is understandable that the electronic device takes four consecutive measurement time slots as sampling points (t0,v0), (t1,v1), (t2,v2), and (t3,v3) to solve for the four coefficients of a cubic polynomial, f(t) = a·t³ + b·t² + c·t + d, such that the polynomial passes through these four sampling points.
[0069] S622 fills in all missing points between adjacent measurement time slots with the same interpolation step size as the micro-time slot width to generate a continuous voltage waveform.
[0070] It can be understood that by using an interpolation step size of micro-slot width, all missing points between adjacent measurement slots (i.e., missing points in the power-taking slots between adjacent measurement slots) are filled in, and then the voltage values of the missing points are fitted by an interpolation algorithm to obtain an uninterrupted voltage waveform, i.e., a continuous voltage waveform.
[0071] This configuration enables the recovery from sparse sampling to dense waveforms, meeting the protection equipment's requirement for a high sampling rate.
[0072] S630 takes the reconstructed complete voltage waveform as the voltage measurement result and outputs it to the protection judgment unit or voltage monitoring unit of the circuit breaker to perform at least one of the following operations: line fault detection, voltage over-limit alarm, or fault recording.
[0073] It is understandable that the protection judgment unit refers to the module inside the circuit breaker that performs logic such as overcurrent, instantaneous trip, and zero-sequence protection, while the voltage monitoring unit refers to the module that monitors indicators such as the effective value of line voltage, harmonics, and voltage sag. Both are common functional modules in existing circuit breakers. The fitted and reconstructed complete voltage waveform is used as the voltage measurement result and output to the protection judgment unit or voltage monitoring unit of the circuit breaker to perform at least one of the following operations: line fault detection, voltage over-limit alarm, or fault waveform recording.
[0074] This setup clarifies how to obtain a continuous and complete voltage waveform after employing an alternating detection method of measurement time slots and power-taking time slots, and what operations can be performed on the complete voltage waveform.
[0075] Optionally, the width of the micro-slot is from 50 microseconds to 200 microseconds; the electronic equipment limits the number of measurement slots within each power frequency cycle to an adjustable range of 5% to 90% of the total number of micro-slots.
[0076] It is understood that the micro-timeslot width is the time base of this application. If the width is less than 50 μs, the real-time requirements of the electronic equipment are too high (interrupt frequency > 20 kHz), which may affect other tasks; if it is greater than 200 μs, the measurement timeslot granularity is too coarse, and the allocation ratio cannot be flexibly adjusted. Therefore, the width of the micro-timeslot is set to 50 microseconds to 200 microseconds. The 5% lower limit ensures that even under the most extreme power demand, basic voltage measurement capability can still be retained; the 90% upper limit ensures that even under the most extreme measurement demand, at least 10% of the power supply time slot is retained to avoid complete depletion of energy storage.
[0077] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0078] Corresponding to the method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker described in the above embodiments, this application also provides a device for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker. Each unit of this device can implement each step of the method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker. Figure 2 The diagram shows a structural block diagram of a capacitor power supply parameter optimization device for a primary and secondary integrated pole-mounted circuit breaker provided in this application embodiment. For ease of explanation, only the parts related to this application embodiment are shown.
[0079] Reference Figure 2 This device is applied to a primary and secondary integrated pole-mounted circuit breaker. The circuit breaker includes at least: electronic equipment, a DC-DC converter connected to the electronic equipment, a capacitor voltage divider connected to the input terminal of the DC-DC converter, and a load and energy storage unit connected to the output terminal of the DC-DC converter. The device includes: The status acquisition module is used to acquire the current measurement accuracy requirement level and the state of charge of the energy storage unit. The ratio determination module is used to determine the allocation ratio of measurement time slots and power extraction time slots within a power frequency cycle based on the required measurement accuracy level and state of charge. The measurement time slots are used to perform voltage measurements, and the power extraction time slots are used to perform power extraction operations. The smallest unit of both measurement and power extraction time slots is collectively referred to as a microtime slot. The time slot configuration module is used to alternately configure the measurement time slot and the power take-off time slot in each power frequency cycle according to the allocation ratio; The measurement control module is used to turn off the DC-DC converter and acquire the voltage measurement value of the capacitor divider node during the measurement time slot; The power supply control module is used to enable the DC-DC converter to supply power to the load and charge the energy storage unit during the power supply time slot.
[0080] It should be noted that the information interaction and execution process between the above-mentioned units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.
[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is used as an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the device can be divided into different functional units to complete all or part of the functions described above. The functional units in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0082] This application also provides a primary and secondary integrated pole-mounted circuit breaker, including electronic equipment, a DC-DC converter connected to the electronic equipment, a capacitor voltage divider node connected to the input terminal of the DC-DC converter, and a load and energy storage unit connected to the output terminal of the DC-DC converter. Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 3 As shown, the electronic device 4 of this embodiment includes: at least one processor 40 ( Figure 3 Only one is shown in the image), at least one memory 41 ( Figure 3 (Only one is shown in the image) and a computer program 42 stored in the at least one memory 41 and executable on the at least one processor 40. When the processor 40 executes the computer program 42, it causes the electronic device 4 to implement the steps in the above embodiments of the capacitor power supply parameter optimization method for any of the primary and secondary fusion pole-mounted circuit breakers, or causes the electronic device 4 to implement the functions of each unit in the above embodiments of the devices.
[0083] For example, the computer program 42 may be divided into one or more units, which are stored in the memory 41 and executed by the processor 40 to complete this application. The one or more units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program 42 in the electronic device 4.
[0084] The electronic device 4 may be a microcontroller or a microprocessor. The electronic device 4 may include, but is not limited to, a processor 40 and a memory 41. Those skilled in the art will understand that... Figure 3 This is merely an example of electronic device 4 and does not constitute a limitation on electronic device 4. It may include more or fewer components than shown, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, buses, etc.
[0085] The processor 40 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.
[0086] In some embodiments, the memory 41 may be an internal storage unit of the electronic device 4, such as a hard disk or memory of the electronic device 4. In other embodiments, the memory 41 may be an external storage device of the electronic device 4, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 4. Furthermore, the memory 41 may include both internal and external storage units of the electronic device 4. The memory 41 is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory 41 can also be used to temporarily store data that has been output or will be output.
[0087] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.
[0088] This application provides a computer program product that, when run on an electronic device, causes the electronic device to perform the steps in any of the above method embodiments.
[0089] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to an electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.
[0090] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0091] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0092] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A method for optimizing the parameters of the capacitor-driven power supply in a primary and secondary integrated pole-mounted circuit breaker, characterized in that, The method is applied to a primary and secondary integrated pole-mounted circuit breaker, wherein the circuit breaker includes at least: electronic equipment, a DC-DC converter connected to the electronic equipment, a capacitor voltage divider node connected to the input terminal of the DC-DC converter, and a load and energy storage unit connected to the output terminal of the DC-DC converter; the method includes: Obtain the current measurement accuracy requirement level and the state of charge of the energy storage unit; Based on the required measurement accuracy level and the state of charge, the allocation ratio of measurement time slots and power-taking time slots within one power frequency cycle is determined; wherein, the measurement time slot is used to perform voltage measurement, the power-taking time slot is used to perform power-taking operation, and the smallest unit of the measurement time slot and the power-taking time slot is collectively referred to as a microtime slot; According to the allocation ratio, the measurement time slot and the power take-up time slot are alternately configured in each power frequency cycle; During the measurement time slot, the DC-DC converter is turned off and the voltage measurement value of the capacitor voltage divider node is collected; during the power draw time slot, the DC-DC converter is enabled and supplies power to the load and charges the energy storage unit.
2. The method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker as described in claim 1, characterized in that, The step of determining the allocation ratio of measurement time slots to power-taking time slots within a power frequency cycle based on the required measurement accuracy level and the state of charge includes: The first weighting coefficient is determined based on the required measurement accuracy level, and the second weighting coefficient is determined based on the state of charge. Obtain the line voltage change rate of the road to be identified, and determine the third weighting coefficient based on the line voltage change rate; The number of candidate measurement time slots for the current period is calculated based on the product of the preset number of reference measurement time slots, the first weighting coefficient, the second weighting coefficient, and the third weighting coefficient. The number of historical measurement time slots in the previous power frequency cycle is obtained, and the number of candidate measurement time slots and the number of historical measurement time slots are weighted and averaged to obtain the number of measurement time slots in the current cycle; wherein, the weight of the number of historical measurement time slots is less than the weight of the number of candidate measurement time slots. The number of measurement time slots in the current cycle is limited to between a preset minimum number of measurement time slots and a preset maximum number of measurement time slots; The allocation ratio is determined based on the ratio of the number of measurement time slots in the current cycle to the total number of micro time slots.
3. The method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker as described in claim 2, characterized in that, The measurement accuracy requirement levels include at least a normal monitoring level, a fault detection window level, and a waveform recording mode level; the electronic device is configured with different first weighting coefficients for different measurement accuracy requirement levels, wherein the first weighting coefficient of the fault detection window level is greater than the first weighting coefficient of the normal monitoring level, and the first weighting coefficient of the waveform recording mode level is greater than the first weighting coefficient of the fault detection window level.
4. The method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker as described in claim 2, characterized in that, The step of determining the second weighting coefficient based on the state of charge includes: When the state of charge is greater than the first preset threshold, the second weighting coefficient is set to a first value greater than 1; When the state of charge is less than the second preset threshold, the second weighting coefficient is set to a second value less than 1; When the state of charge is between the second preset threshold and the first preset threshold, the second weighting coefficient is set to 1.
5. The method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker as described in claim 1, characterized in that, The method further includes: Real-time monitoring of the buffer status of opening and closing operation signals and voltage measurement data; When the opening and closing operation signal is detected, the DC converter is forcibly enabled with high priority, and the alternating scheduling of the measurement time slot and the power supply time slot is blocked, and the preset emergency duration is continued. When the cache status indicates that the storage space is about to be full, the alternating schedule is temporarily performed with low priority during the power-on time slot to continuously execute multiple measurement time slots to read the voltage measurement data in the cache, and then the alternating schedule is resumed.
6. The method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker as described in claim 1, characterized in that, The method further includes: Obtain the voltage sample values and corresponding timestamps collected in multiple consecutive measurement time slots; Based on the voltage sample value and the timestamp, an interpolation algorithm is used to reconstruct the complete voltage waveform; wherein, the interpolation algorithm is cubic spline interpolation or Kalman filtering; The reconstructed complete voltage waveform is used as the voltage measurement result and output to the protection judgment unit or voltage monitoring unit of the circuit breaker to perform at least one of the following operations: line fault detection, voltage over-limit alarm, or fault recording.
7. The method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker as described in claim 6, characterized in that, The method of reconstructing the complete voltage waveform using an interpolation algorithm includes: A cubic polynomial is constructed using the sampled values of at least four consecutive measurement time slots as interpolation nodes; By using the same interpolation step size as the micro-slot width, all missing points between adjacent measurement slots are filled to generate a continuous voltage waveform.
8. The method for optimizing the capacitor power supply parameters of a primary and secondary integrated pole-mounted circuit breaker as described in claim 1, characterized in that, The width of the micro-timeslot is from 50 microseconds to 200 microseconds; the electronic device limits the number of measurement time slots within each power frequency cycle to an adjustable range of 5% to 90% of the total number of micro-time slots.
9. A device for optimizing the parameters of a capacitor-driven power supply in a primary and secondary integrated pole-mounted circuit breaker, characterized in that, An application is made to a primary and secondary integrated pole-mounted circuit breaker, the circuit breaker comprising at least: electronic equipment, a DC-DC converter connected to the electronic equipment, a capacitor voltage divider connected to the input terminal of the DC-DC converter, and a load and energy storage unit connected to the output terminal of the DC-DC converter; the device includes: The status acquisition module is used to acquire the current measurement accuracy requirement level and the state of charge of the energy storage unit. The ratio determination module is used to determine the allocation ratio of measurement time slots and power extraction time slots within one power frequency cycle based on the measurement accuracy requirement level and the state of charge; wherein, the measurement time slot is used to perform voltage measurement, the power extraction time slot is used to perform power extraction operation, and the smallest unit of the measurement time slot and the power extraction time slot is collectively referred to as a micro time slot; The time slot configuration module is used to alternately configure the measurement time slot and the power take-up time slot in each power frequency cycle according to the allocation ratio; The measurement control module is used to turn off the DC-DC converter and acquire the voltage measurement value of the capacitor voltage divider node during the measurement time slot. A power supply control module is used to enable the DC converter to supply power to the load and charge the energy storage unit during the power supply time slot.
10. A primary and secondary integrated pole-mounted circuit breaker, characterized in that, The device includes an electronic device, a DC-DC converter connected to the electronic device, a capacitor voltage divider node connected to the input terminal of the DC-DC converter, a load and an energy storage unit connected to the output terminal of the DC-DC converter, wherein the electronic device includes a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor executes the computer program to implement the method as described in any one of claims 1 to 8.