Semiconductor device and method of manufacturing the same

Abstract

This application provides a semiconductor device and its fabrication method, belonging to the field of semiconductor technology. A first gate oxide layer and a first gate electrode layer of a first transistor are sequentially stacked on a corresponding first active region. The boundaries of the first gate oxide layer and the first gate electrode layer extending along a first direction do not exceed the boundaries of the corresponding first active region. An insulating layer is located on a portion of the substrate of the first device region and covers the sidewalls of the first gate oxide layer extending along the first direction and a portion of the sidewalls of the first gate electrode layer extending along the first direction. A first portion of the first gate sidewall is located on the insulating layer and covers the remaining sidewalls of the first gate electrode layer extending along the first direction; a second portion is located on the corresponding first active region and covers the sidewalls of the first gate electrode layer extending along a second direction. This application narrows the width of the first gate oxide layer and the first gate electrode layer along the second direction, thereby reducing the area of ​​the semiconductor device. The insulating layer can avoid channel punch-through and source-drain short-circuit problems.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its fabrication method. Background Technology

[0002] A DAC (Digital Analog Converter) chip can convert digital signals into analog signals and is widely used in various electronic systems. Its core function is to convert digital codes into a series of discrete step voltages or currents, thereby realizing analog output and control.

[0003] DAC chips typically use NMOS transistors as switches for negative grayscale voltage and PMOS transistors as switches for positive grayscale voltage. In the circuit layout of a DAC chip, NMOS transistors are arranged in an array, and PMOS transistors are also arranged in an array. The NMOS transistor array and PMOS transistor array are arranged in an alternating pattern, resulting in a large area and making it difficult to miniaturize the DAC chip. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide a semiconductor device and a method for fabricating the same, so as to solve the problem of large area of ​​DAC chips in the prior art.

[0005] This application provides a semiconductor device, including a substrate, an insulating layer, and at least one first transistor;

[0006] The substrate has a first device region, and the first device region has at least one first active region within the substrate. The first active regions extend along a first direction and are spaced apart along a second direction.

[0007] The first transistor includes a first gate oxide layer, a first gate electrode layer, and a first gate sidewall. The first gate oxide layer and the first gate electrode layer are stacked sequentially on the corresponding first active region. The boundaries of the first gate oxide layer and the first gate electrode layer extending along the first direction do not exceed the boundaries of the corresponding first active region extending along the first direction.

[0008] The insulating layer is located on a portion of the substrate in the first device region and covers the sidewalls of the first gate oxide layer extending along the first direction and a portion of the sidewalls of the first gate electrode layer extending along the first direction.

[0009] The first gate sidewall includes a first portion and a second portion. The first portion is located on the insulating layer and covers the remaining sidewall of the first gate electrode layer extending along the first direction. The second portion is located on the corresponding first active region and covers the first gate oxide layer and the sidewall of the first gate electrode layer extending along the second direction.

[0010] In some embodiments, the boundaries of the first gate oxide layer and the first gate electrode layer extending along the first direction overlap with the boundaries of the corresponding first active region extending along the first direction.

[0011] In some embodiments, the substrate further includes a second device region, wherein the second device region has a second active region within the substrate;

[0012] The semiconductor device further includes a second transistor, the second transistor comprising a second gate oxide layer, a second gate electrode layer, and a second gate sidewall, the second gate oxide layer and the second gate electrode layer being sequentially stacked on the second active region; and...

[0013] The second gate sidewall is located on the substrate and the second active region of the second device region, and covers the sidewalls of the second gate oxide layer and the second gate electrode layer.

[0014] In some embodiments, the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

[0015] In some embodiments, the insulating layer and the second gate oxide layer are located in the same layer and are formed simultaneously.

[0016] In some embodiments, the thickness of both the insulating layer and the second gate oxide layer is greater than or equal to 700 angstroms; and / or, the operating voltage of the second transistor is greater than or equal to 32V.

[0017] In some embodiments, the first device region is a DAC device region, a portion of the first transistors are NMOS transistors, and another portion of the first transistors are PMOS transistors.

[0018] This application also provides a method for fabricating a semiconductor device, comprising:

[0019] A substrate is provided, the substrate having a first device region, the first device region having at least one first active region within the substrate, the first active region extending along a first direction and spaced apart along a second direction;

[0020] An insulating layer is formed on the substrate of the first device region, the insulating layer being located on both sides of the first active region extending along the first direction;

[0021] A first gate oxide layer and a first gate electrode layer are formed in sequence on each of the first active regions. The boundaries of the first gate oxide layer and the first gate electrode layer extending along the first direction do not exceed the boundaries of the corresponding first active region extending along the first direction. The insulating layer covers the sidewalls of the first gate oxide layer extending along the first direction and a portion of the sidewalls of the first gate electrode layer extending along the first direction.

[0022] The first gate sidewall is formed, comprising a first portion and a second portion, the first portion being located on the insulating layer and covering the remaining sidewall of the first gate electrode layer extending along the first direction, and the second portion being located on the corresponding first active region and covering the sidewall of the first gate electrode layer extending along the second direction; and,

[0023] The first active regions on both sides of the first gate electrode layer along the first direction are doped with source and drain doping.

[0024] In some embodiments, the substrate further includes a second device region, wherein the second device region has a second active region within the substrate;

[0025] While forming the insulating layer, a second gate oxide layer is also formed on the second active region;

[0026] While forming the first gate electrode layer, a second gate electrode layer is also formed on the second gate oxide layer;

[0027] While forming the first gate sidewall, a second gate sidewall is also formed on the substrate and the second active region of the second device region, the second gate sidewall covering the sidewall of the second gate electrode layer; and

[0028] While performing source / drain doping on the first active region, source / drain doping is also performed on the second active regions on both sides of the second gate electrode layer along the first direction.

[0029] In some embodiments, the step of forming the insulating layer and the second gate oxide layer includes:

[0030] A layer of oxide material is deposited all over the substrate; and,

[0031] The oxide material layer is etched such that the remaining oxide material layer in the first device region constitutes the insulating layer, and the remaining oxide material layer in the second device region constitutes the second gate oxide layer.

[0032] Beneficial effects:

[0033] This application provides a semiconductor device and a method for fabricating the same, comprising a substrate, an insulating layer, and at least one first transistor; the substrate has a first device region, and the first device region has at least one first active region within the substrate, the first active regions extending along a first direction and spaced apart along a second direction; the first transistor includes a first gate oxide layer, a first gate electrode layer, and a first gate sidewall, the first gate oxide layer and the first gate electrode layer being stacked sequentially on the corresponding first active region, the boundaries of the first gate oxide layer and the first gate electrode layer extending along the first direction not exceeding the boundaries of the corresponding first active region extending along the first direction; the insulating layer is located on a portion of the substrate of the first device region and covers the sidewalls of the first gate oxide layer extending along the first direction and a portion of the sidewalls of the first gate electrode layer extending along the first direction; the first gate sidewall includes a first portion and a second portion, the first portion being located on the insulating layer and covering the remaining sidewalls of the first gate electrode layer extending along the first direction, the second portion being located on the corresponding first active region and covering the sidewalls of the first gate electrode layer extending along the second direction. An unexpected effect of this application is that it narrows the width of the first gate oxide layer and the first gate electrode layer along the second direction, so that the boundaries of the first gate oxide layer and the first gate electrode layer extending along the first direction do not exceed the boundaries of the corresponding first active region extending along the first direction, thereby reducing the size of a single first transistor along the second direction and thus reducing the overall area of ​​the semiconductor device. At the same time, the insulating layer can cover the sidewalls of the first gate oxide layer extending along the first direction and a portion of the sidewalls of the first gate electrode layer extending along the first direction, thereby preventing the channel region in the first active region from being implanted with ions when the source / drain region is formed in the first active region, thus preventing the channel from being blocked. It can also prevent the formation of metal silicide near the boundary of the first active region extending along the first direction when metal silicide is formed on the source / drain region of the first active region, thus preventing the source / drain region of the first active region from being short-circuited. Attached Figure Description

[0034] Figure 1 This is a planar schematic diagram of a DAC device.

[0035] Figure 2 for Figure 1 A schematic cross-sectional view of the DAC device along the AA direction.

[0036] Figure 3 for Figure 1 A schematic cross-sectional view of the DAC device along the BB direction.

[0037] Figure 4A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.

[0038] Figure 5 This is a planar schematic diagram of a substrate provided in an embodiment of this application.

[0039] Figure 6 for Figure 5 A schematic cross-sectional view of the semiconductor structure along the AA direction.

[0040] Figure 7 This is a planar schematic diagram of an oxide material layer formed on a substrate according to an embodiment of this application.

[0041] Figure 8 for Figure 7 A schematic cross-sectional view of the semiconductor structure along the AA direction.

[0042] Figure 9 This is a planar schematic diagram of etching an oxide material layer using a patterned photoresist layer as a mask, according to an embodiment of this application.

[0043] Figure 10 for Figure 9 A schematic cross-sectional view of the semiconductor structure along the AA direction.

[0044] Figure 11 This is a planar schematic diagram of a solution provided in an embodiment of this application for removing a patterned photoresist layer.

[0045] Figure 12 for Figure 11 A schematic cross-sectional view of the semiconductor structure along the AA direction.

[0046] Figure 13 This is a planar schematic diagram of an electrode material layer formed on a substrate, provided as an embodiment of this application.

[0047] Figure 14 for Figure 13 A schematic cross-sectional view of the semiconductor structure along the AA direction.

[0048] Figure 15 This is a planar schematic diagram of an embodiment of the present application after etching the electrode material layer.

[0049] Figure 16 for Figure 15 A schematic cross-sectional view of the semiconductor structure along the AA direction.

[0050] Figure 17 A planar schematic diagram of forming a first gate sidewall and a second gate sidewall is provided for one embodiment of this application.

[0051] Figure 18 for Figure 17A schematic cross-sectional view of the semiconductor structure along the AA direction.

[0052] Figure 19 for Figure 17 A schematic cross-sectional view of the semiconductor structure along the BB direction.

[0053] Figure 20 A planar schematic diagram of the formation of a first source / drain region and a second source / drain region is provided for one embodiment of this application.

[0054] Figure 21 for Figure 20 A schematic cross-sectional view of the semiconductor structure along the AA direction.

[0055] Figure 22 for Figure 20 A schematic cross-sectional view of the semiconductor structure along the BB direction.

[0056] Figure 23 This is a planar schematic diagram of a semiconductor device provided in an embodiment of this application.

[0057] Figure 24 for Figure 23 A schematic cross-sectional view of the semiconductor device along the AA direction.

[0058] Figure 25 for Figure 23 A schematic cross-sectional view of the semiconductor device along the BB direction.

[0059] The attached figures are labeled as follows:

[0060] 100 - Substrate; 100A - First device region; 100B - Second device region; 101 - First active region; 111 - First source / drain region; 102 - Second active region; 112 - Second source / drain region; 200 - Oxide material layer; 201 - Insulating layer; 202 - Second gate oxide layer; 300 - Patterned photoresist layer; 301 - First gate oxide layer; 400 - Gate electrode material layer; 401 - First gate electrode layer; 402 - Second gate electrode layer; 501 - First gate sidewall; 511 - First portion; 521 - Second portion; 502 - Second gate sidewall; 600 - Contact hole; x - First direction; y - Second direction. Detailed Implementation

[0061] Figure 1 This is a planar schematic diagram of a DAC device. Figure 2 for Figure 1 A cross-sectional view of the DAC device along the AA direction. Figure 3 for Figure 1 A schematic cross-sectional view of the DAC device along the BB direction. (See attached diagram.) Figure 1 , Figure 2 and Figure 3As shown, a DAC device typically includes multiple NMOS transistor arrays and multiple PMOS transistor arrays, arranged in a staggered pattern. Each NMOS transistor array contains multiple NMOS transistors, and each PMOS transistor array contains multiple PMOS transistors. Therefore, the area of ​​a DAC device is already extremely large. Furthermore, to achieve single-transistor control of the NMOS and PMOS transistors, the gate electrode layers G of each NMOS and PMOS transistor are independent. To meet the distance requirements between the contact hole CT and the active region AA, the lateral width of the gate electrode layer G is larger than the lateral width of the active region AA (the contact hole CT of the gate electrode layer G can be laterally offset from the active region AA). Combined with the lateral spacing requirements between adjacent gate electrode layers G and the lateral width requirements of the active region AA, the lateral dimensions of the DAC device further increase, ultimately leading to a further increase in the area of ​​the DAC device.

[0062] Based on this, one embodiment of this application provides a semiconductor device and a method for fabricating the same, including a substrate, an insulating layer, and at least one first transistor; the substrate has a first device region, and the substrate of the first device region has at least one first active region, the first active regions extending along a first direction and spaced apart along a second direction; the first transistor includes a first gate oxide layer, a first gate electrode layer, and a first gate sidewall, the first gate oxide layer and the first gate electrode layer being stacked sequentially on the corresponding first active region, the boundaries of the first gate oxide layer and the first gate electrode layer extending along the first direction not exceeding the boundaries of the corresponding first active region extending along the first direction; the insulating layer is located on a portion of the substrate of the first device region and covers the sidewalls of the first gate oxide layer extending along the first direction and a portion of the sidewalls of the first gate electrode layer extending along the first direction; the first gate sidewall includes a first portion and a second portion, the first portion being located on the insulating layer and covering the remaining sidewalls of the first gate electrode layer extending along the first direction, the second portion being located on the corresponding first active region and covering the sidewalls of the first gate electrode layer extending along the second direction. An unexpected effect of this application is that it narrows the width of the first gate oxide layer and the first gate electrode layer along the second direction, so that the boundaries of the first gate oxide layer and the first gate electrode layer extending along the first direction do not exceed the boundaries of the corresponding first active region extending along the first direction, thereby reducing the size of a single first transistor along the second direction and thus reducing the overall area of ​​the semiconductor device. At the same time, the insulating layer can cover the sidewalls of the first gate oxide layer extending along the first direction and part of the sidewalls of the first gate electrode layer extending along the first direction, thereby preventing the channel portion from being implanted with ions when the source and drain regions are formed in the first active region, thus preventing the channel from being blocked. It can also prevent the formation of metal silicide near the boundary of the first active region extending along the first direction when metal silicide is formed on the source and drain regions of the first active region, thus preventing the source and drain regions of the first active region from being short-circuited.

[0063] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0064] Figure 23 This is a plan view of a semiconductor device provided in an embodiment of this application. Figure 24 for Figure 23 A schematic cross-sectional view of the semiconductor device along the AA direction. Figure 25 for Figure 23 A schematic cross-sectional view of a semiconductor device along the BB direction. (See attached diagram.) Figure 23 , Figure 24 and Figure 25 As shown, the semiconductor device includes a substrate 100, an insulating layer 201, and at least one first transistor.

[0065] Specifically, the substrate 100 can be made of materials such as silicon, silicon-on-insulator, germanium, silicon-germanium, germanium-on-insulator, and silicon carbide. The substrate 100 has a first device region 100A, and the first device region 100A has at least one first active region 101 within the substrate 100. The first active region 101 extends from the substrate 100 into the substrate 100. The first active regions 101 extend along a first direction x and are spaced apart along a second direction y. In some embodiments, the first direction x may be perpendicular to the second direction y.

[0066] Furthermore, the substrate 100 may also have a second device region 100B, within which a second active region 102 is provided. The second active region 102 extends from the substrate 100 into the substrate 100 and extends along a first direction x. There may be one or more second active regions 102. When the second device region 100B includes multiple second active regions 102, the second active regions 102 may also be arranged at intervals along a second direction y.

[0067] Furthermore, a trench isolation structure is also formed within the substrate 100. Figure 23 , Figure 24 and Figure 25(Not shown in the diagram) The trench isolation structure extends from the surface of the substrate 100 into the substrate 100. The trench isolation structure is located in the area within the substrate 100 other than the first active region 101 and the second active region 102, that is, the area surrounding the first active region 101 and the second active region 102 is the trench isolation structure. The top of the trench isolation structure may be higher than the surface of the substrate 100 or may overlap with the surface of the substrate 100. The material of the trench isolation structure is silicon oxide, but it should not be limited thereto. In other embodiments, the trench isolation structure may also be other dielectric materials, such as high-k dielectrics such as metal oxides.

[0068] The first transistor is located in the first device region 100A. The first transistor includes two first source-drain regions 111 and a first gate structure. The two first source-drain regions 111 are located in the corresponding first active regions 101 and are arranged at intervals along the first direction x in the first active regions 101. The first gate structure is located on the corresponding first active regions 101. In the first direction x, the first gate structure is arranged between the corresponding two first source-drain regions 111. The portion of the first active region 101 between the two first source-drain regions 111 is a channel region. The channel region is also located below the first gate structure.

[0069] Further, the first gate structure includes a first gate oxide layer 301, a first gate electrode layer 401, and a first gate sidewall 501. The first gate oxide layer 301 and the first gate electrode layer 401 are sequentially stacked on corresponding first active regions 101 (specifically, stacked on the first active region 101 between two adjacent first source / drain regions 111). The boundaries of the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x do not exceed the boundaries of the corresponding first active region 101 extending along the first direction x; that is, the width of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y is less than or equal to the width of the first active region 101 along the second direction y. (Comparison) Figure 23 and Figure 1 As can be seen, the width of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y is narrowed, which can reduce the size of a single first transistor along the second direction y, thereby reducing the overall area of ​​the semiconductor device.

[0070] In some embodiments, the first device region 100A can be a DAC device region for forming a DAC chip. In this case, some of the first transistors can be NMOS transistors, and others can be PMOS transistors. NMOS transistors can be arranged in an array, and PMOS transistors can also be arranged in an array. The NMOS transistor array and the PMOS transistor array can be arranged alternately. In this case, the number of first transistors is relatively large, and reducing the size of a single first transistor along the second direction y can greatly reduce the area of ​​the semiconductor device. Of course, the first device region 100A can also be used to form other chips, which will not be listed here.

[0071] In some embodiments, the boundaries of the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x can overlap with the boundaries of the corresponding first active region 101 extending along the first direction x. In this case, the width of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y is equal to the width of the first active region 101 along the second direction y, thereby ensuring that the first gate structure has a sufficiently large effective size.

[0072] In some embodiments, the boundaries of the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x may also be located within the boundaries of the corresponding first active region 101 extending along the first direction x. In this case, the width of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y is smaller than the width of the first active region 101 along the second direction y, which does not affect the implementation of this application.

[0073] Please continue reading. Figure 23 and Figure 24 An insulating layer 201 is located on a portion of the substrate 100 in the first device region 100A. Specifically, the insulating layer 201 is arranged on both sides of the first gate structure along the second direction y. The insulating layer 201 may cover the sidewalls of the first gate oxide layer 301 extending along the first direction x and a portion of the sidewalls of the first gate electrode layer 401 extending along the first direction x. Figure 24 As can be seen, the top surface of the insulating layer 201 is higher than the top surface of the first gate oxide layer 301 and lower than the top surface of the first gate electrode layer 401.

[0074] Furthermore, the first gate sidewall 501 includes a first portion 511 and a second portion 521, which are integral structures surrounding the first gate oxide layer 301 and the first gate electrode layer 401. Figure 23 and Figure 24As shown, the first portion 511 is located on the insulating layer 201 and extends along the first direction x. The first portion 511 covers the remaining sidewalls of the first gate electrode layer 401 extending along the first direction x. That is, a portion of the height of the sidewalls of the first gate electrode layer 401 is covered by the insulating layer 201, and another portion of the height of the sidewalls of the first gate electrode layer 401 is covered by the first portion 511. Figure 23 and Figure 25 As shown, the second portion 521 is located on the corresponding first active region 101 and extends along the second direction y. The second portion 521 covers the sidewall of the first gate electrode layer 401 extending along the second direction y.

[0075] It is understandable that, in order to reduce the area of ​​the first transistor, the boundaries of the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x do not exceed the boundaries of the corresponding first active region 101 extending along the first direction x. At this time, the first active regions 101 on both sides of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y may be exposed. Even if the first active regions 101 on both sides of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y are not exposed, the boundaries of the first active region 101 extending along the first direction x are not covered by the first gate oxide layer 301 and the first gate electrode layer 401, and can only be covered by the first gate sidewall 501. When ion implantation is performed in the first active region 101 to form the first source / drain region 111, if the first gate sidewall 501 is offset, the first gate sidewall 501 cannot play a good blocking role, which may cause ions to be implanted into the channel region of the first active region 101, resulting in channel penetration. In addition, when metal silicide is formed on the first source / drain region 111, if the first gate sidewall 501 is offset and cannot completely cover the first active region 101 exposed on both sides of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y, or cannot cover the boundary of the first active region 101 extending along the first direction x well, metal silicide may also be formed near the boundary of the first active region 101 extending along the first direction x, resulting in a short circuit between the first source / drain regions 111.

[0076] In this application, the insulating layer 201 can cover the sidewalls of the first gate oxide layer 301 extending along the first direction x and the partial sidewalls of the first gate electrode layer 401 extending along the first direction x. This can prevent the channel region in the first active region 101 from being implanted with ions when the source / drain region is formed in the first active region 101, thus preventing the channel from being blocked. At the same time, it can also prevent the formation of metal silicide near the boundary of the first active region 101 extending along the first direction x when metal silicide is formed on the first source / drain region 111, thus preventing the short circuit between the first source / drain regions 111.

[0077] Please continue reading. Figure 23 , Figure 24 and Figure 25 In some embodiments, the semiconductor device further includes a second transistor located within the second device region 100B. The second transistor includes two second source / drain regions 112 and a second gate structure. Both second source / drain regions 112 are located within the second active region 102 and are spaced apart along a first direction x within the second active region 102. The second gate structure is located on the corresponding second active region 102. Along the first direction x, the second gate structure is arranged between the corresponding two second source / drain regions 112. The portion of the second active region 102 between the two second source / drain regions 112 forms a channel region, which is also located below the second gate structure.

[0078] Furthermore, the second gate structure includes a second gate oxide layer 202, a second gate electrode layer 402, and a second gate sidewall 502. The second gate oxide layer 202 and the second gate electrode layer 402 are sequentially stacked on the second active region 102 (specifically, stacked on the second active region 102 between the two second source / drain regions 112). The second gate sidewall 502 is located on the substrate 100 of the second device region 100B and the second active region 102, and covers the sidewalls of the second gate oxide layer 202 and the second gate electrode layer 402.

[0079] In some embodiments, the boundaries of the second gate oxide layer 202 and the second gate electrode layer 402 extending along the first direction x can overlap with the boundaries of the corresponding second active region 102 extending along the first direction x. In this case, the width of the second gate oxide layer 202 and the second gate electrode layer 402 along the second direction y is equal to the width of the second active region 102 along the second direction y, thereby ensuring that the second gate structure has a sufficiently large effective size. Furthermore, in order to avoid the problem of channel penetration or short circuit between the second source and drain regions 112 in the second active region 102, the boundaries of the second gate oxide layer 202 and the second gate electrode layer 402 extending along the first direction x can exceed the boundaries of the corresponding second active region 102 along the first direction x. In this case, the second gate oxide layer 202 and the second gate electrode layer 402 can completely cover the channel region, avoiding the deterioration of the blocking effect after the second gate sidewall 502 is offset, which would lead to channel penetration or short circuit between the second source and drain regions 112 in the second active region 102.

[0080] Furthermore, the first transistor and the second transistor can be fabricated simultaneously. For example, the first transistor and the second transistor can be fabricated on different regions of the same wafer. One region of the wafer can be used to fabricate a DAC chip, and another region can be used to fabricate a high-voltage device. In this case, the first transistor can typically be a low-voltage or medium-voltage transistor (used to form a DAC chip), and the thickness of the first gate oxide layer 301 is not too thick, for example, it can be 100 angstroms to 150 angstroms. The second transistor can be a high-voltage transistor (used to form a high-voltage device), and its operating voltage can be greater than or equal to 32V. The thickness of the second gate oxide layer 202 can be greater than the thickness of the first gate oxide layer 301, for example, it can be greater than or equal to 700 angstroms.

[0081] The insulating layer 201 and the second gate oxide layer 202 can be located in the same layer and formed simultaneously. That is to say, the insulating layer 201 in this application is formed at the same time as the second gate oxide layer 202, which is equivalent to using the step of forming the second gate oxide layer 202 to form the insulating layer 201, thus not increasing the complexity of the process or the cost excessively. Furthermore, since the thickness of the second gate oxide layer 202 is greater than the thickness of the first gate oxide layer 301, the thickness of the insulating layer 201 can also be greater than the thickness of the first gate oxide layer 301 (the thickness of the insulating layer 201 can also be greater than or equal to 700 angstroms). A thicker insulating layer 201 can provide better barrier properties and better block implanted ions.

[0082] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 4 As shown, the method for fabricating a semiconductor device includes:

[0083] Step S100: Provide a substrate 100, the substrate 100 having a first device region 100A, the first device region 100A having at least one first active region 101 within the substrate 100, the first active region 101 extending along a first direction x and spaced apart along a second direction y.

[0084] Step S200: An insulating layer 201 is formed on the substrate 100 of the first device region 100A. The insulating layer 201 is located on both sides of the first active region 101 along the second direction y.

[0085] Step S300: A first gate oxide layer 301 and a first gate electrode layer 401 are formed in sequence on the first active region 101. The boundaries of the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x do not exceed the boundaries of the corresponding first active region 101 extending along the first direction x. The insulating layer 201 covers the sidewalls of the first gate oxide layer 301 extending along the first direction x and the partial sidewalls of the first gate electrode layer 401 extending along the first direction x.

[0086] Step S400: Form a first gate sidewall 501, the first gate sidewall 501 including a first portion 511 and a second portion 521, the first portion 511 being located on the insulating layer 201 and covering the remaining sidewall of the first gate electrode layer 401 extending along the first direction x, the second portion 521 being located on the corresponding first active region 101 and covering the sidewall of the first gate electrode layer 401 extending along the second direction y; and,

[0087] Step S500: The first active regions 101 on both sides of the first gate electrode layer 401 along the first direction x are doped with source and drain.

[0088] Figures 5-25 This is a schematic diagram of the structure corresponding to the respective steps of the method for fabricating a semiconductor device according to an embodiment of this application. Next, we will combine... Figures 5-25 A method for fabricating a semiconductor device according to an embodiment of this application will be described in detail.

[0089] like Figure 5 and Figure 6 As shown, in step S100, a substrate 100 is provided. The material of the substrate 100 can be silicon, silicon-on-insulator, germanium, silicon-germanium, germanium-on-insulator, or silicon carbide. The substrate 100 has a first device region 100A, which is used to form a first transistor.

[0090] In some embodiments, the substrate 100 may also have a second device region 100B, which is used to form a second transistor.

[0091] Please continue reading. Figure 5 and Figure 6 The first device region 100A has at least one first active region 101 in the substrate 100. The first active region 101 extends from the substrate 100 into the substrate 100. The first active region 101 extends along a first direction x. The first active regions 101 are also spaced along a second direction y. In some embodiments, the first direction x may be perpendicular to the second direction y.

[0092] Furthermore, the second device region 100B has a second active region 102 within the substrate 100. The second active region 102 extends from the substrate 100 into the substrate 100 and extends along a first direction x. There may be one or more second active regions 102. When the second device region 100B includes multiple second active regions 102, the second active regions 102 may also be arranged at intervals along a second direction y.

[0093] A trench isolation structure is also formed within the substrate 100. Figure 5 and Figure 6(Not shown in the diagram) The trench isolation structure extends from the surface of the substrate 100 into the substrate 100. The trench isolation structure is located in the area within the substrate 100 other than the first active region 101 and the second active region 102, that is, the area surrounding the first active region 101 and the second active region 102 is the trench isolation structure. The top of the trench isolation structure may be higher than the surface of the substrate 100 or may overlap with the surface of the substrate 100. The material of the trench isolation structure is silicon oxide, but it should not be limited thereto. In other embodiments, the trench isolation structure may also be other dielectric materials, such as high-k dielectrics such as metal oxides.

[0094] It should be noted that both the first active region 101 and the second active region 102 include three parts, namely a channel portion and two source-drain portions. The channel portion is used to form the channel region of the transistor, and the source-drain portions are used to form the source-drain region of the transistor. The channel portion is located between two adjacent source-drain portions.

[0095] like Figure 7 and Figure 8 As shown, in step S200, an oxide material layer 200 is deposited over the entire surface of the substrate 100, completely covering the surfaces of the substrate 100, the first active region 101, and the second active region 102. The material of the oxide material layer 200 can be silicon oxide, silicon oxynitride, etc., and the thickness of the oxide material layer 200 can be designed according to the thickness of the second gate oxide layer to be formed subsequently.

[0096] like Figure 9 and Figure 10 As shown, a patterned photoresist layer 300 is formed on the oxide material layer 200, and then the oxide material layer 200 is etched using the patterned photoresist layer 300 as a mask until the oxide material layer 200 on a portion of the substrate 100 of the first device region 100A and on the first active region 101 is removed, while the oxide material layer 200 on the substrate 100 of the second device region 100B and on the source and drain portions of the second active region 102 is also removed.

[0097] like Figure 11 and Figure 12 As shown, after removing the patterned photoresist layer 300, the remaining oxide material layer 200 in the first device region 100A constitutes the insulating layer 201. Figure 11 As can be seen, the insulating layer 201 is located on a portion of the substrate 100 of the first device region 100A, and is located on both sides of the first active region 101 along the second direction y (specifically, on both sides of the channel portion of the first active region 101 along the second direction y); the remaining oxide material layer 200 in the second device region 100B constitutes the second gate oxide layer 202. Figure 11As can be seen, the second gate oxide layer 202 is located on the channel portion of the second active region 102. In this way, the insulating layer 201 and the second gate oxide layer 202 can be formed simultaneously through a one-step deposition and etching process, which is relatively simple. Moreover, only a slight modification to the pattern of the existing photomask used to form the second gate oxide layer 202 is needed to form the photomask used when etching the oxide material layer 200, which can reduce the manufacturing cost.

[0098] like Figure 13 and Figure 14 As shown, in step S300, a first gate oxide layer 301 is formed on the first active region 101, covering the surface of the first active region 101. The first gate oxide layer 301 can be formed by a thermal oxidation process, and its thickness can be 100 angstroms to 150 angstroms. Next, a gate electrode material layer 400 is deposited over the entire surface of the substrate 100.

[0099] like Figure 15 and Figure 16 As shown, the gate electrode material layer 400 is etched to remove the gate electrode material layer 400 on the insulating layer 201, the substrate 100, the source / drain portions of the first active region 101, and the source / drain portions of the second active region 102. The remaining gate electrode material layer 400 in the first device region 100A is located on the channel portion of the first active region 101 and forms the first gate electrode layer 401. The remaining gate electrode material layer 400 in the second active region 102 is located on the channel portion of the second active region 102 (and also on the second gate oxide layer 202) and forms the second gate electrode layer 402. In this way, the second gate electrode layer 402 can be formed simultaneously with the formation of the first gate electrode layer 401.

[0100] It should be noted that after the first gate electrode layer 401 and the second gate electrode layer 402 are formed, the first gate oxide layer 301 on both sides of the first gate electrode layer 401 can be etched to remove the first gate oxide layer 301 on the source and drain portion of the first active region 101, while retaining the first gate oxide layer 301 on the channel portion of the first active region 101.

[0101] Furthermore, from Figure 15 As can be seen, the boundaries of the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x overlap with the boundary of the first active region 101 extending along the first direction x (vertically aligned). That is, the width of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y is the same as the width of the first active region 101 along the second direction y, thereby reducing the width of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y, and thus reducing the device area.

[0102] Of course, in some embodiments, the boundary of the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x can also be located within the boundary of the first active region 101 extending along the first direction x. That is, the width of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y can be smaller than the width of the first active region 101 along the second direction y, thereby further reducing the width of the first gate oxide layer 301 and the first gate electrode layer 401, and thus reducing the device area. In this case, it is only necessary to remove a portion of the oxide material layer 200 on the channel portion of the first active region 101 when etching the oxide material layer 200, so that the remaining oxide material layer 200 in the first device region 100A covers a portion of the channel portion of the first active region 101, thereby allowing the boundary of the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x to be located within the boundary of the first active region 101 extending along the first direction x.

[0103] like Figure 17 , Figure 18 and Figure 19 As shown, in step S400, a first gate sidewall 501 is formed in the first device region 100A. The first gate sidewall 501 includes a first portion 511 and a second portion 521, which are joined together to form an integral structure. Figure 17 and Figure 18 As shown, the first portion 511 is located on the insulating layer 201. Since the insulating layer 201 covers a portion of the sidewalls of the first gate electrode layer 401 extending along the first direction x, the first portion 511 will only cover the remaining sidewalls of the first gate electrode layer 401 extending along the first direction x; as Figure 17 and Figure 19 As shown, the second portion 521 is located on the corresponding first active region 101 and covers the sidewall of the first gate electrode layer 401 extending along the second direction y. At this time, the first gate electrode layer 401, the first gate oxide layer 301, and the first gate sidewall 501 can constitute the gate structure (first gate structure) of the first transistor.

[0104] Please continue reading. Figure 17 , Figure 18 and Figure 19While forming the first gate sidewall 501 in the first device region 100A, a second gate sidewall 502 is also formed in the second device region 100B. The second gate sidewall 502 is located on the substrate 100 of the first device region 100A and on the second active region 102, so as to cover the entire sidewall of the second gate electrode layer 402 (covering the sidewall of the second gate electrode layer 402 extending along the first direction x and the sidewall extending along the second direction y). At this time, the second gate electrode layer 402, the second gate oxide layer 202, and the second gate sidewall 502 can constitute the gate structure of the second transistor (second gate structure).

[0105] like Figure 20 , Figure 21 and Figure 22 As shown, in step S500, the first active regions 101 on both sides of the first gate electrode layer 401 along the first direction x are doped with source and drain ions, that is, corresponding ions are implanted into the source and drain portions of the first active regions 101, thereby forming first source and drain regions 111 in the source and drain portions of the first active regions 101. The first source and drain regions 111 are arranged on both sides of the first gate structure along the first direction x, and the first source and drain regions 111 and the first gate structure can constitute a first transistor.

[0106] Please continue reading. Figure 20 , Figure 21 and Figure 22 While performing source / drain doping on the first active regions 101 on both sides of the first gate electrode layer 401 along the first direction x, source / drain doping can also be performed on the second active regions 102 on both sides of the second gate electrode layer 402 along the first direction x. That is, corresponding ions are implanted into the source / drain portions of the second active regions 102, thereby forming second source / drain regions 112 within the source / drain portions of the second active regions 102. The second source / drain regions 112 are arranged on both sides of the second gate structure along the first direction x, and the second source / drain regions 112 and the second gate structure can constitute a second transistor.

[0107] Understandably, since the insulating layer 201 can cover the sidewalls of the first gate oxide layer 301 extending along the first direction x and a portion of the sidewalls of the first gate electrode layer 401 extending along the first direction x, when the first active regions 101 on both sides of the first gate electrode layer 401 along the first direction x are doped for source and drain, it can prevent the channel region within the first active region 101 from being implanted with ions, thus avoiding the problem of channel punch-through. Furthermore, since the insulating layer 201 is fabricated simultaneously with the second gate oxide layer 202, when the second transistor is a high-voltage device, the thickness of the insulating layer 201 can be larger, thus providing a better barrier effect and effectively preventing the channel punch-through problem.

[0108] like Figure 23 , Figure 24 and Figure 25As shown, a metallization process is performed to form metal silicides on the first source / drain region 111, the second source / drain region 112, the first gate electrode layer 401, and the second gate electrode layer 402, respectively. Figure 23 , Figure 24 and Figure 25 (not shown in the figure), and a contact hole 600 is formed on the metal silicide, through which the first source / drain region 111, the second source / drain region 112, the first gate electrode layer 401 and the second gate electrode layer 402 can be led out through the corresponding contact hole 600.

[0109] It is understandable that since the insulating layer 201 can cover the sidewalls of the first gate oxide layer 301 extending along the first direction x and the partial sidewalls of the first gate electrode layer 401 extending along the first direction x, it can avoid the formation of metal silicide near the boundary of the first active region 101 extending along the first direction x when metal silicide is formed on the first source / drain region 111, thereby preventing a short circuit between the first source / drain regions 111.

[0110] In summary, this embodiment provides a semiconductor device and its fabrication method, including a substrate 100, an insulating layer 201, and at least one first transistor; the substrate 100 has a first device region 100A, and the first device region 100A has at least one first active region 101 within the substrate 100, the first active regions 101 extending along a first direction x and spaced apart along a second direction y; the first transistor includes a first gate oxide layer 301, a first gate electrode layer 401, and a first gate sidewall 501, the first gate oxide layer 301 and the first gate electrode layer 401 being sequentially stacked on the corresponding first active region 101, the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x and spaced apart along a second direction y; the first transistor includes a first gate oxide layer 301, a first gate electrode layer 401, and a first gate sidewall 501, the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x and spaced apart along a second direction y; The boundary extending in the x direction does not exceed the boundary of the corresponding first active region 101 extending in the first direction x; the insulating layer 201 is located on a portion of the substrate 100 of the first device region 100A and covers the sidewall of the first gate oxide layer 301 extending in the first direction x and a portion of the sidewall of the first gate electrode layer 401 extending in the first direction x; the first gate sidewall 501 includes a first portion 511 and a second portion 521, the first portion 511 is located on the insulating layer 201 and covers the remaining sidewall of the first gate electrode layer 401 extending in the first direction x, and the second portion 521 is located on the corresponding first active region 101 and covers the sidewall of the first gate electrode layer 401 extending in the second direction y. An unexpected effect of this application is that it narrows the width of the first gate oxide layer 301 and the first gate electrode layer 401 along the second direction y, so that the boundaries of the first gate oxide layer 301 and the first gate electrode layer 401 extending along the first direction x do not exceed the boundaries of the corresponding first active region 101 extending along the first direction x, thereby reducing the size of a single first transistor along the second direction y, and thus reducing the overall area of ​​the semiconductor device; at the same time, the insulating layer 201 can cover the sidewalls of the first gate oxide layer 301 extending along the first direction x and the partial sidewalls of the first gate electrode layer 401 extending along the first direction x, thereby preventing the channel region in the first active region 101 from being implanted with ions when the source and drain regions are formed in the first active region 101, thus preventing the channel from being blocked. It can also prevent the formation of metal silicide near the boundary of the first active region 101 extending along the first direction x when metal silicide is formed on the source and drain regions of the first active region 101, thus preventing the source and drain regions of the first active region 101 from being short-circuited.

[0111] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0112] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0113] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0114] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized by, Includes a substrate, an insulating layer, and at least one first transistor; The substrate has a first device region, and the first device region has at least one first active region within the substrate. The first active regions extend along a first direction and are spaced apart along a second direction. The first direction and the second direction are in the same plane and perpendicular to each other. The first transistor includes a first gate oxide layer, a first gate electrode layer, and a first gate sidewall. The first gate oxide layer and the first gate electrode layer are stacked sequentially on the corresponding first active region. The orthographic projection of the boundary of the first gate oxide layer and the first gate electrode layer extending along the first direction on the substrate is located within the orthographic projection of the boundary of the corresponding first active region extending along the first direction on the substrate. The insulating layer is located on a portion of the substrate in the first device region and covers the sidewalls of the first gate oxide layer extending along the first direction and a portion of the sidewalls of the first gate electrode layer extending along the first direction. The first gate sidewall includes a first portion and a second portion. The first portion is located on the insulating layer and covers the remaining sidewall of the first gate electrode layer extending along the first direction. The second portion is located on the first active regions on both sides of the first gate electrode layer in the first direction and covers the first gate oxide layer and the sidewall of the first gate electrode layer extending along the second direction. The substrate further has a second device region, and the second device region has a second active region within the substrate; The semiconductor device further includes a second transistor, the second transistor comprising a second gate oxide layer, a second gate electrode layer, and a second gate sidewall, the second gate oxide layer and the second gate electrode layer being sequentially stacked on the second active region; and... The second gate sidewall is located on the substrate and the second active region of the second device region, and covers the sidewalls of the second gate oxide layer and the second gate electrode layer; The thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer, and the insulating layer and the second gate oxide layer are located in the same layer and are formed simultaneously.

2. The semiconductor device of claim 1, wherein, The orthographic projection of the boundary of the first gate oxide layer and the first gate electrode layer extending along the first direction on the substrate overlaps with the orthographic projection of the boundary of the corresponding first active region extending along the first direction on the substrate.

3. The semiconductor device of claim 1, wherein, The thickness of both the insulating layer and the second gate oxide layer is greater than or equal to 700 angstroms; and / or the operating voltage of the second transistor is greater than or equal to 32V.

4. The semiconductor device according to any one of Claims 1 to 3, wherein The first device area is the DAC device area, and part of the first transistors are NMOS transistors, while the other part of the first transistors are PMOS transistors.

5. A method of manufacturing a semiconductor device, characterized by include: A substrate is provided having a first device region, wherein the first device region has at least one first active region within the substrate, the first active regions extending along a first direction and spaced apart along a second direction, the first direction and the second direction being in the same plane and perpendicular to each other; An insulating layer is formed on the substrate of the first device region, the insulating layer being located on both sides of the first active region extending along the first direction; A first gate oxide layer and a first gate electrode layer are formed in sequence on each of the first active regions. The orthographic projection of the boundary of the first gate oxide layer and the first gate electrode layer extending along the first direction on the substrate is located within the orthographic projection of the boundary of the corresponding first active region extending along the first direction on the substrate. The insulating layer covers the sidewall of the first gate oxide layer extending along the first direction and a portion of the sidewall of the first gate electrode layer extending along the first direction. A first gate sidewall is formed, the first gate sidewall comprising a first portion and a second portion, the first portion being located on the insulating layer and covering the remaining sidewall of the first gate electrode layer extending along the first direction, the second portion being located on the first active regions on both sides of the first gate electrode layer in the first direction and covering the sidewall of the first gate electrode layer extending along the second direction; and, The first active regions on both sides of the first gate electrode layer along the first direction are doped with source and drain doping. The substrate further has a second device region, and the second device region has a second active region within the substrate; While forming the insulating layer, a second gate oxide layer is also formed on the second active region, and the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer. While forming the first gate electrode layer, a second gate electrode layer is also formed on the second gate oxide layer; While forming the first gate sidewall, a second gate sidewall is also formed on the substrate and the second active region of the second device region, and the second gate sidewall covers the sidewall of the second gate electrode layer.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, While performing source / drain doping on the first active region, source / drain doping is also performed on the second active regions on both sides of the second gate electrode layer along the first direction.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The steps of forming the insulating layer and the second gate oxide layer include: A layer of oxide material is deposited all over the substrate; and, The oxide material layer is etched such that the remaining oxide material layer in the first device region constitutes the insulating layer, and the remaining oxide material layer in the second device region constitutes the second gate oxide layer.

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