Array substrate, preparation method thereof and display device

Abstract

The invention discloses an array substrate, a preparation method thereof and a display device. The array substrate comprises a substrate body and a first conductive layer located on the substrate body, and the first conductive layer comprises at least one data line; the first insulating layer is located on one side, far away from the substrate, of the first conductive layer and comprises at least one first via hole, and the first via hole exposes a part of the data line; the first semiconductor layer is partially located on the side, away from the substrate, of the first insulating layer, the first semiconductor layer comprises a first active layer of at least one first transistor, and the first active layer of the at least one first transistor comprises a first channel region; wherein at least part of the first channel region is located in the first via hole, and the included angle between the first channel region and the direction perpendicular to the plane where the substrate is located is larger than or equal to 0 degree and smaller than or equal to 5 degrees, so that the pixel density of the display device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to, but is not limited to, the technical field of display, and in particular to an array substrate, a preparation method thereof, and a display device. BACKGROUND

[0002] Liquid Crystal Display (LCD) is a common display type. LCD display uses two polarized materials between which is a liquid crystal solution. When a voltage is applied to the two polarized materials, the liquid crystal is deflected. By controlling the size of the applied voltage, the degree of deflection of the liquid crystal can be controlled. Currently, liquid crystal display (LCD) is developing towards the goal of being light, thin, short and small. SUMMARY

[0003] The present application provides an array substrate, a preparation method thereof, and a display device, which can solve the problem of low pixel density of the existing display device.

[0004] In one aspect, the present application provides an array substrate, comprising:

[0005] a substrate;

[0006] a first conductive layer on the substrate, wherein the first conductive layer comprises at least one data line;

[0007] a first insulating layer on a side of the first conductive layer away from the substrate, wherein the first insulating layer comprises at least one first via hole, and the first via hole exposes part of the data line; and

[0008] a first semiconductor layer on a side of the first insulating layer away from the substrate, wherein the first semiconductor layer comprises a first active layer of at least one first transistor, and the first active layer of the at least one first transistor comprises a first channel region.

[0009] At least part of the first channel region is located in the first via hole, and the angle between the first channel region and the direction perpendicular to the plane of the substrate is greater than or equal to 0 degrees and less than or equal to 5 degrees.

[0010] In some exemplary embodiments, the first active layer of the at least one first transistor further comprises a first region and a second region connected to the first channel region, and the first region and the second region are located on opposite sides of the first channel region, respectively; the first region is located in the first via hole, and the first region is in contact with the data line; at least part of the second region is located on a side of the first insulating layer away from the substrate.

[0011] In some example embodiments, the array substrate further comprises a second conductive layer on a side of the first insulating layer distal to the substrate, the second conductive layer comprises at least one pixel electrode, and the second region on a side proximal to the substrate is in contact with a side of the pixel electrode distal to the substrate.

[0012] In some example embodiments, the first via comprises a sidewall, a projection of the sidewall on a plane in which the substrate lies overlaps with a projection of at least a part of an edge of the pixel electrode proximal to the first via on the plane in which the substrate lies; and the first channel region is in contact with the sidewall.

[0013] In some example embodiments, the array substrate further comprises a third conductive layer on a side of the second conductive layer distal to the substrate; the third conductive layer comprises a plurality of gate lines, and the plurality of gate lines each extend in a first direction and are spaced apart in a second direction; and a plane formed by the first direction and the second direction is parallel to a plane in which the substrate lies.

[0014] The array substrate further comprises a plurality of first insulating portions, the plurality of first insulating portions are arranged in pairs with the plurality of gate lines, at least a part of the first insulating portion is on a side of the gate line distal to the substrate, and the plurality of first insulating portions each extend in the first direction and are spaced apart in the second direction.

[0015] In some example embodiments, the array substrate further comprises a second conductive layer on a side of the first insulating layer distal to the substrate, the second conductive layer comprises at least one pixel connection electrode, and the second region on a side proximal to the substrate is in contact with a side of the pixel connection electrode distal to the substrate, and the pixel connection electrode is configured to be connected with a pixel electrode, and the pixel electrode is on a side of the pixel connection electrode distal to the substrate.

[0016] In some example embodiments, the array substrate further comprises at least one pixel electrode, and the at least one pixel electrode is on a side of the second conductive layer distal to the substrate, and at least one insulating layer is provided between the pixel electrode and the pixel connection electrode, and the at least one insulating layer is provided with at least one via; the pixel electrode is connected with the pixel connection electrode via the via, and a side of the pixel electrode distal to the substrate is a plane.

[0017] In some example embodiments, the array substrate further comprises a fourth conductive layer and a fifth conductive layer sequentially located on the side of the second conductive layer away from the substrate; the fourth conductive layer comprises at least one common electrode line, the fifth conductive layer comprises at least one common electrode, and the at least one common electrode line is in contact with the at least one common electrode; wherein the common electrode line extends along a first direction, the common electrode extends along a second direction, and the plane formed by the first direction and the second direction is parallel to the plane in which the substrate is located.

[0018] In some example embodiments, the common electrode is farther away from the substrate than the pixel electrode; there is a minimum spacing between the common electrode and the pixel electrode along the direction perpendicular to the plane in which the substrate is located, and the minimum spacing is 900 angstroms to 1100 angstroms.

[0019] In some example embodiments, the array substrate comprises a display area and a frame area located on at least one side of the display area.

[0020] The array substrate further comprises at least one second transistor located in the frame area; the at least one second transistor comprises a second active layer, and the second active layer is located in the first semiconductor layer.

[0021] In some example embodiments, the array substrate further comprises at least one first signal connection line, and the at least one first signal connection line is located in the first conductive layer; the first insulating layer further comprises at least one second via, the second via exposes part of the first signal connection line, and part of the second active layer is located in the second via and in contact with the first signal connection line.

[0022] In some example embodiments, the array substrate further comprises a second insulating layer located on the side of the first semiconductor layer away from the substrate; the second insulating layer is provided with at least one via, and the at least one via exposes part of the first signal connection line and part of the second active layer;

[0023] The array substrate further comprises at least one signal connection electrode, and at least part of the signal connection electrode is located in the at least one via and connected with the first signal connection line and the second active layer.

[0024] In some example embodiments, the array substrate comprises a display area and a frame area located on at least one side of the display area.

[0025] The array substrate further comprises at least one second transistor in the frame region; the at least one second transistor comprises a second active layer, and the second active layer is located in the first semiconductor layer or a second semiconductor layer, and the second semiconductor layer is located between the first conductive layer and the substrate; wherein a side surface of the second active layer away from the substrate is a plane.

[0026] In another aspect, the embodiments of the present disclosure provide a display device comprising the array substrate according to any one of the above embodiments.

[0027] In another aspect, the embodiments of the present disclosure provide a method for manufacturing an array substrate, comprising:

[0028] forming a first conductive layer on one side of the substrate, the first conductive layer comprising at least one data line;

[0029] forming a first insulating layer on a side of the first conductive layer away from the substrate, the first insulating layer comprising at least one first via, and the first via exposing part of the data line;

[0030] forming a first semiconductor layer on a side of the first insulating layer away from the substrate, the first semiconductor layer comprising a first active layer of at least one first transistor, and the first active layer of the at least one first transistor comprising a first channel region;

[0031] wherein at least part of the first channel region is located in the first via, and an angle between the first channel region and a direction perpendicular to a plane in which the substrate is located is greater than or equal to 0 degrees and less than or equal to 5 degrees.

[0032] Other features and advantages of the present disclosure will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present disclosure. Other advantages of the present disclosure will be realized and attained by those of ordinary skill in the art, including studying the following description and appended claims as well as practicing the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings are included to provide an understanding of the present technical solution, and constitute a part of the specification, and together with the embodiments of the present disclosure serve to explain the present technical solution, and do not constitute a limitation on the present technical solution.

[0034] Figure 1 FIG. 1 is a partial top view of an array substrate;

[0035] Figure 2 FIG. 2 is a front view of the array substrate according to an embodiment of the present disclosure;

[0036] Figure 3A FIG. 3 is a partial top view of a display region of the array substrate according to an embodiment of the present disclosure;

[0037] Figure 3B for Figure 3A Cross-sectional view of the area marked AA in the middle;

[0038] Figure 4A This is a partial top view of the second border region of an array substrate according to an embodiment of the present disclosure;

[0039] Figure 4B for Figure 4A Cross-sectional view of the area marked BB in the middle;

[0040] Figure 5A This is a partial top view of the display area after the first conductive layer pattern is formed on the array substrate according to an embodiment of the present disclosure;

[0041] Figure 5B for Figure 5A A partial cross-sectional view of the area marked AA in the middle;

[0042] Figure 6A This is a partial top view of the second border region after the formation of the first conductive layer pattern on the array substrate according to an embodiment of the present disclosure;

[0043] Figure 6B for Figure 6A A partial cross-sectional view of the area marked BB in the middle;

[0044] Figure 7A This is a partial top view of the display area after the second conductive layer pattern is formed on the array substrate according to an embodiment of the present disclosure;

[0045] Figure 7B for Figure 7A A partial cross-sectional view of the area marked AA in the middle;

[0046] Figure 8A This is a partial top view of the second border region after the second conductive layer pattern is formed on the array substrate according to an embodiment of the present disclosure;

[0047] Figure 8B for Figure 8A A partial cross-sectional view of the area marked BB in the middle;

[0048] Figure 9A This is a partial top view of the display area after the first insulating layer pattern is formed on the array substrate according to an embodiment of the present disclosure;

[0049] Figure 9B for Figure 9A A partial cross-sectional view of the area marked AA in the middle;

[0050] Figure 10A This is a partial top view of the second border region after the formation of the first insulating layer pattern on the array substrate according to an embodiment of the present disclosure;

[0051] Figure 10B For Figure 10A A partial sectional view of the array substrate in the B-B direction after the first semiconductor layer pattern is formed;

[0052] Figure 11A A partial top view of the array substrate in the display area after the first semiconductor layer pattern is formed in an embodiment of the present disclosure;

[0053] Figure 11B For Figure 11A A partial sectional view of the array substrate in the A-A direction after the first semiconductor layer pattern is formed;

[0054] Figure 12A A partial top view of the array substrate in the second frame area after the first semiconductor layer pattern is formed in an embodiment of the present disclosure;

[0055] Figure 12B For Figure 12A A partial sectional view of the array substrate in the B-B direction after the second insulating layer pattern is formed;

[0056] Figure 13A A partial top view of the array substrate in the display area after the second insulating layer pattern is formed in an embodiment of the present disclosure;

[0057] Figure 13B For Figure 13A A partial sectional view of the array substrate in the A-A direction after the second insulating layer pattern is formed;

[0058] Figure 14A A partial top view of the array substrate in the second frame area after the second insulating layer pattern is formed in an embodiment of the present disclosure;

[0059] Figure 14B For Figure 14A A partial sectional view of the array substrate in the B-B direction after the third conductive layer pattern is formed;

[0060] Figure 15A A partial top view of the array substrate in the display area after the third conductive layer pattern is formed in an embodiment of the present disclosure;

[0061] Figure 15B For Figure 15A A partial sectional view of the array substrate in the A-A direction after the third conductive layer pattern is formed;

[0062] Figure 16A A partial top view of the array substrate in the second frame area after the third conductive layer pattern is formed in an embodiment of the present disclosure;

[0063] Figure 16B For Figure 16A A partial sectional view of the array substrate in the B-B direction after the third insulating layer pattern is formed;

[0064] Figure 17A A partial top view of the array substrate in the display area after the third insulating layer pattern is formed in an embodiment of the present disclosure;

[0065] Figure 17B Figure 1 is a partial cross-sectional view of a display device according to an embodiment of the present disclosure; Figure 17A Figure 2 is a partial cross-sectional view of the display device according to an embodiment of the present disclosure;

[0066] Figure 18A Figure 3 is a partial top view of an array substrate after forming a third insulating layer pattern according to an embodiment of the present disclosure;

[0067] Figure 18B Figure 4 is a partial cross-sectional view of the array substrate according to an embodiment of the present disclosure; Figure 18A Figure 5 is a partial cross-sectional view of the array substrate according to an embodiment of the present disclosure;

[0068] Figure 19A Figure 6 is a partial top view of the array substrate after forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0069] Figure 19B Figure 7 is a partial cross-sectional view of the array substrate according to an embodiment of the present disclosure; Figure 19A

[0070] Figure 8 is a partial top view of the array substrate after forming a fifth conductive layer pattern according to an embodiment of the present disclosure; Figure 20A

[0071] Figure 9 is a partial cross-sectional view of the array substrate according to an embodiment of the present disclosure; Figure 20B Figure 20A Figure 10 is a partial cross-sectional view of the array substrate according to another embodiment of the present disclosure;

[0072] Figure 21A Figure 11 is a partial cross-sectional view of the array substrate according to another embodiment of the present disclosure;

[0073] Figure 21B Figure 12 is a partial cross-sectional view of the array substrate according to another embodiment of the present disclosure;

[0074] Figure 22 Figure 13 is a partial cross-sectional view of the array substrate according to another embodiment of the present disclosure;

[0075] Figure 23A Figure 14 is a partial top view of the array substrate according to another embodiment of the present disclosure;

[0076] Figure 23B Figure 15 is a partial cross-sectional view of the array substrate according to another embodiment of the present disclosure; Figure 23A Figure 16 is a partial cross-sectional view of the array substrate according to another embodiment of the present disclosure; DETAILED DESCRIPTION

[0077] ​For the purpose of making the objects, technical solutions, and advantages of the present disclosure clearer, the following will be used in conjunction with the accompanying drawings to describe embodiments of the present disclosure in detail. The embodiments can be implemented in a variety of different forms. One skilled in the art can easily understand that the modes and contents can be changed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0078] In the drawings, the size, the thickness, or the region of one or more constituent elements can be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to such a scale. The shapes and the sizes of the components shown in the drawings can not reflect the actual ones. Furthermore, the drawings provided are schematic views reflecting the ideal exemplary embodiments of the present disclosure, and the present disclosure is not limited to shapes or values shown in the drawings.

[0079] In the present disclosure, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among constituent elements, and are not used to describe the number of the constituent elements. In the present disclosure, "a plurality of" includes two or more.

[0080] In the present disclosure, for convenience, words indicating the orientation or the positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the constituent elements with reference to the drawings, and are used only for the purpose of facilitating the description of the specification and simplifying the description, and thus cannot be understood as indicating or implying that the device or the element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0081] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connection" should be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through an intermediate device, or communication between two elements. Those skilled in the art can understand the meaning of the above terms in the present disclosure according to the situation.

[0082] In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain) and the source electrode (a source electrode terminal, a source region, or a source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0083] In the present disclosure, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0084] In the present disclosure, "electrically connected" includes a case where components are connected together through an element having some kind of electrical action. The element having some kind of electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between the components to be connected. Examples of the element having some kind of electrical action include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, another element having one or more functions, and the like.

[0085] In the present disclosure, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus can include a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus can include a state where the angle is 85° or more and 95° or less.

[0086] In the present disclosure, "film" and "layer" can be interchanged. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0087] "About" in the present disclosure means that a limit is not strictly defined, and a value within a range of process and measurement error is allowed.

[0088] Figure 1 is a partial top view schematic diagram of an array substrate. As Figure 1As shown, the array substrate can include at least one gate line 1, at least one data line 2, and at least one transistor. The transistor includes an active layer 3, the active layer 3 includes a first region, a second region, and a channel region, and the first region of the active layer 3 can be connected with the data line 2 via a first via D1 located on the insulating layer. The array substrate can further include a pixel electrode 4, and the pixel electrode 4 can be connected with the second region of the active layer 3 via a second via D2 located on the insulating layer. Since the via for connection needs to be arranged on the insulating layer, the light emitting area of the display device is affected, the light efficiency is reduced, and the pixel density of the display device is reduced.

[0089] The array substrate provided by the embodiments of the present disclosure includes a substrate, a first conductive layer located on the substrate, and the first conductive layer includes at least one data line, a first insulating layer located on a side of the first conductive layer away from the substrate, and the first insulating layer includes at least one first via, and the first via exposes part of the data line, and a first semiconductor layer located on a side of the first insulating layer away from the substrate, and the first semiconductor layer includes a first active layer of at least one first transistor, and the first active layer of the at least one first transistor includes a first channel region.

[0090] The first channel region is at least partially located in the first via, and an angle between the first channel region and a direction perpendicular to a plane where the substrate is located is greater than or equal to 0 degrees and less than or equal to 5 degrees.

[0091] The array substrate provided by the embodiments of the present disclosure sets the first channel region of the first active layer in a direction approximately perpendicular to the plane where the substrate is located. On the one hand, the connection between the first active layer and components such as the pixel electrode can not need to set a via, and the number of vias is reduced. On the other hand, the occupied area of the first active layer in the plane where the substrate is located is reduced under the condition of meeting the electrical performance of the first active layer, and the pixel density of the array substrate is improved.

[0092] Figure 2 It is a front view schematic diagram of the array substrate of an embodiment of the present disclosure. As shown, Figure 2 The array substrate can include a display area AA and a frame area BB located on at least one side of the display area AA. The frame area BB can include a first frame area B1 located on one side of the display area AA and a second frame area B2 located on the remaining sides of the display area AA. For example, the first frame area B1 can include the lower frame of the array substrate, and the second frame area B2 can include the upper frame, the left frame, and the right frame of the array substrate. In the embodiments of the present disclosure, the frame area can also be referred to as a non-display area.

[0093] In an exemplary embodiment, as shown in Figure 2As shown, the display area AA may include multiple data lines DL and multiple gate lines GL disposed on a substrate. The multiple gate lines GL may extend along a first direction X and be arranged sequentially along a second direction Y different from the first direction X. The multiple data lines DL may extend along the second direction Y and be arranged sequentially along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The multiple data lines DL and the multiple gate lines GL may be located in different film layers; for example, the multiple data lines DL may be located on the side of the multiple gate lines GL closer to the substrate.

[0094] In one exemplary embodiment, such as Figure 2 As shown, multiple data lines DL and multiple gate lines GL can intersect to form multiple sub-pixel regions. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL can be a sub-pixel region. One sub-pixel can be correspondingly set within a sub-pixel region. A sub-pixel region can include an open area and a non-open area surrounding the open area. The non-open area can be an area obscured by the black matrix of the opposing substrate of the array substrate, and the open area can be an area not obscured by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL can both be located within the non-open area. The array substrate of this embodiment can be used to implement a display function, and the open area of ​​each sub-pixel region can be configured for display. The non-open area can surround the open area and not be displayed. However, this embodiment is not limited in this respect. In some examples, the array substrate can be used to implement other functions.

[0095] In one exemplary embodiment, the display area AA may include a plurality of pixel units disposed on a substrate. At least one pixel unit may include three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may, for example, be a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, red sub-pixel, and green sub-pixel. Figure 2 As shown, at least one sub-pixel may include: a pixel electrode 10 and a common electrode ( Figure 2(Not shown), and the orthographic projections of the pixel electrode 10 and the common electrode of the sub-pixel onto the substrate may partially overlap. For example, the common electrode of multiple sub-pixels in the display area AA may be a single structure. For example, the common electrode may be located on the side of the pixel electrode 10 away from the substrate. The sub-pixel may also include a first transistor 21. The first transistor 21 may be located near the intersection of the data line DL and the gate line GL. The first transistor 21 may include a first gate, a first electrode, and a second electrode. The first gate may be electrically connected to the gate line GL, the first electrode of the first transistor 21 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of a sub-pixel. The first transistor 21 may be configured to provide the data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0096] In one exemplary embodiment, the second bezel region B2 may include at least a gate driving circuit (e.g., including multiple cascaded shift registers), which may be electrically connected to multiple gate lines GL in the display region AA. The gate driving circuit may also include a second transistor. The structure of the second transistor located in the second bezel region B2 may be the same as or different from the structure of the first transistor located in the display region AA.

[0097] Figure 3A This is a partial top view of the display area of ​​an array substrate according to an embodiment of the present disclosure. Figure 3B for Figure 3A A cross-sectional view of the section marked AA. Figure 4A This is a partial top view of the second border region of an array substrate according to an embodiment of the present disclosure. Figure 4B for Figure 4A A cross-sectional view at point BB is shown. In this embodiment, the direction perpendicular to the plane of the array substrate is defined as the third direction Z, which can also be referred to as the thickness direction of the array substrate. The plane of the array substrate is parallel to the plane formed by the first direction X and the second direction Y.

[0098] like Figure 3B , Figure 4BAs shown, in a plane perpendicular to the plane of the array substrate, the array substrate may include a substrate 30 and a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on one side of the substrate 30. The array substrate may also include a first semiconductor layer, a portion of which is located between the second and third conductive layers. The array substrate may also include a first insulating layer 11 located between the first and second conductive layers, a second insulating layer 12 located between the first semiconductor layer and the third conductive layer, and a third insulating layer 13 located between the third and fourth conductive layers. In embodiments of this disclosure, the first insulating layer may also be referred to as a buffer layer, the second insulating layer may also be referred to as a gate insulating (GI) layer, and the third insulating layer may also be referred to as a planarization (PLN) layer.

[0099] In one exemplary embodiment, such as Figure 3A , Figure 3B As shown, the first conductive layer may include at least one data line DL, and the orthographic projection of the at least one data line DL onto the plane of the array substrate is located in the display area AA. Multiple data lines DL may extend along the second direction Y and be spaced apart along the first direction X. For example, the data line DL may be a zigzag line extending along the second direction Y.

[0100] In one exemplary embodiment, such as Figure 3A , Figure 3B As shown, the second conductive layer may include at least one pixel electrode 10, and the orthographic projection of at least one pixel electrode 10 onto the plane of the array substrate is located in the display area AA. The orthographic projection of the pixel electrode 10 onto the plane of the array substrate and the orthographic projection of the data line DL onto the plane of the array substrate may partially overlap. The first insulating layer 11 may include at least one first via K1, and the orthographic projection of at least one first via K1 onto the plane of the array substrate is located in the display area AA. The orthographic projection of the first via K1 onto the plane of the array substrate and the orthographic projection of the data line DL onto the plane of the array substrate at least partially overlap. For example, the orthographic projection of the first via K1 onto the plane of the array substrate may be located within the orthographic projection of the data line DL onto the plane of the array substrate, and the first via K1 may penetrate the first insulating layer 11 along a third direction Z and expose a portion of the surface of the data line DL.

[0101] like Figure 3A , Figure 3BAs shown, the first semiconductor layer may include at least one first active layer 14, and the orthographic projection of at least one first active layer 14 onto the plane of the array substrate is located in the display area AA. The first active layer 14 may include a first channel region 14-3 and a first region 14-1 and a second region 14-2 located on opposite sides of the first channel region 14-3. The first region 14-1 can be used as the first electrode of the first transistor 21, and the second region 14-2 can be used as the second electrode of the first transistor 21.

[0102] like Figure 3A , Figure 3B As shown, at least a portion of the first region 14-1 may be located within the first via K1, and the first region 14-1 is connected to the data line DL via the first via K1. For example, the orthographic projection of the second region 14-2 onto the plane of the array substrate may partially overlap with the orthographic projection of the first via K1 onto the plane of the array substrate, or the orthographic projection of the second region 14-2 onto the plane of the array substrate may not overlap with the orthographic projection of the first via K1 onto the plane of the array substrate. At least a portion of the second region 14-2 may be located on the side of the pixel electrode 10 away from the substrate 30. For example, the entire second region 14-2 is located on the side of the pixel electrode 10 away from the substrate 30. At least a portion of the surface of the second region 14-2 near the substrate 30 is in contact with at least a portion of the surface of the pixel electrode 10 away from the substrate 30.

[0103] like Figure 3B As shown, the orthographic projection of the first channel region 14-3 onto the plane of the array substrate can lie within the orthographic projection of the first via K1 onto the plane of the array substrate, and at least a portion of the first channel region 14-3 can contact the wall of the first via K1. The angle between the first channel region 14-3 and the third direction Z can range from 0 degrees to 5 degrees. That is, the angle between the first channel region 14-3 and the plane of the array substrate can range from 85 degrees to 95 degrees. For example, the angle between the first channel region 14-3 and the third direction Z can be 0 degrees, that is, the first channel region 14-3 can be perpendicular to the plane of the array substrate. Alternatively, the angle between the first channel region 14-3 and the third direction Z can be 1 degree, etc. By limiting the angle range between the first channel region 14-3 and the third direction Z, the occupied area of ​​the first active layer can be reduced, the light-emitting area of ​​the display area of ​​the array substrate can be increased, and the light emission efficiency of the display device can be improved. Furthermore, a first via can be used to connect the first transistor to the data line and the pixel electrode, which reduces the number of vias overall, increases the light-emitting area of ​​the display area, and reduces the probability of light leakage problems caused by vias.

[0104] In one exemplary embodiment, such as Figure 3A , Figure 3BAs shown, the third conductive layer may include at least one gate line GL, and the orthographic projection of the at least one gate line GL onto the plane of the array substrate is located in the display area AA. Multiple gate lines GL may extend along a first direction X and be spaced apart along a second direction Y. For example, the gate line GL may be a straight line extending along the first direction X. The third conductive layer may also include at least one first gate 15, and the first gate 15 and the gate line GL may be an integral structure interconnected. For example, a portion of the gate line GL may be used as the first gate 15.

[0105] The orthographic projection of the first gate 15 onto the plane of the array substrate and the orthographic projection of the first active layer 14 onto the plane of the array substrate may at least partially overlap. For example, the orthographic projection of the first gate 15 onto the plane of the array substrate may include the orthographic projection of the first active layer 14 onto the plane of the array substrate. For example, the orthographic projection of the first gate 15 onto the plane of the array substrate may include the orthographic projection of the first channel region 14-3 onto the plane of the array substrate. In the embodiments of this disclosure, the first gate can be used as a light-shielding layer to prevent light from affecting the first active layer and to improve the performance of the first transistor.

[0106] In one exemplary embodiment, such as Figure 3A As shown, the third insulating layer 13 may include at least one first insulating portion 13-1, each extending along a first direction X, and multiple first insulating portions 13-1 may be arranged at intervals along a second direction Y. For example, the first insulating portion 13-1 may be a straight line extending along the first direction X. The first insulating portion 13-1 and the gate line GL may be arranged in pairs, and the orthographic projection of the first insulating portion 13-1 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the gate line GL onto the plane of the array substrate. For example, the orthographic projection of the first insulating portion 13-1 onto the plane of the array substrate overlaps with the orthographic projection of the gate line GL onto the plane of the array substrate. Alternatively, the orthographic projection of the first insulating portion 13-1 onto the plane of the array substrate includes the orthographic projection of the gate line GL onto the plane of the array substrate, and the area of ​​the orthographic projection of the first insulating portion 13-1 onto the plane of the array substrate is larger than the area of ​​the orthographic projection of the gate line GL onto the plane of the array substrate. In the subsequent cell assembly process between the array substrate and the opposing substrate, the first insulating part can be used as a support pillar, which can reduce the fabrication steps of the array substrate and reduce the fabrication cost of the array substrate.

[0107] In one exemplary embodiment, such as Figure 3A , Figure 3BAs shown, the fourth conductive layer may include at least one common electrode line CM, which may extend along a first direction X, and multiple common electrode lines CM may be arranged at intervals along a second direction Y. The orthographic projection of at least one common electrode line CM onto the plane of the array substrate is located in the display area AA. The common electrode lines CM and the first insulating portion 13-1 may be provided in pairs. For example, the orthographic projection of the common electrode line CM onto the plane of the array substrate may be located within the orthographic projection of the first insulating portion 13-1 onto the plane of the array substrate.

[0108] In one exemplary embodiment, such as Figure 3A , Figure 3B As shown, the fifth conductive layer may include at least one common electrode 16. The orthographic projection of at least one common electrode 16 onto the plane of the array substrate is located in the display area AA. The orthographic projection of the common electrode 16 onto the plane of the array substrate may partially overlap with the orthographic projection of the pixel electrode 10 onto the plane of the array substrate, and the orthographic projection of the common electrode 16 onto the plane of the array substrate may partially overlap with the orthographic projection of the first insulating portion 13-1 onto the plane of the array substrate, and the orthographic projection of the common electrode 16 onto the plane of the array substrate may partially overlap with the orthographic projection of the second insulating layer 12 onto the plane of the array substrate. A portion of the surface of the common electrode 16 near the substrate 30 contacts a portion of the surface of the common electrode line CM away from the substrate 30. Multiple common electrode lines and multiple common electrodes form a grid-like shape, which can enhance the deflection electric field of the liquid crystal, improve light efficiency, and reduce optical crosstalk between adjacent sub-pixels.

[0109] In an exemplary embodiment, the common electrode 16 and the pixel electrode 10 have a minimum spacing L along the third direction Z. The minimum spacing L can range from 900 angstroms to 1100 angstroms. By limiting this minimum spacing, the performance of the deflection electric field formed between the common electrode and the pixel electrode can be improved, and the refresh rate of the array substrate can be increased.

[0110] In one exemplary embodiment, such as Figure 4A , Figure 4B As shown, the first conductive layer may further include at least one first signal connection line L11, and the orthographic projection of the at least one first signal connection line L11 onto the plane of the array substrate is located in the second border region B2. For example, multiple first signal connection lines L11 may all extend along the first direction X and be spaced apart along the second direction Y. For example, the first signal connection line L11 may be a straight line extending along the first direction X.

[0111] In one exemplary embodiment, such as Figure 4A , Figure 4BAs shown, the first insulating layer 11 may further include at least one second via K2, and the orthographic projection of at least one second via K2 onto the plane of the array substrate is located in the second border region B2. The orthographic projection of the second via K2 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the first signal connection line L11 onto the plane of the array substrate. For example, the orthographic projection of the second via K2 onto the plane of the array substrate may be located within the orthographic projection of the first signal connection line L11 onto the plane of the array substrate, and the second via K2 may penetrate the first insulating layer 11 along the third direction Z and expose a portion of the surface of the first signal connection line L11.

[0112] In one exemplary embodiment, such as Figure 4A , Figure 4B As shown, the first semiconductor layer may further include at least one second active layer 17, and the orthographic projection of at least one second active layer 17 onto the plane of the array substrate is located in the second border region B2. The second active layer 17 may include a second channel region 17-2 and a third region 17-3 and a fourth region 17-4 located on opposite sides of the second channel region 17-2. The third region 17-3 may be used as the first electrode of the second transistor 22, and the fourth region 17-4 may be used as the second electrode of the second transistor 22. The second transistor may include a second active layer and a second gate.

[0113] The orthographic projection of the third region 17-3 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the second via K2 onto the plane of the array substrate. For example, the orthographic projection of the third region 17-3 onto the plane of the array substrate may include the orthographic projection of the second via K2 onto the plane of the array substrate. A portion of the third region 17-3 may be located within the second via K2 and in contact with a portion of the surface of the first signal connection line L11 away from the substrate 30, thus achieving the connection between the third region 17-3 and the first signal connection line L11, that is, the connection between the second transistor 22 and the first signal connection line L11.

[0114] In one exemplary embodiment, such as Figure 4A , Figure 4BAs shown, the second insulating layer 12 may include at least one third via K3, and the orthographic projection of at least one third via K3 onto the plane of the array substrate is located in the second border region B2. The orthographic projection of the third via K3 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the fourth region 17-4 onto the plane of the array substrate. For example, the orthographic projection of the third via K3 onto the plane of the array substrate may be located within the orthographic projection of the fourth region 17-4 onto the plane of the array substrate. The third via K3 may penetrate the second insulating layer 12 along a third direction Z and expose a portion of the surface of the fourth region 17-4 away from the substrate 30. The second signal connection line L12 located in the third conductive layer may contact the fourth region 17-4 via the third via K3, thus realizing the connection between the second signal connection line L12 and the fourth region 17-4, that is, the connection between the second signal connection line L12 and the second transistor 22.

[0115] In one exemplary embodiment, such as Figure 4A , Figure 4B As shown, the third conductive layer may further include at least one second gate 18, and the orthographic projection of at least one second gate 18 onto the plane of the array substrate is located in the second border region B2. The orthographic projection of the second gate 18 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the second channel region 17-2 onto the plane of the array substrate. For example, the orthographic projection of the second gate 18 onto the plane of the array substrate may include the orthographic projection of the second channel region 17-2 onto the plane of the array substrate. In this embodiment, the second gate can be used as a light-shielding layer for the second channel region, which can prevent light from affecting the second channel region, improve the performance of the second transistor, and improve the reliability of the array substrate.

[0116] The following description uses the fabrication process of an array substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the array substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0117] The fabrication process of the array substrate may include the following steps:

[0118] (01) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: depositing a first conductive thin film on one side of the substrate 30, and patterning the first conductive thin film using a patterning process, so that the first conductive thin film forms a first conductive layer pattern located on one side of the substrate 30. The first conductive layer may include at least one data line GL and at least one first signal connection line L11, such as... Figure 5A , Figure 5B , Figure 6A , Figure 6B As shown, Figure 5A A partial top view of the display area after the first conductive layer pattern has been formed on the array substrate. Figure 5B for Figure 5A A partial cross-sectional view of the area marked AA. Figure 6A A partial top view of the second border region after the first conductive layer pattern has been formed on the array substrate. Figure 6B for Figure 6A A partial cross-sectional view of the area marked BB.

[0119] In an exemplary embodiment, the substrate 30 may be a transparent substrate. For example, the substrate 30 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the embodiments disclosed herein are not limited in this respect. The substrate 30 may be a single-layer or composite layer structure; for example, the substrate 30 may be a composite layer structure of a rigid substrate and a flexible substrate.

[0120] In one exemplary embodiment, the material of the first conductive layer can be a metallic material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, it can be an alloy of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0121] In an exemplary embodiment, the data line GL can be designed with non-uniform linewidth. For example, the portion of the data line GL that connects to the first transistor can be widened, which can improve the reliability of the connection between the data line and the first transistor and improve the overall rationality of the wiring.

[0122] (02) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a first insulating film 11-1 and a second conductive film on one side of the substrate 30, and patterning the second conductive film using a patterning process, so that the second conductive film forms a second conductive layer pattern located on the side of the first insulating film 11-1 away from the substrate 30. The second conductive layer may include at least one pixel electrode 10, such as... Figure 7A , Figure 7B , Figure 8A , Figure 8B As shown, Figure 7A A partial top view of the display area after the second conductive layer pattern is formed on the array substrate. Figure 7B for Figure 7A A partial cross-sectional view of the area marked AA. Figure 8A A partial top view of the second border region after the second conductive layer pattern has been formed on the array substrate. Figure 8B for Figure 8AA partial cross-sectional view of the area marked BB. The second conductive layer is located only in the display area.

[0123] In an exemplary embodiment, the pixel electrode 10 may include a connecting portion 10-1 and an extension portion 10-2 connected to each other. The extension portion 10-2 may be located on the side of the connecting portion 10-1 opposite to the second direction Y. Both the connecting portion 10-1 and the extension portion 10-2 may be rectangular. The orthographic projection area of ​​the extension portion 10-2 on the plane of the array substrate may be larger than the orthographic projection area of ​​the connecting portion 10-1 on the plane of the array substrate. The connecting portion 10-1 may be configured to connect to a subsequently formed first active layer, thereby realizing the connection between the pixel electrode and the first transistor. The first transistor includes a first active layer and a first gate.

[0124] In one exemplary embodiment, the material of the second conductive layer may be the same as or different from the material of the first conductive layer.

[0125] In an exemplary embodiment, the material of the second conductive layer can be a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO), etc. For example, the second conductive layer can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO, etc.

[0126] (03) Forming a first insulating layer pattern. Forming the first insulating layer pattern may include: patterning the aforementioned substrate 30 using a patterning process, so that the first insulating film 11-1 forms a first insulating layer pattern, such as... Figure 9A , Figure 9B , Figure 10A , Figure 10B As shown, Figure 9A A partial top view of the display area after the first insulating layer pattern has been formed on the array substrate. Figure 9B for Figure 9A A partial cross-sectional view of the area marked AA. Figure 10A A partial top view of the second border region after the first insulating layer pattern has been formed on the array substrate. Figure 10B for Figure 10A A partial cross-sectional view of the area marked BB.

[0127] The first insulating layer 11 may include a plurality of vias, which may include at least one first via K1 and at least one second via K2. The first insulating film located within the first via K1 and the second via K2 is etched away. The first via K1 exposes a portion of the surface of the data line DL, and the second via K2 exposes a portion of the surface of the first signal connection line L11. The first via K1 is configured to allow the subsequently formed first active layer to be connected to the data line DL via the via, and the second via K2 is configured to allow the subsequently formed second active layer to be connected to the first signal connection line L11 via the via.

[0128] In an exemplary embodiment, the first via K1 may include a sidewall K11, the orthographic projection of the sidewall K11 onto the plane of the array substrate being located may overlap with the orthographic projection of at least a portion of the edge of the pixel electrode 10 near the first via K1 onto the plane of the array substrate.

[0129] In an exemplary embodiment, the sidewall K11 has an angle α with the plane of the array substrate. The angle α can range from 85 degrees to 95 degrees. For example, the angle α can be 90 degrees, that is, the sidewall K11 is perpendicular to the plane of the array substrate. In this embodiment of the present disclosure, by defining the angle of the sidewall of the first via, it is convenient to control the angle of the subsequently formed first channel region, which can reduce the complexity of the fabrication process.

[0130] In an exemplary embodiment, the dimension of the data line DL exposed by the first via K1 along the second direction Y is denoted as b. b can be 1.5 micrometers, 2 micrometers, etc., as long as it satisfies the connection between the first active layer and the data line. This disclosure does not limit the value of b.

[0131] In an exemplary embodiment, the dimension by which the data line DL extends beyond the sidewall K11 along the second direction Y is denoted as a, where a can be greater than 0. The subsequently formed first channel region is located within the first via. Since the data line DL extends beyond the sidewall K11, the data line DL can be used as a light-shielding layer for the first channel region, thereby improving the reliability of the first transistor.

[0132] In one exemplary embodiment, the dimensions of the data line DL along the second direction Y may include a and c, where c may be equal to b, or c may be greater than b. For example, c may be 3 micrometers.

[0133] In an exemplary embodiment, the orthographic projection of the first via K1 onto the plane of the array substrate can be a rectangle, etc. For example, the first via K1 can be a square hole of 2 micrometers.

[0134] In an exemplary embodiment, the orthographic projection of the second via K2 onto the plane of the array substrate can be a circle, an ellipse, a rectangle, or a hexagon, etc.

[0135] In one exemplary embodiment, the material of the first insulating layer may include an inorganic material. Inorganic materials, for example, are silicon oxynitride (SiO₂). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x One or more of the following: ) etc. The first insulating layer can be a single layer, multiple layers, or a composite layer structure.

[0136] (04) Forming a first semiconductor layer pattern. Forming the first semiconductor layer pattern may include: depositing a semiconductor thin film on one side of the substrate 30, and patterning the semiconductor thin film using a patterning process to form a first semiconductor layer pattern, such as... Figure 11A , Figure 11B , Figure 12A , Figure 12B As shown, Figure 11A A partial top view of the display area after the first semiconductor layer pattern has been formed on the array substrate. Figure 11B for Figure 11A A partial cross-sectional view of the area marked AA. Figure 12A A partial top view of the second border region after the first semiconductor layer pattern has been formed on the array substrate. Figure 12B for Figure 12A A partial cross-sectional view of the area marked BB.

[0137] The first semiconductor layer pattern may include at least one first active layer 14 and at least one second active layer 17. The orthographic projection of the first active layer 14 and the second active layer 17 onto the plane of the array substrate may be rectangular or the like. The first active layer 14 may include a first channel region 14-3 and a first region 14-1 and a second region 14-2 located on opposite sides of the first channel region 14-3. Forming the first semiconductor layer pattern may further include partially conductiveizing the first active layer 14, such that portions of the first active layer 14 respectively form the first region 14-1 and the second region 14-2. The first region 14-1 may be used as the first electrode of the first transistor 21, and the second region 14-2 may be used as the second electrode of the first transistor 21. The second active layer 17 may include a second channel region 17-2 and a third region 17-3 and a fourth region 17-4 located on opposite sides of the second channel region 17-2. The formation of the first semiconductor layer pattern may further include partially conductiveizing the second active layer 17, such that portions of the second active layer 17 respectively form a third region 17-3 and a fourth region 17-4. The third region 17-3 can be used as the first electrode of the second transistor 22, and the fourth region 17-4 can be used as the second electrode of the second transistor 22.

[0138] In an exemplary embodiment, the first channel region 14-3 may be an elongated strip extending along the first direction X. For example, the first region 14-1 may be located on one side of the first channel region 14-3 along the second direction Y, and the second region 14-2 may be located on the opposite side of the first channel region 14-3 along the second direction Y. The orthographic projections of the first region 14-1 and the second region 14-2 onto the plane of the array substrate may both be rectangular, etc.

[0139] In an exemplary embodiment, the first region 14-1 and the first channel region 14-3 may both be located within the first via K1, a portion of the first channel region 14-3 may contact the sidewall K11 of the first via K1, and the first region 14-1 may contact the data line DL.

[0140] In an exemplary embodiment, the orthographic projection of the first channel region 14-3 onto the plane of the array substrate can be located within the orthographic projection of the data line DL onto the plane of the array substrate. The data line DL can be used as a light-shielding layer to prevent light from affecting the first channel region.

[0141] In an exemplary embodiment, the second channel region 17-2 can be rectangular, extending along the first direction X. For example, the third region 17-3 can be located on one side of the second channel region 17-2 along the second direction Y, and the fourth region 17-4 can be located on the side of the second channel region 17-2 opposite to the second direction Y. Alternatively, the third region 17-3 can be located on the side of the second channel region 17-2 opposite to the second direction Y, and the fourth region 17-4 can be located on one side of the second channel region 17-2 along the second direction Y. The orthographic projections of the third region 17-3 and the fourth region 17-4 onto the plane of the array substrate can both be rectangular.

[0142] In an exemplary embodiment, a portion of the third region 17-3 may be located within the second via K2 and in contact with the first signal connection line L11.

[0143] In one exemplary embodiment, the material of the first semiconductor layer may include one or more of the following: indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), and indium gallium zinc y oxide (IGZYO, where Y represents tin doping). In one example, the material of the first semiconductor layer may include various materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. The array substrate provided in this embodiment is suitable for transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0144] (05) Forming a second insulating layer pattern. Forming a second insulating layer pattern may include: depositing a second insulating film on one side of the substrate 30, and patterning the second insulating film using a patterning process to form a second insulating layer pattern, such as... Figure 13A , Figure 13B , Figure 14A , Figure 14B As shown, Figure 13A A partial top view of the display area after the second insulating layer pattern is formed on the array substrate. Figure 13B for Figure 13A A partial cross-sectional view of the area marked AA. Figure 14A A partial top view of the second border region after the second insulating layer pattern has been formed on the array substrate. Figure 14B for Figure 14A A partial cross-sectional view of the area marked BB.

[0145] The second insulating layer 12 may include at least one third via K3, within which the second insulating film is etched away, exposing a portion of the surface of the fourth region 17-4. The third via K3 is configured such that a subsequently formed second signal connection line is connected to the fourth region 17-4 via the via.

[0146] In an exemplary embodiment, the orthographic projection of the third via K3 onto the plane of the array substrate can be a circle, an ellipse, a rectangle, a hexagon, etc.

[0147] In one exemplary embodiment, the material of the second insulating layer may be the same as or different from the material of the first insulating layer.

[0148] (06) Forming a third conductive layer pattern. Forming a third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 30, and patterning the third conductive film using a patterning process to form a third conductive layer pattern, such as... Figure 15A , Figure 15B , Figure 16A , Figure 16B As shown, Figure 15A A partial top view of the display area after the third conductive layer pattern has been formed on the array substrate. Figure 15B for Figure 15A A partial cross-sectional view of the area marked AA. Figure 16A A partial top view of the second border region after the third conductive layer pattern has been formed on the array substrate. Figure 16B for Figure 16A A partial cross-sectional view of the area marked BB.

[0149] The third conductive layer may include at least one gate line GL, at least one first gate 15, at least one second signal connection line L12, and at least one second gate 18. The orthographic projection of the first gate 15 onto the plane of the array substrate may include the orthographic projection of the first channel region 14-3 onto the plane of the array substrate, which can avoid the influence of light on the first channel region and improve the reliability of the first transistor.

[0150] In one exemplary embodiment, the material of the third conductive layer may be the same as or different from the material of the first conductive layer.

[0151] In an exemplary embodiment, the dimension of the first gate 15 extending beyond the surface of the first channel region 14-3 near the pixel electrode 10 along the second direction Y is denoted as d. d can be greater than 0, for example, d can be 0.5 micrometers.

[0152] In an exemplary embodiment, two adjacent second signal connection lines L12 may be connected to the same signal connection line L13.

[0153] In an exemplary embodiment, the second gates of a plurality of second transistors located between two adjacent second signal connection lines L12 can be an integral structure interconnected with each other.

[0154] (07) Forming a third insulating layer pattern. Forming a third insulating layer pattern may include: depositing a third insulating film on one side of the substrate 30, and patterning the third insulating film using a patterning process to form a third insulating layer pattern, such as... Figure 17A , Figure 17B , Figure 18A , Figure 18B As shown, Figure 17A A partial top view of the display area after the third insulating layer pattern is formed on the array substrate. Figure 17B for Figure 17A A partial cross-sectional view of the area marked AA. Figure 18A A partial top view of the second border region after the third insulating layer pattern has been formed on the array substrate. Figure 18B for Figure 18A A partial cross-sectional view of the area marked BB.

[0155] The third insulating layer 13 may include at least one first insulating portion 13-1 and at least one second insulating portion 13-2, wherein the first insulating portion 13-1 and the gate line GL may be provided in pairs. For example, the orthographic projection of the first insulating portion 13-1 onto the plane of the array substrate may include the orthographic projection of the gate line GL onto the plane of the array substrate. The first insulating portion 13-1 may be a line extending along a first direction X. The second insulating portion 13-2 may be rectangular, etc.

[0156] In some exemplary embodiments, the material of the third insulating layer may be the same as or different from the material of the first insulating layer.

[0157] In some exemplary embodiments, the material of the third insulating layer may include organic materials. Examples of organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. The third insulating layer may be a single layer, multiple layers, or a composite layer structure.

[0158] (08) Forming a fourth conductive layer pattern. Forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on one side of the substrate 30, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern, such as... Figure 19A , Figure 19B As shown, Figure 19A A partial top view of the display area after the fourth conductive layer pattern is formed on the array substrate. Figure 19B for Figure 19A A partial cross-sectional view of the area marked AA. The orthographic projection of the fourth conductive layer pattern onto the plane of the array substrate does not overlap with the second border area.

[0159] The fourth conductive layer may include at least one common electrode line CM, which may extend along a first direction X. Multiple common electrode lines CM may be arranged at intervals along a second direction Y. The common electrode lines CM and gate lines GL may be arranged in pairs. The orthographic projection of the common electrode line CM onto the plane of the array substrate and the orthographic projection of the gate line GL onto the plane of the array substrate may at least partially overlap. For example, the orthographic projection of the common electrode line CM onto the plane of the array substrate may be located within the orthographic projection of the gate line GL onto the plane of the array substrate, which can avoid the influence of the common electrode line CM on the light-emitting area of ​​the array substrate and improve the display performance of the display device.

[0160] In some exemplary embodiments, the material of the fourth conductive layer may be the same as or different from the material of the first conductive layer.

[0161] (09) Forming a fifth conductive layer pattern. Forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on one side of the substrate 30, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer pattern, such as... Figure 20A , Figure 20B As shown, Figure 20A A partial top view of the display area after the fifth conductive layer pattern has been formed on the array substrate. Figure 20B for Figure 20AA partial cross-sectional view at point AA is shown. The orthographic projection of the fifth conductive layer pattern onto the plane of the array substrate does not overlap with the second border region. The fifth conductive layer may include at least one common electrode 16, which may extend along the second direction Y. For example, the common electrode 16 may be a zigzag shape.

[0162] In some exemplary embodiments, the material of the fifth conductive layer can be a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO), etc. For example, the fifth conductive layer can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO, etc.

[0163] Figure 21A This is a partial cross-sectional schematic diagram of the display area of ​​the array substrate according to another embodiment of this disclosure. Figure 21A As shown, in the display area, within a plane perpendicular to the plane of the array substrate, the array substrate may include a substrate 30 and a first conductive layer, a second conductive layer, a third conductive layer, a pixel electrode layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on one side of the substrate 30. The array substrate may also include a first semiconductor layer, a portion of which is located between the second and third conductive layers. The array substrate may further include a first insulating layer 11 located between the first and second conductive layers, a second insulating layer 12 located between the first semiconductor layer and the third conductive layer, a third insulating layer 13 located between the third conductive layer and the pixel electrode layer, and a fourth insulating layer 24 located between the pixel electrode layer and the fourth conductive layer.

[0164] The second conductive layer may include at least one pixel connection electrode 25. The first insulating layer 11 may include at least one first via K1, and the orthographic projection of the first via K1 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the data line DL onto the plane of the array substrate. For example, the orthographic projection of the first via K1 onto the plane of the array substrate may be located within the orthographic projection of the data line DL onto the plane of the array substrate, and the first via K1 may penetrate the first insulating layer 11 along a third direction Z and expose a portion of the surface of the data line DL.

[0165] The first semiconductor layer may include at least one first active layer 14, which may include a first channel region 14-3 and a first region 14-1 and a second region 14-2 located on opposite sides of the first channel region 14-3. The first region 14-1 may be used as the first electrode of the first transistor 21, and the second region 14-2 may be used as the second electrode of the first transistor 21. At least a portion of the first region 14-1 may be located within a first via K1, and the first region 14-1 is connected to the data line DL via the first via K1. At least a portion of the second region 14-2 may be located on the side of the pixel connection electrode 25 away from the substrate 30. For example, the entire second region 14-2 is located on the side of the pixel connection electrode 25 away from the substrate 30. At least a portion of the surface of the second region 14-2 near the substrate 30 is in contact with at least a portion of the surface of the pixel connection electrode 25 away from the substrate 30.

[0166] The pixel electrode layer may include at least one pixel electrode 10. The pixel electrode 10 is connected to the pixel connection electrode 25, thereby achieving the connection between the pixel electrode 10 and the second region 14-2. The array substrate may also include at least one fourth via K4, in which the second insulating layer 12 and the third insulating layer 13 located within the fourth via K4 are etched away, exposing at least a portion of the surface of the pixel connection electrode 25 on the side away from the substrate 30. The pixel electrode 10 is connected to the pixel connection electrode 25 via the fourth via K4. At least a portion of the pixel electrode 10 is located within the fourth via K4.

[0167] In some exemplary embodiments, a portion of the pixel electrode 10 is located on the side of the third insulating layer 13 away from the substrate 30, and the surface of this portion away from the substrate 30 is planar. The orthographic projection of this portion onto the plane of the array substrate includes the orthographic projection of the fourth via K4 onto the plane of the array substrate. In other words, the portion of the third insulating layer 13 that contacts the pixel electrode 10 is planar, and the fourth via is substantially filled or flattened. This design avoids light leakage problems caused by vias and ensures that the pixel electrode can form an electric field that meets the design requirements, thereby improving the performance of the array substrate.

[0168] In some exemplary embodiments, the pixel electrode layer can be made of a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO), etc. For example, the pixel electrode layer can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO, etc.

[0169] In this embodiment, by designing the third and fourth insulating layers, a larger gap can be created between the common electrode and the first gate, reducing or avoiding parasitic capacitance between them and improving the electrical performance of the array substrate. Other structures of the display area of ​​the array substrate can be found in the foregoing embodiments and will not be elaborated further here.

[0170] Figure 21B This is a partial cross-sectional schematic diagram of the display area of ​​an array substrate according to another embodiment of this disclosure. Figure 21B As shown, the array substrate structure is basically similar to that of the aforementioned embodiment, with the main difference being that the pixel electrode 10 may include a first portion 10a and a second portion 10b connected together. The first portion 10a and the filling material can jointly fill the fourth via K4, and the filling material can be the same as or different from the material of the third insulating layer. The second portion 10b can be located on the side of the first portion 10a away from the substrate 30. The material of the first portion 10a and the material of the second portion 10b can be the same as or different. Other structures of the display area of ​​the array substrate can be referred to the description of the aforementioned embodiment, and will not be elaborated here.

[0171] Figure 22 This is a partial cross-sectional schematic diagram of the second border region of the array substrate according to another embodiment of this disclosure. Figure 22 As shown, in the second border region, the array substrate may include a substrate 30 and a first conductive layer, a first semiconductor layer, and a third conductive layer sequentially disposed on one side of the substrate 30. The array substrate may also include a first insulating layer 11 located between the first conductive layer and the first semiconductor layer, a second insulating layer 12 located between the first semiconductor layer and the third conductive layer, and a third insulating layer 13 located on the side of the third conductive layer away from the substrate 30.

[0172] The third conductive layer may further include at least one signal connection electrode 26, the orthographic projection of which onto the plane of the array substrate is located in the second border region. The second insulating layer 12 may further include at least one fifth via K5, the orthographic projection of which onto the plane of the array substrate is located in the second border region. The second insulating layer 12 and the third region 17-3 within the fifth via K5 are etched away, exposing a portion of the surface of the first signal connection line L11 and the third region 17-3. At least a portion of the signal connection electrode 26 is located within the fifth via K5 and is connected to both the first signal connection line L11 and the third region 17-3. In this embodiment, the use of a signal connection electrode avoids the problem of increased connection resistance between the first signal connection line and the second transistor, and this structure does not increase the fabrication process.

[0173] Other structures of the second border region of the array substrate can be referred to the description in the foregoing embodiments, and will not be elaborated here.

[0174] Figure 23A This is a partial top view of the second border region of the array substrate according to another embodiment of the present disclosure. Figure 23B for Figure 23A A cross-sectional view at the CC mark. In the second border region, the array substrate may include a substrate 30 and a second semiconductor layer, a first conductive layer, and a third conductive layer sequentially disposed on one side of the substrate 30. The array substrate may also include a dielectric layer 27 located between the second semiconductor layer and the first conductive layer, a first insulating layer 11 and a second insulating layer 12 located between the first conductive layer and the third conductive layer, and a third insulating layer 13 located on the side of the third conductive layer away from the substrate 30.

[0175] The second semiconductor layer may include at least one second active layer 17. The second active layer 17 may include a second channel region 17-2 and a third region 17-3 and a fourth region 17-4 located on opposite sides of the second channel region 17-2. The third region 17-3 may be used as the first electrode of the second transistor, and the fourth region 17-4 may be used as the second electrode of the second transistor. The second transistor may include the second active layer 17 and a second gate 18. The second gate 18 is located in the first conductive layer.

[0176] The array substrate may further include at least one sixth via K6 and at least one seventh via K7, wherein the second insulating layer 12, the first insulating layer 11, and the dielectric layer 27 located within the sixth via K6 and the seventh via K7 are all etched away. The orthographic projection of the sixth via K6 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the third region 17-3 onto the plane of the array substrate, and the sixth via K6 exposes a portion of the surface of the third region 17-3 away from the substrate 30. The orthographic projection of the seventh via K7 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the fourth region 17-4 onto the plane of the array substrate, and the seventh via K7 exposes a portion of the surface of the fourth region 17-4 away from the substrate 30.

[0177] The third conductive layer may include at least one first signal connection line L11 and at least one second signal connection line L12. The orthographic projection of the first signal connection line L11 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the sixth via K6 onto the plane of the array substrate, and a portion of the first signal connection line L11 may be located within the sixth via K6 and connected to the third region 17-3. The orthographic projection of the second signal connection line L12 onto the plane of the array substrate at least partially overlaps with the orthographic projection of the seventh via K7 onto the plane of the array substrate, and a portion of the second signal connection line L12 may be located within the seventh via K7 and connected to the fourth region 17-4. Placing the first and second signal connection lines in the same conductive layer can reduce the area occupied by the structure, which is beneficial for improving the narrow bezel design of the array substrate.

[0178] In some possible exemplary embodiments, the second active layer 17 is located on the first semiconductor layer, the second gate 18 is located on the first conductive layer, and the first signal connection line L11 and the second signal connection line L12 are both located on the third conductive layer.

[0179] Other structures of the second border region of the array substrate can be referred to the description in the foregoing embodiments, and will not be elaborated here.

[0180] In this embodiment of the disclosure, the structure of the display area and the structure of the second border area can be arbitrarily combined. For example, Figure 3A The structure shown is Figure 4A The structural combination shown, or Figure 3A The structure shown is Figure 23A The structural combination shown, or Figure 3A The structure shown is Figure 22 The structural combination shown, or Figure 21B The structure shown is Figure 4A The structural combinations shown are examples of such combinations.

[0181] This disclosure provides a method for fabricating an array substrate, comprising:

[0182] A first conductive layer is formed on one side of the substrate, the first conductive layer including at least one data line;

[0183] A first insulating layer is formed on the side of the first conductive layer away from the substrate, the first insulating layer including at least one first via, and the first via exposing a portion of the data line;

[0184] A first semiconductor layer is formed on the side of the first insulating layer away from the substrate. The first semiconductor layer includes a first active layer of at least one first transistor, and the first active layer of the at least one first transistor includes a first channel region.

[0185] Wherein, at least a portion of the first channel region is located within the first via, and the angle between the first channel region and the direction perpendicular to the plane of the substrate is greater than or equal to 0 degrees and less than or equal to 5 degrees.

[0186] This disclosure also provides a display device. The display device includes the array substrate described in any of the foregoing embodiments. The display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This disclosure is not limited in this respect.

[0187] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate; a first conductive layer located on the substrate, and the first conductive layer comprises at least one data line; a first insulating layer located on a side of the first conductive layer away from the substrate, and the first insulating layer comprises at least one first via hole, and the first via hole exposes part of the data line; and a first semiconductor layer partially located on a side of the first insulating layer away from the substrate, and the first semiconductor layer comprises a first active layer of at least one first transistor, and the first active layer of the at least one first transistor comprises a first channel region; wherein at least part of the first channel region is located in the first via hole, and the first channel region forms an angle with a direction perpendicular to a plane in which the substrate is located, and the angle is greater than or equal to 0 degrees and less than or equal to 5 degrees.

2. The array substrate of claim 1, wherein, The first active layer of the at least one first transistor further comprises a first region and a second region connected to the first channel region, and the first region and the second region are located on opposite sides of the first channel region respectively; the first region is located in the first via hole, and the first region is in contact with the data line; at least part of the second region is located on a side of the first insulating layer away from the substrate.

3. The array substrate of claim 2, wherein, The array substrate further comprises a second conductive layer located on a side of the first insulating layer away from the substrate, and the second conductive layer comprises at least one pixel electrode, and a side of the second region close to the substrate is in contact with a side of the pixel electrode away from the substrate.

4. The array substrate of claim 3, wherein, The first via hole comprises a sidewall, and a projection of the sidewall on a plane in which the substrate is located overlaps with a projection of at least part of an edge of the pixel electrode close to the first via hole on the plane in which the substrate is located; wherein the first channel region is in contact with the sidewall.

5. The array substrate of claim 3, wherein, The array substrate further comprises a third conductive layer located on a side of the second conductive layer away from the substrate; the third conductive layer comprises a plurality of gate lines, and the plurality of gate lines all extend along a first direction and are arranged at intervals along a second direction; wherein a plane formed by the first direction and the second direction is parallel to a plane in which the substrate is located; The array substrate further comprises a plurality of first insulating portions, and the plurality of first insulating portions are arranged in pairs with the plurality of gate lines respectively, and at least part of the first insulating portion is located on a side of the gate line away from the substrate, and the plurality of first insulating portions all extend along the first direction and are arranged at intervals along the second direction.

6. The array substrate of claim 2, wherein, The array substrate further comprises a second conductive layer located on a side of the first insulating layer away from the substrate, and the second conductive layer comprises at least one pixel connection electrode, and a side of the second region close to the substrate is in contact with a side of the pixel connection electrode away from the substrate, and the pixel connection electrode is configured to be connected with a pixel electrode, and the pixel electrode is located on a side of the pixel connection electrode away from the substrate.

7. The array substrate of claim 6, wherein, The array substrate further comprises at least one pixel electrode, and the at least one pixel electrode is located on the side of the second conductive layer away from the substrate, and at least one insulating layer is arranged between the pixel electrode and the pixel connecting electrode, and the at least one insulating layer is provided with at least one via hole; the pixel electrode is connected with the pixel connecting electrode through the via hole, and the side of the pixel electrode away from the substrate is a plane.

8. The array substrate according to any one of claims 3 to 7, wherein, The array substrate further comprises a fourth conductive layer and a fifth conductive layer which are sequentially located on the side of the second conductive layer away from the substrate; the fourth conductive layer comprises at least one common electrode line, and the fifth conductive layer comprises at least one common electrode, and the at least one common electrode line is in contact with the at least one common electrode; wherein the common electrode line extends along a first direction, the common electrode extends along a second direction, and the plane formed by the first direction and the second direction is parallel to the plane where the substrate is located.

9. The array substrate of claim 8, wherein, The common electrode is away from the substrate compared with the pixel electrode; there is a minimum spacing between the common electrode and the pixel electrode along the direction perpendicular to the plane where the substrate is located, and the minimum spacing is 900 angstroms to 1100 angstroms.

10. The array substrate of any one of claims 1 to 7, wherein, The array substrate comprises a display area and a frame area located on at least one side of the display area. The array substrate further comprises at least one second transistor located in the frame area; the at least one second transistor comprises a second active layer, and the second active layer is located in the first semiconductor layer.

11. The array substrate of claim 10, wherein, The array substrate further comprises at least one first signal connecting line, and the at least one first signal connecting line is located in the first conductive layer; the first insulating layer further comprises at least one second via hole, the second via hole exposes part of the first signal connecting line, and part of the second active layer is located in the second via hole and in contact with the first signal connecting line.

12. The array substrate of claim 11, wherein, The array substrate further comprises a second insulating layer located on the side of the first semiconductor layer away from the substrate; the second insulating layer is provided with at least one via hole, and the at least one via hole exposes part of the first signal connecting line and the second active layer; The array substrate further comprises at least one signal connecting electrode, and at least part of the signal connecting electrode is located in the at least one via hole and connected with the first signal connecting line and the second active layer.

13. The array substrate of any one of claims 1 to 7, wherein, The array substrate comprises a display area and a frame area located on at least one side of the display area. The array substrate further comprises at least one second transistor located in the frame area; the at least one second transistor comprises a second active layer, and the second active layer is located in the first semiconductor layer or a second semiconductor layer, and the second semiconductor layer is located between the first conductive layer and the substrate; wherein the surface of the side of the second active layer away from the substrate is a plane.

14. A display device comprising: The array substrate comprises the array substrate according to any one of claims 1 to 13.

15. A method for fabricating an array substrate, characterized in that, The array substrate comprises: forming a first conductive layer on one side of a substrate, the first conductive layer comprising at least one data line; A first insulating layer is formed on a side of the first conductive layer distal to the substrate, the first insulating layer includes at least one first via, and the first via exposes a portion of the data line; A first semiconductor layer is formed on a side of the first insulating layer distal to the substrate, the first semiconductor layer includes a first active layer of at least one first transistor, and the first active layer of the at least one first transistor includes a first channel region; At least a portion of the first channel region is located within the first via, and an angle between the first channel region and a direction perpendicular to a plane in which the substrate is located is greater than or equal to 0 degrees and less than or equal to 5 degrees.

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